Attachment 130384 Details for Bug 100322 – dmesg during

dmesg during

dmesg-during.log (text/plain), 27.51 MB, created by Jani Saarinen on 2017-03-22 16:42:08 UTC

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Creator: Jani Saarinen

Created: 2017-03-22 16:42:08 UTC

Size: 27.51 MB

patch

obsolete

>[   24.013529] Console: switching to colour dummy device 80x25
>[   24.013878] [IGT] core_auth: executing
>[   24.025621] [IGT] core_auth: starting subtest basic-auth
>[   24.026124] [IGT] core_auth: exiting, ret=0
>[   24.057651] Console: switching to colour frame buffer device 240x75
>[   24.113905] Console: switching to colour dummy device 80x25
>[   24.114064] [IGT] core_prop_blob: executing
>[   24.132418] [IGT] core_prop_blob: starting subtest basic
>[   24.132690] [IGT] core_prop_blob: exiting, ret=0
>[   24.174331] Console: switching to colour frame buffer device 240x75
>[   24.235831] Console: switching to colour dummy device 80x25
>[   24.236003] [IGT] drv_getparams_basic: executing
>[   24.248323] [IGT] drv_getparams_basic: starting subtest basic-eu-total
>[   24.248457] [IGT] drv_getparams_basic: exiting, ret=0
>[   24.291091] Console: switching to colour frame buffer device 240x75
>[   24.352743] Console: switching to colour dummy device 80x25
>[   24.352879] [IGT] drv_getparams_basic: executing
>[   24.382893] [IGT] drv_getparams_basic: starting subtest basic-subslice-total
>[   24.383016] [IGT] drv_getparams_basic: exiting, ret=0
>[   24.424529] Console: switching to colour frame buffer device 240x75
>[   24.485495] Console: switching to colour dummy device 80x25
>[   24.485718] [IGT] drv_hangman: executing
>[   24.499573] [IGT] drv_hangman: starting subtest error-state-basic
>[   24.499795] [drm:error_state_write [i915]] Resetting error state
>[   24.503854] [drm] GPU HANG: ecode 8:-1:0x00000000, reason: Manually setting wedged to 1, action: reset
>[   24.503868] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
>[   24.503872] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
>[   24.503876] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
>[   24.503880] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
>[   24.503884] [drm] GPU crash dump saved to /sys/class/drm/card0/error
>[   24.504384] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   24.504532] drm/i915: Resetting chip after gpu hang
>[   24.505315] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[   24.506727] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   24.506753] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[   24.506781] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   24.506807] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   24.506833] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   24.506858] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   24.525025] [drm:error_state_write [i915]] Resetting error state
>[   24.525199] [IGT] drv_hangman: exiting, ret=0
>[   24.541303] Console: switching to colour frame buffer device 240x75
>[   24.597870] Console: switching to colour dummy device 80x25
>[   24.597975] [IGT] gem_basic: executing
>[   24.609347] [IGT] gem_basic: starting subtest bad-close
>[   24.609446] [IGT] gem_basic: exiting, ret=0
>[   24.641372] Console: switching to colour frame buffer device 240x75
>[   24.699518] Console: switching to colour dummy device 80x25
>[   24.699831] [IGT] gem_basic: executing
>[   24.713349] [IGT] gem_basic: starting subtest create-close
>[   24.713495] [IGT] gem_basic: exiting, ret=0
>[   24.741450] Console: switching to colour frame buffer device 240x75
>[   24.798238] Console: switching to colour dummy device 80x25
>[   24.798381] [IGT] gem_basic: executing
>[   24.823814] [IGT] gem_basic: starting subtest create-fd-close
>[   24.824394] [IGT] gem_basic: exiting, ret=0
>[   24.874886] Console: switching to colour frame buffer device 240x75
>[   24.937038] Console: switching to colour dummy device 80x25
>[   24.937208] [IGT] gem_busy: executing
>[   24.949499] [IGT] gem_busy: starting subtest basic-busy-default
>[   24.972290] [IGT] gem_busy: exiting, ret=0
>[   25.025020] Console: switching to colour frame buffer device 240x75
>[   25.087337] Console: switching to colour dummy device 80x25
>[   25.087501] [IGT] gem_busy: executing
>[   25.100315] [IGT] gem_busy: starting subtest basic-hang-default
>[   40.746596] [drm] GPU HANG: ecode 8:0:0xe757fefe, in gem_busy [6259], reason: Hang on render ring, action: reset
>[   40.747265] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   40.747599] drm/i915: Resetting chip after gpu hang
>[   40.748711] [drm:i915_gem_reset [i915]] context gem_busy[6259]/0 marked guilty (score 10) banned? no
>[   40.748757] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x168
>[   40.749153] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[   40.751726] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   40.751777] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x168, 0x0]
>[   40.751830] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[   40.751890] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   40.752123] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   40.752161] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   40.752198] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   40.752978] [IGT] gem_busy: exiting, ret=0
>[   40.804182] Console: switching to colour frame buffer device 240x75
>[   40.867325] Console: switching to colour dummy device 80x25
>[   40.867497] [IGT] gem_close_race: executing
>[   40.882537] [IGT] gem_close_race: starting subtest basic-process
>[   40.889458] [IGT] gem_close_race: exiting, ret=0
>[   40.937610] Console: switching to colour frame buffer device 240x75
>[   40.999487] Console: switching to colour dummy device 80x25
>[   40.999638] [IGT] gem_close_race: executing
>[   41.014992] [IGT] gem_close_race: starting subtest basic-threads
>[   42.091169] [IGT] gem_close_race: exiting, ret=0
>[   42.138571] Console: switching to colour frame buffer device 240x75
>[   42.200882] Console: switching to colour dummy device 80x25
>[   42.201056] [IGT] gem_cpu_reloc: executing
>[   42.212689] [IGT] gem_cpu_reloc: starting subtest basic
>[   42.217527] [IGT] gem_cpu_reloc: exiting, ret=0
>[   42.255318] Console: switching to colour frame buffer device 240x75
>[   42.317983] Console: switching to colour dummy device 80x25
>[   42.318158] [IGT] gem_cs_tlb: executing
>[   42.329678] [IGT] gem_cs_tlb: starting subtest basic-default
>[   43.930198] [IGT] gem_cs_tlb: exiting, ret=0
>[   43.973359] Console: switching to colour frame buffer device 240x75
>[   44.033913] Console: switching to colour dummy device 80x25
>[   44.034029] [IGT] gem_ctx_basic: executing
>[   48.147557] [IGT] gem_ctx_basic: exiting, ret=0
>[   48.259997] Console: switching to colour frame buffer device 240x75
>[   48.355522] Console: switching to colour dummy device 80x25
>[   48.355761] [IGT] gem_ctx_create: executing
>[   48.379357] [IGT] gem_ctx_create: starting subtest basic
>[   48.380636] [IGT] gem_ctx_create: exiting, ret=0
>[   48.426796] Console: switching to colour frame buffer device 240x75
>[   48.495868] Console: switching to colour dummy device 80x25
>[   48.495990] [IGT] gem_ctx_create: executing
>[   48.522168] [IGT] gem_ctx_create: starting subtest basic-files
>[   53.560106] [IGT] gem_ctx_create: exiting, ret=0
>[   53.614346] Console: switching to colour frame buffer device 240x75
>[   53.676676] Console: switching to colour dummy device 80x25
>[   53.676810] [IGT] gem_ctx_exec: executing
>[   53.688874] [IGT] gem_ctx_exec: starting subtest basic
>[   53.689831] [IGT] gem_ctx_exec: exiting, ret=0
>[   53.714416] Console: switching to colour frame buffer device 240x75
>[   53.787118] Console: switching to colour dummy device 80x25
>[   53.787270] [IGT] gem_ctx_param: executing
>[   53.799612] [IGT] gem_ctx_param: starting subtest basic
>[   53.799794] [IGT] gem_ctx_param: exiting, ret=0
>[   53.847855] Console: switching to colour frame buffer device 240x75
>[   53.909415] Console: switching to colour dummy device 80x25
>[   53.909591] [IGT] gem_ctx_param: executing
>[   53.922614] [IGT] gem_ctx_param: starting subtest basic-default
>[   53.922807] [IGT] gem_ctx_param: exiting, ret=0
>[   53.981293] Console: switching to colour frame buffer device 240x75
>[   54.044181] Console: switching to colour dummy device 80x25
>[   54.044426] [IGT] gem_ctx_switch: executing
>[   54.057881] [IGT] gem_ctx_switch: starting subtest basic-default
>[   59.068788] [IGT] gem_ctx_switch: exiting, ret=0
>[   59.118692] Console: switching to colour frame buffer device 240x75
>[   59.180494] Console: switching to colour dummy device 80x25
>[   59.180651] [IGT] gem_ctx_switch: executing
>[   59.194597] [IGT] gem_ctx_switch: starting subtest basic-default-heavy
>[   78.457779] [IGT] gem_ctx_switch: exiting, ret=0
>[   78.517475] Console: switching to colour frame buffer device 240x75
>[   78.579982] Console: switching to colour dummy device 80x25
>[   78.580150] [IGT] gem_exec_basic: executing
>[   78.596830] [IGT] gem_exec_basic: starting subtest basic-blt
>[   78.598281] [IGT] gem_exec_basic: exiting, ret=0
>[   78.650835] Console: switching to colour frame buffer device 240x75
>[   78.712289] Console: switching to colour dummy device 80x25
>[   78.712573] [IGT] gem_exec_basic: executing
>[   78.724755] [IGT] gem_exec_basic: starting subtest basic-bsd
>[   78.725976] [IGT] gem_exec_basic: exiting, ret=0
>[   78.784269] Console: switching to colour frame buffer device 240x75
>[   78.847361] Console: switching to colour dummy device 80x25
>[   78.847533] [IGT] gem_exec_basic: executing
>[   78.862778] [IGT] gem_exec_basic: starting subtest basic-bsd1
>[   78.864154] [IGT] gem_exec_basic: exiting, ret=0
>[   78.917711] Console: switching to colour frame buffer device 240x75
>[   78.982617] Console: switching to colour dummy device 80x25
>[   78.982797] [IGT] gem_exec_basic: executing
>[   78.996791] [IGT] gem_exec_basic: starting subtest basic-bsd2
>[   78.998178] [IGT] gem_exec_basic: exiting, ret=0
>[   79.051141] Console: switching to colour frame buffer device 240x75
>[   79.113712] Console: switching to colour dummy device 80x25
>[   79.113881] [IGT] gem_exec_basic: executing
>[   79.132406] [IGT] gem_exec_basic: starting subtest basic-default
>[   79.133771] [IGT] gem_exec_basic: exiting, ret=0
>[   79.184586] Console: switching to colour frame buffer device 240x75
>[   79.246056] Console: switching to colour dummy device 80x25
>[   79.246186] [IGT] gem_exec_basic: executing
>[   79.261804] [IGT] gem_exec_basic: starting subtest basic-render
>[   79.263205] [IGT] gem_exec_basic: exiting, ret=0
>[   79.318024] Console: switching to colour frame buffer device 240x75
>[   79.379758] Console: switching to colour dummy device 80x25
>[   79.379863] [IGT] gem_exec_basic: executing
>[   79.391837] [IGT] gem_exec_basic: starting subtest basic-vebox
>[   79.393119] [IGT] gem_exec_basic: exiting, ret=0
>[   79.434784] Console: switching to colour frame buffer device 240x75
>[   79.497482] Console: switching to colour dummy device 80x25
>[   79.497635] [IGT] gem_exec_basic: executing
>[   79.507782] [IGT] gem_exec_basic: starting subtest gtt-blt
>[   79.509877] [IGT] gem_exec_basic: exiting, ret=0
>[   79.568230] Console: switching to colour frame buffer device 240x75
>[   79.632687] Console: switching to colour dummy device 80x25
>[   79.632825] [IGT] gem_exec_basic: executing
>[   79.643795] [IGT] gem_exec_basic: starting subtest gtt-bsd
>[   79.645556] [IGT] gem_exec_basic: exiting, ret=0
>[   79.701674] Console: switching to colour frame buffer device 240x75
>[   79.763399] Console: switching to colour dummy device 80x25
>[   79.763510] [IGT] gem_exec_basic: executing
>[   79.782370] [IGT] gem_exec_basic: starting subtest gtt-bsd1
>[   79.784012] [IGT] gem_exec_basic: exiting, ret=0
>[   79.835106] Console: switching to colour frame buffer device 240x75
>[   79.896488] Console: switching to colour dummy device 80x25
>[   79.896630] [IGT] gem_exec_basic: executing
>[   79.910728] [IGT] gem_exec_basic: starting subtest gtt-bsd2
>[   79.912072] [IGT] gem_exec_basic: exiting, ret=0
>[   79.951872] Console: switching to colour frame buffer device 240x75
>[   80.014723] Console: switching to colour dummy device 80x25
>[   80.014896] [IGT] gem_exec_basic: executing
>[   80.029833] [IGT] gem_exec_basic: starting subtest gtt-default
>[   80.031209] [IGT] gem_exec_basic: exiting, ret=0
>[   80.085319] Console: switching to colour frame buffer device 240x75
>[   80.145869] Console: switching to colour dummy device 80x25
>[   80.146022] [IGT] gem_exec_basic: executing
>[   80.157733] [IGT] gem_exec_basic: starting subtest gtt-render
>[   80.159355] [IGT] gem_exec_basic: exiting, ret=0
>[   80.202056] Console: switching to colour frame buffer device 240x75
>[   80.264826] Console: switching to colour dummy device 80x25
>[   80.264997] [IGT] gem_exec_basic: executing
>[   80.278745] [IGT] gem_exec_basic: starting subtest gtt-vebox
>[   80.280559] [IGT] gem_exec_basic: exiting, ret=0
>[   80.335518] Console: switching to colour frame buffer device 240x75
>[   80.397729] Console: switching to colour dummy device 80x25
>[   80.397860] [IGT] gem_exec_basic: executing
>[   80.408818] [IGT] gem_exec_basic: starting subtest readonly-blt
>[   80.410413] [IGT] gem_exec_basic: exiting, ret=0
>[   80.452287] Console: switching to colour frame buffer device 240x75
>[   80.513869] Console: switching to colour dummy device 80x25
>[   80.513982] [IGT] gem_exec_basic: executing
>[   80.529701] [IGT] gem_exec_basic: starting subtest readonly-bsd
>[   80.530851] [IGT] gem_exec_basic: exiting, ret=0
>[   80.585692] Console: switching to colour frame buffer device 240x75
>[   80.647008] Console: switching to colour dummy device 80x25
>[   80.647169] [IGT] gem_exec_basic: executing
>[   80.661720] [IGT] gem_exec_basic: starting subtest readonly-bsd1
>[   80.663598] [IGT] gem_exec_basic: exiting, ret=0
>[   80.719134] Console: switching to colour frame buffer device 240x75
>[   80.780567] Console: switching to colour dummy device 80x25
>[   80.780688] [IGT] gem_exec_basic: executing
>[   80.793776] [IGT] gem_exec_basic: starting subtest readonly-bsd2
>[   80.795363] [IGT] gem_exec_basic: exiting, ret=0
>[   80.852566] Console: switching to colour frame buffer device 240x75
>[   80.914507] Console: switching to colour dummy device 80x25
>[   80.914613] [IGT] gem_exec_basic: executing
>[   80.929709] [IGT] gem_exec_basic: starting subtest readonly-default
>[   80.931187] [IGT] gem_exec_basic: exiting, ret=0
>[   80.986013] Console: switching to colour frame buffer device 240x75
>[   81.048929] Console: switching to colour dummy device 80x25
>[   81.049101] [IGT] gem_exec_basic: executing
>[   81.069555] [IGT] gem_exec_basic: starting subtest readonly-render
>[   81.070853] [IGT] gem_exec_basic: exiting, ret=0
>[   81.119477] Console: switching to colour frame buffer device 240x75
>[   81.181678] Console: switching to colour dummy device 80x25
>[   81.181849] [IGT] gem_exec_basic: executing
>[   81.193683] [IGT] gem_exec_basic: starting subtest readonly-vebox
>[   81.195060] [IGT] gem_exec_basic: exiting, ret=0
>[   81.236233] Console: switching to colour frame buffer device 240x75
>[   81.298726] Console: switching to colour dummy device 80x25
>[   81.298896] [IGT] gem_exec_create: executing
>[   81.312712] [IGT] gem_exec_create: starting subtest basic
>[   86.514237] [IGT] gem_exec_create: exiting, ret=0
>[   86.557137] Console: switching to colour frame buffer device 240x75
>[   86.620507] Console: switching to colour dummy device 80x25
>[   86.620677] [IGT] gem_exec_fence: executing
>[   86.632580] [IGT] gem_exec_fence: starting subtest basic-busy-default
>[   86.660415] [IGT] gem_exec_fence: exiting, ret=0
>[   86.707247] Console: switching to colour frame buffer device 240x75
>[   86.771174] Console: switching to colour dummy device 80x25
>[   86.771422] [IGT] gem_exec_fence: executing
>[   86.781438] [IGT] gem_exec_fence: starting subtest basic-wait-default
>[   86.817428] [IGT] gem_exec_fence: exiting, ret=0
>[   86.857325] Console: switching to colour frame buffer device 240x75
>[   86.919758] Console: switching to colour dummy device 80x25
>[   86.919880] [IGT] gem_exec_fence: executing
>[   86.932410] [IGT] gem_exec_fence: starting subtest basic-await-default
>[   87.942141] [IGT] gem_exec_fence: exiting, ret=0
>[   87.991563] Console: switching to colour frame buffer device 240x75
>[   88.054982] Console: switching to colour dummy device 80x25
>[   88.055161] [IGT] gem_exec_fence: executing
>[   88.066497] [IGT] gem_exec_fence: starting subtest await-hang-default
>[   91.745131] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[   97.767233] [drm] GPU HANG: ecode 8:0:0xe757fefe, in gem_exec_fence [6430], reason: Hang on render ring, action: reset
>[   97.767430] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   97.767618] drm/i915: Resetting chip after gpu hang
>[   97.768181] [drm:i915_gem_reset [i915]] context gem_exec_fence[6430]/0 marked guilty (score 10) banned? no
>[   97.768227] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x2aea7
>[   97.769307] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[   97.770818] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   97.770853] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x2aea9, 0x0]
>[   97.770888] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[   97.770926] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   97.770962] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   97.770998] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   97.771032] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   97.782053] [IGT] gem_exec_fence: exiting, ret=0
>[   97.832739] Console: switching to colour frame buffer device 240x75
>[   97.895767] Console: switching to colour dummy device 80x25
>[   97.895941] [IGT] gem_exec_fence: executing
>[   97.908086] [IGT] gem_exec_fence: starting subtest nb-await-default
>[   98.910915] [IGT] gem_exec_fence: exiting, ret=0
>[   98.950246] Console: switching to colour frame buffer device 240x75
>[   99.012948] Console: switching to colour dummy device 80x25
>[   99.013118] [IGT] gem_exec_flush: executing
>[   99.027053] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-cmd
>[   99.028568] [IGT] gem_exec_flush: exiting, ret=77
>[   99.083712] Console: switching to colour frame buffer device 240x75
>[   99.146441] Console: switching to colour dummy device 80x25
>[   99.146678] [IGT] gem_exec_flush: executing
>[   99.160082] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-uc
>[  104.665175] [IGT] gem_exec_flush: exiting, ret=0
>[  104.721505] Console: switching to colour frame buffer device 240x75
>[  104.786136] Console: switching to colour dummy device 80x25
>[  104.786293] [IGT] gem_exec_flush: executing
>[  104.800846] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-wb
>[  110.449052] [IGT] gem_exec_flush: exiting, ret=0
>[  110.509372] Console: switching to colour frame buffer device 240x75
>[  110.573381] Console: switching to colour dummy device 80x25
>[  110.573554] [IGT] gem_exec_flush: executing
>[  110.585652] [IGT] gem_exec_flush: starting subtest basic-uc-pro-default
>[  115.967300] [IGT] gem_exec_flush: exiting, ret=0
>[  116.013750] Console: switching to colour frame buffer device 240x75
>[  116.077500] Console: switching to colour dummy device 80x25
>[  116.077674] [IGT] gem_exec_flush: executing
>[  116.090418] [IGT] gem_exec_flush: starting subtest basic-uc-prw-default
>[  121.469859] [IGT] gem_exec_flush: exiting, ret=0
>[  121.518102] Console: switching to colour frame buffer device 240x75
>[  121.580487] Console: switching to colour dummy device 80x25
>[  121.580671] [IGT] gem_exec_flush: executing
>[  121.600213] [IGT] gem_exec_flush: starting subtest basic-uc-ro-default
>[  126.980189] [IGT] gem_exec_flush: exiting, ret=0
>[  127.022509] Console: switching to colour frame buffer device 240x75
>[  127.086288] Console: switching to colour dummy device 80x25
>[  127.086613] [IGT] gem_exec_flush: executing
>[  127.099867] [IGT] gem_exec_flush: starting subtest basic-uc-rw-default
>[  132.479207] [IGT] gem_exec_flush: exiting, ret=0
>[  132.526815] Console: switching to colour frame buffer device 240x75
>[  132.591568] Console: switching to colour dummy device 80x25
>[  132.591740] [IGT] gem_exec_flush: executing
>[  132.604702] [IGT] gem_exec_flush: starting subtest basic-uc-set-default
>[  137.986458] [IGT] gem_exec_flush: exiting, ret=0
>[  138.031204] Console: switching to colour frame buffer device 240x75
>[  138.094535] Console: switching to colour dummy device 80x25
>[  138.094707] [IGT] gem_exec_flush: executing
>[  138.107503] [IGT] gem_exec_flush: starting subtest basic-wb-pro-default
>[  143.487471] [IGT] gem_exec_flush: exiting, ret=0
>[  143.535527] Console: switching to colour frame buffer device 240x75
>[  143.598763] Console: switching to colour dummy device 80x25
>[  143.598972] [IGT] gem_exec_flush: executing
>[  143.612294] [IGT] gem_exec_flush: starting subtest basic-wb-prw-default
>[  148.993530] [IGT] gem_exec_flush: exiting, ret=0
>[  149.039906] Console: switching to colour frame buffer device 240x75
>[  149.102752] Console: switching to colour dummy device 80x25
>[  149.102907] [IGT] gem_exec_flush: executing
>[  149.119076] [IGT] gem_exec_flush: starting subtest basic-wb-ro-before-default
>[  154.500240] [IGT] gem_exec_flush: exiting, ret=0
>[  154.544340] Console: switching to colour frame buffer device 240x75
>[  154.609233] Console: switching to colour dummy device 80x25
>[  154.609411] [IGT] gem_exec_flush: executing
>[  154.622830] [IGT] gem_exec_flush: starting subtest basic-wb-ro-default
>[  160.003094] [IGT] gem_exec_flush: exiting, ret=0
>[  160.048659] Console: switching to colour frame buffer device 240x75
>[  160.111688] Console: switching to colour dummy device 80x25
>[  160.111796] [IGT] gem_exec_flush: executing
>[  160.125148] [IGT] gem_exec_flush: starting subtest basic-wb-rw-before-default
>[  165.509314] [IGT] gem_exec_flush: exiting, ret=0
>[  165.552988] Console: switching to colour frame buffer device 240x75
>[  165.617041] Console: switching to colour dummy device 80x25
>[  165.617215] [IGT] gem_exec_flush: executing
>[  165.631229] [IGT] gem_exec_flush: starting subtest basic-wb-rw-default
>[  171.011362] [IGT] gem_exec_flush: exiting, ret=0
>[  171.057366] Console: switching to colour frame buffer device 240x75
>[  171.120994] Console: switching to colour dummy device 80x25
>[  171.121102] [IGT] gem_exec_flush: executing
>[  171.136190] [IGT] gem_exec_flush: starting subtest basic-wb-set-default
>[  176.517705] [IGT] gem_exec_flush: exiting, ret=0
>[  176.578433] Console: switching to colour frame buffer device 240x75
>[  176.642170] Console: switching to colour dummy device 80x25
>[  176.642445] [IGT] gem_exec_gttfill: executing
>[  176.657337] [IGT] gem_exec_gttfill: starting subtest basic
>[  176.668410] gem_exec_gttfil (6561): drop_caches: 4
>[  180.896477] [IGT] gem_exec_gttfill: exiting, ret=0
>[  180.948533] Console: switching to colour frame buffer device 240x75
>[  181.041198] Console: switching to colour dummy device 80x25
>[  181.041326] [IGT] gem_exec_nop: executing
>[  181.068255] [IGT] gem_exec_nop: starting subtest basic-parallel
>[  191.431408] [IGT] gem_exec_nop: exiting, ret=0
>[  191.473565] Console: switching to colour frame buffer device 240x75
>[  191.536606] Console: switching to colour dummy device 80x25
>[  191.536910] [IGT] gem_exec_nop: executing
>[  191.550364] [IGT] gem_exec_nop: starting subtest basic-series
>[  201.921796] [IGT] gem_exec_nop: exiting, ret=0
>[  201.981888] Console: switching to colour frame buffer device 240x75
>[  202.048606] Console: switching to colour dummy device 80x25
>[  202.048733] [IGT] gem_exec_parallel: executing
>[  202.062545] [IGT] gem_exec_parallel: starting subtest basic
>[  203.339475] [IGT] gem_exec_parallel: exiting, ret=0
>[  203.383028] Console: switching to colour frame buffer device 240x75
>[  203.450964] Console: switching to colour dummy device 80x25
>[  203.451134] [IGT] gem_exec_parse: executing
>[  203.461538] [IGT] gem_exec_parse: exiting, ret=77
>[  203.483035] Console: switching to colour frame buffer device 240x75
>[  203.542785] Console: switching to colour dummy device 80x25
>[  203.542960] [IGT] gem_exec_parse: executing
>[  203.556592] [IGT] gem_exec_parse: exiting, ret=77
>[  203.583099] Console: switching to colour frame buffer device 240x75
>[  203.644681] Console: switching to colour dummy device 80x25
>[  203.644852] [IGT] gem_exec_reloc: executing
>[  203.655403] [IGT] gem_exec_reloc: starting subtest basic-cpu
>[  203.656739] [IGT] gem_exec_reloc: exiting, ret=0
>[  203.699907] Console: switching to colour frame buffer device 240x75
>[  203.764137] Console: switching to colour dummy device 80x25
>[  203.764363] [IGT] gem_exec_reloc: executing
>[  203.776542] [IGT] gem_exec_reloc: starting subtest basic-gtt
>[  203.778675] [IGT] gem_exec_reloc: exiting, ret=0
>[  203.833370] Console: switching to colour frame buffer device 240x75
>[  203.898068] Console: switching to colour dummy device 80x25
>[  203.898383] [IGT] gem_exec_reloc: executing
>[  203.910460] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt
>[  203.912289] [IGT] gem_exec_reloc: exiting, ret=0
>[  203.966771] Console: switching to colour frame buffer device 240x75
>[  204.031106] Console: switching to colour dummy device 80x25
>[  204.031378] [IGT] gem_exec_reloc: executing
>[  204.042478] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu
>[  204.044359] [IGT] gem_exec_reloc: exiting, ret=0
>[  204.100237] Console: switching to colour frame buffer device 240x75
>[  204.164626] Console: switching to colour dummy device 80x25
>[  204.164799] [IGT] gem_exec_reloc: executing
>[  204.176452] [IGT] gem_exec_reloc: starting subtest basic-cpu-read
>[  204.178065] [IGT] gem_exec_reloc: exiting, ret=0
>[  204.233657] Console: switching to colour frame buffer device 240x75
>[  204.298023] Console: switching to colour dummy device 80x25
>[  204.298262] [IGT] gem_exec_reloc: executing
>[  204.309505] [IGT] gem_exec_reloc: starting subtest basic-gtt-read
>[  204.311458] [IGT] gem_exec_reloc: exiting, ret=0
>[  204.367085] Console: switching to colour frame buffer device 240x75
>[  204.431585] Console: switching to colour dummy device 80x25
>[  204.431796] [IGT] gem_exec_reloc: executing
>[  204.444441] [IGT] gem_exec_reloc: starting subtest basic-write-cpu
>[  204.446249] [IGT] gem_exec_reloc: exiting, ret=0
>[  204.500541] Console: switching to colour frame buffer device 240x75
>[  204.565336] Console: switching to colour dummy device 80x25
>[  204.565514] [IGT] gem_exec_reloc: executing
>[  204.575432] [IGT] gem_exec_reloc: starting subtest basic-write-gtt
>[  204.577317] [IGT] gem_exec_reloc: exiting, ret=0
>[  204.633960] Console: switching to colour frame buffer device 240x75
>[  204.698221] Console: switching to colour dummy device 80x25
>[  204.698362] [IGT] gem_exec_reloc: executing
>[  204.710522] [IGT] gem_exec_reloc: starting subtest basic-write-read
>[  204.712210] [IGT] gem_exec_reloc: exiting, ret=0
>[  204.767399] Console: switching to colour frame buffer device 240x75
>[  204.830730] Console: switching to colour dummy device 80x25
>[  204.830900] [IGT] gem_exec_reloc: executing
>[  204.843436] [IGT] gem_exec_reloc: starting subtest basic-cpu-noreloc
>[  204.845039] [IGT] gem_exec_reloc: exiting, ret=0
>[  204.900836] Console: switching to colour frame buffer device 240x75
>[  204.964756] Console: switching to colour dummy device 80x25
>[  204.964926] [IGT] gem_exec_reloc: executing
>[  204.975516] [IGT] gem_exec_reloc: starting subtest basic-gtt-noreloc
>[  204.977285] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.017619] Console: switching to colour frame buffer device 240x75
>[  205.081493] Console: switching to colour dummy device 80x25
>[  205.081674] [IGT] gem_exec_reloc: executing
>[  205.095509] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt-noreloc
>[  205.097331] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.134359] Console: switching to colour frame buffer device 240x75
>[  205.198715] Console: switching to colour dummy device 80x25
>[  205.198869] [IGT] gem_exec_reloc: executing
>[  205.209496] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu-noreloc
>[  205.211264] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.251126] Console: switching to colour frame buffer device 240x75
>[  205.316556] Console: switching to colour dummy device 80x25
>[  205.316739] [IGT] gem_exec_reloc: executing
>[  205.329504] [IGT] gem_exec_reloc: starting subtest basic-cpu-read-noreloc
>[  205.331204] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.384565] Console: switching to colour frame buffer device 240x75
>[  205.449000] Console: switching to colour dummy device 80x25
>[  205.449216] [IGT] gem_exec_reloc: executing
>[  205.461417] [IGT] gem_exec_reloc: starting subtest basic-gtt-read-noreloc
>[  205.463315] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.501345] Console: switching to colour frame buffer device 240x75
>[  205.564260] Console: switching to colour dummy device 80x25
>[  205.564369] [IGT] gem_exec_reloc: executing
>[  205.577369] [IGT] gem_exec_reloc: starting subtest basic-write-cpu-noreloc
>[  205.578897] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.618105] Console: switching to colour frame buffer device 240x75
>[  205.681196] Console: switching to colour dummy device 80x25
>[  205.681374] [IGT] gem_exec_reloc: executing
>[  205.694402] [IGT] gem_exec_reloc: starting subtest basic-write-gtt-noreloc
>[  205.695968] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.734829] Console: switching to colour frame buffer device 240x75
>[  205.798660] Console: switching to colour dummy device 80x25
>[  205.798803] [IGT] gem_exec_reloc: executing
>[  205.812465] [IGT] gem_exec_reloc: starting subtest basic-write-read-noreloc
>[  205.813817] [IGT] gem_exec_reloc: exiting, ret=0
>[  205.868305] Console: switching to colour frame buffer device 240x75
>[  205.932608] Console: switching to colour dummy device 80x25
>[  205.932797] [IGT] gem_exec_reloc: executing
>[  205.946493] [IGT] gem_exec_reloc: starting subtest basic-cpu-active
>[  206.053470] [IGT] gem_exec_reloc: exiting, ret=0
>[  206.085105] Console: switching to colour frame buffer device 240x75
>[  206.150104] Console: switching to colour dummy device 80x25
>[  206.150275] [IGT] gem_exec_reloc: executing
>[  206.165484] [IGT] gem_exec_reloc: starting subtest basic-gtt-active
>[  206.271213] [IGT] gem_exec_reloc: exiting, ret=0
>[  206.318590] Console: switching to colour frame buffer device 240x75
>[  206.383348] Console: switching to colour dummy device 80x25
>[  206.383522] [IGT] gem_exec_reloc: executing
>[  206.394416] [IGT] gem_exec_reloc: starting subtest basic-cpu-gtt-active
>[  206.500421] [IGT] gem_exec_reloc: exiting, ret=0
>[  206.552190] Console: switching to colour frame buffer device 240x75
>[  206.617378] Console: switching to colour dummy device 80x25
>[  206.617554] [IGT] gem_exec_reloc: executing
>[  206.647328] [IGT] gem_exec_reloc: starting subtest basic-gtt-cpu-active
>[  206.753118] [IGT] gem_exec_reloc: exiting, ret=0
>[  206.785662] Console: switching to colour frame buffer device 240x75
>[  206.850781] Console: switching to colour dummy device 80x25
>[  206.850953] [IGT] gem_exec_reloc: executing
>[  206.861433] [IGT] gem_exec_reloc: starting subtest basic-cpu-read-active
>[  206.966931] [IGT] gem_exec_reloc: exiting, ret=0
>[  207.019224] Console: switching to colour frame buffer device 240x75
>[  207.083827] Console: switching to colour dummy device 80x25
>[  207.083993] [IGT] gem_exec_reloc: executing
>[  207.097339] [IGT] gem_exec_reloc: starting subtest basic-gtt-read-active
>[  207.202935] [IGT] gem_exec_reloc: exiting, ret=0
>[  207.252698] Console: switching to colour frame buffer device 240x75
>[  207.324906] Console: switching to colour dummy device 80x25
>[  207.325206] [IGT] gem_exec_reloc: executing
>[  207.337304] [IGT] gem_exec_reloc: starting subtest basic-write-cpu-active
>[  207.443419] [IGT] gem_exec_reloc: exiting, ret=0
>[  207.502902] Console: switching to colour frame buffer device 240x75
>[  207.568063] Console: switching to colour dummy device 80x25
>[  207.568243] [IGT] gem_exec_reloc: executing
>[  207.582616] [IGT] gem_exec_reloc: starting subtest basic-write-gtt-active
>[  207.688441] [IGT] gem_exec_reloc: exiting, ret=0
>[  207.736396] Console: switching to colour frame buffer device 240x75
>[  207.801172] Console: switching to colour dummy device 80x25
>[  207.801279] [IGT] gem_exec_reloc: executing
>[  207.814314] [IGT] gem_exec_reloc: starting subtest basic-write-read-active
>[  207.919892] [IGT] gem_exec_reloc: exiting, ret=0
>[  207.953276] Console: switching to colour frame buffer device 240x75
>[  208.018124] Console: switching to colour dummy device 80x25
>[  208.018298] [IGT] gem_exec_reloc: executing
>[  208.028413] [IGT] gem_exec_reloc: starting subtest basic-softpin
>[  208.029135] [IGT] gem_exec_reloc: exiting, ret=0
>[  208.070065] Console: switching to colour frame buffer device 240x75
>[  208.135095] Console: switching to colour dummy device 80x25
>[  208.135210] [IGT] gem_exec_store: executing
>[  208.150670] [IGT] gem_exec_store: starting subtest basic-all
>[  208.194643] [IGT] gem_exec_store: exiting, ret=0
>[  208.236821] Console: switching to colour frame buffer device 240x75
>[  208.303306] Console: switching to colour dummy device 80x25
>[  208.303481] [IGT] gem_exec_store: executing
>[  208.317319] [IGT] gem_exec_store: starting subtest basic-blt
>[  208.350700] [IGT] gem_exec_store: exiting, ret=0
>[  208.403608] Console: switching to colour frame buffer device 240x75
>[  208.468646] Console: switching to colour dummy device 80x25
>[  208.468816] [IGT] gem_exec_store: executing
>[  208.483452] [IGT] gem_exec_store: starting subtest basic-bsd
>[  208.511542] [IGT] gem_exec_store: exiting, ret=0
>[  208.553752] Console: switching to colour frame buffer device 240x75
>[  208.618179] Console: switching to colour dummy device 80x25
>[  208.618309] [IGT] gem_exec_store: executing
>[  208.630476] [IGT] gem_exec_store: starting subtest basic-bsd1
>[  208.659505] [IGT] gem_exec_store: exiting, ret=0
>[  208.703860] Console: switching to colour frame buffer device 240x75
>[  208.769305] Console: switching to colour dummy device 80x25
>[  208.769425] [IGT] gem_exec_store: executing
>[  208.780077] [IGT] gem_exec_store: starting subtest basic-bsd2
>[  208.820679] [IGT] gem_exec_store: exiting, ret=0
>[  208.870652] Console: switching to colour frame buffer device 240x75
>[  208.935017] Console: switching to colour dummy device 80x25
>[  208.935182] [IGT] gem_exec_store: executing
>[  208.947438] [IGT] gem_exec_store: starting subtest basic-default
>[  208.981623] [IGT] gem_exec_store: exiting, ret=0
>[  209.037449] Console: switching to colour frame buffer device 240x75
>[  209.102782] Console: switching to colour dummy device 80x25
>[  209.103024] [IGT] gem_exec_store: executing
>[  209.117494] [IGT] gem_exec_store: starting subtest basic-render
>[  209.150552] [IGT] gem_exec_store: exiting, ret=0
>[  209.204266] Console: switching to colour frame buffer device 240x75
>[  209.271407] Console: switching to colour dummy device 80x25
>[  209.271564] [IGT] gem_exec_store: executing
>[  209.282456] [IGT] gem_exec_store: starting subtest basic-vebox
>[  209.314415] [IGT] gem_exec_store: exiting, ret=0
>[  209.371085] Console: switching to colour frame buffer device 240x75
>[  209.437607] Console: switching to colour dummy device 80x25
>[  209.437777] [IGT] gem_exec_suspend: executing
>[  209.451470] [IGT] gem_exec_suspend: starting subtest basic
>[  209.590655] [IGT] gem_exec_suspend: exiting, ret=0
>[  209.637973] Console: switching to colour frame buffer device 240x75
>[  209.704193] Console: switching to colour dummy device 80x25
>[  209.704374] [IGT] gem_exec_suspend: executing
>[  209.719479] [IGT] gem_exec_suspend: starting subtest basic-S3
>[  210.664541] PM: Syncing filesystems ... done.
>[  210.665580] PM: Preparing system for sleep (mem)
>[  210.666231] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  210.668049] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  210.669653] PM: Suspending system (mem)
>[  210.669816] Suspending console(s) (use no_console_suspend to debug)
>[  210.672260] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  210.672998] sd 0:0:0:0: [sda] Stopping disk
>[  210.673979] e1000e: EEE TX LPI TIMER: 00000011
>[  210.689164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  210.705223] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  210.705297] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  210.724384] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  210.724460] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  210.724497] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  210.724542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  210.724576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  210.724610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  210.724640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  210.724674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  210.724714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  210.724758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  210.724800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  210.724842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  210.724883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  210.724951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  210.724986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  210.725037] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  210.727540] PM: suspend of devices complete after 56.501 msecs
>[  210.729348] [drm:intel_power_well_disable [i915]] disabling display
>[  210.729407] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  210.729427] [drm:intel_power_well_disable [i915]] disabling always-on
>[  210.729454] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  210.741024] PM: late suspend of devices complete after 13.477 msecs
>[  210.743631] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  210.743914] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  210.755908] PM: noirq suspend of devices complete after 14.878 msecs
>[  210.756284] ACPI: Preparing to enter system sleep state S3
>[  210.781403] PM: Saving platform NVS memory
>[  210.781575] Disabling non-boot CPUs ...
>[  210.798293] smpboot: CPU 1 is now offline
>[  210.815032] Broke affinity for irq 23
>[  210.815039] Broke affinity for irq 42
>[  210.816371] smpboot: CPU 2 is now offline
>[  210.832913] Broke affinity for irq 8
>[  210.832916] Broke affinity for irq 9
>[  210.832922] Broke affinity for irq 23
>[  210.832926] Broke affinity for irq 42
>[  210.832929] Broke affinity for irq 44
>[  210.833977] smpboot: CPU 3 is now offline
>[  210.837539] ACPI: Low-level resume complete
>[  210.837684] PM: Restoring platform NVS memory
>[  210.838297] Suspended for 15.579 seconds
>[  210.839191] Enabling non-boot CPUs ...
>[  210.839557] x86: Booting SMP configuration:
>[  210.839572] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  210.842215]  cache: parent cpu1 should not be sleeping
>[  210.843702] CPU1 is up
>[  210.843823] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  210.845272]  cache: parent cpu2 should not be sleeping
>[  210.846222] CPU2 is up
>[  210.846285] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  210.847529]  cache: parent cpu3 should not be sleeping
>[  210.849466] CPU3 is up
>[  210.858856] ACPI: Waking up from system sleep state S3
>[  210.884479] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  210.884488] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  210.884660] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  210.885104] PM: noirq resume of devices complete after 13.199 msecs
>[  210.889391] hpet1: lost 5710 rtc interrupts
>[  210.890242] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  210.890385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  210.890412] [drm:intel_power_well_enable [i915]] enabling display
>[  210.891604] PM: early resume of devices complete after 6.381 msecs
>[  210.892065] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  210.892158] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  210.892189] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  210.894383] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  210.898333] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  210.898365] [drm:intel_opregion_setup [i915]] ASLE supported
>[  210.898395] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  210.898423] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  210.898436] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  210.898805] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  210.898850] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  210.898889] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  210.898927] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  210.898964] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  210.899000] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  210.899382] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  210.899477] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  210.899508] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  210.899538] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  210.899563] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  210.899592] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  210.899617] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  210.899645] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  210.899672] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  210.899699] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  210.899724] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  210.899749] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  210.899774] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  210.899801] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  210.899828] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  210.899853] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  210.899879] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  210.899904] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  210.899952] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  210.899985] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  210.900014] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  210.900052] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  210.900077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  210.900114] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  210.900138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  210.900144] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  210.900168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  210.900172] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  210.900198] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  210.900223] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  210.900248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  210.900272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  210.900297] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  210.900321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  210.900346] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  210.900371] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  210.900396] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  210.900423] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  210.900447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  210.900472] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  210.900496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  210.900500] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  210.900524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  210.900528] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  210.900553] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  210.900578] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  210.900603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  210.900627] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  210.900652] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  210.900676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  210.900701] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  210.900726] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  210.900751] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  210.900778] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  210.900802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  210.900827] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  210.900851] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  210.900855] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  210.900879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  210.900883] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  210.900908] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  210.900932] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  210.900957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  210.900981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  210.901006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  210.901030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  210.901055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  210.901080] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  210.901117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  210.901146] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  210.901171] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  210.901195] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  210.901272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  210.901297] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  210.901323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  210.901351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  210.901375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  210.901401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  210.901426] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  210.901451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  210.901476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  210.901500] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  210.901524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  210.901529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  210.901553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  210.901557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  210.901582] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  210.901607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  210.901632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  210.901656] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  210.901681] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  210.901705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  210.901730] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  210.901755] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  210.901779] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  210.901806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  210.901833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  210.902262] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  210.902300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  210.902323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  210.902353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  210.902382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  210.902507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  210.902508] sd 0:0:0:0: [sda] Starting disk
>[  210.902536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  210.902557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  210.902580] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  210.902602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  210.902623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  210.902643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  210.902668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  210.902693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  210.902717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  210.902755] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  210.902784] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  210.904913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  210.904934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  210.904956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  210.904980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  210.906551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  210.906571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  210.906588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  210.908185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  210.908204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  210.910061] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  210.913463] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  210.913559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  210.913592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  210.913656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  210.913790] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  210.913828] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  210.930300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  210.930344] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  210.930409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  210.930445] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  210.930483] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  210.930682] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  210.931232] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  210.932329] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  210.932361] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  210.934433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  210.934441] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  210.936577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  210.936614] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  210.938744] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  210.938755] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  210.938762] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  210.938803] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  210.939978] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  210.940915] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  210.940939] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  210.940960] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  210.940980] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  210.941999] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  210.942018] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  210.943044] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  210.943079] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  210.945212] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  210.945252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  210.947339] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  210.947349] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  210.949426] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  210.949462] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  210.951597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  210.951607] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  210.951614] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  211.098714] PM: resume of devices complete after 207.114 msecs
>[  211.099939] PM: Finishing wakeup.
>[  211.099942] Restarting tasks ... done.
>[  211.109584] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  211.110225] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  211.110237] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  211.210807] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  211.226672] ata1.00: configured for UDMA/133
>[  212.130471] [IGT] gem_exec_suspend: exiting, ret=0
>[  212.181421] Console: switching to colour frame buffer device 240x75
>[  212.251997] Console: switching to colour dummy device 80x25
>[  212.252205] [IGT] gem_exec_suspend: executing
>[  212.279576] [IGT] gem_exec_suspend: starting subtest basic-S4-devices
>[  213.402950] PM: Syncing filesystems ... 
>[  213.407040] PM: done.
>[  213.407045] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  213.409020] PM: Marking nosave pages: [mem 0x00000000-0x00000fff]
>[  213.409034] PM: Marking nosave pages: [mem 0x00058000-0x00058fff]
>[  213.409038] PM: Marking nosave pages: [mem 0x0009f000-0x000fffff]
>[  213.409044] PM: Marking nosave pages: [mem 0x9cf8f000-0x9d459fff]
>[  213.409074] PM: Marking nosave pages: [mem 0xa22c1000-0xa2ffefff]
>[  213.409151] PM: Marking nosave pages: [mem 0xa3000000-0xffffffff]
>[  213.410412] PM: Basic memory bitmaps created
>[  213.411538] PM: Preallocating image memory... done (allocated 187505 pages)
>[  213.603356] PM: Allocated 750020 kbytes in 0.19 seconds (3947.47 MB/s)
>[  213.603358] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  213.606166] Suspending console(s) (use no_console_suspend to debug)
>[  213.619453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  213.623117] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  213.623123] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  213.632415] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  213.632455] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  213.651541] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  213.651585] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  213.651618] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  213.651659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  213.651693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  213.651729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  213.651761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  213.651791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  213.651823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  213.651859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  213.651892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  213.651924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  213.651955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  213.652018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  213.652046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  213.652106] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  213.655522] PM: freeze of devices complete after 49.310 msecs
>[  213.655525] PM: hibernation debug: Waiting for 5 seconds.
>[  218.835362] usb usb1: root hub lost power or was reset
>[  218.835419] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  218.835475] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  218.835501] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  218.839272] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
>[  218.841910] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  218.842833] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  218.842856] [drm:intel_opregion_setup [i915]] ASLE supported
>[  218.842876] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  218.842895] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  218.843034] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  218.843056] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  218.843082] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  218.843107] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  218.843131] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  218.843154] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  218.843385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  218.843466] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  218.843491] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  218.843520] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  218.843546] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  218.843575] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  218.843600] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  218.843627] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  218.843655] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  218.843682] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  218.843707] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  218.843733] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  218.843758] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  218.843797] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  218.843824] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  218.843850] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  218.843875] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  218.843900] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  218.843929] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  218.843958] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  218.843987] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  218.844019] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  218.844045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  218.844069] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  218.844093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  218.844099] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  218.844130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  218.844137] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  218.844162] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  218.844182] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  218.844200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  218.844218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  218.844239] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  218.844257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  218.844275] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  218.844292] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  218.844309] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  218.844329] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  218.844346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  218.844362] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  218.844378] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  218.844382] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  218.844399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  218.844402] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  218.844419] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  218.844436] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  218.844452] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  218.844468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  218.844489] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  218.844506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  218.844523] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  218.844540] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  218.844557] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  218.844575] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  218.844592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  218.844608] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  218.844625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  218.844628] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  218.844645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  218.844648] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  218.844665] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  218.844681] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  218.844698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  218.844714] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  218.844734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  218.844753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  218.844788] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  218.844812] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  218.844837] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  218.844865] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  218.844891] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  218.844916] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  218.844974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  218.844999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  218.845025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  218.845053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  218.845077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  218.845103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  218.845128] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  218.845153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  218.845178] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  218.845203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  218.845228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  218.845232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  218.845256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  218.845261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  218.845286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  218.845310] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  218.845335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  218.845360] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  218.845385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  218.845409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  218.845434] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  218.845458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  218.845483] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  218.845510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  218.845537] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  218.845619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  218.845645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  218.845670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  218.845695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  218.845720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  218.845745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  218.845783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  218.845811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  218.845838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  218.845865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  218.845892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  218.845916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  218.845940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  218.845967] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  218.845992] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  218.846798] sd 0:0:0:0: [sda] Starting disk
>[  218.848078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  218.848109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  218.848138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  218.848168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  218.849795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  218.849827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  218.849857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  218.851406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  218.851428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  218.853304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  218.856686] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  218.856739] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  218.856799] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  218.856842] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  218.856905] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  218.856936] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  218.873484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  218.873531] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  218.873603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  218.873646] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  218.873694] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  218.873906] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  218.874210] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  218.876423] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  218.876443] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  218.878519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  218.878528] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  218.880635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  218.880673] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  218.882742] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  218.882781] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  218.882789] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  218.882829] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  218.883941] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  218.884891] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  218.884912] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  218.884930] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  218.884948] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  218.885964] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  218.885984] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  218.886930] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  218.886967] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  218.889050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  218.889081] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  218.891160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  218.891168] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  218.893261] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  218.893293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  218.895377] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  218.895383] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  218.895388] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  219.154585] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  219.165266] usb 1-1: reset high-speed USB device number 2 using ehci-pci
>[  219.167110] ata1.00: configured for UDMA/133
>[  219.564858] usb 1-1.7: reset full-speed USB device number 3 using ehci-pci
>[  219.644932] PM: restore of devices complete after 811.118 msecs
>[  219.646490] PM: Image restored successfully.
>[  219.646649] PM: Basic memory bitmaps freed
>[  219.646652] Restarting tasks ... done.
>[  219.671514] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  220.734856] [IGT] gem_exec_suspend: exiting, ret=0
>[  220.791814] Console: switching to colour frame buffer device 240x75
>[  220.869186] Console: switching to colour dummy device 80x25
>[  220.869306] [IGT] gem_flink_basic: executing
>[  220.883932] [IGT] gem_flink_basic: starting subtest bad-flink
>[  220.884002] [IGT] gem_flink_basic: exiting, ret=0
>[  220.908644] Console: switching to colour frame buffer device 240x75
>[  220.978839] Console: switching to colour dummy device 80x25
>[  220.979004] [IGT] gem_flink_basic: executing
>[  220.992866] [IGT] gem_flink_basic: starting subtest bad-open
>[  220.992945] [IGT] gem_flink_basic: exiting, ret=0
>[  221.025321] Console: switching to colour frame buffer device 240x75
>[  221.088135] Console: switching to colour dummy device 80x25
>[  221.088249] [IGT] gem_flink_basic: executing
>[  221.100900] [IGT] gem_flink_basic: starting subtest basic
>[  221.101004] [IGT] gem_flink_basic: exiting, ret=0
>[  221.125376] Console: switching to colour frame buffer device 240x75
>[  221.189800] Console: switching to colour dummy device 80x25
>[  221.189918] [IGT] gem_flink_basic: executing
>[  221.201883] [IGT] gem_flink_basic: starting subtest double-flink
>[  221.201978] [IGT] gem_flink_basic: exiting, ret=0
>[  221.225451] Console: switching to colour frame buffer device 240x75
>[  221.298263] Console: switching to colour dummy device 80x25
>[  221.298444] [IGT] gem_flink_basic: executing
>[  221.310864] [IGT] gem_flink_basic: starting subtest flink-lifetime
>[  221.311146] [IGT] gem_flink_basic: exiting, ret=0
>[  221.342296] Console: switching to colour frame buffer device 240x75
>[  221.405262] Console: switching to colour dummy device 80x25
>[  221.405373] [IGT] gem_linear_blits: executing
>[  221.417937] [IGT] gem_linear_blits: starting subtest basic
>[  221.433611] [IGT] gem_linear_blits: exiting, ret=0
>[  221.475692] Console: switching to colour frame buffer device 240x75
>[  221.547225] Console: switching to colour dummy device 80x25
>[  221.547340] [IGT] gem_mmap: executing
>[  221.558846] [IGT] gem_mmap: starting subtest basic
>[  221.559109] [IGT] gem_mmap: exiting, ret=0
>[  221.592447] Console: switching to colour frame buffer device 240x75
>[  221.665925] Console: switching to colour dummy device 80x25
>[  221.666107] [IGT] gem_mmap: executing
>[  221.678862] [IGT] gem_mmap: starting subtest basic-small-bo
>[  221.935827] [IGT] gem_mmap: exiting, ret=0
>[  221.976098] Console: switching to colour frame buffer device 240x75
>[  222.084147] Console: switching to colour dummy device 80x25
>[  222.084334] [IGT] gem_mmap_gtt: executing
>[  222.095831] [IGT] gem_mmap_gtt: starting subtest basic
>[  222.096074] [IGT] gem_mmap_gtt: exiting, ret=0
>[  222.126168] Console: switching to colour frame buffer device 240x75
>[  222.197248] Console: switching to colour dummy device 80x25
>[  222.197361] [IGT] gem_mmap_gtt: executing
>[  222.208862] [IGT] gem_mmap_gtt: starting subtest basic-copy
>[  222.367357] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  222.416127] [IGT] gem_mmap_gtt: exiting, ret=0
>[  222.476463] Console: switching to colour frame buffer device 240x75
>[  222.549047] Console: switching to colour dummy device 80x25
>[  222.549229] [IGT] gem_mmap_gtt: executing
>[  222.562856] [IGT] gem_mmap_gtt: starting subtest basic-read
>[  222.589924] [IGT] gem_mmap_gtt: exiting, ret=0
>[  222.643793] Console: switching to colour frame buffer device 240x75
>[  222.716969] Console: switching to colour dummy device 80x25
>[  222.717091] [IGT] gem_mmap_gtt: executing
>[  222.733878] [IGT] gem_mmap_gtt: starting subtest basic-read-no-prefault
>[  222.734026] Setting dangerous option prefault_disable - tainting kernel
>[  222.763654] Setting dangerous option prefault_disable - tainting kernel
>[  222.763793] [IGT] gem_mmap_gtt: exiting, ret=0
>[  222.763891] Setting dangerous option prefault_disable - tainting kernel
>[  222.826845] Console: switching to colour frame buffer device 240x75
>[  222.895722] Console: switching to colour dummy device 80x25
>[  222.895913] [IGT] gem_mmap_gtt: executing
>[  222.909968] [IGT] gem_mmap_gtt: starting subtest basic-read-write
>[  222.919395] [IGT] gem_mmap_gtt: exiting, ret=0
>[  222.960272] Console: switching to colour frame buffer device 240x75
>[  223.027045] Console: switching to colour dummy device 80x25
>[  223.027174] [IGT] gem_mmap_gtt: executing
>[  223.040957] [IGT] gem_mmap_gtt: starting subtest basic-read-write-distinct
>[  223.050378] [IGT] gem_mmap_gtt: exiting, ret=0
>[  223.093755] Console: switching to colour frame buffer device 240x75
>[  223.160830] Console: switching to colour dummy device 80x25
>[  223.160990] [IGT] gem_mmap_gtt: executing
>[  223.171778] [IGT] gem_mmap_gtt: starting subtest basic-short
>[  223.187825] [IGT] gem_mmap_gtt: exiting, ret=0
>[  223.227155] Console: switching to colour frame buffer device 240x75
>[  223.293716] Console: switching to colour dummy device 80x25
>[  223.293890] [IGT] gem_mmap_gtt: executing
>[  223.305908] [IGT] gem_mmap_gtt: starting subtest basic-small-bo
>[  223.417686] [IGT] gem_mmap_gtt: exiting, ret=0
>[  223.510761] Console: switching to colour frame buffer device 240x75
>[  223.610108] Console: switching to colour dummy device 80x25
>[  223.610285] [IGT] gem_mmap_gtt: executing
>[  223.623855] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledX
>[  223.714881] [IGT] gem_mmap_gtt: exiting, ret=0
>[  223.810934] Console: switching to colour frame buffer device 240x75
>[  223.907079] Console: switching to colour dummy device 80x25
>[  223.907252] [IGT] gem_mmap_gtt: executing
>[  223.923870] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledY
>[  224.015140] [IGT] gem_mmap_gtt: exiting, ret=0
>[  224.111190] Console: switching to colour frame buffer device 240x75
>[  224.202364] Console: switching to colour dummy device 80x25
>[  224.202498] [IGT] gem_mmap_gtt: executing
>[  224.214844] [IGT] gem_mmap_gtt: starting subtest basic-small-copy
>[  224.494281] [IGT] gem_mmap_gtt: exiting, ret=0
>[  224.544880] Console: switching to colour frame buffer device 240x75
>[  224.634865] Console: switching to colour dummy device 80x25
>[  224.635044] [IGT] gem_mmap_gtt: executing
>[  224.645912] [IGT] gem_mmap_gtt: starting subtest basic-small-copy-XY
>[  224.983297] [IGT] gem_mmap_gtt: exiting, ret=0
>[  225.028515] Console: switching to colour frame buffer device 240x75
>[  225.108577] Console: switching to colour dummy device 80x25
>[  225.108753] [IGT] gem_mmap_gtt: executing
>[  225.119834] [IGT] gem_mmap_gtt: starting subtest basic-wc
>[  225.749545] [IGT] gem_mmap_gtt: exiting, ret=0
>[  225.795844] Console: switching to colour frame buffer device 240x75
>[  225.863742] Console: switching to colour dummy device 80x25
>[  225.863921] [IGT] gem_mmap_gtt: executing
>[  225.876852] [IGT] gem_mmap_gtt: starting subtest basic-write
>[  225.971167] [IGT] gem_mmap_gtt: exiting, ret=0
>[  226.029373] Console: switching to colour frame buffer device 240x75
>[  226.097329] Console: switching to colour dummy device 80x25
>[  226.097528] [IGT] gem_mmap_gtt: executing
>[  226.109770] [IGT] gem_mmap_gtt: starting subtest basic-write-cpu-read-gtt
>[  226.307700] [IGT] gem_mmap_gtt: exiting, ret=0
>[  226.346284] Console: switching to colour frame buffer device 240x75
>[  226.413280] Console: switching to colour dummy device 80x25
>[  226.413519] [IGT] gem_mmap_gtt: executing
>[  226.426753] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt
>[  226.548822] [IGT] gem_mmap_gtt: exiting, ret=0
>[  226.596537] Console: switching to colour frame buffer device 240x75
>[  226.664073] Console: switching to colour dummy device 80x25
>[  226.664232] [IGT] gem_mmap_gtt: executing
>[  226.674751] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt-no-prefault
>[  226.674893] Setting dangerous option prefault_disable - tainting kernel
>[  226.796354] Setting dangerous option prefault_disable - tainting kernel
>[  226.796633] [IGT] gem_mmap_gtt: exiting, ret=0
>[  226.796849] Setting dangerous option prefault_disable - tainting kernel
>[  226.846681] Console: switching to colour frame buffer device 240x75
>[  226.915549] Console: switching to colour dummy device 80x25
>[  226.915729] [IGT] gem_mmap_gtt: executing
>[  226.925763] [IGT] gem_mmap_gtt: starting subtest basic-write-no-prefault
>[  226.925849] Setting dangerous option prefault_disable - tainting kernel
>[  227.020316] Setting dangerous option prefault_disable - tainting kernel
>[  227.020514] [IGT] gem_mmap_gtt: exiting, ret=0
>[  227.020625] Setting dangerous option prefault_disable - tainting kernel
>[  227.063558] Console: switching to colour frame buffer device 240x75
>[  227.130788] Console: switching to colour dummy device 80x25
>[  227.130925] [IGT] gem_mmap_gtt: executing
>[  227.143817] [IGT] gem_mmap_gtt: starting subtest basic-write-read
>[  227.153387] [IGT] gem_mmap_gtt: exiting, ret=0
>[  227.196973] Console: switching to colour frame buffer device 240x75
>[  227.263455] Console: switching to colour dummy device 80x25
>[  227.263597] [IGT] gem_mmap_gtt: executing
>[  227.277796] [IGT] gem_mmap_gtt: starting subtest basic-write-read-distinct
>[  227.287418] [IGT] gem_mmap_gtt: exiting, ret=0
>[  227.330439] Console: switching to colour frame buffer device 240x75
>[  227.398791] Console: switching to colour dummy device 80x25
>[  227.398899] [IGT] gem_pread: executing
>[  227.409845] [IGT] gem_pread: starting subtest basic
>[  228.498300] [IGT] gem_pread: exiting, ret=0
>[  228.548029] Console: switching to colour frame buffer device 240x75
>[  228.619876] Console: switching to colour dummy device 80x25
>[  228.619980] [IGT] gem_pwrite: executing
>[  228.631704] [IGT] gem_pwrite: starting subtest basic
>[  229.838240] [IGT] gem_pwrite: exiting, ret=0
>[  229.882467] Console: switching to colour frame buffer device 240x75
>[  229.952694] Console: switching to colour dummy device 80x25
>[  229.952881] [IGT] gem_render_linear_blits: executing
>[  229.966627] [IGT] gem_render_linear_blits: starting subtest basic
>[  229.977392] [IGT] gem_render_linear_blits: exiting, ret=0
>[  230.015871] Console: switching to colour frame buffer device 240x75
>[  230.079191] Console: switching to colour dummy device 80x25
>[  230.079408] [IGT] gem_render_tiled_blits: executing
>[  230.092624] [IGT] gem_render_tiled_blits: starting subtest basic
>[  230.103441] [IGT] gem_render_tiled_blits: exiting, ret=0
>[  230.132617] Console: switching to colour frame buffer device 240x75
>[  230.196269] Console: switching to colour dummy device 80x25
>[  230.196472] [IGT] gem_ringfill: executing
>[  230.224065] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  230.225389] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  230.234236] [IGT] gem_ringfill: starting subtest basic-default
>[  230.270686] [IGT] gem_ringfill: exiting, ret=0
>[  230.316097] Console: switching to colour frame buffer device 240x75
>[  230.383480] Console: switching to colour dummy device 80x25
>[  230.383661] [IGT] gem_ringfill: executing
>[  230.401626] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  230.406928] [IGT] gem_ringfill: starting subtest basic-default-interruptible
>[  231.592668] [IGT] gem_ringfill: exiting, ret=0
>[  231.650497] Console: switching to colour frame buffer device 240x75
>[  231.718335] Console: switching to colour dummy device 80x25
>[  231.718512] [IGT] gem_ringfill: executing
>[  231.737557] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  231.742861] [IGT] gem_ringfill: starting subtest basic-default-forked
>[  231.788497] [IGT] gem_ringfill: exiting, ret=0
>[  231.833975] Console: switching to colour frame buffer device 240x75
>[  231.904252] Console: switching to colour dummy device 80x25
>[  231.904434] [IGT] gem_ringfill: executing
>[  231.924181] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  231.929573] [IGT] gem_ringfill: starting subtest basic-default-fd
>[  231.978545] [IGT] gem_ringfill: exiting, ret=0
>[  232.034113] Console: switching to colour frame buffer device 240x75
>[  232.102839] Console: switching to colour dummy device 80x25
>[  232.103008] [IGT] gem_ringfill: executing
>[  232.119543] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  232.124754] [IGT] gem_ringfill: starting subtest basic-default-hang
>[  235.741130] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  246.755664] [drm] GPU HANG: ecode 8:0:0xe757fffe, in gem_ringfill [8271], reason: No progress on render ring, action: reset
>[  246.756343] drm/i915: Resetting chip after gpu hang
>[  246.756424] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  246.758252] [drm:i915_gem_reset [i915]] context gem_ringfill[8271]/0 marked guilty (score 10) banned? no
>[  246.758285] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x168247
>[  246.758604] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  246.760971] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  246.761011] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x1682df, 0x0]
>[  246.761051] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  246.761091] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  246.761129] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  246.761167] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  246.761203] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  246.791895] [IGT] gem_ringfill: exiting, ret=0
>[  246.829176] Console: switching to colour frame buffer device 240x75
>[  246.900507] Console: switching to colour dummy device 80x25
>[  246.900816] [IGT] gem_sync: executing
>[  246.912802] [IGT] gem_sync: starting subtest basic-all
>[  252.075195] [IGT] gem_sync: exiting, ret=0
>[  252.133361] Console: switching to colour frame buffer device 240x75
>[  252.201585] Console: switching to colour dummy device 80x25
>[  252.201752] [IGT] gem_sync: executing
>[  252.217129] [IGT] gem_sync: starting subtest basic-each
>[  257.415000] [IGT] gem_sync: exiting, ret=0
>[  257.470936] Console: switching to colour frame buffer device 240x75
>[  257.538688] Console: switching to colour dummy device 80x25
>[  257.538850] [IGT] gem_sync: executing
>[  257.552739] [IGT] gem_sync: starting subtest basic-many-each
>[  263.058998] [IGT] gem_sync: exiting, ret=0
>[  263.108735] Console: switching to colour frame buffer device 240x75
>[  263.176329] Console: switching to colour dummy device 80x25
>[  263.176436] [IGT] gem_sync: executing
>[  263.190701] [IGT] gem_sync: starting subtest basic-store-all
>[  268.323424] [IGT] gem_sync: exiting, ret=0
>[  268.379580] Console: switching to colour frame buffer device 240x75
>[  268.448313] Console: switching to colour dummy device 80x25
>[  268.448487] [IGT] gem_sync: executing
>[  268.461439] [IGT] gem_sync: starting subtest basic-store-each
>[  273.784646] [IGT] gem_sync: exiting, ret=0
>[  273.833898] Console: switching to colour frame buffer device 240x75
>[  273.905894] Console: switching to colour dummy device 80x25
>[  273.905998] [IGT] gem_tiled_blits: executing
>[  273.915974] [IGT] gem_tiled_blits: starting subtest basic
>[  273.929221] [IGT] gem_tiled_blits: exiting, ret=0
>[  273.967346] Console: switching to colour frame buffer device 240x75
>[  274.039007] Console: switching to colour dummy device 80x25
>[  274.039176] [IGT] gem_tiled_fence_blits: executing
>[  274.049722] [IGT] gem_tiled_fence_blits: starting subtest basic
>[  274.057332] [IGT] gem_tiled_fence_blits: exiting, ret=0
>[  274.100783] Console: switching to colour frame buffer device 240x75
>[  274.172991] Console: switching to colour dummy device 80x25
>[  274.173159] [IGT] gem_tiled_pread_basic: executing
>[  274.320543] [IGT] gem_tiled_pread_basic: exiting, ret=0
>[  274.367686] Console: switching to colour frame buffer device 240x75
>[  274.438012] Console: switching to colour dummy device 80x25
>[  274.438139] [IGT] gem_wait: executing
>[  274.449806] [IGT] gem_wait: starting subtest basic-busy-all
>[  274.973041] [IGT] gem_wait: exiting, ret=0
>[  275.018166] Console: switching to colour frame buffer device 240x75
>[  275.089448] Console: switching to colour dummy device 80x25
>[  275.089620] [IGT] gem_wait: executing
>[  275.103400] [IGT] gem_wait: starting subtest basic-wait-all
>[  276.119098] [IGT] gem_wait: exiting, ret=0
>[  276.169089] Console: switching to colour frame buffer device 240x75
>[  276.239283] Console: switching to colour dummy device 80x25
>[  276.239557] [IGT] gem_wait: executing
>[  276.252729] [IGT] gem_wait: starting subtest basic-await-all
>[  276.267877] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  277.279206] [IGT] gem_wait: exiting, ret=0
>[  277.336677] Console: switching to colour frame buffer device 240x75
>[  277.410781] Console: switching to colour dummy device 80x25
>[  277.410907] [IGT] gem_workarounds: executing
>[  277.424904] [IGT] gem_workarounds: starting subtest basic-read
>[  277.438926] [IGT] gem_workarounds: exiting, ret=0
>[  277.470120] Console: switching to colour frame buffer device 240x75
>[  277.552801] Console: switching to colour dummy device 80x25
>[  277.552971] [IGT] kms_addfb_basic: executing
>[  277.565177] [drm:drm_mode_addfb2] [FB:58]
>[  277.565616] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
>[  277.565697] [drm:intel_framebuffer_init [i915]] Unsupported fb modifier 0xffffffffffffffff!
>[  277.565707] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  277.571249] [drm:drm_mode_addfb2] [FB:58]
>[  277.571388] [IGT] kms_addfb_basic: exiting, ret=0
>[  277.620203] Console: switching to colour frame buffer device 240x75
>[  277.697578] Console: switching to colour dummy device 80x25
>[  277.697751] [IGT] kms_addfb_basic: executing
>[  277.722627] [drm:drm_mode_addfb2] [FB:76]
>[  277.722895] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling
>[  277.722932] [drm:drm_mode_addfb2] [FB:76]
>[  277.728104] [drm:drm_mode_addfb2] [FB:76]
>[  277.728184] [IGT] kms_addfb_basic: exiting, ret=0
>[  277.770367] Console: switching to colour frame buffer device 240x75
>[  277.841627] Console: switching to colour dummy device 80x25
>[  277.841786] [IGT] kms_addfb_basic: executing
>[  277.851183] [drm:drm_mode_addfb2] [FB:58]
>[  277.851555] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
>[  277.851594] [drm:drm_internal_framebuffer_create] bad fb modifier 72057594037927937 for plane 0
>[  277.857173] [drm:drm_mode_addfb2] [FB:58]
>[  277.857255] [IGT] kms_addfb_basic: exiting, ret=0
>[  277.903799] Console: switching to colour frame buffer device 240x75
>[  277.975451] Console: switching to colour dummy device 80x25
>[  277.975581] [IGT] kms_addfb_basic: executing
>[  277.988114] [drm:drm_mode_addfb2] [FB:76]
>[  277.988494] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled
>[  277.988534] [drm:drm_mode_addfb2] [FB:76]
>[  277.993617] [drm:drm_mode_addfb2] [FB:76]
>[  277.993699] [IGT] kms_addfb_basic: exiting, ret=0
>[  278.037219] Console: switching to colour frame buffer device 240x75
>[  278.109113] Console: switching to colour dummy device 80x25
>[  278.109258] [IGT] kms_addfb_basic: executing
>[  278.121123] [drm:drm_mode_addfb2] [FB:58]
>[  278.121495] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled-mismatch
>[  278.121594] [drm:intel_framebuffer_init [i915]] tiling_mode doesn't match fb modifier
>[  278.121605] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  278.126923] [drm:drm_mode_addfb2] [FB:58]
>[  278.127004] [IGT] kms_addfb_basic: exiting, ret=0
>[  278.170670] Console: switching to colour frame buffer device 240x75
>[  278.242894] Console: switching to colour dummy device 80x25
>[  278.243067] [IGT] kms_addfb_basic: executing
>[  278.260096] [drm:drm_mode_addfb2] [FB:76]
>[  278.260563] [IGT] kms_addfb_basic: starting subtest addfb25-Yf-tiled
>[  278.260640] [drm:intel_framebuffer_init [i915]] Unsupported tiling 0x100000000000003!
>[  278.260650] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  278.265878] [drm:drm_mode_addfb2] [FB:76]
>[  278.265957] [IGT] kms_addfb_basic: exiting, ret=0
>[  278.320756] Console: switching to colour frame buffer device 240x75
>[  278.393852] Console: switching to colour dummy device 80x25
>[  278.394012] [IGT] kms_addfb_basic: executing
>[  278.408129] [drm:drm_mode_addfb2] [FB:58]
>[  278.408610] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled
>[  278.408687] [drm:intel_framebuffer_init [i915]] Unsupported tiling 0x100000000000002!
>[  278.408698] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  278.413946] [drm:drm_mode_addfb2] [FB:58]
>[  278.414026] [IGT] kms_addfb_basic: exiting, ret=0
>[  278.454370] Console: switching to colour frame buffer device 240x75
>[  278.527520] Console: switching to colour dummy device 80x25
>[  278.527693] [IGT] kms_addfb_basic: executing
>[  278.552581] [drm:drm_mode_addfb2] [FB:76]
>[  278.552910] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled-small
>[  278.558249] [drm:drm_mode_addfb2] [FB:76]
>[  278.558411] [IGT] kms_addfb_basic: exiting, ret=77
>[  278.604375] Console: switching to colour frame buffer device 240x75
>[  278.676876] Console: switching to colour dummy device 80x25
>[  278.677010] [IGT] kms_addfb_basic: executing
>[  278.686113] [drm:drm_mode_addfb2] [FB:58]
>[  278.686236] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
>[  278.686266] [drm:drm_internal_framebuffer_create] bad pitch 0 for plane 0
>[  278.691769] [drm:drm_mode_addfb2] [FB:58]
>[  278.691851] [IGT] kms_addfb_basic: exiting, ret=0
>[  278.737794] Console: switching to colour frame buffer device 240x75
>[  278.810229] Console: switching to colour dummy device 80x25
>[  278.810506] [IGT] kms_addfb_basic: executing
>[  278.824111] [drm:drm_mode_addfb2] [FB:76]
>[  278.824238] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
>[  278.824322] [drm:drm_internal_framebuffer_create] bad pitch 1024 for plane 0
>[  278.829590] [drm:drm_mode_addfb2] [FB:76]
>[  278.829671] [IGT] kms_addfb_basic: exiting, ret=0
>[  278.871227] Console: switching to colour frame buffer device 240x75
>[  278.943686] Console: switching to colour dummy device 80x25
>[  278.943864] [IGT] kms_addfb_basic: executing
>[  278.973575] [drm:drm_mode_addfb2] [FB:58]
>[  278.973706] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
>[  278.973736] [drm:drm_internal_framebuffer_create] bad pitch 128 for plane 0
>[  278.979072] [drm:drm_mode_addfb2] [FB:58]
>[  278.979152] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.004657] Console: switching to colour frame buffer device 240x75
>[  279.076295] Console: switching to colour dummy device 80x25
>[  279.076455] [IGT] kms_addfb_basic: executing
>[  279.088087] [drm:drm_mode_addfb2] [FB:76]
>[  279.088218] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
>[  279.088248] [drm:drm_internal_framebuffer_create] bad pitch 256 for plane 0
>[  279.093841] [drm:drm_mode_addfb2] [FB:76]
>[  279.093921] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.138097] Console: switching to colour frame buffer device 240x75
>[  279.210206] Console: switching to colour dummy device 80x25
>[  279.210419] [IGT] kms_addfb_basic: executing
>[  279.222112] [drm:drm_mode_addfb2] [FB:58]
>[  279.222237] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
>[  279.222342] [drm:drm_internal_framebuffer_create] bad pitch 32 for plane 0
>[  279.227805] [drm:drm_mode_addfb2] [FB:58]
>[  279.227888] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.271538] Console: switching to colour frame buffer device 240x75
>[  279.343079] Console: switching to colour dummy device 80x25
>[  279.343188] [IGT] kms_addfb_basic: executing
>[  279.357059] [drm:drm_mode_addfb2] [FB:76]
>[  279.357187] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
>[  279.357217] [drm:drm_internal_framebuffer_create] bad pitch 63 for plane 0
>[  279.363010] [drm:drm_mode_addfb2] [FB:76]
>[  279.363090] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.421673] Console: switching to colour frame buffer device 240x75
>[  279.493617] Console: switching to colour dummy device 80x25
>[  279.493791] [IGT] kms_addfb_basic: executing
>[  279.506134] [drm:drm_mode_addfb2] [FB:58]
>[  279.506331] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
>[  279.506438] [drm:intel_framebuffer_init [i915]] linear pitch (65536) must be at most 32768
>[  279.506454] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  279.511897] [drm:drm_mode_addfb2] [FB:58]
>[  279.511978] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.555099] Console: switching to colour frame buffer device 240x75
>[  279.628016] Console: switching to colour dummy device 80x25
>[  279.628174] [IGT] kms_addfb_basic: executing
>[  279.640118] [drm:drm_mode_addfb2] [FB:76]
>[  279.640306] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
>[  279.640352] [drm:drm_internal_framebuffer_create] bad pitch 999 for plane 0
>[  279.645741] [drm:drm_mode_addfb2] [FB:76]
>[  279.645821] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.705214] Console: switching to colour frame buffer device 240x75
>[  279.777033] Console: switching to colour dummy device 80x25
>[  279.777169] [IGT] kms_addfb_basic: executing
>[  279.789076] [drm:drm_mode_addfb2] [FB:58]
>[  279.789199] [IGT] kms_addfb_basic: starting subtest basic
>[  279.789299] [drm:drm_mode_addfb2] [FB:58]
>[  279.794671] [drm:drm_mode_addfb2] [FB:58]
>[  279.794738] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.838663] Console: switching to colour frame buffer device 240x75
>[  279.912606] Console: switching to colour dummy device 80x25
>[  279.912789] [IGT] kms_addfb_basic: executing
>[  279.924068] [drm:drm_mode_addfb2] [FB:76]
>[  279.929417] [IGT] kms_addfb_basic: starting subtest basic-X-tiled
>[  279.929456] [drm:drm_mode_addfb2] [FB:76]
>[  279.929542] [drm:drm_mode_addfb2] [FB:76]
>[  279.929602] [IGT] kms_addfb_basic: exiting, ret=0
>[  279.988778] Console: switching to colour frame buffer device 240x75
>[  280.062860] Console: switching to colour dummy device 80x25
>[  280.063031] [IGT] kms_addfb_basic: executing
>[  280.076068] [drm:drm_mode_addfb2] [FB:58]
>[  280.081522] [IGT] kms_addfb_basic: starting subtest basic-Y-tiled
>[  280.081577] [drm:intel_framebuffer_init [i915]] No Y tiling for legacy addfb
>[  280.081586] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  280.081680] [drm:drm_mode_addfb2] [FB:58]
>[  280.081758] [IGT] kms_addfb_basic: exiting, ret=0
>[  280.138897] Console: switching to colour frame buffer device 240x75
>[  280.212584] Console: switching to colour dummy device 80x25
>[  280.212759] [IGT] kms_addfb_basic: executing
>[  280.238565] [drm:drm_mode_addfb2] [FB:76]
>[  280.238760] [IGT] kms_addfb_basic: starting subtest bo-too-small
>[  280.238839] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4190208 bytes)
>[  280.238848] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  280.243994] [drm:drm_mode_addfb2] [FB:76]
>[  280.244077] [IGT] kms_addfb_basic: exiting, ret=0
>[  280.289014] Console: switching to colour frame buffer device 240x75
>[  280.361642] Console: switching to colour dummy device 80x25
>[  280.361808] [IGT] kms_addfb_basic: executing
>[  280.373058] [drm:drm_mode_addfb2] [FB:58]
>[  280.373333] [IGT] kms_addfb_basic: starting subtest bo-too-small-due-to-tiling
>[  280.373466] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4194304 bytes, have 4190208 bytes)
>[  280.373481] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  280.378966] [drm:drm_mode_addfb2] [FB:58]
>[  280.379047] [IGT] kms_addfb_basic: exiting, ret=0
>[  280.422461] Console: switching to colour frame buffer device 240x75
>[  280.495409] Console: switching to colour dummy device 80x25
>[  280.495530] [IGT] kms_addfb_basic: executing
>[  280.508076] [drm:drm_mode_addfb2] [FB:76]
>[  280.508147] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
>[  280.508252] [drm:drm_mode_addfb2] [FB:76]
>[  280.513528] [drm:drm_mode_addfb2] [FB:76]
>[  280.513609] [IGT] kms_addfb_basic: exiting, ret=0
>[  280.572571] Console: switching to colour frame buffer device 240x75
>[  280.645121] Console: switching to colour dummy device 80x25
>[  280.645403] [IGT] kms_addfb_basic: executing
>[  280.658059] [drm:drm_mode_addfb2] [FB:58]
>[  280.663462] [IGT] kms_addfb_basic: starting subtest framebuffer-vs-set-tiling
>[  280.663513] [drm:drm_mode_addfb2] [FB:58]
>[  280.663607] [drm:drm_mode_addfb2] [FB:58]
>[  280.663668] [IGT] kms_addfb_basic: exiting, ret=0
>[  280.722688] Console: switching to colour frame buffer device 240x75
>[  280.797154] Console: switching to colour dummy device 80x25
>[  280.797472] [IGT] kms_addfb_basic: executing
>[  280.809044] [drm:drm_mode_addfb2] [FB:76]
>[  280.814431] [drm:drm_mode_addfb2] [FB:76]
>[  280.814472] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
>[  280.814669] [IGT] kms_addfb_basic: exiting, ret=0
>[  280.872812] Console: switching to colour frame buffer device 240x75
>[  280.946514] Console: switching to colour dummy device 80x25
>[  280.946634] [IGT] kms_addfb_basic: executing
>[  280.971525] [drm:drm_mode_addfb2] [FB:58]
>[  280.976725] [drm:drm_mode_addfb2] [FB:58]
>[  280.976766] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
>[  280.976890] [IGT] kms_addfb_basic: exiting, ret=0
>[  281.022931] Console: switching to colour frame buffer device 240x75
>[  281.096028] Console: switching to colour dummy device 80x25
>[  281.096274] [IGT] kms_addfb_basic: executing
>[  281.109102] [drm:drm_mode_addfb2] [FB:76]
>[  281.114379] [drm:drm_mode_addfb2] [FB:76]
>[  281.114421] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
>[  281.114552] [IGT] kms_addfb_basic: exiting, ret=0
>[  281.156402] Console: switching to colour frame buffer device 240x75
>[  281.230438] Console: switching to colour dummy device 80x25
>[  281.230613] [IGT] kms_addfb_basic: executing
>[  281.243952] [drm:drm_mode_addfb2] [FB:58]
>[  281.249526] [drm:drm_mode_addfb2] [FB:58]
>[  281.249578] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
>[  281.249718] [IGT] kms_addfb_basic: exiting, ret=0
>[  281.306488] Console: switching to colour frame buffer device 240x75
>[  281.378860] Console: switching to colour dummy device 80x25
>[  281.379029] [IGT] kms_addfb_basic: executing
>[  281.394038] [drm:drm_mode_addfb2] [FB:76]
>[  281.394228] [IGT] kms_addfb_basic: starting subtest no-handle
>[  281.394279] [drm:drm_internal_framebuffer_create] no buffer object handle for plane 0
>[  281.399470] [drm:drm_mode_addfb2] [FB:76]
>[  281.399538] [IGT] kms_addfb_basic: exiting, ret=0
>[  281.456607] Console: switching to colour frame buffer device 240x75
>[  281.528758] Console: switching to colour dummy device 80x25
>[  281.528927] [IGT] kms_addfb_basic: executing
>[  281.541978] [drm:drm_mode_addfb2] [FB:58]
>[  281.542240] [IGT] kms_addfb_basic: starting subtest size-max
>[  281.542295] [drm:drm_mode_addfb2] [FB:58]
>[  281.542314] [drm:drm_mode_addfb2] [FB:58]
>[  281.542332] [drm:drm_mode_addfb2] [FB:58]
>[  281.547679] [drm:drm_mode_addfb2] [FB:58]
>[  281.547747] [IGT] kms_addfb_basic: exiting, ret=0
>[  281.606726] Console: switching to colour frame buffer device 240x75
>[  281.678929] Console: switching to colour dummy device 80x25
>[  281.679105] [IGT] kms_addfb_basic: executing
>[  281.694955] [drm:drm_mode_addfb2] [FB:76]
>[  281.695205] [IGT] kms_addfb_basic: starting subtest small-bo
>[  281.695264] [drm:drm_mode_addfb2] [FB:76]
>[  281.700388] [drm:drm_mode_addfb2] [FB:76]
>[  281.700455] [IGT] kms_addfb_basic: exiting, ret=0
>[  281.756852] Console: switching to colour frame buffer device 240x75
>[  281.828734] Console: switching to colour dummy device 80x25
>[  281.828896] [IGT] kms_addfb_basic: executing
>[  281.854455] [drm:drm_mode_addfb2] [FB:58]
>[  281.859671] [IGT] kms_addfb_basic: starting subtest tile-pitch-mismatch
>[  281.859722] [drm:intel_framebuffer_init [i915]] pitch (2048) must match tiling stride (4096)
>[  281.859730] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  281.859812] [drm:drm_mode_addfb2] [FB:58]
>[  281.859876] [IGT] kms_addfb_basic: exiting, ret=0
>[  281.906971] Console: switching to colour frame buffer device 240x75
>[  281.979456] Console: switching to colour dummy device 80x25
>[  281.979609] [IGT] kms_addfb_basic: executing
>[  281.990960] [drm:drm_mode_addfb2] [FB:76]
>[  281.991225] [IGT] kms_addfb_basic: starting subtest too-high
>[  281.991334] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes)
>[  281.991350] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  281.991414] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes)
>[  281.991427] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  281.991477] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes)
>[  281.991487] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  281.996656] [drm:drm_mode_addfb2] [FB:76]
>[  281.996742] [IGT] kms_addfb_basic: exiting, ret=0
>[  282.040396] Console: switching to colour frame buffer device 240x75
>[  282.113707] Console: switching to colour dummy device 80x25
>[  282.113883] [IGT] kms_addfb_basic: executing
>[  282.147486] [drm:drm_mode_addfb2] [FB:58]
>[  282.147690] [IGT] kms_addfb_basic: starting subtest too-wide
>[  282.147721] [drm:drm_internal_framebuffer_create] bad pitch 4096 for plane 0
>[  282.147727] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  282.147733] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  282.152863] [drm:drm_mode_addfb2] [FB:58]
>[  282.152944] [IGT] kms_addfb_basic: exiting, ret=0
>[  282.190514] Console: switching to colour frame buffer device 240x75
>[  282.263997] Console: switching to colour dummy device 80x25
>[  282.264236] [IGT] kms_addfb_basic: executing
>[  282.289432] [drm:drm_mode_addfb2] [FB:76]
>[  282.289502] [IGT] kms_addfb_basic: starting subtest unused-handle
>[  282.289537] [drm:drm_internal_framebuffer_create] buffer object handle for unused plane 1
>[  282.294880] [drm:drm_mode_addfb2] [FB:76]
>[  282.294948] [IGT] kms_addfb_basic: exiting, ret=0
>[  282.340646] Console: switching to colour frame buffer device 240x75
>[  282.412687] Console: switching to colour dummy device 80x25
>[  282.412801] [IGT] kms_addfb_basic: executing
>[  282.423982] [drm:drm_mode_addfb2] [FB:58]
>[  282.424051] [IGT] kms_addfb_basic: starting subtest unused-modifier
>[  282.424085] [drm:drm_internal_framebuffer_create] non-zero modifier for unused plane 1
>[  282.429542] [drm:drm_mode_addfb2] [FB:58]
>[  282.429609] [IGT] kms_addfb_basic: exiting, ret=0
>[  282.474089] Console: switching to colour frame buffer device 240x75
>[  282.546894] Console: switching to colour dummy device 80x25
>[  282.547019] [IGT] kms_addfb_basic: executing
>[  282.557944] [drm:drm_mode_addfb2] [FB:76]
>[  282.558014] [IGT] kms_addfb_basic: starting subtest unused-offsets
>[  282.558050] [drm:drm_internal_framebuffer_create] non-zero offset for unused plane 1
>[  282.563549] [drm:drm_mode_addfb2] [FB:76]
>[  282.563632] [IGT] kms_addfb_basic: exiting, ret=0
>[  282.607517] Console: switching to colour frame buffer device 240x75
>[  282.681543] Console: switching to colour dummy device 80x25
>[  282.681704] [IGT] kms_addfb_basic: executing
>[  282.697971] [drm:drm_mode_addfb2] [FB:58]
>[  282.698038] [IGT] kms_addfb_basic: starting subtest unused-pitches
>[  282.698073] [drm:drm_internal_framebuffer_create] non-zero pitch for unused plane 1
>[  282.703540] [drm:drm_mode_addfb2] [FB:58]
>[  282.703620] [IGT] kms_addfb_basic: exiting, ret=0
>[  282.757647] Console: switching to colour frame buffer device 240x75
>[  282.833848] Console: switching to colour dummy device 80x25
>[  282.834019] [IGT] kms_busy: executing
>[  282.860913] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  282.860947] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  282.863096] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  282.863183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  282.865298] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  282.865311] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  282.867428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  282.867468] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  282.869584] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  282.869595] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  282.869603] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  282.870267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  282.870309] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  282.871450] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  282.872373] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  282.872395] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  282.872415] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  282.872433] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  282.873454] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  282.873474] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  282.874677] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  282.874680] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  282.874786] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  282.874788] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  282.874793] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  282.874796] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  282.874801] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  282.874803] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  282.874976] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  282.874980] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  282.874983] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  282.874986] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  282.874989] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  282.874992] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  282.874995] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  282.874998] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  282.875001] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  282.875004] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  282.875007] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  282.875009] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  282.875012] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  282.875015] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  282.875018] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  282.875021] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  282.875024] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  282.875027] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  282.875030] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  282.875033] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  282.875036] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  282.875039] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  282.875042] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  282.875045] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  282.875048] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  282.875050] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  282.875053] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  282.875056] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  282.875059] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  282.875062] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  282.875065] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  282.875634] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  282.875662] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  282.877185] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  282.877226] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  282.879233] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  282.879245] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  282.881206] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  282.881246] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  282.883220] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  282.883232] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  282.883240] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  282.883808] [IGT] kms_busy: starting subtest basic-flip-default-A
>[  282.889621] [drm:drm_mode_addfb2] [FB:78]
>[  282.991080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  282.991117] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  283.024464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  283.024663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  283.030138] [drm:drm_mode_addfb2] [FB:58]
>[  283.677534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  283.691637] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  283.691713] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  283.692216] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  283.709359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  283.709459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  283.709502] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  283.709548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  283.709581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  283.709614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  283.709643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  283.709672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  283.709703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  283.709737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  283.709769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  283.709800] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  283.709830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  283.709857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  283.709884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  283.709974] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  283.710757] [IGT] kms_busy: exiting, ret=0
>[  283.728944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  283.728990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  283.729029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  283.729069] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  283.729132] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  283.729174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  283.729214] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  283.729253] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  283.729293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  283.729333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  283.729371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  283.729379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  283.729417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  283.729423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  283.729463] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  283.729503] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  283.729546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  283.729574] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  283.729604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  283.729629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  283.729653] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  283.729677] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  283.729699] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  283.729727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  283.729757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  283.729876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  283.729901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  283.729924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  283.729947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  283.729969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  283.729994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  283.730022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  283.730048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  283.730076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  283.730133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  283.730164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  283.730213] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  283.730251] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  283.732398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  283.732418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  283.732436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  283.732454] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  283.734054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  283.734072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  283.734100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  283.735661] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  283.735679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  283.737619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  283.740568] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  283.740621] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  283.740652] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  283.740708] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  283.740940] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  283.740971] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  283.757445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  283.757494] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  283.757563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  283.757804] Console: switching to colour frame buffer device 240x75
>[  283.828323] Console: switching to colour dummy device 80x25
>[  283.828478] [IGT] kms_busy: executing
>[  283.866331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  283.866360] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  283.868469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  283.868508] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  283.870628] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  283.870641] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  283.872764] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  283.872807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  283.874928] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  283.874939] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  283.874947] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  283.875663] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  283.875705] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  283.876938] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  283.877863] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  283.877886] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  283.877905] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  283.877923] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  283.878947] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  283.878968] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  283.880112] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  283.880115] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  283.880217] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  283.880220] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  283.880225] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  283.880227] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  283.880232] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  283.880234] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  283.880244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  283.880247] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  283.880251] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  283.880253] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  283.880256] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  283.880260] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  283.880262] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  283.880265] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  283.880268] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  283.880271] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  283.880274] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  283.880277] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  283.880280] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  283.880283] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  283.880286] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  283.880289] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  283.880292] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  283.880295] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  283.880298] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  283.880301] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  283.880304] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  283.880307] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  283.880310] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  283.880313] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  283.880316] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  283.880318] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  283.880321] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  283.880324] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  283.880327] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  283.880330] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  283.880333] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  283.880630] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  283.880653] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  283.882130] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  283.882161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  283.884252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  283.884261] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  283.886360] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  283.886397] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  283.888510] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  283.888522] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  283.888529] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  283.889384] [IGT] kms_busy: starting subtest basic-flip-default-B
>[  283.894860] [drm:drm_mode_addfb2] [FB:76]
>[  283.930459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  283.930518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  283.940943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  283.941039] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  283.941944] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  283.960085] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  283.960220] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  283.960272] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  283.960328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  283.960370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  283.960415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  283.960456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  283.960496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  283.960536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  283.960580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  283.960623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  283.960665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  283.960707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  283.960747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  283.960786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  283.960889] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  283.961025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  283.961044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  283.961239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  283.961274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  283.961310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  283.961348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  283.961379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  283.961413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  283.961441] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  283.961463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  283.961484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  283.961504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  283.961522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  283.961528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  283.961546] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  283.961550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  283.961576] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  283.961601] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  283.961628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  283.961653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  283.961680] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  283.961705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  283.961731] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  283.961757] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  283.961783] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  283.961809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  283.961838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  283.965237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  283.965258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  283.965277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  283.965294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  283.965311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  283.965330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  283.965350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  283.965369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  283.965387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  283.965404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  283.965420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  283.965441] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  283.965460] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  283.967570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  283.967591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  283.967609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  283.967627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  283.969218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  283.969241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  283.969262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  283.970825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  283.970847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  283.972714] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  283.976025] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  283.976178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  283.976237] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  283.976318] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  283.992877] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  283.992927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  283.992993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  284.009540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  284.015289] [drm:drm_mode_addfb2] [FB:78]
>[  284.665325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  284.665527] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  284.665613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  284.665746] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  284.677808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  284.677846] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  284.677888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  284.677922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  284.677957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  284.677989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  284.678019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  284.678134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  284.678198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  284.678253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  284.678304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  284.678354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  284.678402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  284.678449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  284.678545] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  284.679286] [IGT] kms_busy: exiting, ret=0
>[  284.701890] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  284.701931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  284.701973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  284.702017] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  284.702076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  284.702113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  284.702151] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  284.702185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  284.702218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  284.702250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  284.702280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  284.702287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  284.702316] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  284.702321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  284.702351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  284.702380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  284.702409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  284.702437] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  284.702471] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  284.702500] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  284.702535] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  284.702552] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  284.702568] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  284.702593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  284.702620] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  284.702696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  284.702720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  284.702744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  284.702768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  284.702791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  284.702815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  284.702841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  284.702867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  284.702892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  284.702915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  284.702938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  284.702964] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  284.702987] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  284.705329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  284.705349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  284.705366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  284.705384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  284.706959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  284.706977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  284.706993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  284.708588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  284.708607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  284.710483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  284.713527] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  284.713581] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  284.713613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  284.713656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  284.713746] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  284.713771] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  284.730398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  284.730447] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  284.730517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  284.730758] Console: switching to colour frame buffer device 240x75
>[  284.801778] Console: switching to colour dummy device 80x25
>[  284.801938] [IGT] kms_busy: executing
>[  284.844068] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  284.844095] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  284.846200] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  284.846238] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  284.848332] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  284.848342] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  284.850438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  284.850472] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  284.852590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  284.852602] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  284.852611] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  284.853233] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  284.853275] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  284.854336] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  284.855259] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  284.855282] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  284.855301] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  284.855319] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  284.856340] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  284.856360] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  284.857480] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  284.857483] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  284.857587] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  284.857590] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  284.857595] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  284.857597] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  284.857602] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  284.857604] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  284.857614] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  284.857617] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  284.857620] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  284.857623] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  284.857626] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  284.857629] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  284.857632] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  284.857635] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  284.857638] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  284.857641] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  284.857644] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  284.857647] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  284.857650] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  284.857653] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  284.857656] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  284.857658] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  284.857661] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  284.857664] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  284.857667] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  284.857670] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  284.857673] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  284.857676] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  284.857679] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  284.857682] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  284.857685] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  284.857688] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  284.857691] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  284.857694] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  284.857697] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  284.857700] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  284.857703] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  284.857983] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  284.858006] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  284.860124] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  284.860164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  284.862124] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  284.862135] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  284.864255] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  284.864294] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  284.866391] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  284.866401] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  284.866409] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  284.867443] [IGT] kms_busy: starting subtest basic-flip-default-C
>[  284.872895] [drm:drm_mode_addfb2] [FB:58]
>[  284.908511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  284.908569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  284.913863] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  284.913914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  284.913988] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  284.931039] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  284.931117] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  284.931150] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  284.931189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  284.931223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  284.931259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  284.931290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  284.931319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  284.931351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  284.931387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  284.931419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  284.931459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  284.931501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  284.931541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  284.931580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  284.931654] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  284.931817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  284.932005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  284.932086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  284.932219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  284.932254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  284.932289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  284.932326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  284.932357] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  284.932391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  284.932425] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  284.932457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  284.932489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  284.932518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  284.932548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  284.932555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  284.932583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  284.932591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  284.932620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  284.932649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  284.932678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  284.932707] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  284.932739] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  284.932768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  284.932797] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  284.932826] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  284.932852] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  284.932884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  284.932918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  284.936210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  284.936231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  284.936250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  284.936267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  284.936284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  284.936302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  284.936322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  284.936340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  284.936358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  284.936375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  284.936391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  284.936412] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  284.936430] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  284.938481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  284.938502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  284.938520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  284.938539] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  284.940136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  284.940156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  284.940173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  284.941732] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  284.941753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  284.943626] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  284.946921] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  284.947009] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  284.947120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  284.947170] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  284.963790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  284.963841] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  284.963909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  284.986167] [drm:drm_mode_addfb2] [FB:78]
>[  285.636122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  285.636226] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  285.636271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  285.636358] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  285.649275] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  285.649313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  285.649354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  285.649389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  285.649423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  285.649453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  285.649483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  285.649515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  285.649551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  285.649583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  285.649622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  285.649651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  285.649677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  285.649703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  285.649762] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  285.650778] [IGT] kms_busy: exiting, ret=0
>[  285.672822] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  285.672863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  285.672905] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  285.672948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  285.672982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  285.673055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  285.673090] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  285.673122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  285.673153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  285.673183] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  285.673220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  285.673228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  285.673265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  285.673270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  285.673308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  285.673346] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  285.673384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  285.673422] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  285.673460] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  285.673497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  285.673535] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  285.673572] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  285.673609] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  285.673648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  285.673690] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  285.673806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  285.673844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  285.673882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  285.673920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  285.673957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  285.673994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  285.674051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  285.674100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  285.674122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  285.674141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  285.674159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  285.674181] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  285.674200] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  285.676266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  285.676285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  285.676302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  285.676321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  285.677879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  285.677902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  285.677926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  285.679481] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  285.679501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  285.681404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  285.684402] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  285.684435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  285.684454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  285.684480] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  285.684544] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  285.684563] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  285.701279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  285.701327] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  285.701396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  285.701636] Console: switching to colour frame buffer device 240x75
>[  285.774850] Console: switching to colour dummy device 80x25
>[  285.775108] [IGT] kms_cursor_legacy: executing
>[  285.801893] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  285.801922] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  285.804054] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  285.804090] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  285.806204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  285.806216] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  285.808333] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  285.808372] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  285.810486] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  285.810497] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  285.810505] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  285.811159] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  285.811202] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  285.812297] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  285.813220] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  285.813242] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  285.813261] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  285.813280] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  285.814301] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  285.814322] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  285.815446] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  285.815450] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  285.815548] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  285.815551] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  285.815556] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  285.815558] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  285.815563] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  285.815565] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  285.815574] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  285.815578] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  285.815581] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  285.815584] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  285.815587] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  285.815590] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  285.815592] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  285.815595] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  285.815598] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  285.815601] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  285.815604] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  285.815607] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  285.815610] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  285.815613] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  285.815616] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  285.815619] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  285.815622] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  285.815625] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  285.815627] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  285.815630] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  285.815633] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  285.815636] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  285.815639] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  285.815642] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  285.815645] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  285.815648] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  285.815651] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  285.815654] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  285.815656] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  285.815659] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  285.815662] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  285.815943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  285.815966] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  285.818097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  285.818133] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  285.820230] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  285.820240] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  285.822356] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  285.822395] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  285.824509] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  285.824519] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  285.824527] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  285.825309] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-atomic
>[  285.825883] [drm:drm_mode_addfb2] [FB:76]
>[  285.865287] [drm:drm_mode_addfb2] [FB:79]
>[  285.937007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  285.951452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  285.951500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  285.951587] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  285.968606] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  285.968650] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  285.968684] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  285.968723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  285.968757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  285.968792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  285.968823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  285.968853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  285.968884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  285.968919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  285.968951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  285.968983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  285.969094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  285.969135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  285.969178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  285.969273] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  285.969543] [IGT] kms_cursor_legacy: exiting, ret=0
>[  285.987811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  285.987849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  285.987888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  285.987928] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  285.987960] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  285.987995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  285.988058] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  285.988099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  285.988139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  285.988179] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  285.988218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  285.988225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  285.988264] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  285.988270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  285.988310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  285.988349] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  285.988389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  285.988429] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  285.988469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  285.988507] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  285.988547] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  285.988586] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  285.988626] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  285.988667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  285.988711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  285.988834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  285.988855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  285.988875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  285.988896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  285.988920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  285.988943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  285.988980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  285.989016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  285.989047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  285.989065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  285.989082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  285.989104] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  285.989124] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  285.991189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  285.991208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  285.991225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  285.991244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  285.992821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  285.992838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  285.992854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  285.994423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  285.994441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  285.996322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  285.999364] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  285.999399] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  285.999421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  285.999453] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  285.999519] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  285.999539] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  286.016239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  286.016286] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  286.016355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.016591] Console: switching to colour frame buffer device 240x75
>[  286.097431] Console: switching to colour dummy device 80x25
>[  286.097601] [IGT] kms_cursor_legacy: executing
>[  286.121805] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  286.121838] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  286.123067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  286.123096] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  286.125067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  286.125079] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  286.127097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  286.127134] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  286.129071] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  286.129082] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  286.129090] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  286.129607] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  286.129651] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  286.130752] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  286.131673] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  286.131697] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  286.131720] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  286.131743] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  286.132771] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  286.132792] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  286.133904] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  286.133908] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  286.134095] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  286.134100] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  286.134109] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  286.134113] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  286.134120] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  286.134122] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  286.134131] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  286.134134] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.134137] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.134140] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.134143] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  286.134146] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  286.134149] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  286.134152] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  286.134155] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.134158] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.134161] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  286.134164] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  286.134167] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  286.134170] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  286.134173] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  286.134176] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  286.134179] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  286.134182] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.134185] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.134187] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  286.134190] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  286.134193] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  286.134196] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  286.134199] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  286.134202] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  286.134205] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.134208] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.134211] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  286.134214] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.134217] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.134219] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  286.134504] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  286.134528] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  286.136047] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.136072] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.138051] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.138061] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  286.140089] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.140127] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.142070] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.142081] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  286.142088] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  286.142682] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-legacy
>[  286.143325] [drm:drm_mode_addfb2] [FB:58]
>[  286.182723] [drm:drm_mode_addfb2] [FB:79]
>[  286.251578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.266420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  286.266472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  286.266562] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  286.283570] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  286.283613] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  286.283646] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  286.283684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  286.283716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  286.283750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  286.283780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  286.283809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  286.283841] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  286.283875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  286.283907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  286.283938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  286.283968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.284075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  286.284117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  286.284214] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  286.284529] [IGT] kms_cursor_legacy: exiting, ret=0
>[  286.302839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  286.302877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  286.302915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  286.302955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  286.303012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  286.303047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  286.303082] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  286.303114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  286.303146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  286.303176] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  286.303205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  286.303212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.303240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  286.303245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.303273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  286.303302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  286.303330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  286.303357] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  286.303390] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  286.303422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  286.303462] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  286.303502] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  286.303542] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  286.303583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.303627] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  286.303766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  286.303807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  286.303856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  286.303878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  286.303899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  286.303919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  286.303940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  286.303960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  286.303998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.304015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  286.304032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  286.304053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  286.304073] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  286.306136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  286.306155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  286.306172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  286.306191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  286.307766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  286.307783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  286.307800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  286.309361] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  286.309379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  286.311253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  286.314336] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  286.314368] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  286.314386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  286.314412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  286.314474] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  286.314502] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  286.331221] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  286.331268] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  286.331337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.331574] Console: switching to colour frame buffer device 240x75
>[  286.406394] Console: switching to colour dummy device 80x25
>[  286.406514] [IGT] kms_cursor_legacy: executing
>[  286.435548] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  286.435578] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  286.437707] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  286.437748] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  286.439866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  286.439878] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  286.442024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  286.442064] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  286.444180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  286.444192] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  286.444200] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  286.444727] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  286.444771] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  286.445877] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  286.446802] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  286.446825] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  286.446845] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  286.446864] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  286.447886] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  286.447907] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  286.449043] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  286.449047] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  286.449149] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  286.449151] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  286.449157] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  286.449159] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  286.449164] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  286.449166] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  286.449175] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  286.449179] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.449182] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.449185] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.449188] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  286.449191] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  286.449194] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  286.449197] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  286.449200] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.449203] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.449206] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  286.449208] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  286.449211] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  286.449214] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  286.449217] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  286.449220] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  286.449223] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  286.449226] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.449229] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.449232] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  286.449235] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  286.449238] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  286.449241] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  286.449244] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  286.449247] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  286.449250] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.449253] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.449256] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  286.449258] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.449261] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.449264] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  286.449551] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  286.449575] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  286.451024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.451049] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.453057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.453068] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  286.455057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.455097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.457054] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.457064] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  286.457072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  286.457694] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-atomic
>[  286.458435] [drm:drm_mode_addfb2] [FB:76]
>[  286.497929] [drm:drm_mode_addfb2] [FB:79]
>[  286.566909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.581402] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  286.581454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  286.581544] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  286.598552] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  286.598595] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  286.598628] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  286.598666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  286.598698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  286.598733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  286.598763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  286.598793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  286.598824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  286.598858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  286.598890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  286.598920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  286.598950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.599055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  286.599098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  286.599194] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  286.599465] [IGT] kms_cursor_legacy: exiting, ret=0
>[  286.617768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  286.617807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  286.617846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  286.617887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  286.617920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  286.617955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  286.618018] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  286.618051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  286.618083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  286.618113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  286.618147] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  286.618155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.618193] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  286.618199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.618239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  286.618279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  286.618318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  286.618357] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  286.618397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  286.618436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  286.618475] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  286.618515] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  286.618554] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  286.618595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.618638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  286.618759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  286.618780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  286.618799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  286.618817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  286.618834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  286.618854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  286.618876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  286.618895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  286.618914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.618931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  286.618962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  286.619010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  286.619030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  286.621097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  286.621116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  286.621133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  286.621151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  286.622728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  286.622745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  286.622761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  286.624330] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  286.624348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  286.626231] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  286.629411] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  286.629461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  286.629490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  286.629531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  286.629606] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  286.629635] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  286.646258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  286.646305] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  286.646379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.646661] Console: switching to colour frame buffer device 240x75
>[  286.720848] Console: switching to colour dummy device 80x25
>[  286.721022] [IGT] kms_cursor_legacy: executing
>[  286.758883] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  286.758911] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  286.761035] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  286.761074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  286.763191] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  286.763202] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  286.765305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  286.765341] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  286.767440] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  286.767451] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  286.767459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  286.768051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  286.768107] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  286.769212] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  286.770143] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  286.770164] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  286.770183] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  286.770200] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  286.771220] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  286.771240] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  286.772359] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  286.772363] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  286.772464] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  286.772467] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  286.772472] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  286.772474] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  286.772479] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  286.772482] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  286.772491] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  286.772494] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.772497] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.772500] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.772503] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  286.772506] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  286.772509] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  286.772512] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  286.772515] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.772518] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.772521] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  286.772524] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  286.772526] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  286.772529] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  286.772532] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  286.772535] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  286.772538] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  286.772541] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.772544] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.772547] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  286.772550] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  286.772553] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  286.772556] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  286.772559] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  286.772562] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  286.772565] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.772568] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.772570] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  286.772573] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.772576] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.772579] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  286.772877] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  286.772900] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  286.775024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.775062] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.777045] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.777055] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  286.779043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.779082] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.781042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.781053] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  286.781060] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  286.781644] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-legacy
>[  286.782304] [drm:drm_mode_addfb2] [FB:58]
>[  286.822015] [drm:drm_mode_addfb2] [FB:79]
>[  286.881909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.896432] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  286.896482] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  286.896571] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  286.913583] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  286.913627] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  286.913661] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  286.913700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  286.913734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  286.913770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  286.913801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  286.913830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  286.913862] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  286.913896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  286.913928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  286.914040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  286.914082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.914109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  286.914137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  286.914202] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  286.914476] [IGT] kms_cursor_legacy: exiting, ret=0
>[  286.932752] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  286.932796] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  286.932840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  286.932888] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  286.932928] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  286.933014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  286.933056] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  286.933096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  286.933137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  286.933176] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  286.933215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  286.933223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.933261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  286.933267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  286.933308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  286.933348] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  286.933387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  286.933427] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  286.933473] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  286.933506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  286.933535] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  286.933562] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  286.933588] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  286.933618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.933650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  286.933764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  286.933791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  286.933817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  286.933842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  286.933866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  286.933892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  286.933922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  286.933967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  286.933995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.934019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  286.934043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  286.934073] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  286.934100] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  286.936172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  286.936191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  286.936213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  286.936236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  286.937807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  286.937827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  286.937845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  286.939396] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  286.939415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  286.941293] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  286.944447] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  286.944498] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  286.944535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  286.944587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  286.944681] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  286.944710] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  286.961318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  286.961368] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  286.961444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  286.961743] Console: switching to colour frame buffer device 240x75
>[  287.034757] Console: switching to colour dummy device 80x25
>[  287.034972] [IGT] kms_cursor_legacy: executing
>[  287.058979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  287.059006] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  287.061131] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  287.061174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  287.063273] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  287.063285] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  287.065382] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  287.065417] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  287.067531] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  287.067543] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  287.067551] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  287.068171] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  287.068214] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  287.069306] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  287.070231] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  287.070253] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  287.070272] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  287.070291] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  287.071312] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  287.071332] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  287.072445] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  287.072448] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  287.072550] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  287.072553] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  287.072558] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  287.072560] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  287.072565] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  287.072568] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  287.072577] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  287.072580] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.072583] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.072586] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.072589] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  287.072592] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  287.072595] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  287.072598] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  287.072601] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.072604] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.072607] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  287.072610] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  287.072613] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  287.072616] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  287.072619] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  287.072621] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  287.072624] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  287.072627] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  287.072630] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  287.072633] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  287.072636] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  287.072639] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  287.072642] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  287.072645] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  287.072648] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  287.072651] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  287.072654] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  287.072657] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  287.072660] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  287.072663] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  287.072666] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  287.073035] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  287.073069] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  287.075004] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  287.075028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  287.077030] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  287.077040] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  287.079029] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  287.079067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  287.081031] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  287.081043] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  287.081050] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  287.081649] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-varying-size
>[  287.082401] [drm:drm_mode_addfb2] [FB:76]
>[  287.121764] [drm:drm_mode_addfb2] [FB:79]
>[  287.121893] [drm:drm_mode_addfb2] [FB:80]
>[  287.180330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  287.194814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  287.194865] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  287.194953] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  287.212023] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  287.212067] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  287.212101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  287.212141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  287.212175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  287.212210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  287.212241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  287.212271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  287.212302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  287.212337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  287.212370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  287.212401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  287.212431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.212478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  287.212496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  287.212535] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  287.212741] [IGT] kms_cursor_legacy: exiting, ret=0
>[  287.234780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  287.234822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  287.234863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  287.234909] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  287.234949] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  287.235034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  287.235075] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  287.235114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  287.235155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  287.235194] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  287.235233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  287.235240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.235279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  287.235285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.235325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  287.235366] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  287.235405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  287.235444] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  287.235485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  287.235524] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  287.235563] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  287.235603] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  287.235642] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  287.235684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  287.235727] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  287.235849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  287.235889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  287.235942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  287.235979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  287.236009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  287.236029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  287.236052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  287.236073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  287.236092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.236110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  287.236127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  287.236149] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  287.236169] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  287.238235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  287.238254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  287.238271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  287.238289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  287.239869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  287.239887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  287.239903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  287.241480] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  287.241498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  287.243391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  287.246922] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  287.246998] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  287.247030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  287.247073] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  287.247161] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  287.247187] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  287.263820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  287.263868] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  287.263937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.264209] Console: switching to colour frame buffer device 240x75
>[  287.337744] Console: switching to colour dummy device 80x25
>[  287.337896] [IGT] kms_cursor_legacy: executing
>[  287.375996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  287.376029] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  287.378157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  287.378199] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  287.380320] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  287.380332] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  287.382452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  287.382491] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  287.384608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  287.384619] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  287.384627] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  287.385240] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  287.385281] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  287.386349] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  287.387273] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  287.387294] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  287.387313] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  287.387330] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  287.388352] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  287.388372] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  287.389495] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  287.389499] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  287.389599] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  287.389601] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  287.389606] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  287.389609] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  287.389613] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  287.389616] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  287.389625] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  287.389628] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.389631] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.389634] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.389637] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  287.389640] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  287.389643] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  287.389646] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  287.389649] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.389652] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.389655] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  287.389658] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  287.389661] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  287.389664] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  287.389667] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  287.389670] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  287.389673] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  287.389676] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  287.389679] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  287.389682] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  287.389684] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  287.389687] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  287.389690] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  287.389693] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  287.389696] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  287.389699] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  287.389702] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  287.389705] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  287.389708] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  287.389711] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  287.389714] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  287.390124] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  287.390149] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  287.392014] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  287.392050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  287.394016] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  287.394027] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  287.396015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  287.396054] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  287.398015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  287.398025] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  287.398033] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  287.398627] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-atomic
>[  287.399322] [drm:drm_mode_addfb2] [FB:58]
>[  287.438838] [drm:drm_mode_addfb2] [FB:79]
>[  287.499369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  287.513995] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  287.514048] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  287.514135] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  287.531150] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  287.531195] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  287.531228] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  287.531267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  287.531301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  287.531337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  287.531368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  287.531407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  287.531447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  287.531491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  287.531533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  287.531575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  287.531616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.531655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  287.531692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  287.531764] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  287.532187] [IGT] kms_cursor_legacy: exiting, ret=0
>[  287.553711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  287.553755] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  287.553800] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  287.553847] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  287.553888] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  287.553931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  287.553998] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  287.554039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  287.554081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  287.554121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  287.554161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  287.554168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.554208] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  287.554214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.554254] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  287.554295] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  287.554335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  287.554375] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  287.554415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  287.554455] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  287.554495] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  287.554535] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  287.554575] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  287.554617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  287.554660] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  287.554789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  287.554819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  287.554845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  287.554871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  287.554895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  287.554921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  287.554966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  287.554993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  287.555019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.555043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  287.555066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  287.555095] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  287.555120] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  287.557194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  287.557213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  287.557230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  287.557248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  287.558821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  287.558838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  287.558855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  287.560441] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  287.560460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  287.562357] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  287.565867] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  287.565920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  287.565975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  287.566024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  287.566110] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  287.566149] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  287.582730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  287.582778] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  287.582847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.583122] Console: switching to colour frame buffer device 240x75
>[  287.659156] Console: switching to colour dummy device 80x25
>[  287.659330] [IGT] kms_cursor_legacy: executing
>[  287.685752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  287.685785] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  287.686999] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  287.687033] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  287.689016] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  287.689029] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  287.691131] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  287.691166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  287.693259] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  287.693269] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  287.693276] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  287.693782] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  287.693821] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  287.694904] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  287.695826] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  287.695855] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  287.695874] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  287.695891] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  287.696987] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  287.697008] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  287.698159] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  287.698163] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  287.698264] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  287.698267] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  287.698272] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  287.698274] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  287.698279] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  287.698282] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  287.698291] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  287.698294] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.698297] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.698300] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.698303] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  287.698306] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  287.698309] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  287.698312] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  287.698315] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.698318] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  287.698321] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  287.698324] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  287.698327] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  287.698330] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  287.698333] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  287.698336] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  287.698339] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  287.698342] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  287.698345] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  287.698347] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  287.698350] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  287.698353] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  287.698356] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  287.698359] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  287.698362] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  287.698365] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  287.698368] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  287.698371] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  287.698374] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  287.698377] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  287.698379] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  287.698663] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  287.698686] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  287.700789] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  287.700830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  287.702005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  287.702016] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  287.704002] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  287.704041] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  287.706030] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  287.706040] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  287.706048] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  287.706634] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-legacy
>[  287.707431] [drm:drm_mode_addfb2] [FB:76]
>[  287.746929] [drm:drm_mode_addfb2] [FB:79]
>[  287.818417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  287.832913] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  287.832996] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  287.833083] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  287.850070] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  287.850115] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  287.850149] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  287.850188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  287.850222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  287.850257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  287.850289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  287.850319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  287.850350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  287.850385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  287.850425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  287.850453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  287.850480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.850504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  287.850529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  287.850584] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  287.850862] [IGT] kms_cursor_legacy: exiting, ret=0
>[  287.872732] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  287.872773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  287.872815] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  287.872857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  287.872892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  287.872973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  287.873014] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  287.873055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  287.873096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  287.873136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  287.873176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  287.873184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.873223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  287.873229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  287.873270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  287.873310] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  287.873350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  287.873389] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  287.873430] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  287.873469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  287.873508] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  287.873548] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  287.873587] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  287.873629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  287.873672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  287.873815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  287.873856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  287.873909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  287.873955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  287.873975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  287.873995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  287.874018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  287.874037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  287.874056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.874073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  287.874093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  287.874118] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  287.874142] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  287.876208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  287.876228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  287.876245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  287.876264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  287.877831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  287.877849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  287.877865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  287.879454] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  287.879476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  287.881363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  287.884906] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  287.884982] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  287.885013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  287.885056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  287.885144] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  287.885169] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  287.901793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  287.901841] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  287.901910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  287.902191] Console: switching to colour frame buffer device 240x75
>[  287.976616] Console: switching to colour dummy device 80x25
>[  287.976785] [IGT] kms_cursor_legacy: executing
>[  288.001625] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  288.001657] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  288.003760] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  288.003797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  288.005926] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  288.005958] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  288.008012] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  288.008050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  288.010164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  288.010176] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  288.010184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  288.010704] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  288.010750] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  288.011835] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  288.012757] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  288.012780] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  288.012804] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  288.012828] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  288.013850] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  288.013872] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  288.015083] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  288.015087] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  288.015192] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  288.015194] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  288.015200] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  288.015202] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  288.015207] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  288.015209] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  288.015219] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  288.015222] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.015225] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.015228] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.015231] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  288.015234] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  288.015237] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  288.015240] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  288.015243] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.015246] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.015249] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  288.015252] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  288.015255] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  288.015258] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  288.015261] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  288.015264] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  288.015267] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  288.015270] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  288.015273] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  288.015275] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  288.015278] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  288.015281] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  288.015284] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  288.015287] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  288.015290] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  288.015293] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  288.015296] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  288.015299] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  288.015302] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  288.015305] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  288.015308] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  288.015592] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  288.015615] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  288.016973] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  288.017000] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  288.018993] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  288.019004] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  288.020999] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  288.021036] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  288.022989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  288.023000] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  288.023007] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  288.023608] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-varying-size
>[  288.024272] [drm:drm_mode_addfb2] [FB:58]
>[  288.063682] [drm:drm_mode_addfb2] [FB:79]
>[  288.063814] [drm:drm_mode_addfb2] [FB:80]
>[  288.137502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.151971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.152023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.152110] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.169126] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.169171] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.169204] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.169243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.169278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.169313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.169343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.169373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.169406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.169441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.169474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.169514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.169556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.169595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.169633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.169705] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.170162] [IGT] kms_cursor_legacy: exiting, ret=0
>[  288.191822] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.191863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.191904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.191973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.192007] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.192044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.192080] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.192114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.192147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.192178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.192208] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.192216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.192245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.192250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.192280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.192309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.192344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.192384] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.192425] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.192464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.192505] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  288.192544] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.192584] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.192626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.192669] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.192799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.192832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.192864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.192896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.192944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.192976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.193011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.193045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.193078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.193110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.193141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.193175] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.193206] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.195283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.195303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.195320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.195339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.196940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.196959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.196976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.198538] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.198556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.200442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.203943] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.204002] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.204028] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.204065] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.204149] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.204188] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.220813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.220861] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.220967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.221206] Console: switching to colour frame buffer device 240x75
>[  288.295850] Console: switching to colour dummy device 80x25
>[  288.296078] [IGT] kms_flip: executing
>[  288.309808] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  288.309855] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  288.312005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  288.312043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  288.314160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  288.314173] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  288.316293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  288.316337] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  288.318452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  288.318464] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  288.318473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  288.318505] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  288.318548] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  288.319664] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  288.320617] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  288.320640] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  288.320660] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  288.320679] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  288.321696] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  288.321716] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  288.322828] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  288.322832] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  288.323006] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  288.323009] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  288.323015] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  288.323017] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  288.323023] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  288.323025] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  288.323035] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  288.323039] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.323042] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.323045] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.323048] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  288.323052] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  288.323055] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  288.323058] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  288.323061] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.323064] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  288.323067] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  288.323071] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  288.323083] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  288.323085] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  288.323088] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  288.323091] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  288.323094] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  288.323097] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  288.323100] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  288.323103] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  288.323106] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  288.323109] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  288.323112] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  288.323115] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  288.323118] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  288.323120] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  288.323123] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  288.323126] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  288.323129] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  288.323132] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  288.323135] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  288.323174] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  288.323197] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  288.324973] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  288.325010] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  288.326981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  288.326992] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  288.328991] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  288.329028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  288.330987] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  288.330998] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  288.331005] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  288.331410] [IGT] kms_flip: starting subtest basic-flip-vs-dpms
>[  288.332284] [drm:drm_mode_addfb2] [FB:76]
>[  288.332330] [drm:drm_mode_addfb2] [FB:79]
>[  288.385210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  288.385271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.387620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.387672] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.387752] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.406616] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.406661] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.406694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.406734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.406768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.406804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.406835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.406865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.406986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.407044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.407097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.407146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.407197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.407238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.407281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.407360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.407467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  288.407609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  288.407667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  288.407678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  288.407730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.407750] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.407772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.407799] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.407822] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.407846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.407869] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.407937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.407974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.408003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.408033] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.408041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.408070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.408078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.408109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.408136] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.408166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.408193] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.408227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.408254] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.408285] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  288.408312] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.408341] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.408372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.408405] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.411982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.412006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.412028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.412048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.412067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.412087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.412110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.412131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.412152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.412171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.412189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.412212] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.412233] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.414304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.414327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.414346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.414366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.415933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.415953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.415972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.417536] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.417559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.419432] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.422735] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.422781] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.422812] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.422854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.423052] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.423095] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.439607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.439659] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.439730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.473208] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.473248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.473288] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.473329] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.473362] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.473398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.473435] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.473468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.473501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.473532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.473563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.473570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.473600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.473606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.473636] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.473666] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.473696] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.473725] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.473760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.473795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.473838] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.473879] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.473997] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.474049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.474100] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.506318] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.506365] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.506438] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.524862] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.524940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.524972] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.525011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.525043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.525074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.525112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.525152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.525192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.525234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.525276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.525318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.525356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.525395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.525460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.525505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.525553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.526013] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.526063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.526119] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.526164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.526193] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.526226] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.526253] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.526274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.526294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.526318] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.526344] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.526350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.526375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.526380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.526406] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.526431] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.526457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.526483] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.526508] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.526534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.526561] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.526588] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.526613] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.526641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.526670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.526734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.526760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.526784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.526809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.526836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.526861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.526919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.526952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.526985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.527012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.527039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.527073] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.527102] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.529168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.529191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.529214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.529238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.530800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.530821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.530840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.532424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.532445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.534414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.537698] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.537749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.537781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.537823] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.537986] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.538221] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.538323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.538349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.538387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.554801] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.554838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.554875] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.555009] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.555058] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.555112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.555166] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.555215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.555265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.555312] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.555357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.555370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.555414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.555425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.555471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.555517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.555562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.555606] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.555652] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.555705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.555736] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.555765] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.555791] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.555824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.555857] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.587946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.587991] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.588059] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.605086] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.605129] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.605161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.605199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.605231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.605262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.605292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.605331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.605370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.605413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.605455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.605496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.605535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.605573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.605638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.605683] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.605731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.606181] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.606216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.606241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.606267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.606287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.606309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.606331] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.606352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.606373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.606398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.606423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.606429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.606454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.606459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.606485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.606510] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.606537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.606561] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.606588] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.606612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.606640] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.606665] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.606691] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.606718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.606746] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.606821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.606847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.606875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.606930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.606963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.606993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.607026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.607058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.607089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.607116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.607142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.607174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.607204] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.609267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.609288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.609306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.609325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.610910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.610930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.610948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.612511] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.612532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.614413] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.617727] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.617779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.617817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.617868] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.618251] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.618272] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.618328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.618357] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.618399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.634824] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.634866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.634987] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.635046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.635092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.635144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.635191] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.635239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.635283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.635328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.635369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.635381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.635422] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.635433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.635478] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.635518] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.635559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.635586] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.635617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.635642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.635673] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.635699] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.635726] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.635755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.635787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.667949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.667993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.668062] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.685076] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.685119] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.685151] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.685189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.685222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.685253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.685282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.685311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.685342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.685383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.685426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.685467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.685506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.685544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.685609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.685655] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.685698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.686230] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.686262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.686297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.686333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.686361] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.686393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.686422] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.686452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.686480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.686509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.686535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.686543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.686570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.686576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.686606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.686632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.686661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.686687] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.686718] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.686744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.686773] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.686799] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.686827] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.686856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.686914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.687210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.687237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.687265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.687290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.687316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.687342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.687372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.687402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.687431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.687455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.687481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.687512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.687538] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.689624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.689646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.689665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.689684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.691265] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.691285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.691302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.692876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.692915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.694814] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.698065] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.698098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.698122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.698153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.698216] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.698238] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.698291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.698317] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.698364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.715163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.715204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.715243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.715285] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.715317] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.715353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.715389] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.715423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.715456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.715487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.715517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.715524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.715554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.715561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.715592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.715621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.715651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.715680] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.715715] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.715744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.715775] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.715804] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.715833] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.715867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.715989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.748272] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.748323] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.748396] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.765423] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.765467] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.765500] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.765539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.765572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.765604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.765635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.765664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.765695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.765729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.765760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.765791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.765819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.765847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.765996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.766055] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.766095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.766449] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.766471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.766495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.766520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.766539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.766561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.766582] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.766603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.766622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.766641] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.766659] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.766665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.766682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.766686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.766705] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.766723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.766742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.766759] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.766781] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.766805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.766833] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.766858] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.766910] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.766942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.766975] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.767078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.767103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.767122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.767142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.767160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.767181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.767203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.767223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.767242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.767261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.767278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.767301] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.767325] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.769366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.769387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.769406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.769425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.770995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.771014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.771032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.772584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.772604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.774477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.777782] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.777824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.777850] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.777956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.778203] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.778236] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.778306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.778344] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.778400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.794933] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.794977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.795020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.795066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.795107] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.795149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.795190] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.795230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.795267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.795308] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.795348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.795355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.795395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.795402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.795443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.795484] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.795524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.795565] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.795604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.795644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.795686] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.795727] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.795768] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.795810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.795853] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.828071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.828164] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.828306] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.845341] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.845388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.845422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.845461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.845494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.845525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.845555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.845584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.845615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.845649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.845680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.845711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.845749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.845788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.845856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.845994] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.846059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.846302] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.846323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.846346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.846372] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.846391] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.846412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.846434] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.846454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.846473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.846492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.846510] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.846515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.846533] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.846537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.846556] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.846573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.846592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.846609] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.846631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.846649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.846668] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.846686] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.846704] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.846725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.846748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.846816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.846836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.846859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.846912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.846941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.846970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.847001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.847032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.847062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.847088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.847114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.847145] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.847175] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.849236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.849256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.849274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.849292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.850853] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.850888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.850906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.852468] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.852489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.854361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.857671] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.857721] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.857752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.857793] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.857870] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.858192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.858287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.858313] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.858351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.874782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.874822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.874861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.874992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.875041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.875098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.875150] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.875200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.875249] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.875295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.875336] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.875348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.875392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.875402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.875449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.875495] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.875540] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.875585] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.875636] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.875663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.875694] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.875723] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.875753] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.875783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.875817] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.907872] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.907951] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.908021] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  288.925031] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  288.925074] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  288.925107] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  288.925145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.925178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.925210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.925240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.925269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.925307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.925351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.925392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.925434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.925473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.925512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.925577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.925622] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.925669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.926466] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.926511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.926558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.926607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.926648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.926692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.926735] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.926775] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.926823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.926850] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.926915] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.926928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.926958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.926967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.926997] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.927028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.927059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.927089] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.927123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.927153] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.927185] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.927211] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.927477] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.927508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.927530] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.927594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  288.927613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  288.927631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  288.927648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  288.927664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  288.927682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  288.927702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  288.927720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  288.927739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.927755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  288.927771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  288.927791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  288.927810] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  288.929914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  288.929935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  288.929954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.929973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  288.931554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  288.931578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  288.931600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  288.933173] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  288.933195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  288.935076] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  288.938375] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  288.938424] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  288.938459] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  288.938505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  288.938595] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  288.938641] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  288.938743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  288.938799] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  288.938862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  288.955509] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  288.955548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  288.955588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  288.955629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  288.955661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  288.955697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  288.955734] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  288.955768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  288.955800] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  288.955835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  288.955875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  288.955951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.955999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  288.956011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  288.956062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  288.956106] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  288.956152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.956194] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  288.956246] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  288.956287] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  288.956335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  288.956376] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  288.956423] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  288.956475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  288.956519] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  288.988600] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  288.988647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  288.988734] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.005730] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.005773] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.005813] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.005857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.005973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.006021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.006071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.006115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.006165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.006219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.006271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.006322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.006368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.006412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.006496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.006553] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.006609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.007003] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.007034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.007055] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.007079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.007096] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.007119] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.007143] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.007166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.007188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.007211] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.007233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.007238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.007261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.007265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.007288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.007312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.007335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.007358] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.007380] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.007403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.007427] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.007450] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.007473] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.007498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.007523] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.007591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.007615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.007638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.007661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.007685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.007708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.007733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.007758] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.007782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.007805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.007828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.007852] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.007921] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.009997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.010018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.010037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.010056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.011629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.011649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.011667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.013234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.013255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.015135] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.018455] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.018508] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.018541] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.018583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.018677] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.018727] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.018839] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.018980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.019041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.035544] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.035584] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.035623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.035665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.035698] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.035735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.035777] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.035819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.035857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.035980] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.036028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.036043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.036093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.036106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.036155] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.036203] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.036251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.036298] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.036354] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.036383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.036416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.036445] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.036475] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.036508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.036542] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.068644] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.068691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.068761] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.085791] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.085833] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.085951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.086011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.086063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.086113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.086161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.086198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.086230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.086266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.086299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.086330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.086358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.086386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.086445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.086491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.086548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.086788] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.086808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.086829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.086852] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.086923] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.086953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.086984] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.087013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.087042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.087069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.087096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.087105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.087131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.087139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.087166] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.087193] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.087219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.087245] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.087276] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.087302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.087331] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.087359] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.087388] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.087419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.087454] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.087560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.087591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.087621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.087651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.087680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.087711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.087741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.087762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.087782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.087800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.087818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.087840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.087891] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.089954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.089975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.089994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.090013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.091586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.091606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.091624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.093186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.093207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.095076] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.098397] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.098451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.098491] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.098542] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.098623] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.098663] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.098749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.098803] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.098860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.115478] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.115519] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.115558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.115600] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.115633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.115669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.115704] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.115738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.115771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.115802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.115832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.115907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.115952] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.115962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.116006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.116049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.116090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.116146] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.116178] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.116205] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.116236] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.116265] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.116294] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.116327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.116361] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.148583] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.148630] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.148701] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.165740] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.165782] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.165815] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.165853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.165967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.166009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.166041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.166070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.166102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.166137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.166170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.166200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.166229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.166257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.166311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.166355] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.166378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.166606] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.166633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.166660] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.166689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.166715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.166741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.166767] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.166789] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.166815] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.166842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.166897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.166907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.166936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.166944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.166974] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.167002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.167029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.167057] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.167088] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.167115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.167143] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.167169] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.167196] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.167227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.167260] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.167534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.167557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.167577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.167596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.167615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.167634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.167655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.167675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.167695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.167713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.167736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.167763] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.167789] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.169826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.169847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.169925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.169958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.171527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.171547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.171565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.173118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.173139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.175000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.178331] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.178383] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.178415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.178457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.178533] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.178564] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.178616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.178642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.178689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.195422] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.195462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.195502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.195544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.195576] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.195612] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.195649] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.195683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.195715] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.195746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.195776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.195784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.195814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.195821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.195851] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.195953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.195996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.196037] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.196084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.196126] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.196171] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.196213] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.196253] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.196302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.196355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.228510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.228558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.228628] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.246650] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.246694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.246726] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.246764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.246797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.246827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.246935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.246979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.247030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.247243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.247274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.247302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.247330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.247363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.247421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.247463] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.247506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.247844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.247931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.247980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.248029] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.248069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.248121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.248270] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.248289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.248307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.248325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.248341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.248346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.248362] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.248366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.248383] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.248400] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.248416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.248432] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.248452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.248468] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.248486] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.248502] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.248518] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.248537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.248558] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.248621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.248639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.248656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.248672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.248688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.248705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.248724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.248742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.248759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.248775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.248790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.248811] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.248829] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.250933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.250954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.250972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.250991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.252562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.252583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.252605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.254178] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.254208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.256088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.259363] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.259396] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.259415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.259440] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.259500] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.259521] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.259573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.259600] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.259647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.276420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.276461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.276501] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.276541] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.276574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.276610] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.276650] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.276691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.276730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.276771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.276811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.276818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.276859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.276929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.276982] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.277030] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.277076] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.277119] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.277167] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.277210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.277256] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.277297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.277345] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.277681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.277722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.309546] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.309593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.309665] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.326688] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.326731] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.326764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.326803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.326842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.326959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.327005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.327037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.327069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.327104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.327136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.327167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.327195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.327224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.327277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.327314] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.327349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.327698] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.327730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.327765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.327804] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.327834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.327914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.327970] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.328006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.328041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.328076] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.328110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.328121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.328154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.328163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.328197] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.328230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.328264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.328296] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.328333] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.328365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.328402] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.328434] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.328469] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.328509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.328549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.328650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.328682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.328713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.328746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.328778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.328809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.328848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.328916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.328958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.328996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.329025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.329062] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.329092] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.331133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.331154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.331173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.331192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.332761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.332781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.332799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.334373] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.334394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.336383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.339699] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.339754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.339794] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.339845] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.340029] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.340080] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.340188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.340228] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.340292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.356807] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.356847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.356974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.357032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.357081] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.357128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.357180] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.357229] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.357279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.357326] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.357371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.357384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.357429] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.357440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.357486] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.357533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.357588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.357618] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.357650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.357680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.357711] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.357741] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.357770] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.357802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.357836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.389909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.389955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.390026] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.407054] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.407097] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.407130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.407168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.407200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.407230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.407259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.407287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.407325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.407367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.407409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.407450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.407489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.407528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.407593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.407638] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.407685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.408099] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.408134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.408169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.408206] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.408237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.408270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.408304] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.408335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.408367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.408397] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.408427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.408435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.408464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.408471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.408501] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.408531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.408561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.408590] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.408620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.408649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.408680] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.408709] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.408737] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.408770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.408805] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.408931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.408964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.408996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.409027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.409055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.409087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.409120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.409152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.409184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.409213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.409242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.409274] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.409305] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.411373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.411396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.411419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.411443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.413027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.413049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.413068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.414621] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.414642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.416517] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.419805] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.419931] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.419967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.420011] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.420114] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.420147] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.420229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.420266] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.420307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.436984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.437021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.437059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.437098] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.437128] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.437162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.437196] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.437228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.437258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.437287] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.437314] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.437321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.437348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.437354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.437382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.437409] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.437436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.437462] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.437495] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.437530] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.437556] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.437585] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.437620] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.437657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.437694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.470054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.470112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.470218] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.487225] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.487268] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.487307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.487351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.487391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.487430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.487470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.487509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.487548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.487591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.487632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.487673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.487707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.487726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.487759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.487786] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.487813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.488127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.488154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.488180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.488209] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.488234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.488261] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.488287] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.488313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.488339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.488365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.488390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.488396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.488420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.488425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.488451] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.488477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.488502] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.488524] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.488550] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.488575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.488601] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.488627] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.488653] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.488679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.488707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.488779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.488806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.488831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.488886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.488917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.488948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.488982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.489014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.489044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.489070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.489097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.489129] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.489158] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.491224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.491245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.491267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.491291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.492882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.492903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.492922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.494490] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.494511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.496384] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.499662] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.499711] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.499743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.499784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.499949] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.499983] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.500064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.500105] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.500168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.516805] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.516847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.516964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.517023] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.517068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.517120] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.517168] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.517218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.517262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.517307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.517347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.517368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.517404] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.517412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.517450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.517484] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.517521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.517554] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.517597] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.517631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.517669] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.517703] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.517739] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.517778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.517820] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.549841] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.549919] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.550007] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.567014] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.567062] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.567103] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.567147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.567187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.567226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.567265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.567305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.567343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.567386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.567427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.567469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.567508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.567546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.567605] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.567629] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.567653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.567897] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.567929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.567965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.568003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.568032] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.568066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.568096] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.568127] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.568156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.568185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.568212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.568221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.568250] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.568258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.568286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.568626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.568656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.568685] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.568715] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.568744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.568772] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.568800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.568826] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.568883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.568919] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.569195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.569222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.569250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.569275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.569301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.569326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.569356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.569385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.569413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.569437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.569462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.569493] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.569520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.571598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.571620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.571638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.571656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.573236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.573256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.573275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.574826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.574859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.576727] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.579954] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.579984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.580004] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.580029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.580086] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.580116] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.580190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.580226] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.580264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.597116] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.597154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.597191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.597230] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.597261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.597294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.597327] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.597358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.597388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.597416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.597443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.597450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.597477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.597484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.597512] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.597539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.597566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.597592] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.597624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.597651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.597680] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.597707] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.597733] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.597766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.597800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.630137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.630184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.630271] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.647293] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.647340] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.647380] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.647424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.647464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.647503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.647542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.647581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.647620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.647662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.647704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.647745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.647784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.647823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.647954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.648019] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.648082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.648721] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.648742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.648764] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.648787] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.648805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.648826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.648892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.648927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.648955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.648987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.649014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.649023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.649051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.649059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.649087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.649332] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.649367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.649393] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.649421] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.649448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.649477] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.649502] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.649528] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.649559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.649590] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.649687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.649713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.649739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.649764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.649790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.649815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.649884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.649920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.649953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.649980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.650010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.650045] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.650074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.652338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.652361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.652384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.652408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.654062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.654094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.654121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.655685] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.655707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.657580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.659898] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.659929] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.659949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.659974] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.660033] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.660062] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.660135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.660172] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.660210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.677011] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.677053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.677096] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.677143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.677183] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.677225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.677266] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.677306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.677343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.677383] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.677423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.677431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.677471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.677478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.677519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.677559] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.677600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.677641] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.677680] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.677720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.677762] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.677803] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.677843] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.677938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.678001] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.710078] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.710125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.710212] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.727232] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.727276] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.727308] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.727346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.727379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.727411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.727441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.727471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.727502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.727536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.727568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.727600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.727628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.727655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.727709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.727744] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.727780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.728549] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.728571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.728593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.728616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.728634] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.728653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.728673] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.728692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.728710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.728727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.728743] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.728748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.728764] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.728768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.728784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.728801] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.728817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.728879] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.728915] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.728942] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.728974] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.729001] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.729029] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.729060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.729094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.729436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.729466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.729496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.729523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.729552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.729580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.729614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.729646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.729677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.729703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.729731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.729762] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.729792] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.731881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.731902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.731920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.731939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.733514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.733534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.733552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.735105] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.735126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.737000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.740319] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.740371] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.740404] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.740446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.740526] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.740567] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.740643] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.740671] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.740710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.757402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.757439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.757476] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.757521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.757560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.757601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.757641] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.757680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.757714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.757753] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.757791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.757799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.757837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.757919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.757975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.758023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.758082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.758110] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.758144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.758172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.758207] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.758234] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.758264] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.758294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.758653] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.790508] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.790552] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.790617] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.807661] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.807704] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.807743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.807788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.807828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.807945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.807995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.808047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.808095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.808149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.808200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.808249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.808276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.808304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.808358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.808393] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.808429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.808720] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.808740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.808762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.808788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.808811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.808881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.808917] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.808945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.808978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.809006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.809035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.809044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.809073] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.809081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.809110] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.809137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.809166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.809193] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.809223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.809250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.809280] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.809305] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.809332] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.809362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.809394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.809495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.809523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.809551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.809577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.809605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.809632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.809663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.809694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.809725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.809750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.809778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.809808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.809867] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.811931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.811952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.811970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.811988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.813549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.813569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.813587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.815149] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.815171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.817045] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.820372] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.820425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.820458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.820516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.820582] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.820609] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.820681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.820722] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.820780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.837432] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.837472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.837512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.837553] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.837586] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.837622] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.837658] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.837692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.837725] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.837756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.837786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.837793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.837823] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.837903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.837948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.837990] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.838032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.838072] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.838120] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.838162] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.838213] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.838256] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.838298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.838351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.838390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.870556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.870603] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.870671] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.887695] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.887741] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.887781] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.887826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.887951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.888004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.888054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.888103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.888143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.888183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.888204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.888224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.888243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.888261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.888297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.888320] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.888344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.888568] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.888589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.888611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.888636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.888660] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.888686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.888712] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.888737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.888760] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.888785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.888810] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.888846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.888878] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.888886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.888916] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.888945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.888974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.889001] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.889032] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.889059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.889088] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.889115] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.889141] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.889173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.889205] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.889309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.889340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.889371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.889400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.889431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.889462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.889495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.889529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.889561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.889591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.889614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.889640] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.889667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.891707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.891728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.891747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.891765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.893363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.893383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.893401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.895048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.895069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.896945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.900245] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.900299] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.900347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.900377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.900437] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.900458] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.900510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.900537] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.900584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.917369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.917409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.917449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.917496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.917536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.917579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.917620] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.917660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.917697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.917738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.917778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.917785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.917825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.917897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.917951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.917998] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.918045] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.918088] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.918136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.918179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.918225] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.918269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.918315] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.918673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.918717] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.950454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  289.950506] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  289.950579] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  289.968768] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  289.968813] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  289.968933] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  289.969024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.969075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.969123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.969156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.969185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.969223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.969253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.969280] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.969308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.969332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.969357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.969402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.969433] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.969463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.969750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.969777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.969807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.969895] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.969933] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.969976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.970015] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.970054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.970092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.970128] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.970163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.970175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.970209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.970227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.970254] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.970280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.970310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.970338] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.970368] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.970399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.970430] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.970460] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.970488] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.970522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.970555] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  289.970661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  289.970682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  289.970706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  289.970732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  289.970759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  289.970784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  289.970812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  289.970874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  289.970908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.970935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  289.970963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  289.970996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  289.971024] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  289.973088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  289.973111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  289.973133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.973157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  289.974729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  289.974750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  289.974769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  289.976345] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  289.976366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  289.978365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  289.981604] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  289.981636] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  289.981655] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  289.981681] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  289.981739] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  289.981769] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  289.981898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  289.981939] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  289.981999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  289.998690] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  289.998728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  289.998765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  289.998804] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  289.998918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  289.998966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  289.999020] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  289.999066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  289.999115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  289.999158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  289.999205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  289.999217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.999259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  289.999270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  289.999315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  289.999355] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  289.999399] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  289.999439] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  289.999488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  289.999528] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  289.999573] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  289.999613] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  289.999656] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  289.999701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  289.999751] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.031824] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.031905] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.031978] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.048982] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.049025] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.049058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.049096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.049129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.049159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.049189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.049218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.049249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.049283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.049315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.049346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.049374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.049412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.049477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.049523] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.049570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.050038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.050061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.050085] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.050110] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.050130] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.050152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.050174] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.050194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.050213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.050232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.050250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.050255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.050273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.050277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.050296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.050314] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.050332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.050350] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.050372] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.050389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.050409] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.050426] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.050445] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.050465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.050489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.050546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.050566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.050590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.050616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.050642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.050668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.050696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.050723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.050750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.050775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.050804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.050857] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.050888] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.052954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.052976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.052994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.053013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.054596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.054618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.054636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.056207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.056228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.058098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.061357] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.061389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.061408] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.061434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.061494] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.061515] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.061564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.061590] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.061638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.078461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.078501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.078540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.078582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.078614] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.078650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.078686] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.078720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.078753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.078783] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.078813] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.078895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.078939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.078950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.078994] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.079036] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.079077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.079121] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.079172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.079215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.079263] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.079298] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.079326] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.079361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.079395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.111556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.111603] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.111673] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.128712] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.128755] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.128787] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.128912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.128969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.129022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.129071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.129118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.129167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.129220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.129270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.129321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.129366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.129411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.129496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.129552] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.129611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.129968] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.129990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.130013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.130041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.130074] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.130095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.130114] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.130132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.130150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.130166] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.130182] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.130186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.130202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.130206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.130222] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.130238] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.130254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.130269] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.130289] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.130305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.130322] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.130338] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.130354] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.130373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.130394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.130458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.130476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.130492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.130509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.130525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.130542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.130561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.130579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.130597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.130613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.130629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.130649] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.130668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.132730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.132754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.132777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.132802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.134427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.134448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.134467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.136031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.136052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.137914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.141188] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.141220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.141240] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.141266] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.141327] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.141348] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.141400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.141426] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.141473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.158279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.158319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.158359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.158400] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.158433] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.158468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.158504] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.158539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.158572] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.158603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.158633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.158640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.158674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.158681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.158723] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.158763] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.158804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.158920] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.158974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.159026] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.159081] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.159130] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.159179] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.159234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.159288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.191373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.191419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.191491] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.209760] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.209803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.209925] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.209987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.210038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.210087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.210134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.210181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.210230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.210284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.210335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.210386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.210432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.210478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.210563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.210619] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.210672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.211036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.211058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.211080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.211103] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.211125] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.211149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.211173] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.211196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.211217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.211240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.211263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.211267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.211290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.211294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.211318] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.211341] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.211364] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.211387] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.211409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.211432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.211456] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.211479] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.211502] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.211526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.211551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.211619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.211643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.211667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.211690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.211713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.211736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.211761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.211786] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.211859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.211892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.211925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.211961] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.211995] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.214067] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.214091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.214113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.214137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.215711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.215732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.215750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.217330] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.217351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.219226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.222542] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.222598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.222638] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.222690] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.222772] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.222810] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.223065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.223094] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.223135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.239657] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.239698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.239737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.239778] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.239810] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.239931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.240090] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.240123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.240154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.240184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.240212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.240220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.240248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.240254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.240285] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.240315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.240334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.240351] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.240373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.240391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.240410] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.240435] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.240461] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.240489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.240516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.272737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.272783] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.273056] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.290063] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.290110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.290151] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.290195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.290235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.290274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.290314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.290353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.290392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.290435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.290476] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.290520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.290547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.290572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.290619] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.290650] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.290682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.291253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.291288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.291324] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.291362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.291395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.291430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.291464] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.291508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.291533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.291554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.291574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.291580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.291598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.291603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.291622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.291640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.291659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.291676] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.291698] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.291722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.291749] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.291775] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.291800] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.291856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.291890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.292154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.292176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.292196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.292216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.292235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.292256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.292279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.292299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.292326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.292356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.292375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.292398] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.292418] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.294482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.294504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.294523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.294543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.296119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.296139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.296158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.297716] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.297737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.299612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.302842] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.302873] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.302892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.302917] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.302976] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.302999] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.303053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.303080] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.303126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.319987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.320028] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.320069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.320114] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.320152] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.320193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.320233] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.320272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.320306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.320345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.320384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.320392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.320430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.320437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.320476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.320515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.320554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.320593] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.320631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.320669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.320710] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.320749] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.320789] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.320886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.320940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.353022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.353069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.353138] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.370202] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.370245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.370278] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.370316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.370355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.370396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.370435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.370475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.370514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.370557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.370598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.370639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.370678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.370717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.370781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.370907] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.370970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.371353] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.371380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.371406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.371436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.371460] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.371487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.371513] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.371539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.371562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.371588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.371612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.371619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.371644] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.371649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.371674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.371700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.371726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.371751] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.371777] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.371803] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.371859] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.371891] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.371921] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.371953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.371987] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.372086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.372108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.372127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.372146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.372165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.372185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.372206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.372227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.372247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.372265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.372283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.372306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.372327] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.374395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.374416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.374434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.374453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.376035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.376057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.376076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.377639] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.377662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.379536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.382802] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.382873] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.382903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.382939] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.383006] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.383035] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.383104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.383140] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.383194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.399975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.400013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.400049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.400088] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.400118] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.400152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.400186] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.400217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.400248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.400276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.400304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.400311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.400349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.400356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.400396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.400435] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.400474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.400512] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.400550] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.400588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.400629] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.400668] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.400706] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.400747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.400789] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.433048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.433096] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.433168] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.450200] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.450243] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.450275] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.450313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.450346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.450376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.450406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.450435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.450465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.450499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.450530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.450561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.450589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.450616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.450670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.450705] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.450741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.451228] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.451251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.451277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.451307] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.451332] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.451359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.451385] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.451411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.451436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.451462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.451487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.451493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.451518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.451523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.451548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.451574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.451599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.451625] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.451651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.451676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.451704] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.451729] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.451755] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.451781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.451838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.451944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.451977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.452008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.452039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.452071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.452103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.452138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.452170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.452193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.452211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.452231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.452253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.452275] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.454325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.454347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.454366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.454384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.455954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.455974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.455995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.457554] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.457575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.459446] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.462760] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.462887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.462928] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.462973] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.463068] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.463119] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.463241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.463303] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.463344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.479898] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.479938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.479980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.480026] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.480066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.480108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.480149] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.480190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.480226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.480267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.480307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.480314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.480354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.480361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.480402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.480443] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.480484] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.480524] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.480563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.480602] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.480645] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.480685] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.480727] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.480752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.480777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.512957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.513003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.513089] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.530114] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.530157] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.530189] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.530227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.530260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.530290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.530320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.530348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.530379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.530412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.530443] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.530474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.530502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.530529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.530582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.530617] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.530653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.531197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.531220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.531245] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.531270] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.531291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.531312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.531334] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.531355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.531375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.531393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.531411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.531416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.531434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.531438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.531464] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.531490] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.531515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.531541] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.531566] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.531591] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.531618] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.531643] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.531669] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.531696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.531724] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.531801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.531855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.531887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.531916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.531944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.531973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.532006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.532036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.532067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.532094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.532121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.532154] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.532183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.534453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.534474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.534492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.534512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.536085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.536105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.536127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.537686] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.537707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.539580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.542901] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.542967] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.543000] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.543042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.543141] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.543170] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.543244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.543280] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.543318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.559995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.560036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.560076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.560119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.560160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.560202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.560243] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.560284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.560320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.560360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.560400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.560408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.560448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.560455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.560496] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.560537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.560584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.560620] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.560655] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.560690] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.560728] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.560764] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.560800] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.560887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.560935] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.593107] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.593151] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.593237] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.610246] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.610289] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.610320] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.610358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.610390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.610421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.610451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.610480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.610511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.610544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.610575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.610605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.610632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.610659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.610712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.610747] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.610792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.611246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.611268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.611292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.611316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.611336] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.611359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.611380] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.611401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.611420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.611440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.611458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.611464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.611481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.611485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.611504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.611529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.611554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.611580] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.611605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.611630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.611657] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.611683] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.611709] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.611736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.611764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.611883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.611917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.612119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.612140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.612160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.612181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.612206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.612227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.612249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.612267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.612286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.612309] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.612330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.614406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.614426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.614444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.614463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.616036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.616056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.616074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.617633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.617654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.619528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.622842] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.622893] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.622924] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.622966] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.623041] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.623071] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.623145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.623182] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.623221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.639983] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.640023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.640062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.640103] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.640136] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.640173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.640214] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.640256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.640293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.640334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.640374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.640382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.640422] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.640429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.640471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.640511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.640552] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.640592] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.640631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.640671] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.640713] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.640754] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.640794] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.640892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.640946] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.673039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.673086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.673172] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.690196] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.690238] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.690271] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.690309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.690342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.690373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.690403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.690432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.690463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.690496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.690528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.690560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.690588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.690615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.690670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.690700] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.690730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.691239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.691268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.691300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.691332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.691358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.691387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.691415] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.691442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.691468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.691493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.691516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.691523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.691546] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.691552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.691586] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.691620] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.691655] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.691674] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.691699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.691719] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.691741] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.691760] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.691780] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.691848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.691884] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.692197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.692221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.692243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.692264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.692284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.692306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.692330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.692358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.692389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.692416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.692444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.692473] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.692501] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.694572] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.694596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.694619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.694644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.696222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.696243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.696261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.697895] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.697916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.699780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.703090] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.703134] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.703161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.703197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.703276] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.703318] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.703420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.703471] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.703523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.720201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.720244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.720287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.720334] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.720374] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.720416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.720458] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.720498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.720534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.720574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.720614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.720622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.720662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.720668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.720710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.720751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.720791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.720963] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.721235] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.721279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.721302] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.721322] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.721343] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.721365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.721390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.753300] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.753347] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.753432] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.770456] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.770499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.770531] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.770568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.770601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.770632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.770661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.770690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.770721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.770755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.770787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.770893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.770937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.770980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.771274] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.771314] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.771353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.771642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.771661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.771682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.771705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.771722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.771745] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.771769] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.771839] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.771870] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.771898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.771925] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.771934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.771961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.771968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.771996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.772023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.772053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.772261] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.772284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.772308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.772335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.772361] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.772386] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.772415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.772442] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.772515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.772541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.772568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.772593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.772620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.772645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.772674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.772701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.772729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.772755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.772781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.772840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.772871] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.775103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.775127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.775149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.775173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.776781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.776818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.776837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.778387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.778408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.780276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.783590] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.783643] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.783676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.783718] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.783777] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.783854] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.783928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.783970] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.784032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.800744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.800782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.800909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.800969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.801017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.801065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.801116] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.801166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.801217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.801265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.801311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.801323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.801368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.801379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.801426] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.801472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.801520] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.801565] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.801611] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.801656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.801705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.801751] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.801792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.801880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.801933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.833785] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.833865] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.833933] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.852078] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.852122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.852154] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.852197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.852237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.852276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.852316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.852355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.852394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.852436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.852477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.852519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.852557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.852596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.852661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.852707] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.852754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.853327] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.853378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.853435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.853471] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.853499] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.853532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.853562] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.853592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.853620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.853649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.853674] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.853682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.853708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.853715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.853744] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.853770] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.853826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.853853] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.853886] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.853913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.853945] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.853972] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.854001] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.854032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.854066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.854172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.854200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.854229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.854255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.854283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.854311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.854342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.854373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.854404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.854429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.854457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.854487] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.854518] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.856593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.856617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.856640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.856664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.858255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.858277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.858297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.859911] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.859933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.861891] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.865232] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.865284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.865316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.865359] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.865435] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.865467] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.865545] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.865591] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.865639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.882364] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.882403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.882443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.882484] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.882517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.882553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.882588] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.882622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.882655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.882686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.882716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.882723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.882752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.882759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.882867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.882911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.882953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.882998] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.883038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.883074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.883113] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.883148] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.883182] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.883225] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.883270] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.915453] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.915500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.915568] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.932594] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.932638] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  290.932670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  290.932707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.932739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.932770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.932879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.932929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.932975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.933032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.933084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.933135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.933181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.933222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.933275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.933299] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.933322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.933551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.933572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.933595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.933620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.933640] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.933661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.933682] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.933703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.933722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.933741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.933758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.933792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.933819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.933826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.933854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.933881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.933907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.933933] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.933963] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.933990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.934019] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.934045] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.934072] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.934103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.934135] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.934238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.934269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  290.934299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  290.934328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  290.934357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  290.934387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  290.934421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  290.934453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  290.934481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.934499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  290.934517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  290.934539] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  290.934560] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  290.936606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.936627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.936645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.936664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.938239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  290.938258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  290.938276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.939832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.939853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  290.941721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.945050] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.945101] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  290.945133] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  290.945174] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.945250] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.945283] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.945361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  290.945401] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.945459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  290.962136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  290.962176] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.962215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  290.962256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  290.962289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  290.962324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.962361] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.962395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.962427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  290.962458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.962488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.962495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.962525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.962531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  290.962562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  290.962592] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  290.962621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.962650] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  290.962684] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  290.962713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.962744] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  290.962773] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  290.962870] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  290.962900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.962932] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  290.995232] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.995283] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  290.995356] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.013766] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.013843] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.013875] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.013914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.013946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.013977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.014006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.014035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.014072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.014115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.014164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.014195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.014221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.014246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.014294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.014326] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.014359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.014650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.014679] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.014710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.014748] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.014782] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.014868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.014911] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.014952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.014990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.015028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.015065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.015076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.015112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.015123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.015169] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.015195] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.015222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.015247] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.015277] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.015303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.015332] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.015358] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.015384] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.015415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.015450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.015755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.015806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.015836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.015866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.015971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.015993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.016015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.016037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.016057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.016076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.016093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.016116] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.016137] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.018179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.018200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.018218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.018237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.019822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.019842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.019860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.021414] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.021435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.023320] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.026565] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.026598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.026618] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.026643] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.026703] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.026724] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.026820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.026862] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.026985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.043693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.043733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.043775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.043903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.043963] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.044016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.044070] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.044120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.044166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.044197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.044226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.044234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.044262] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.044268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.044299] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.044326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.044356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.044383] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.044416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.044444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.044474] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.044502] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.044530] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.044562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.044598] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.076780] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.076858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.076928] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.093937] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.093981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.094012] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.094051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.094099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.094142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.094173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.094211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.094250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.094293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.094334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.094376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.094414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.094453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.094517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.094563] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.094609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.095188] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.095214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.095242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.095271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.095296] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.095323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.095349] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.095375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.095401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.095426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.095451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.095457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.095482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.095487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.095513] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.095539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.095565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.095590] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.095616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.095641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.095668] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.095693] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.095719] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.095745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.095777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.095904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.096096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.096118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.096138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.096158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.096179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.096206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.096234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.096262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.096287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.096314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.096341] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.096367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.098531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.098555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.098577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.098601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.100177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.100198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.100216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.101770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.101801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.103667] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.106974] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.107025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.107057] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.107098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.107172] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.107197] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.107253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.107293] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.107333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.124052] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.124093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.124132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.124174] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.124206] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.124242] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.124278] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.124312] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.124346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.124377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.124407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.124415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.124449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.124457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.124498] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.124540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.124581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.124621] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.124660] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.124700] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.124743] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.124784] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.124905] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.124957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.125010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.157179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.157226] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.157296] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.174326] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.174370] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.174403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.174441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.174474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.174512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.174552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.174591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.174630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.174672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.174714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.174755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.174851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.174880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.174939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.174977] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.175017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.175277] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.175303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.175331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.175360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.175385] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.175411] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.175437] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.175461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.175487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.175513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.175538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.175543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.175568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.175573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.175600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.175626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.175652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.175677] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.175703] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.175728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.175756] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.175813] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.175845] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.175878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.175912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.176019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.176051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.176082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.176112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.176142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.176173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.176208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.176240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.176262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.176281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.176300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.176322] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.176343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.178395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.178418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.178437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.178456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.180041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.180063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.180082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.181631] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.181655] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.183520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.186857] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.186912] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.186951] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.186979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.187039] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.187060] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.187114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.187140] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.187190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.204051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.204088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.204126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.204169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.204208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.204248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.204288] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.204327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.204362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.204401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.204440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.204447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.204486] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.204492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.204532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.204572] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.204610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.204649] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.204687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.204725] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.204765] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.204863] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.204911] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.204963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.205015] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.237082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.237129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.237199] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.254222] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.254270] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.254310] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.254354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.254394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.254434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.254473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.254513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.254552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.254594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.254636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.254677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.254716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.254754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.254915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.254978] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.255044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.255463] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.255501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.255525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.255550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.255569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.255592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.255613] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.255634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.255659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.255686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.255711] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.255716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.255741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.255746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.255801] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.255832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.255860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.255889] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.255921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.255948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.255977] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.256004] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.256030] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.256060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.256093] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.256196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.256227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.256258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.256288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.256317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.256348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.256371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.256392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.256412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.256430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.256448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.256470] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.256495] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.258563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.258586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.258607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.258631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.260208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.260229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.260247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.261855] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.261877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.263754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.267093] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.267144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.267180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.267232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.267313] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.267353] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.267438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.267486] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.267554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.284162] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.284202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.284241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.284282] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.284315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.284351] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.284387] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.284421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.284454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.284486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.284516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.284524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.284554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.284560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.284591] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.284621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.284651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.284679] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.284714] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.284743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.284849] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.284891] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.284932] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.284982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.285015] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.317276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.317323] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.317392] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.335851] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.335898] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.335938] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.335983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.336022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.336062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.336101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.336141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.336180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.336222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.336263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.336305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.336344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.336382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.336447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.336493] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.336540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.337053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.337087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.337123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.337161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.337188] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.337212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.337233] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.337255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.337274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.337294] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.337312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.337318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.337336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.337341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.337360] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.337378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.337396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.337414] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.337436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.337454] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.337472] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.337497] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.337522] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.337550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.337579] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.337643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.337669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.337696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.337722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.337748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.337802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.337838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.337870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.337901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.337928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.337956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.337989] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.338019] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.340083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.340103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.340122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.340141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.341701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.341721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.341739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.343326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.343346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.345226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.348468] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.348502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.348525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.348556] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.348619] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.348641] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.348694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.348720] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.348800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.365601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.365642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.365681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.365722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.365755] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.365873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.366083] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.366116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.366148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.366178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.366207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.366215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.366242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.366249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.366280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.366307] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.366337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.366364] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.366399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.366427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.366459] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.366486] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.366515] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.366547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.366585] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.398686] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.398733] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.399000] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.417863] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.417926] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.417959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.417998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.418032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.418063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.418094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.418123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.418154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.418189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.418220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.418251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.418279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.418306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.418360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.418396] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.418431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.418743] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.418818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.418861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.418907] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.418942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.418981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.419018] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.419054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.419089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.419123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.419156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.419167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.419199] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.419208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.419245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.419281] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.419317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.419350] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.419388] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.419420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.419458] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.419485] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.419507] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.419534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.419562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.419648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.419674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.419705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.419738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.419796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.419826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.419856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.419886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.419918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.419945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.419971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.420005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.420026] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.422065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.422086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.422106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.422129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.423691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.423712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.423731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.425325] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.425346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.427230] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.430538] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.430588] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.430620] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.430661] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.430736] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.430834] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.431046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.431074] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.431115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.447649] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.447689] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.447728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.447770] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.447880] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.448076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.448116] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.448158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.448199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.448239] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.448279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.448290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.448329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.448336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.448386] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.448409] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.448431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.448450] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.448475] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.448501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.448528] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.448554] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.448579] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.448606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.448634] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.480740] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.480818] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.480889] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.497898] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.497941] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.497973] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.498011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.498044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.498075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.498105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.498134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.498165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.498199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.498231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.498262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.498289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.498317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.498370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.498405] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.498441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.498762] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.498854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.498898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.498944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.498982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.499022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.499061] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.499099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.499135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.499171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.499206] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.499217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.499253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.499511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.499539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.499564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.499599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.499619] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.499642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.499662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.499683] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.499702] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.499721] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.499744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.499803] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.500076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.500105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.500133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.500161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.500189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.500217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.500248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.500277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.500306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.500334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.500362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.500391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.500419] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.502477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.502499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.502518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.502537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.504110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.504130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.504148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.505696] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.505718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.507623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.510904] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.510935] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.510954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.510980] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.511038] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.511059] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.511110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.511136] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.511182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.528033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.528073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.528113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.528154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.528194] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.528236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.528277] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.528318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.528355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.528396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.528436] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.528444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.528484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.528491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.528532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.528573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.528614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.528654] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.528693] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.528733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.528827] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.528878] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.528923] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.528973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.529025] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.561084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.561131] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.561200] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.579700] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.579743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.579859] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.579936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.579995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.580055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.580095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.580136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.580175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.580220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.580268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.580293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.580314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.580333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.580370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.580395] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.580419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.580636] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.580655] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.580676] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.580699] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.580717] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.580737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.580807] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.580835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.580865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.580892] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.580918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.580926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.580952] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.580960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.580987] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.581013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.581039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.581065] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.581095] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.581121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.581150] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.581175] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.581202] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.581233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.581267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.581372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.581404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.581434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.581464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.581493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.581524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.581557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.581589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.581622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.581643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.581661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.581683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.581703] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.583786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.583807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.583825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.583845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.585421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.585441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.585458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.587021] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.587042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.588914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.592244] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.592296] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.592329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.592370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.592455] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.592476] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.592527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.592553] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.592600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.609333] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.609373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.609413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.609454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.609487] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.609523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.609559] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.609593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.609626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.609656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.609686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.609693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.609722] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.609729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.609842] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.609885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.609934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.609970] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.610013] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.610050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.610089] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.610125] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.610162] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.610208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.610472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.642424] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.642470] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.642540] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.661511] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.661558] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.661598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.661642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.661682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.661721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.661761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.661878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.661927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.661983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.662151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.662173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.662192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.662211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.662246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.662271] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.662294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.662531] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.662550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.662571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.662594] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.662612] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.662631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.662651] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.662669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.662687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.662704] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.662726] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.662731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.662801] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.662809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.662837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.662864] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.662891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.662917] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.662948] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.662974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.663002] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.663028] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.663054] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.663085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.663117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.663401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.663423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.663443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.663462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.663481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.663500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.663523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.663543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.663563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.663581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.663599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.663622] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.663642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.665692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.665713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.665731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.665801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.667432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.667452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.667470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.669036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.669056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.670927] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.674256] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.674309] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.674345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.674381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.674448] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.674482] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.674555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.674595] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.674653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.691336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.691376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.691416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.691457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.691490] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.691526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.691562] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.691596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.691628] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.691659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.691689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.691697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.691727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.691796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.691843] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.691885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.691927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.691968] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.692016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.692058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.692105] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.692147] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.692193] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.692527] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.692567] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.724437] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.724485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.724554] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.742697] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.742740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.742918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.742977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.743029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.743068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.743099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.743131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.743163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.743200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.743233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.743265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.743304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.743344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.743410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.743457] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.743505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.743879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.743902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.743926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.743958] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.743979] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.744003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.744026] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.744050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.744071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.744094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.744117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.744122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.744145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.744149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.744172] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.744195] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.744219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.744241] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.744263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.744286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.744310] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.744334] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.744357] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.744381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.744406] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.744472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.744496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.744519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.744542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.744566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.744589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.744614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.744638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.744663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.744686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.744708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.744733] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.744804] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.746857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.746878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.746896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.746915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.748485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.748508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.748530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.750095] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.750116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.751988] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.755301] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.755353] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.755385] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.755427] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.755503] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.755536] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.755614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.755655] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.755716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.772411] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.772451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.772490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.772532] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.772564] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.772600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.772635] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.772669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.772701] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.772732] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.772837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.772851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.772892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.772904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.772947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.772989] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.773035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.773304] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.773337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.773357] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.773377] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.773396] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.773414] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.773436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.773459] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.805499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.805545] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.805615] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.822876] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.822920] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.822952] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.822990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.823023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.823053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.823083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.823112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.823142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.823176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.823208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.823239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.823267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.823293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.823347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.823381] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.823417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.823816] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.823856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.823899] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.823946] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.823983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.824024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.824063] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.824101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.824138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.824178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.824215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.824227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.824265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.824275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.824314] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.824352] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.824391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.824429] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.824471] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.824510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.824538] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.824561] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.824585] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.824617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.824641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.824710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.824729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.824780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.824808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.824835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.824862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.824893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.824924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.824954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.824980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.825005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.825039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.825069] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.827135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.827155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.827174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.827193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.828786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.828807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.828825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.830388] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.830408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.832271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.835558] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.835607] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.835643] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.835695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.835824] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.835857] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.835937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.835971] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.836013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.852655] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.852695] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.852734] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.852864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.852915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.852969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.853022] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.853071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.853121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.853167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.853213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.853225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.853270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.853282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.853327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.853373] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.853419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.853464] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.853511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.853555] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.853603] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.853649] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.853690] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.853740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.853834] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.885796] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.885843] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.885931] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.902946] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.902989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.903022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.903060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.903093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.903124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.903153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.903181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.903212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.903253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.903295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.903336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.903384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.903411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.903460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.903491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.903522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.903935] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.903979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.904025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.904074] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.904103] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.904132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.904161] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.904187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.904213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.904237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.904262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.904268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.904292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.904297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.904321] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.904345] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.904368] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.904403] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.904424] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.904447] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.904475] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.904501] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.904526] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.904553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.904582] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.904645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.904672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.904697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.904723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.904776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.904808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.904841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.904873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.904904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.904931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.904958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.904990] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.905019] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.907088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.907109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.907127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.907146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.908736] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.908773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.908791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.910346] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.910366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.912282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.915581] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.915613] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.915632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.915657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.915717] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.915943] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.916019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.916044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.916082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.932716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.932792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.932835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.932881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.932922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.932964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.933005] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.933046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.933083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.933123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.933163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.933171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.933211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.933218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.933259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.933300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.933341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.933381] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.933420] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.933459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.933502] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.933542] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.933582] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.933625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.933668] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.965794] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  291.965841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  291.965909] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  291.982944] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  291.982988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  291.983020] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  291.983059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.983091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.983121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.983151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.983179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.983210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.983243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.983275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.983306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.983334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.983361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.983415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.983450] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.983485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.983941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  291.983991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  291.984026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  291.984063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  291.984094] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  291.984126] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  291.984159] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  291.984190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  291.984221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  291.984251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  291.984280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  291.984287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.984315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  291.984322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  291.984351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  291.984381] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  291.984410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  291.984439] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  291.984471] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  291.984501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  291.984532] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  291.984561] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  291.984588] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  291.984620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  291.984654] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  291.984779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  291.984809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  291.984843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  291.984873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  291.984905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  291.984936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  291.984973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  291.985007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  291.985041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  291.985071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  291.985101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  291.985136] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  291.985168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  291.987236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  291.987257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  291.987276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.987295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  291.988980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  291.989002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  291.989021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  291.990577] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  291.990598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  291.992468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  291.995791] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  291.995841] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  291.995872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  291.995913] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  291.995989] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  291.996021] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  291.996094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  291.996134] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  291.996198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.012922] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.012959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.012996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.013035] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.013066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.013099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.013139] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.013179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.013215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.013254] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.013293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.013301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.013339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.013346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.013386] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.013425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.013465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.013504] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.013541] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.013575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.013596] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.013614] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.013631] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.013651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.013673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.045980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.046027] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.046098] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.063132] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.063175] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.063207] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.063245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.063278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.063308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.063338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.063367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.063397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.063431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.063462] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.063493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.063521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.063547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.063600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.063635] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.063670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.064210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.064253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.064298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.064346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.064386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.064429] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.064472] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.064514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.064554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.064594] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.064633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.064642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.064680] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.064689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.064728] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.064806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.064835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.064866] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.064900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.064930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.064963] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.064993] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.065024] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.065058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.065094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.065198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.065229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.065259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.065288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.065315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.065345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.065378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.065411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.065443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.065472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.065500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.065534] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.065565] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.067633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.067654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.067677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.067701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.069320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.069341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.069362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.070942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.070965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.072835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.076110] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.076142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.076162] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.076188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.076247] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.076277] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.076367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.076404] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.076443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.093265] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.093303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.093340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.093379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.093411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.093444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.093478] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.093509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.093539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.093568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.093596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.093604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.093631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.093638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.093666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.093693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.093731] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.093846] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.093895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.093943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.093997] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.094039] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.094086] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.094140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.094193] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.126311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.126358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.126446] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.143592] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.143635] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.143667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.143705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.143738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.143851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.143895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.143943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.143988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.144042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.144093] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.144143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.144184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.144227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.144308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.144363] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.144418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.144709] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.144776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.144813] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.144849] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.144879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.144913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.144944] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.144977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.145005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.145035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.145061] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.145070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.145096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.145103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.145131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.145157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.145185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.145210] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.145241] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.145266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.145296] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.145322] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.145349] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.145377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.145411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.145514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.145542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.145571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.145597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.145625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.145652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.145683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.145714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.145767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.145797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.145824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.145858] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.145888] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.147960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.147981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.147998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.148017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.149591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.149610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.149628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.151184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.151204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.153075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.156401] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.156453] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.156486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.156528] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.156621] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.156678] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.156790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.156833] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.156893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.173547] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.173585] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.173623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.173660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.173691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.173724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.173837] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.173885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.173937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.173981] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.174028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.174042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.174096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.174107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.174150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.174188] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.174231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.174270] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.174317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.174355] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.174398] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.174435] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.174476] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.174518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.174567] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.206601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.206647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.206736] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.223830] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.223873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.223905] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.223944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.223976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.224007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.224045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.224085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.224124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.224169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.224201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.224231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.224257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.224283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.224333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.224367] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.224400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.224730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.224840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.224887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.224943] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.224985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.225034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.225079] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.225125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.225168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.225199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.225226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.225235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.225264] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.225272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.225302] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.225329] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.225358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.225384] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.225415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.225440] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.225472] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.225498] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.225526] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.225558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.225591] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.225695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.225724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.225842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.225869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.225898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.225925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.225957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.225988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.226019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.226044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.226071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.226101] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.226132] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.228224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.228245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.228263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.228282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.229871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.229891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.229909] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.231472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.231492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.233369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.236629] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.236672] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.236698] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.236795] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.237025] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.237069] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.237162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.237213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.237291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.253937] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.253990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.254044] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.254101] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.254147] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.254196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.254245] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.254283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.254314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.254343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.254370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.254378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.254406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.254412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.254441] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.254468] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.254495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.254523] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.254555] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.254582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.254612] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.254639] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.254666] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.254698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.254733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.286828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.286875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.286944] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.303986] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.304029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.304062] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.304100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.304132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.304163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.304192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.304221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.304252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.304286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.304317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.304348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.304376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.304404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.304457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.304492] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.304528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.304980] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.305013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.305047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.305084] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.305115] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.305148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.305180] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.305212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.305243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.305273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.305302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.305310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.305338] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.305345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.305374] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.305404] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.305433] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.305459] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.305492] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.305521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.305552] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.305581] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.305610] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.305642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.305677] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.305809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.305842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.305873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.305906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.305937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.305964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.305999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.306031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.306063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.306092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.306120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.306155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.306186] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.308253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.308274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.308293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.308312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.309911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.309933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.309952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.311515] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.311536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.313411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.316724] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.316807] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.316840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.316882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.316957] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.316999] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.317051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.317078] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.317124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.333916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.333956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.333997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.334038] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.334071] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.334107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.334143] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.334177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.334210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.334241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.334270] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.334278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.334307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.334314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.334344] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.334374] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.334403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.334432] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.334466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.334496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.334533] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.334574] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.334615] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.334658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.334701] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.366972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.367019] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.367087] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.384260] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.384303] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.384335] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.384374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.384406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.384437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.384467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.384496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.384527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.384560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.384591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.384623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.384651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.384678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.384813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.384876] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.384937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.385528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.385558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.385590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.385624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.385652] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.385684] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.385714] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.385785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.385819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.385851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.385881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.385890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.385919] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.385927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.385957] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.385987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.386013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.386043] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.386077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.386106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.386138] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.386167] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.386197] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.386230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.386263] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.386367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.386398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.386428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.386458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.386487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.386517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.386550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.386583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.386615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.386644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.386673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.386707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.386762] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.388823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.388845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.388868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.388892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.390466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.390490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.390512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.392079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.392100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.393971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.397292] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.397346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.397385] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.397436] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.397517] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.397556] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.397640] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.397684] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.397836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.414355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.414395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.414435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.414476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.414512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.414554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.414596] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.414637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.414673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.414713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.414838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.414854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.414904] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.414917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.414968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.415018] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.415068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.415116] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.415169] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.415225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.415258] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.415555] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.415583] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.415615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.415647] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.447479] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.447526] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.447594] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.464630] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.464674] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.464706] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.464836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.464887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.464936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.464984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.465031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.465080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.465133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.465184] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.465235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.465290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.465318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.465373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.465410] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.465447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.465707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.465783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.465820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.465861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.465893] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.465928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.465962] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.465995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.466027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.466059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.466089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.466099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.466127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.466135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.466166] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.466195] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.466226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.466255] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.466285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.466313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.466344] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.466369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.466397] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.466430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.466465] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.466569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.466600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.466630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.466659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.466688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.466718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.466773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.466808] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.466842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.466871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.466902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.466937] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.466969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.469034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.469055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.469074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.469093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.470663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.470684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.470702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.472300] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.472321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.474237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.477512] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.477543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.477562] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.477587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.477646] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.477666] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.477944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.477971] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.478008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.494610] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.494650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.494689] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.494815] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.494870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.494927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.494980] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.495032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.495081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.495127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.495173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.495185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.495230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.495241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.495287] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.495332] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.495377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.495417] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.495467] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.495512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.495562] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.495603] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.495649] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.495701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.495784] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.527698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.527777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.527846] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.544854] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.544897] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.544928] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.544966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.544999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.545030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.545068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.545108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.545148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.545199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.545234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.545266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.545294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.545320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.545372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.545407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.545441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.545864] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.546262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.546295] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.546329] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.546358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.546389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.546419] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.546448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.546477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.546506] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.546533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.546540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.546567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.546573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.546601] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.546628] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.546654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.546681] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.546708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.546775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.546805] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.546836] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.546866] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.546900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.546935] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.547259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.547293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.547322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.547352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.547382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.547414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.547448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.547481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.547514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.547543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.547571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.547605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.547637] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.549750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.549771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.549790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.549809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.551379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.551400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.551418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.552982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.553003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.554875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.558205] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.558258] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.558290] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.558332] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.558415] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.558436] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.558488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.558515] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.558562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.575270] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.575310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.575350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.575391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.575424] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.575460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.575496] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.575530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.575562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.575593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.575624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.575631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.575661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.575668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.575699] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.575802] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.575855] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.575900] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.575945] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.575990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.576038] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.576079] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.576122] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.576173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.576224] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.608403] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.608451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.608525] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.626972] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.627019] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.627059] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.627104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.627144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.627183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.627223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.627262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.627301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.627344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.627385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.627427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.627466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.627504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.627570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.627615] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.627662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.628236] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.628266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.628297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.628332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.628358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.628387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.628415] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.628443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.628469] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.628495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.628519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.628526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.628550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.628556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.628583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.628607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.628633] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.628656] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.628685] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.628722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.628778] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.628809] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.628836] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.628868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.628903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.628994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.629021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.629050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.629076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.629104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.629131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.629163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.629194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.629226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.629252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.629279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.629309] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.629340] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.631407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.631431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.631454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.631478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.633044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.633065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.633084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.634632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.634652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.636516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.639829] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.639879] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.639911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.639952] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.640028] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.640061] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.640143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.640184] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.640244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.656981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.657025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.657068] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.657114] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.657154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.657196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.657237] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.657278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.657313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.657353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.657393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.657401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.657441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.657447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.657489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.657529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.657570] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.657609] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.657648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.657688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.657773] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.657805] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.657834] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.657866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.657898] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.690026] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.690073] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.690142] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.707177] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.707220] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.707252] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.707290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.707323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.707354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.707383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.707412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.707442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.707476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.707508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.707539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.707567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.707594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.707648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.707683] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.707785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.708043] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.708064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.708087] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.708112] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.708132] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.708154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.708179] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.708205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.708231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.708257] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.708282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.708289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.708313] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.708318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.708341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.708367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.708393] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.708418] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.708444] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.708469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.708496] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.708521] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.708548] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.708574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.708601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.708675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.708702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.708762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.708794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.708823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.708853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.708886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.708917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.708947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.708975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.709002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.709035] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.709064] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.711129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.711150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.711169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.711188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.712754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.712774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.712792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.714358] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.714380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.716248] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.719563] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.719616] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.719648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.719690] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.719866] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.719914] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.720023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.720084] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.720146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.736713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.736786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.736823] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.736862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.736892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.736926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.736959] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.736990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.737020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.737049] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.737077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.737085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.737112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.737118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.737146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.737173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.737211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.737250] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.737288] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.737327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.737368] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.737407] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.737453] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.737477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.737502] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.769783] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.769828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.769897] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.786912] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.786955] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.786987] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.787025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.787058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.787089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.787119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.787148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.787179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.787212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.787244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.787275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.787304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.787332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.787386] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.787430] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.787478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.787917] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.787951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.787986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.788022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.788050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.788084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.788113] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.788143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.788171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.788199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.788225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.788232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.788259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.788266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.788294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.788320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.788348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.788373] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.788404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.788430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.788460] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.788486] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.788513] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.788543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.788576] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.788677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.788704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.788757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.788785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.788815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.788844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.788877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.788910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.788942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.788968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.788997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.789032] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.789061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.791128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.791149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.791167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.791187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.792752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.792772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.792789] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.794339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.794360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.796247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.799532] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.799583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.799615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.799656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.799812] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.799859] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.799968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.800007] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.800068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.816720] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.816793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.816831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.816874] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.816913] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.816953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.816992] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.817031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.817065] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.817104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.817142] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.817150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.817188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.817195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.817235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.817274] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.817312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.817351] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.817392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.817422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.817450] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.817476] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.817500] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.817529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.817558] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.849759] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.849803] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.849870] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.866913] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.866956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.866988] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.867026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.867059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.867090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.867120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.867148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.867179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.867212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.867244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.867276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.867304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.867332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.867385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.867420] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.867465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.867778] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.867809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.867844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.867882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.867911] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.867945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.867976] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.868006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.868038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.868066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.868094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.868102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.868129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.868135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.868164] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.868191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.868219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.868244] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.868276] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.868302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.868332] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.868357] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.868385] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.868414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.868447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.868550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.868577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.868605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.868631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.868658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.868685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.868741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.868774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.868806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.868833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.868863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.868898] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.868927] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.870995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.871015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.871034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.871053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.872623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.872643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.872661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.874262] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.874284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.876154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.879467] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.879518] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.879549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.879591] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.879667] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.879701] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.881909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.881960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.882030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.896584] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.896624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.896663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.896709] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.896832] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.896880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.896918] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.896949] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.896980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.897018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.897058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.897067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.897106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.897113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.897155] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.897195] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.897237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.897283] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.897308] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.897330] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.897352] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.897371] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.897391] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.897412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.897436] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.929665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  292.929788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  292.929891] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  292.946896] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  292.946944] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  292.946984] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  292.947028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.947068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.947107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.947147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.947186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.947225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.947267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.947309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.947355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.947383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.947409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.947457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.947489] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.947521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.947982] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.948025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.948071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.948119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.948160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.948203] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.948248] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.948289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.948330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.948373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.948402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.948410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.948438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.948445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.948475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.948505] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.948534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.948564] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.948593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.948622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.948653] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.948682] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.948742] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.948773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.948810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  292.948913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  292.948944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  292.948974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  292.949004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  292.949031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  292.949062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  292.949096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  292.949129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  292.949161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.949190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  292.949219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  292.949253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  292.949283] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  292.951358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  292.951381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  292.951403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.951427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  292.953009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  292.953030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  292.953048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  292.954601] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  292.954622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  292.956502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  292.959754] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  292.959786] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  292.959805] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  292.959831] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  292.959890] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  292.959919] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  292.960009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  292.960046] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  292.960085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  292.976904] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  292.976944] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  292.976983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  292.977024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  292.977056] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  292.977092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  292.977128] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  292.977162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  292.977195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  292.977226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  292.977255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  292.977263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.977292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  292.977299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  292.977330] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  292.977359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  292.977388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  292.977417] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  292.977451] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  292.977479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  292.977510] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  292.977539] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  292.977574] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  292.977617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  292.977661] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.009976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.010026] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.010118] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.027165] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.027208] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.027240] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.027279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.027312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.027343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.027372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.027400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.027432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.027465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.027496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.027536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.027576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.027614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.027679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.027791] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.027860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.028463] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.028484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.028506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.028529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.028547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.028567] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.028587] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.028605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.028623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.028640] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.028656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.028661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.028677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.028722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.028753] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.028786] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.028816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.028847] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.028881] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.028912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.028945] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.028974] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.029005] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.029040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.029074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.029407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.029439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.029470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.029500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.029530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.029561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.029594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.029627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.029658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.029688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.029743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.029779] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.029812] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.031993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.032015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.032035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.032056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.033595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.033616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.033635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.035163] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.035185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.037028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.040356] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.040413] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.040432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.040458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.040517] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.040547] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.040629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.040669] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.040766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.057470] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.057510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.057550] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.057591] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.057624] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.057661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.057703] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.057821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.057872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.057923] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.057973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.057987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.058034] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.058046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.058095] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.058140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.058189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.058235] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.058286] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.058330] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.058374] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.058418] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.058464] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.058515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.058568] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.090578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.090625] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.090712] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.109423] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.109467] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.109499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.109538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.109577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.109617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.109657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.109696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.109822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.109890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.109925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.109959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.109989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.110020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.110077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.110114] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.110151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.110453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.110473] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.110495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.110517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.110536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.110555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.110575] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.110593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.110610] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.110627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.110643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.110648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.110664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.110667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.110735] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.110765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.110796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.110828] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.110858] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.110889] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.110921] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.110950] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.110980] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.111014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.111049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.111154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.111185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.111212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.111241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.111270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.111298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.111331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.111363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.111395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.111424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.111452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.111486] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.111517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.113584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.113605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.113623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.113642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.115218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.115238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.115256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.116904] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.116926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.118791] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.122139] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.122171] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.122191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.122216] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.122276] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.122297] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.122350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.122378] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.122425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.139223] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.139260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.139298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.139337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.139368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.139401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.139435] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.139467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.139497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.139526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.139554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.139561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.139588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.139594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.139622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.139649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.139676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.139789] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.139836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.139878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.139924] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.139965] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.140007] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.140057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.140106] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.172350] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.172399] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.172470] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.189511] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.189554] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.189586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.189625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.189658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.189689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.189806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.189973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.190006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.190041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.190073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.190106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.190134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.190163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.190215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.190252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.190287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.190634] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.190666] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.190761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.190825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.190854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.190884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.190915] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.190946] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.190976] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.191003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.191033] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.191220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.191240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.191244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.191263] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.191280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.191297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.191314] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.191334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.191350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.191368] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.191384] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.191400] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.191423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.191448] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.191513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.191532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.191549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.191565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.191582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.191599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.191623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.191648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.191673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.191741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.191771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.191804] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.191833] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.194108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.194129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.194148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.194168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.195785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.195805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.195823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.197371] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.197392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.199264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.202581] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.202634] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.202667] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.202785] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.202933] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.202982] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.203063] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.203111] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.203151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.219689] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.219764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.219804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.219845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.219878] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.219913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.219949] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.219982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.220014] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.220045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.220075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.220082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.220111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.220118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.220148] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.220177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.220206] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.220234] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.220269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.220299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.220330] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.220360] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.220388] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.220422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.220458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.252774] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.252821] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.252890] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.270012] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.270055] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.270087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.270125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.270158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.270189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.270219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.270248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.270279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.270313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.270344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.270384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.270423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.270462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.270528] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.270573] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.270620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.271053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.271086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.271118] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.271154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.271181] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.271213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.271242] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.271272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.271301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.271329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.271356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.271363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.271390] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.271396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.271426] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.271452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.271480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.271505] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.271536] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.271561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.271590] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.271616] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.271642] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.271675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.271736] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.271824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.271851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.271881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.271908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.271937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.271964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.271996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.272027] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.272058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.272083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.272111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.272143] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.272171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.274276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.274297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.274315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.274334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.275907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.275931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.275951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.277511] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.277533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.279402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.282689] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.282769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.282802] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.282843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.282918] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.282951] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.283016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.283043] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.283090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.299835] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.299875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.299915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.299958] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.299998] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.300040] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.300082] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.300122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.300159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.300199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.300239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.300247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.300287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.300294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.300343] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.300379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.300411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.300441] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.300475] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.300504] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.300535] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.300563] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.300591] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.300624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.300659] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.332915] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.332966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.333041] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.350066] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.350113] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.350154] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.350198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.350238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.350278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.350318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.350357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.350396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.350439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.350481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.350522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.350560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.350609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.350647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.350672] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.350761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.351137] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.351158] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.351180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.351202] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.351220] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.351240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.351260] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.351278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.351296] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.351313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.351329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.351333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.351349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.351353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.351370] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.351386] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.351402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.351424] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.351448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.351471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.351495] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.351518] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.351541] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.351566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.351591] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.351661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.351729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.351765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.351794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.351827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.351857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.351891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.351924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.351957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.351984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.352013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.352049] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.352078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.354166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.354187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.354205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.354224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.355810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.355831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.355849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.357408] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.357429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.359302] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.362587] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.362637] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.362669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.362791] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.362894] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.362924] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.363001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.363041] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.363099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.379761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.379801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.379841] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.379882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.379915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.379952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.379988] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.380021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.380053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.380083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.380113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.380120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.380150] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.380156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.380186] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.380216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.380245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.380274] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.380313] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.380340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.380367] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.380393] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.380418] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.380449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.380481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.412811] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.412858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.412926] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.429965] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.430008] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.430041] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.430079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.430111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.430142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.430172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.430201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.430233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.430266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.430298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.430328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.430356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.430383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.430427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.430448] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.430469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.430655] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.430738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.430772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.430810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.430838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.430872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.430902] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.430933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.430963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.430992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.431018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.431028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.431054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.431062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.431091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.431117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.431144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.431171] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.431204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.431231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.431260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.431285] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.431312] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.431341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.431374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.431476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.431503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.431531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.431557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.431584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.431611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.431642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.431674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.431728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.431755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.431785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.431817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.431847] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.433914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.433935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.433953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.433972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.435541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.435561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.435579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.437141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.437162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.439030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.442351] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.442404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.442436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.442477] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.442552] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.442585] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.442653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.442722] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.442785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.459450] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.459491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.459530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.459572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.459605] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.459641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.459677] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.459800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.459848] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.459898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.459949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.459963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.460009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.460020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.460072] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.460115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.460158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.460198] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.460244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.460286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.460328] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.460369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.460409] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.460455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.460502] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.492539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.492588] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.492661] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.509761] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.509804] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.509836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.509878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.509918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.509958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.509998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.510037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.510076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.510119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.510161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.510199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.510219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.510237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.510271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.510297] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.510325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.510548] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.510572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.510596] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.510623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.510645] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.510669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.510744] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.510778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.510813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.510845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.510876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.510885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.510914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.510922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.510953] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.510983] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.511014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.511043] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.511077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.511107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.511140] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.511170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.511201] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.511236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.511271] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.511743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.511776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.511808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.511839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.511870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.511902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.511936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.511968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.512001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.512030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.512056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.512090] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.512122] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.514206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.514227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.514246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.514265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.515836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.515860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.515880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.517419] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.517440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.519316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.522575] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.522609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.522632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.522663] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.522796] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.522830] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.522908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.522947] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.522989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.539683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.539757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.539800] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.539846] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.539886] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.539928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.539970] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.540011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.540047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.540087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.540127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.540135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.540175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.540182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.540223] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.540263] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.540304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.540344] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.540383] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.540423] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.540465] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.540506] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.540546] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.540589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.540632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.572776] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.572823] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.572890] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.589915] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.589958] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.589990] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.590028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.590061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.590093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.590123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.590162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.590201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.590244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.590286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.590327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.590367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.590405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.590470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.590515] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.590562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.591129] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.591172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.591216] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.591262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.591301] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.591343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.591384] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.591423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.591463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.591500] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.591538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.591548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.591584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.591592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.591630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.591666] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.591739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.591777] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.591820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.591858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.591900] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.591937] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.591976] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.592019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.592063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.592183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.592216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.592247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.592278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.592309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.592341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.592376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.592409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.592442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.592473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.592504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.592538] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.592571] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.594639] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.594662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.594742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.594776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.596334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.596355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.596373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.597936] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.597956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.599823] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.603144] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.603196] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.603233] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.603285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.603371] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.603399] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.603463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.603496] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.603545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.620244] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.620284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.620324] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.620365] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.620398] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.620434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.620471] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.620505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.620539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.620575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.620615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.620623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.620663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.620748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.620809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.620857] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.620905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.620951] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.621002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.621047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.621096] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.621140] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.621186] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.621239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.621290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.653344] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.653391] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.653463] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.671913] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.671961] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.672001] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.672045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.672085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.672124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.672163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.672203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.672242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.672282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.672318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.672355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.672393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.672432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.672497] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.672543] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.672590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.673154] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.673188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.673221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.673258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.673286] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.673318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.673347] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.673377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.673405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.673433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.673458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.673466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.673492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.673499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.673527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.673553] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.673580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.673605] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.673637] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.673662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.673716] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.673743] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.673772] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.673806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.673841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.673930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.673960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.673990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.674019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.674048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.674079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.674112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.674145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.674175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.674201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.674228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.674259] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.674289] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.676365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.676387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.676406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.676425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.677991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.678011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.678028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.679587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.679607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.681471] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.684785] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.684836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.684868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.684909] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.684983] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.685019] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.685103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.685144] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.685206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.701886] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.701928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.701970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.702014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.702052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.702093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.702132] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.702171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.702206] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.702245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.702283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.702290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.702328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.702335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.702375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.702414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.702453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.702492] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.702529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.702567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.702603] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.702623] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.702642] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.702716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.702749] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.734980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.735024] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.735090] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.752136] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.752179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.752211] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.752249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.752281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.752312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.752342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.752371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.752402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.752435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.752467] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.752498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.752526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.752553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.752607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.752642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.752758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.753186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.753208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.753232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.753257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.753276] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.753298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.753320] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.753339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.753359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.753377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.753395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.753400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.753417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.753422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.753440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.753464] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.753490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.753515] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.753540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.753564] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.753590] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.753616] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.753641] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.753707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.753742] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.754005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.754028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.754048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.754067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.754085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.754105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.754127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.754147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.754167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.754186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.754203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.754226] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.754246] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.756311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.756333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.756352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.756371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.757947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.757971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.757994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.759554] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.759576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.761439] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.764784] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.764839] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.764878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.764930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.765010] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.765052] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.765106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.765134] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.765181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.781943] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.781983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.782023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.782064] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.782096] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.782132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.782168] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.782202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.782235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.782266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.782296] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.782304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.782334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.782341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.782372] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.782402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.782431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.782461] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.782503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.782529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.782556] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.782583] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.782608] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.782639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.782717] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.815000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.815047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.815115] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.833562] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.833605] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.833637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.833769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.833823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.833874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.833921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.833968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.834017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.834071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.834122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.834173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.834219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.834264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.834351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.834407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.834466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.834957] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.834989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.835014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.835037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.835056] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.835076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.835096] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.835118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.835141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.835164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.835186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.835191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.835214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.835218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.835242] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.835265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.835289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.835311] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.835334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.835356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.835380] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.835404] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.835427] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.835451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.835476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.835547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.835570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.835594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.835617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.835640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.835713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.835749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.835784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.835820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.835851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.835881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.835918] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.835951] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.838046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.838067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.838086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.838105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.839663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.839708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.839726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.841289] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.841311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.843207] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.846512] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.846562] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.846592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.846631] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.846787] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.846836] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.846948] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.847005] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.847097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.863602] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.863642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.863758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.863816] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.863860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.863910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.863957] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.864005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.864049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.864094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.864134] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.864146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.864189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.864200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.864244] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.864285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.864328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.864367] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.864416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.864456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.864502] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.864541] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.864568] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.864598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.864630] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.896718] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.896764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.896833] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.913869] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.913916] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.913957] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.914001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.914041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.914080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.914120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.914159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.914198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.914240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.914282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.914323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.914362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.914400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.914464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.914510] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.914556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.915231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.915253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.915275] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.915298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.915316] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.915336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.915356] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.915379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.915402] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.915425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.915448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.915452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.915476] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.915480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.915504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.915527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.915550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.915573] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.915596] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.915618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.915643] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.915712] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.915748] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.915780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.915816] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.916160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.916192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.916221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.916248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.916277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.916305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.916337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.916368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.916399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.916425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.916453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.916484] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.916514] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  293.918590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  293.918611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  293.918629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.918648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  293.920237] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  293.920257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  293.920275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  293.921838] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  293.921858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  293.923720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  293.927064] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  293.927109] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  293.927137] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  293.927173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  293.927237] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  293.927264] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  293.927331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.927366] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.927416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.944198] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.944238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.944277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.944317] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.944350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.944385] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.944421] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.944455] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.944487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.944517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.944547] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.944554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.944593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.944601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.944642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.944759] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.944804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.944852] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.944900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.944948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.944999] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.945042] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.945087] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.945140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.945194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.977279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  293.977325] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  293.977394] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  293.995675] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  293.995749] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  293.995789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  293.995833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.995873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.995912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.995951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.995991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.996030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.996072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.996113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.996154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.996193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.996231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.996296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  293.996341] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  293.996388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.996759] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  293.996791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  293.996827] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  293.997111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  293.997140] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  293.997173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  293.997203] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  293.997234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  293.997261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  293.997289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  293.997315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  293.997323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.997350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  293.997357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  293.997386] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  293.997412] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  293.997440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.997465] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  293.997496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  293.997521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  293.997550] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  293.997575] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  293.997602] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  293.997634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  293.997691] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  293.998029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  293.998056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  293.998083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  293.998108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  293.998134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  293.998160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  293.998190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  293.998219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  293.998248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  293.998272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  293.998298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  293.998329] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  293.998355] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.000438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.000461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.000483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.000507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.002096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.002119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.002138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.003807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.003829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.005755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.009018] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.009052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.009076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.009106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.009168] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.009189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.009242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.009269] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.009316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.026120] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.026164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.026207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.026253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.026293] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.026335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.026377] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.026417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.026454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.026495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.026535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.026542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.026583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.026590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.026631] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.026753] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.026802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.026852] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.026902] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.026951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.027003] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.027047] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.027093] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.027147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.027202] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.059214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.059262] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.059331] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.076370] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.076417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.076457] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.076502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.076541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.076581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.076620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.076660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.076775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.076832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.076887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.076939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.076982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.077026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.077112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.077168] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.077225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.077643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.077710] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.077747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.077784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.077814] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.077846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.077877] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.077909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.077936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.077965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.077991] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.077998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.078026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.078033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.078061] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.078087] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.078115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.078140] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.078171] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.078198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.078227] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.078252] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.078279] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.078308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.078341] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.078443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.078471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.078499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.078526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.078553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.078580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.078613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.078645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.078700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.078726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.078755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.078790] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.078821] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.080886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.080907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.080925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.080944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.082514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.082535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.082553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.084115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.084136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.086008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.089319] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.089374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.089413] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.089464] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.089545] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.089585] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.089722] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.089778] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.089840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.106437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.106480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.106524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.106570] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.106611] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.106653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.106776] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.106823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.106857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.106896] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.106936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.106944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.106983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.106990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.107030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.107071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.107111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.107145] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.107170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.107191] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.107212] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.107231] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.107250] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.107272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.107295] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.139519] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.139566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.139635] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.156739] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.156782] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.156814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.156852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.156892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.156932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.156971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.157011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.157050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.157093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.157134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.157177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.157203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.157228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.157281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.157319] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.157359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.157646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.157733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.157780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.157834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.157877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.157924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.157969] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.158013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.158055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.158097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.158136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.158148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.158186] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.158194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.158225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.158254] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.158285] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.158314] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.158347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.158375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.158408] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.158437] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.158466] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.158500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.158534] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.158637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.158694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.158723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.158752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.158779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.158811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.158846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.158880] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.158913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.158942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.158973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.159008] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.159040] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.161128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.161149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.161168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.161187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.162771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.162792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.162815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.164377] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.164398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.166270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.169506] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.169538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.169557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.169583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.169642] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.169717] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.169796] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.169836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.169898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.186639] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.186714] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.186754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.186795] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.186828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.186864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.186900] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.186933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.186965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.186996] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.187025] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.187032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.187062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.187068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.187098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.187138] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.187179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.187220] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.187261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.187301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.187344] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.187385] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.187425] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.187468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.187511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.219727] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.219774] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.219842] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.237631] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.237708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.237741] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.237779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.237812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.237842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.237871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.237899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.237930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.237964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.237995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.238026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.238053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.238081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.238143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.238165] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.238186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.238399] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.238418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.238439] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.238464] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.238487] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.238512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.238535] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.238558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.238582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.238604] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.238627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.238675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.238710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.238721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.238755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.238788] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.238822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.238852] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.238887] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.238918] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.238952] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.238982] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.239012] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.239047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.239082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.239186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.239217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.239247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.239277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.239306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.239334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.239367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.239400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.239432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.239458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.239486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.239520] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.239552] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.241618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.241638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.241713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.241750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.243408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.243428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.243446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.245010] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.245031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.246890] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.250189] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.250239] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.250270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.250312] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.250388] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.250410] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.250464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.250491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.250538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.267291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.267332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.267372] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.267413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.267445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.267481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.267517] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.267551] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.267584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.267615] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.267645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.267730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.267778] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.267792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.267842] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.267890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.267939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.267986] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.268040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.268088] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.268139] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.268184] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.268227] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.268279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.268331] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.300399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.300445] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.300514] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.317548] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.317591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.317630] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.317766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.317820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.317871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.317919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.317974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.318015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.318060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.318102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.318145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.318184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.318222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.318294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.318341] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.318390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.318799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.318844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.318890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.318929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.318962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.319003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.319028] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.319050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.319071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.319090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.319113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.319119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.319145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.319150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.319178] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.319205] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.319232] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.319259] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.319287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.319313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.319342] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.319369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.319396] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.319424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.319452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.319518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.319546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.319574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.319601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.319629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.319695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.319733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.319773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.319811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.319845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.319880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.319919] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.319954] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.322041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.322062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.322081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.322100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.323691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.323732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.323755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.325327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.325350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.327221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.330506] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.330551] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.330578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.330613] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.330761] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.330804] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.330902] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.330956] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.331010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.347656] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.347729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.347769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.347810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.347844] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.347880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.347916] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.347950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.347982] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.348013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.348043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.348050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.348080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.348086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.348117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.348147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.348176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.348205] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.348239] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.348269] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.348300] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.348329] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.348357] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.348392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.348428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.380734] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.380782] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.380850] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.398064] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.398108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.398140] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.398179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.398212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.398243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.398272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.398301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.398332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.398366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.398398] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.398430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.398458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.398485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.398538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.398573] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.398609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.399113] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.399146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.399180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.399217] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.399247] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.399280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.399313] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.399344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.399376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.399406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.399435] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.399443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.399470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.399478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.399507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.399536] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.399562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.399591] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.399623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.399676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.399706] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.399736] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.399766] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.399800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.399836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.399940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.399970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.400000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.400026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.400055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.400086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.400119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.400151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.400184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.400213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.400244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.400277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.400308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.402374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.402395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.402413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.402432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.403997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.404020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.404043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.405627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.405660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.407519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.410854] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.410907] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.410939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.410978] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.411037] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.411058] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.411110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.411136] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.411183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.427958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.427998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.428038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.428078] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.428112] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.428148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.428184] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.428218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.428252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.428292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.428332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.428340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.428380] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.428387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.428429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.428470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.428510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.428551] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.428589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.428629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.428756] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.428813] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.428865] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.428921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.428978] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.461079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.461126] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.461195] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.478230] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.478274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.478307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.478345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.478378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.478409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.478439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.478469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.478501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.478535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.478567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.478598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.478626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.478742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.478816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.478864] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.478915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.479397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.479440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.479485] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.479533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.479575] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.479617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.479698] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.479739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.479774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.479805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.479835] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.479844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.479874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.479883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.479912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.479941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.479972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.480002] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.480031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.480059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.480087] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.480115] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.480140] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.480172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.480207] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.480310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.480341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.480372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.480402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.480431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.480462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.480495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.480527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.480559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.480587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.480616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.480673] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.480706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.482770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.482790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.482808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.482828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.484387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.484407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.484429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.485994] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.486015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.487885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.491162] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.491208] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.491241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.491284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.491352] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.491384] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.491452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.491488] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.491539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.508255] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.508295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.508338] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.508384] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.508425] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.508467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.508508] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.508548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.508590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.508630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.508758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.508773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.508825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.508838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.508889] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.508939] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.508989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.509037] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.509091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.509139] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.509190] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.509236] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.509279] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.509331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.509380] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.541344] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.541394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.541468] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.558488] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.558531] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.558563] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.558602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.558634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.558765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.558816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.558867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.558915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.558971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.559022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.559072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.559117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.559162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.559247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.559303] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.559361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.559778] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.559810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.559834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.559857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.559876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.559896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.559917] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.559936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.559954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.559977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.560000] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.560005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.560027] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.560032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.560055] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.560078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.560102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.560125] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.560148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.560171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.560195] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.560218] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.560241] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.560266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.560290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.560358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.560382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.560405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.560428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.560452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.560475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.560500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.560524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.560548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.560571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.560594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.560618] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.560691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.562760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.562781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.562799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.562818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.564387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.564407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.564425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.565987] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.566007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.567880] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.571183] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.571232] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.571263] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.571303] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.571373] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.571404] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.571477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.571515] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.571571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.588283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.588325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.588369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.588415] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.588454] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.588496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.588538] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.588578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.588620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.588747] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.588803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.588817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.588869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.588882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.588933] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.588983] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.589032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.589079] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.589132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.589178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.589229] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.589269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.589298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.589333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.589366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.621389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.621436] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.621505] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.638540] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.638582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.638614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.638744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.638798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.638849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.638897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.638946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.638994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.639048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.639099] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.639150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.639196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.639241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.639326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.639374] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.639412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.639749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.639781] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.639814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.639840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.639859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.639879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.639899] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.639918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.639936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.639953] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.639970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.639974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.639990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.639994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.640011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.640028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.640044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.640059] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.640078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.640094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.640112] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.640128] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.640143] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.640163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.640184] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.640236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.640255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.640272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.640289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.640306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.640323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.640342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.640360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.640378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.640394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.640410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.640430] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.640448] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.642511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.642533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.642552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.642572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.644163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.644188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.644211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.645787] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.645809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.647676] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.650988] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.651041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.651073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.651115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.651190] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.651223] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.651301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.651342] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.651402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.668105] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.668146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.668186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.668227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.668259] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.668295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.668332] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.668374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.668416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.668456] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.668496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.668503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.668544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.668551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.668592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.668632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.668750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.668807] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.668863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.668916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.668970] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.669027] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.669068] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.669114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.669161] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.701226] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.701273] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.701361] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.718417] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.718459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.718491] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.718529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.718561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.718591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.718630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.718745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.718791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.718847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.718894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.718945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.718976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.719003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.719057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.719094] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.719129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.719384] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.719405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.719428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.719455] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.719480] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.719508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.719534] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.719560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.719586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.719611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.719668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.719677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.719706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.719714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.719743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.719771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.719798] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.719825] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.719856] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.719883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.719913] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.719939] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.719965] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.719995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.720030] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.720104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.720124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.720142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.720160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.720178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.720197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.720218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.720238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.720257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.720275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.720299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.720327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.720353] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.722410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.722432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.722451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.722474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.724052] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.724073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.724091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.725671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.725693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.727564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.730898] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.730950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.730983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.731025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.731102] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.731135] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.731213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.731254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.731314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.748037] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.748081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.748124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.748170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.748210] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.748252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.748293] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.748334] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.748375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.748415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.748455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.748463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.748503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.748510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.748551] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.748592] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.748632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.748809] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.748844] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.748880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.748916] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.748946] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.748977] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.749011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.749045] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.781125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.781172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.781241] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.799579] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.799622] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.799744] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.799804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.799857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.799906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.799953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.800000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.800054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.800087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.800120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.800152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.800182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.800210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.800266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.800302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.800340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.800581] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.800600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.800674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.800712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.800744] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.800779] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.800812] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.800845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.800876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.800908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.800938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.800946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.800976] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.800984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.801014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.801043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.801074] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.801103] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.801133] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.801163] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.801196] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.801225] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.801256] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.801288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.801322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.801425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.801456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.801486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.801517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.801545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.801576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.801609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.801665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.801699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.801727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.801757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.801792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.801824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.803888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.803911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.803934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.803958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.805520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.805544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.805566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.807146] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.807169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.809147] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.812409] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.812451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.812483] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.812524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.812590] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.812621] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.812774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.812827] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.812906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.829518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.829558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.829598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.829726] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.829931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.829967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.830007] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.830047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.830087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.830126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.830164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.830172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.830211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.830218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.830258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.830297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.830336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.830375] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.830413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.830451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.830492] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.830531] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.830570] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.830611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.830715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.862608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.862687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.862758] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.879765] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.879812] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.879852] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.879896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.879936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.879976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.880015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.880055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.880093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.880136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.880177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.880217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.880255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.880294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.880359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.880404] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.880451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.881090] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.881123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.881155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.881189] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.881218] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.881248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.881280] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.881309] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.881338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.881366] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.881393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.881400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.881427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.881433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.881461] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.881488] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.881514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.881541] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.881568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.881594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.881662] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.881693] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.881723] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.881759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.881794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.882094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.882117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.882137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.882157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.882175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.882196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.882217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.882238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.882258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.882276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.882294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.882316] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.882337] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.884379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.884399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.884417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.884436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.886000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.886020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.886038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.887613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.887650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.889523] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.892885] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.892939] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.892958] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.892983] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.893043] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.893063] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.893116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.893142] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.893190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.909995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.910037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.910080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.910127] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.910166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.910208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.910249] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.910290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.910331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.910371] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.910411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.910418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.910458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.910465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.910507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.910547] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.910587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.910628] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.910758] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.910815] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.910872] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.910923] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.910975] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.911031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.911087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.943084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  294.943131] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  294.943201] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  294.960234] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  294.960277] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  294.960309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  294.960347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.960380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.960412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.960450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.960490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.960529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.960572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.960613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.960745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.960798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.960849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.960938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.960996] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.961057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.961556] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.961576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.961598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.961676] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.961710] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.961747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.961781] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.961814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.961846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.961878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.961908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.961916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.961944] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.961951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.961980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.962009] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.962039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.962067] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.962096] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.962125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.962156] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.962186] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.962212] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.962245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.962279] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  294.962383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  294.962413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  294.962445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  294.962474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  294.962503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  294.962534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  294.962567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  294.962599] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  294.962663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.962694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  294.962724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  294.962759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  294.962791] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  294.964856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  294.964876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  294.964894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.964913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  294.966483] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  294.966502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  294.966520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  294.968082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  294.968103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  294.969972] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  294.973294] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  294.973349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  294.973389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  294.973440] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  294.973520] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  294.973560] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  294.973721] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  294.973765] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  294.973830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  294.990355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  294.990396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  294.990436] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  294.990477] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  294.990511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  294.990547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  294.990584] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  294.990625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  294.990744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  294.990792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  294.990843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  294.990856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.990902] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  294.990912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  294.990962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  294.991010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  294.991068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.991096] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  294.991129] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  294.991158] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  294.991186] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  294.991215] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  294.991245] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  294.991279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  294.991313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  295.023482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  295.023533] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.023606] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  295.040699] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  295.040742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  295.040773] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.040817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.040858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.040897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.040937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.040977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.041016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.041058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.041100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.041141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.041180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.041200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.041238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.041265] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  295.041294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.041508] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.041529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.041551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.041573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.041591] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.041666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.041699] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  295.041733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  295.041766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.041797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.041829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.041838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.041867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.041875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.041905] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.041936] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.041967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.041996] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  295.042030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.042060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.042092] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.042122] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  295.042152] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  295.042187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.042222] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  295.042325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.042356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.042387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.042413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.042442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.042473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.042506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.042538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.042570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.042596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.042650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.042683] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  295.042715] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.044784] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.044804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.044823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.044842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.046403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.046423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.046441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.047994] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.048014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.049885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.053183] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  295.053233] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.053271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  295.053322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.053387] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  295.053413] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  295.053469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.053500] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  295.053544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.070311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.070353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.070397] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.070443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.070483] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.070525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.070566] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  295.070607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  295.070736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.070791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.070842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.070856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.070904] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.070916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.070965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.071013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.071062] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.071106] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  295.071157] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.071204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.071254] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.071299] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  295.071340] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  295.071390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.071443] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  295.103393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  295.103440] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.103509] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  295.120544] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  295.120591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  295.120723] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.120785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.120836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.120886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.120933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.120981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.121030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.121087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.121120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.121153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.121182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.121211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.121266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.121302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  295.121340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.121576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.121596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.121670] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.121709] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.121742] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.121777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.121811] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  295.121843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  295.121875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.121906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.121936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.121944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.121974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.121982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.122012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.122041] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.122068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.122097] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  295.122130] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.122160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.122192] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.122222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  295.122247] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  295.122279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.122313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  295.122399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.122429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.122459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.122488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.122515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.122544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.122577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.122609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.122662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.122692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.122723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.122759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  295.122791] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.124856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.124877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.124895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.124914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.126485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.126505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.126523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.128084] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.128105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.130016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.133335] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  295.133379] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.133406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  295.133441] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.133506] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  295.133534] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  295.133601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.133693] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  295.133778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.150415] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.150454] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.150494] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.150535] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.150568] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.150604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.150726] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  295.150774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  295.150826] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.150875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.150924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.150936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.150981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.150992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.151039] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.151086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.151133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.151178] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  295.151224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.151269] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.151316] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.151360] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  295.151400] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  295.151451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.151504] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  295.183524] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  295.183572] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.183732] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  295.200732] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  295.200774] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  295.200806] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.200845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.200879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.200910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.200939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.200969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.201000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.201033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.201066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.201097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.201125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.201153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.201206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.201241] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  295.201277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.201832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.202301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.202322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.202347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.202365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.202382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.202401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.202426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.202451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.202476] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.202501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.202524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.202547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.202594] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  295.202967] [drm:drm_mode_addfb2] [FB:76]
>[  295.202996] [drm:drm_mode_addfb2] [FB:78]
>[  295.235059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  295.235164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  295.235235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  295.235303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  295.235315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  295.235373] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.235395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.235417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.235441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.235459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.235479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.235499] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.235518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.235536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.235553] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.235570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.235574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.235590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.235637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.235667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.235699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.235726] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.235752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.235786] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.235813] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.235842] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  295.235868] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.235897] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.235934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.235968] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.239361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.239382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.239400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.239417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.239434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.239457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.239483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.239508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.239533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.239556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.239579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.239663] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.239694] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.241777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.241800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.241822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.241847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.243419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.243440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.243459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.245012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.245032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.246903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.250211] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.250256] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.250283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.250319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.267066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.267116] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.267182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.300724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.300761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.300798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.300837] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.300868] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.300901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.300935] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.300973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.301014] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.301053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.301091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.301099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.301137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.301144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.301184] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.301223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.301262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.301301] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.301341] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.301380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.301420] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.301459] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.301498] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.301539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.301580] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.317182] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.317226] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.317294] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.334323] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.334361] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.334400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.334433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.334463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.334492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.334520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.334552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.334585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.334702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.334758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.334801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.334847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.334933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.334990] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.335029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.335393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.335420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.335451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.335484] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.335510] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.335539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.335566] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.335605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.335672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.335703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.335730] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.335740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.335767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.335775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.335805] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.335831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.335860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.335889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.335922] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.335951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.335982] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.336011] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.336039] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.336073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.336107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.336208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.336238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.336265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.336293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.336319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.336348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.336380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.336411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.336442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.336467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.336494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.336524] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.336554] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.338655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.338675] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.338693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.338712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.340288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.340308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.340325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.341903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.341926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.343789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.347134] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.347187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.347225] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.347251] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.347333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.347361] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.347401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.364266] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.364307] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.364346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.364387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.364420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.364456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.364492] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.364525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.364558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.364589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.364712] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.364727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.364774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.364787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.364836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.364884] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.364931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.364978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.365031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.365077] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.365126] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.365174] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.365220] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.365272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.365326] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.380781] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.380828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.380898] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.397896] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.397934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.397974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.398007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.398038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.398068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.398097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.398134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.398177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.398219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.398261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.398299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.398337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.398397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.398421] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.398446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.398725] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.398759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.398794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.398831] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.398863] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.398898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.398931] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.398963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.398994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.399023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.399053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.399060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.399088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.399095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.399125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.399154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.399183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.399212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.399244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.399274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.399305] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.399335] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.399364] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.399397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.399431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.399533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.399564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.399594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.399647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.399678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.399711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.399746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.399779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.399813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.399842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.399872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.399908] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.399940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.402006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.402027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.402050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.402074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.403757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.403778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.403796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.405344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.405365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.407237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.410514] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.410564] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.410596] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.410697] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.410924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.410950] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.410988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.427605] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.427681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.427721] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.427762] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.427795] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.427831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.427867] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.427901] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.427934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.427965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.427995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.428003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.428032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.428039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.428069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.428100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.428129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.428158] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.428193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.428223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.428255] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.428284] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.428312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.428347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.428383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.444101] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.444152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.444227] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.462434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.462472] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.462511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.462543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.462573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.462686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.462730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.462781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.462839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.462884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.462928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.462964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.463002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.463077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.463125] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.463177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.463698] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.463746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.463804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.463840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.463863] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.463888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.463912] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.463935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.463958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.463979] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.464000] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.464005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.464025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.464030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.464050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.464071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.464091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.464110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.464134] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.464153] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.464174] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.464193] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.464213] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.464236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.464262] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.464326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.464348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.464369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.464390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.464410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.464431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.464454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.464476] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.464498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.464517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.464536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.464561] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.464583] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.466688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.466709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.466727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.466747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.468315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.468336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.468354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.469921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.469942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.471813] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.475089] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.475122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.475141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.475167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.475248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.475275] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.475315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.492191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.492234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.492277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.492324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.492364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.492406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.492446] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.492487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.492528] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.492569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.492683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.492698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.492749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.492762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.492812] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.492859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.492906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.492948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.493002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.493044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.493093] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.493134] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.493179] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.493226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.493278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.508677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.508723] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.508795] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.525846] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.525888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.525933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.525973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.526013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.526052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.526091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.526128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.526171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.526212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.526253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.526292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.526330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.526395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.526440] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.526487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.527236] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.527259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.527283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.527310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.527333] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.527357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.527380] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.527403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.527427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.527450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.527472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.527477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.527500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.527504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.527528] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.527551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.527574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.527644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.527682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.527713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.527746] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.527774] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.527806] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.527841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.527877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.528263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.528295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.528323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.528352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.528379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.528408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.528442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.528474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.528505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.528531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.528558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.528592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.528649] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.530868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.530889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.530908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.530927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.532498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.532518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.532536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.534122] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.534143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.536035] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.539324] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.539356] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.539376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.539401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.539480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.539508] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.539548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.556455] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.556495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.556537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.556584] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.556713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.556773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.556829] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.556878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.556926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.556968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.557014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.557027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.557070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.557082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.557128] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.557173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.557214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.557259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.557309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.557353] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.557402] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.557447] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.557492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.557539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.557591] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.572962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.573013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.573088] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.590142] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.590179] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.590218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.590251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.590282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.590311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.590340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.590371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.590405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.590436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.590467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.590495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.590533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.590653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.590701] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.590754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.591251] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.591295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.591340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.591388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.591428] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.591471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.591514] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.591555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.591634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.591664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.591696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.591705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.591735] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.591743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.591774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.591804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.591836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.591865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.591895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.591925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.591956] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.591983] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.592011] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.592040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.592074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.592176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.592207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.592238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.592268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.592297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.592328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.592361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.592394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.592426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.592455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.592483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.592517] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.592548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.594642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.594662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.594680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.594700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.596276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.596298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.596317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.597882] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.597903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.599778] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.603025] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.603057] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.603076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.603101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.603190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.603229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.603288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.620125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.620166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.620206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.620247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.620280] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.620316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.620351] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.620385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.620417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.620448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.620478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.620485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.620514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.620521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.620551] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.620580] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.620690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.620732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.620784] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.620827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.620876] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.620918] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.620963] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.621019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.621074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.636692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.636743] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.636819] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.653763] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.653805] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.653850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.653890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.653930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.653969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.654009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.654048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.654090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.654132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.654173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.654212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.654251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.654315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.654361] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.654408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.654964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.655013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.655062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.655097] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.655125] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.655157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.655187] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.655217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.655245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.655274] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.655300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.655307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.655334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.655340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.655369] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.655395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.655423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.655449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.655480] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.655506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.655536] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.655561] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.655616] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.655646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.655681] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.655769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.655796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.655825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.655851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.655879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.655906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.655938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.655969] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.656000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.656025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.656053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.656083] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.656113] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.658188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.658209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.658228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.658247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.659831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.659852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.659871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.661430] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.661451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.663326] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.666660] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.666709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.666740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.666780] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.666918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.666978] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.667072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.683834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.683875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.683914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.683954] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.683987] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.684023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.684058] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.684092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.684124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.684155] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.684185] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.684192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.684221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.684228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.684258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.684298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.684339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.684380] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.684421] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.684460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.684503] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.684544] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.684584] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.684672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.684712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.700318] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.700368] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.700459] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.717417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.717455] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.717494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.717527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.717557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.717587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.717752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.717798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.717850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.717901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.717950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.717990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.718033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.718117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.718171] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.718226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.718649] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.718672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.718699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.718736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.718777] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.718808] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.718839] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.718869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.718891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.718908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.718925] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.718930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.718946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.718950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.718967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.718984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.719000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.719016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.719036] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.719052] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.719069] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.719085] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.719101] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.719120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.719141] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.719203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.719221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.719239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.719256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.719279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.719302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.719328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.719352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.719377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.719400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.719423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.719447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.719471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.721563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.721602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.721621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.721640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.723207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.723230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.723253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.724812] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.724834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.726704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.730017] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.730064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.730094] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.730132] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.730224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.730262] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.730317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.747091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.747131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.747171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.747218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.747259] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.747301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.747343] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.747383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.747425] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.747465] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.747505] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.747513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.747553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.747560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.747675] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.747723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.747768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.747812] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.747859] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.747904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.747951] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.747993] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.748036] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.748089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.748146] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.763664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.763710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.763782] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.780795] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.780832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.780871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.780904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.780934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.780962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.780990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.781027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.781070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.781112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.781153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.781192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.781231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.781296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.781341] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.781388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.781999] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.782023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.782048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.782074] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.782094] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.782116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.782138] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.782159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.782179] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.782198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.782216] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.782222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.782240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.782244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.782264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.782281] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.782300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.782317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.782339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.782357] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.782378] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.782395] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.782414] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.782435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.782459] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.782527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.782547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.782565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.782617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.782644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.782673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.782704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.782734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.782763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.782789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.782815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.782847] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.782877] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.785177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.785198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.785216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.785235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.786809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.786830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.786848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.788406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.788427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.790300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.793645] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.793697] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.793729] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.793771] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.793917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.793982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.794081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.810811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.810852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.810892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.810932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.810965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.811000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.811036] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.811069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.811101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.811132] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.811162] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.811170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.811200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.811206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.811237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.811267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.811296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.811325] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.811359] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.811388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.811419] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.811449] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.811477] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.811512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.811548] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.827291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.827342] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.827433] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.844403] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.844440] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.844480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.844513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.844544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.844574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.844684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.844732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.844790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.844842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.845154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.845186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.845215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.845269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.845306] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.845343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.845558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.845625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.845663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.845700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.845729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.845762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.845792] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.845823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.846024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.846051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.846080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.846087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.846115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.846121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.846150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.846176] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.846205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.846230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.846261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.846286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.846315] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.846341] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.846369] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.846398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.846431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.846539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.846565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.846629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.846658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.846687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.846716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.846749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.846782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.846815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.846842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.846871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.846906] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.846935] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.849253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.849276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.849299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.849323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.850901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.850922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.850941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.852499] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.852520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.854372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.857683] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.857727] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.857759] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.857800] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.857920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.857973] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.858053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.874806] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.874846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.874885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.874932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.874972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.875014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.875056] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.875097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.875138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.875178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.875218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.875226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.875266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.875272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.875314] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.875354] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.875395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.875435] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.875476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.875516] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.875558] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.875649] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.875701] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.875755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.875807] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.891311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.891358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.891446] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.908402] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.908440] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.908479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.908512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.908543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.908573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.908686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.908732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.908787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.908839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.908893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.908920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.908948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.909002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.909038] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.909075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.909360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.909380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.909401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.909423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.909442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.909461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.909480] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.909499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.909516] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.909533] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.909550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.909554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.909617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.909627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.909659] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.909686] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.909716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.909742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.909775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.909802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.909832] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.909859] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.909889] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.909920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.909954] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.910058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.910086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.910115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.910141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.910169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.910196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.910227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.910258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.910290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.910315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.910342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.910372] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.910402] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.912469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.912490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.912512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.912536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.914153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.914176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.914198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.915760] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.915784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.917641] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.920988] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.921041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.921072] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.921097] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.921173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.921201] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.921241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.938125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.938166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.938205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.938252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.938292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.938334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.938375] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.938416] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.938453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.938493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.938533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.938541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.938580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.938665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.938722] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.938777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.938830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.938880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.938936] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.938985] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.939038] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.939086] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.939135] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.939190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.939244] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.954655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  295.954720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  295.954789] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  295.971825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  295.971862] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  295.971902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.971934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.971964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.971993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.972021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.972052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.972086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.972126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.972168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.972207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.972247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.972300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.972335] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.972370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.972779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  295.972828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.972878] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  295.972932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  295.972977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  295.973025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.973072] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  295.973114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  295.973158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  295.973197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.973242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.973250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.973278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.973285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  295.973314] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  295.973340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  295.973367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.973392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.973424] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  295.973450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.973479] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  295.973504] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  295.973532] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  295.973561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.973621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  295.973724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.973755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  295.973787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  295.973818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  295.973848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  295.973878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  295.973912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  295.973945] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  295.973977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  295.974003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  295.974031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  295.974062] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  295.974093] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  295.976196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.976219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.976238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.976257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.977824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  295.977845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  295.977863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.979422] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.979443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  295.981315] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.984545] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  295.984632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  295.984661] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  295.984704] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.984803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  295.984834] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  295.984888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.001665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.001705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.001745] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.001786] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.001819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.001855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.001895] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.001936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.001978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.002018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.002058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.002066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.002105] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.002112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.002153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.002194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.002234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.002275] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.002316] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.002356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.002398] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.002438] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.002479] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.002521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.002564] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.018153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.018199] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.018270] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.035265] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.035302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.035342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.035382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.035421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.035461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.035500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.035540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.035582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.035705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.035755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.035796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.035838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.035917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.035969] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.036025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.036540] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.036582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.036677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.036722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.036754] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.036794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.036833] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.036868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.036904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.036937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.036968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.036977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.037008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.037016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.037048] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.037077] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.037110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.037141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.037176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.037205] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.037237] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.037266] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.037297] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.037330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.037367] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.037484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.037516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.037548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.037607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.037637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.037673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.037714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.037747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.037779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.037806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.037835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.037870] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.037899] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.039969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.039990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.040008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.040027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.041617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.041638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.041660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.043225] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.043250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.045108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.048429] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.048482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.048514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.048555] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.049012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.049040] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.049078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.065542] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.065665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.065727] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.065787] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.065836] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.065888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.065940] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.065991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.066040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.066087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.066133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.066145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.066190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.066201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.066248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.066294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.066341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.066386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.066429] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.066458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.066490] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.066520] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.066549] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.066606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.066643] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.082035] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.082082] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.082155] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.099189] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.099231] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.099275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.099316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.099356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.099395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.099435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.099474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.099517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.099558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.099692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.099745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.099796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.099885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.099943] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.100003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.100394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.100419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.100443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.100469] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.100492] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.100516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.100539] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.100563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.100639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.100674] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.100708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.100718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.100749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.100757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.100789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.100820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.100851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.100882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.100916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.100947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.100978] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.101007] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.101038] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.101071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.101106] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.101211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.101242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.101272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.101303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.101333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.101360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.101393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.101426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.101458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.101488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.101516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.101550] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.101606] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.103686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.103708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.103727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.103747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.105308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.105329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.105347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.106911] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.106932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.108805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.112111] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.112162] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.112195] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.112236] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.112384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.112459] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.112538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.129229] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.129269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.129308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.129349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.129382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.129417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.129453] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.129487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.129519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.129550] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.129660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.129673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.129719] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.129732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.129780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.129831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.129873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.129911] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.129956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.129994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.130037] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.130425] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.130463] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.130507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.130554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.145745] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.145792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.145880] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.162890] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.162927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.162967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.163000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.163031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.163061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.163090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.163121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.163154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.163185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.163216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.163243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.163270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.163323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.163358] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.163393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.164054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.164079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.164103] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.164130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.164153] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.164177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.164200] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.164224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.164247] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.164270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.164293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.164298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.164321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.164325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.164349] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.164372] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.164395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.164418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.164441] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.164464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.164488] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.164511] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.164534] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.164559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.164630] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.164738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.165037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.165067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.165097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.165125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.165155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.165189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.165221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.165252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.165278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.165306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.165337] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.165368] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.167437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.167458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.167476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.167495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.169083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.169102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.169120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.170784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.170805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.172667] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.175923] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.175954] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.175972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.175997] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.176086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.176124] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.176184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.192997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.193041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.193083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.193130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.193170] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.193212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.193253] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.193294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.193335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.193375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.193415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.193422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.193461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.193468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.193509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.193550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.193671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.193720] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.193774] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.193821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.193870] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.193914] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.193962] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.194017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.194072] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.209546] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.209624] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.209695] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.226745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.226782] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.226821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.226853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.226884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.226912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.226940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.226972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.227005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.227036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.227066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.227094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.227121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.227174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.227209] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.227245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.227679] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.227734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.227791] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.227849] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.227897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.227949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.227996] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.228028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.228059] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.228089] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.228118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.228126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.228154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.228161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.228190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.228225] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.228252] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.228279] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.228308] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.228334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.228363] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.228390] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.228414] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.228444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.228475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.228608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.228642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.228672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.228702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.228733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.228764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.228798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.228831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.228862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.228892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.228919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.228953] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.228985] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.231072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.231094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.231113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.231132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.232699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.232727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.232745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.234308] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.234329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.236200] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.239475] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.239517] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.239544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.239649] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.239787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.239842] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.239928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.256578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.256652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.256692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.256736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.256777] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.256819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.256860] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.256900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.256942] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.256982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.257022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.257030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.257070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.257077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.257118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.257159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.257200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.257240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.257281] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.257321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.257363] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.257404] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.257444] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.257487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.257530] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.273081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.273129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.273203] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.290251] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.290289] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.290328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.290361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.290392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.290422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.290450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.290481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.290515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.290547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.290665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.290716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.290764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.290853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.291152] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.291213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.291468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.291488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.291510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.291536] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.291607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.291640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.291676] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.291708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.291741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.291771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.291802] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.291811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.291839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.292004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.292034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.292065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.292096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.292123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.292155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.292185] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.292215] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.292244] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.292273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.292306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.292340] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.292448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.292476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.292503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.292530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.292568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.292623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.292661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.292696] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.292729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.292758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.292788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.292823] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.292856] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.295143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.295164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.295182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.295200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.296781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.296802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.296822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.298383] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.298404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.300276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.303537] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.303585] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.303604] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.303629] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.303709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.303736] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.303775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.320655] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.320699] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.320742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.320788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.320828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.320870] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.320911] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.320951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.320992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.321032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.321072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.321079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.321119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.321126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.321167] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.321207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.321248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.321288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.321328] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.321368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.321411] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.321451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.321492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.321534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.321637] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.337157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.337204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.337276] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.354326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.354364] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.354402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.354435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.354466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.354495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.354523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.354554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.354674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.354735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.354784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.355103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.355148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.355228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.355266] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.355302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.355810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.355834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.355858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.355885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.355908] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.355932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.355955] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.355978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.355999] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.356022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.356045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.356050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.356071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.356076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.356099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.356122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.356145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.356168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.356191] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.356213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.356237] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.356261] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.356284] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.356308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.356334] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.356402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.356425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.356449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.356472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.356496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.356519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.356544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.356620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.356659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.356691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.356724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.356761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.356793] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.358863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.358884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.358902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.358922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.360492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.360512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.360530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.362133] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.362154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.364036] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.367339] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.367388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.367419] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.367458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.367657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.367722] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.367814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.384461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.384502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.384541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.384669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.384720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.384774] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.384829] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.384880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.384930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.384978] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.385025] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.385039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.385083] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.385094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.385140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.385186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.385231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.385272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.385321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.385367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.385408] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.385438] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.385469] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.385503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.385537] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.400968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.401016] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.401089] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.418130] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.418166] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.418205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.418238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.418268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.418297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.418325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.418355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.418389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.418420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.418450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.418477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.418505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.418558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.418665] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.418727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.419370] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.419391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.419413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.419436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.419454] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.419473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.419493] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.419511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.419529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.419546] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.419615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.419625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.419657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.419666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.419696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.419726] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.419757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.419786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.419820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.419849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.419882] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.420116] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.420144] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.420177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.420212] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.420320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.420349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.420377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.420405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.420432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.420461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.420492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.420521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.420562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.420617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.420649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.420685] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.420717] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.422961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.422982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.423000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.423019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.424701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.424721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.424739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.426297] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.426318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.428181] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.431446] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.431479] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.431503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.431533] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.431694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.431738] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.431805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.448550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.448624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.448664] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.448710] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.448750] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.448792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.448834] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.448874] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.448915] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.448956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.448996] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.449003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.449041] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.449048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.449088] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.449129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.449169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.449210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.449251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.449291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.449333] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.449374] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.449415] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.449457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.449500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.465050] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.465097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.465168] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.482238] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.482275] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.482315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.482347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.482378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.482407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.482435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.482466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.482500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.482531] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.482664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.482710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.482757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.482840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.483162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.483219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.483635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.483658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.483683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.483721] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.483753] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.483787] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.483820] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.483850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.483870] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.483888] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.483906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.483911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.483929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.483933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.483951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.483976] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.484001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.484026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.484051] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.484076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.484103] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.484128] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.484153] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.484180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.484207] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.484280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.484305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.484331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.484357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.484382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.484407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.484434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.484461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.484488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.484513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.484538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.484600] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.484632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.486707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.486728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.486746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.486766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.488339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.488359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.488377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.489939] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.489959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.491830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.495145] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.495192] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.495221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.495265] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.495399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.495457] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.495546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.512261] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.512301] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.512340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.512382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.512414] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.512450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.512486] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.512519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.512552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.512663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.512706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.512722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.512765] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.512777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.512823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.512866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.512911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.512952] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.513003] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.513044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.513093] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.513132] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.513175] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.513220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.513268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.528769] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.528816] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.528905] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.545910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.545948] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.545988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.546021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.546052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.546082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.546112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.546144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.546178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.546210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.546242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.546270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.546298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.546352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.546387] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.546424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.546907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.546940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.546972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.547008] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.547036] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.547067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.547096] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.547126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.547154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.547182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.547210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.547217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.547244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.547251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.547279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.547305] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.547332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.547357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.547389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.547414] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.547444] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.547469] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.547496] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.547525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.547584] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.547688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.547715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.547744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.547770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.547798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.547825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.547857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.547888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.547919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.547944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.547971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.548002] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.548032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.550137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.550158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.550176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.550194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.551769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.551790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.551808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.553370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.553390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.555261] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.558536] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.558614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.558646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.558688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.558833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.558897] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.558996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.575727] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.575764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.575802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.575841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.575878] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.575918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.575957] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.575997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.576032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.576071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.576110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.576117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.576156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.576163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.576201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.576240] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.576280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.576318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.576356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.576402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.576425] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.576445] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.576463] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.576483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.576505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.592201] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.592248] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.592335] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.609354] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.609391] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.609430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.609464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.609494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.609524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.609637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.609683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.609738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.609789] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.609838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.609880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.609932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.609986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.610021] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.610057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.610349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.610369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.610393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.610419] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.610442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.610466] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.610490] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.610513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.610534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.610604] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.610639] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.610648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.610678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.610686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.610717] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.610745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.610777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.610804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.610838] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.610865] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.610897] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.610924] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.610951] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.610984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.611019] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.611120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.611150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.611177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.611206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.611232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.611261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.611293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.611324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.611355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.611380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.611408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.611438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.611468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.613555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.613602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.613620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.613640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.615219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.615245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.615270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.616826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.616848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.618719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.622053] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.622106] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.622139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.622181] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.622324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.622378] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.622462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.639171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.639214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.639257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.639304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.639345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.639386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.639427] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.639468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.639509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.639549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.639669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.639683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.639736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.639749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.639800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.639845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.639895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.639938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.639989] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.640030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.640078] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.640118] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.640162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.640213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.640267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.655685] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.655732] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.655802] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.672854] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.672892] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.672931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.672964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.672994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.673023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.673051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.673082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.673116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.673147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.673178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.673215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.673254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.673319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.673364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.673411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.673982] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.674031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.674091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.674127] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.674155] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.674187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.674217] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.674247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.674275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.674304] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.674330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.674338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.674364] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.674371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.674400] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.674426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.674454] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.674479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.674511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.674536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.674591] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.674618] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.674648] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.674677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.674712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.674818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.674846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.674874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.674901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.674929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.674956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.674988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.675019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.675050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.675076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.675104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.675134] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.675165] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.677224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.677245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.677263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.677282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.678855] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.678875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.678897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.680458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.680479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.682349] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.685675] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.685725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.685760] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.685806] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.685940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.686000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.686088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.702803] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.702847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.702890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.702936] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.702976] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.703018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.703060] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.703100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.703141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.703182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.703221] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.703229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.703267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.703274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.703316] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.703357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.703397] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.703438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.703478] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.703518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.703611] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.703663] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.703714] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.703759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.703796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.719263] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.719311] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.719381] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.736403] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.736440] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.736479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.736512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.736542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.736931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.736971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.737011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.737054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.737095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.737137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.737175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.737214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.737277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.737323] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.737374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.738035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.738067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.738098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.738130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.738157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.738185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.738213] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.738239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.738265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.738289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.738312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.738319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.738342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.738347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.738371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.738402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.738421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.738447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.738475] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.738502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.738531] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.738594] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.738632] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.738665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.738706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.739062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.739097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.739127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.739159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.739188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.739220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.739256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.739290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.739325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.739354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.739383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.739424] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.739455] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.741543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.741580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.741599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.741618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.743195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.743217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.743236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.744806] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.744827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.746700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.750023] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.750073] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.750103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.750143] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.750241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.750282] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.750340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.767079] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.767118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.767157] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.767198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.767231] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.767267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.767303] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.767336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.767369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.767400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.767429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.767437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.767466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.767472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.767503] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.767532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.767653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.767703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.767757] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.767805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.767855] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.767902] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.767949] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.768005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.768040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.783652] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.783699] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.783769] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.800797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.800835] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.800874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.800907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.800938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.800967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.800996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.801027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.801061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.801092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.801123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.801151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.801178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.801232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.801267] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.801303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.801768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.801809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.801853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.801899] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.801938] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.801979] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.802021] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.802060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.802099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.802136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.802172] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.802181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.802216] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.802225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.802261] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.802298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.802335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.802370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.802407] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.802443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.802482] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.802518] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.802583] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.802630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.802666] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.802770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.802801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.802831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.802857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.802887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.802914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.802948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.802981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.803013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.803042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.803071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.803105] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.803137] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.805218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.805240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.805259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.805278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.806854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.806874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.806892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.808452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.808473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.810344] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.813659] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.813710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.813742] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.813784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.813919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.813958] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.814017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.830778] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.830814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.830851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.830889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.830920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.830954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.830988] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.831019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.831049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.831078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.831105] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.831113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.831139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.831146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.831173] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.831201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.831228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.831255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.831287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.831325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.831366] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.831405] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.831441] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.831483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.831525] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.847274] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.847321] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.847391] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.866085] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.866123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.866164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.866197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.866228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.866259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.866288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.866326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.866369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.866411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.866452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.866491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.866528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.866686] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.866747] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.866808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.867256] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.867300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.867344] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.867387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.867413] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.867441] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.867472] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.867503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.867535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.867607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.867651] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.867661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.867699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.867709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.867748] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.867783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.867819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.867853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.867896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.867924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.867957] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.867983] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.868014] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.868045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.868079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.868185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.868214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.868244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.868271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.868299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.868328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.868360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.868393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.868424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.868451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.868479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.868510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.868567] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.870632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.870653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.870671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.870690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.872260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.872280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.872298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.873860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.873880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.875749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.879057] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.879107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.879149] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.879183] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.879300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.879352] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.879431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.896155] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.896196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.896235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.896276] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.896309] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.896345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.896381] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.896414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.896447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.896477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.896507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.896515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.896626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.896638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.896686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.896730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.896777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.896819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.896869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.896910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.896960] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.897001] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.897047] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.897092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.897146] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.912703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.912750] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.912821] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.931726] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.931768] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.931813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.931854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.931894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.931933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.931973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.932019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.932056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.932088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.932118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.932145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.932171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.932222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.932257] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.932292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.932756] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.932800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.932850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.932903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.932943] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.932990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.933042] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.933079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.933112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.933145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.933176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.933184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.933216] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.933224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.933258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.933288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.933321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.933351] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.933388] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.933419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.933453] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.933484] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.933516] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.933584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.933627] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.933748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.933782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.933816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.933848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.933881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.933913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.933951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.933989] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.934026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.934056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.934095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.934125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.934155] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  296.936221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.936242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.936260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.936279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.937853] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  296.937873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  296.937891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.939447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.939468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.941339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.944642] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.944689] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  296.944718] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  296.944757] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  296.944894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.944954] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.945047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.961800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.961840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.961880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.961920] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.961954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.961990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.962026] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.962059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.962092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.962123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.962154] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.962161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.962191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.962197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.962228] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.962257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.962287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.962322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.962364] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.962404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.962446] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.962487] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.962528] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.962609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.962649] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.978252] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  296.978300] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  296.978369] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  296.995403] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  296.995441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  296.995480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.995513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.995599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.995654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.995699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.995749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.995803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.996145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.996180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.996210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.996240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.996273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  296.996295] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  296.996317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.996501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  296.996520] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  296.996589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  296.996631] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  296.996659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  296.996695] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  296.996725] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  296.996756] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  296.996785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  296.996815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  296.997055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  296.997063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.997094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  296.997101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  296.997131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  296.997158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  296.997186] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  296.997212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  296.997243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  296.997268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  296.997298] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  296.997323] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  296.997350] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  296.997380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  296.997412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  296.997523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  296.997587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  296.997620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  296.997646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  296.997676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  296.997704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  296.997739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  296.997771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  296.997803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  296.997830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  296.997859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  296.997894] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  296.997922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.000236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.000257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.000275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.000294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.001869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.001888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.001906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.003455] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.003476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.005348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.008592] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.008622] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.008641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.008667] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.008756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.008794] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.008854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.025751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.025791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.025830] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.025871] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.025903] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.025939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.025974] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.026007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.026040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.026071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.026101] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.026108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.026138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.026144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.026175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.026204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.026234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.026262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.026296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.026326] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.026363] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.026405] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.026445] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.026488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.026532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.042214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.042261] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.042332] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.059391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.059428] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.059468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.059501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.059531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.059642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.059686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.059736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.059790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.060131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.060172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.060212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.060250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.060313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.060359] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.060406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.060952] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.060974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.060996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.061019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.061037] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.061057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.061077] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.061096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.061115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.061132] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.061149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.061154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.061170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.061174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.061190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.061207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.061223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.061239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.061259] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.061275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.061292] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.061308] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.061323] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.061343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.061364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.061427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.061445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.061462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.061484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.061508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.061574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.061612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.061645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.061679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.061705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.061734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.061766] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.061798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.063866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.063887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.063905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.063924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.065522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.065558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.065577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.067139] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.067162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.069059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.072372] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.072425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.072457] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.072498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.072904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.072946] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.072984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.089475] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.089518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.089640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.089700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.089745] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.089797] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.089844] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.089893] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.089937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.089981] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.090022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.090033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.090075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.090085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.090130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.090170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.090213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.090253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.090301] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.090340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.090391] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.090418] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.090447] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.090476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.090509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.105973] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.106023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.106097] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.123146] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.123183] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.123222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.123255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.123285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.123323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.123363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.123402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.123445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.123487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.123528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.123644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.123693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.123782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.124187] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.124223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.124439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.124462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.124487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.124513] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.124582] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.124620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.124651] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.124684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.124713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.124743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.124770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.124778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.124805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.125024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.125051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.125079] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.125104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.125130] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.125157] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.125183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.125211] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.125235] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.125261] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.125290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.125322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.125417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.125443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.125469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.125494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.125520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.125593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.125627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.125660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.125692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.125719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.125747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.125782] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.125811] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.128121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.128144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.128167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.128192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.129768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.129791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.129813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.131369] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.131393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.133273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.136576] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.136619] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.136646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.136680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.136768] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.136803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.136855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.153724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.153769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.153811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.153858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.153897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.153939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.153979] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.154020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.154061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.154101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.154141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.154149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.154189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.154196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.154237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.154277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.154318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.154358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.154397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.154436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.154479] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.154519] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.154626] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.154681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.154741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.170200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.170247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.170318] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.188472] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.188509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.188639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.188693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.188743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.188791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.188838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.188888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.188942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.188992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.189043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.189089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.189134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.189220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.189277] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.189335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.189769] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.189795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.189820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.189846] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.189869] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.189893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.189916] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.189939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.189960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.189983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.190006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.190010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.190032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.190037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.190059] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.190082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.190105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.190128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.190150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.190173] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.190197] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.190220] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.190243] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.190268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.190293] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.190361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.190385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.190408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.190432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.190456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.190479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.190504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.190579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.190615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.190648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.190681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.190718] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.190750] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.192829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.192849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.192867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.192889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.194454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.194474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.194492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.196088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.196108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.197987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.201304] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.201359] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.201399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.201450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.201657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.201728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.201834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.218397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.218434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.218471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.218510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.218632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.218684] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.218739] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.218788] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.218837] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.218885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.218932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.218944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.218988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.218999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.219046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.219091] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.219132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.219185] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.219217] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.219246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.219277] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.219306] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.219332] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.219364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.219398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.234911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.234956] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.235043] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.252093] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.252130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.252170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.252203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.252234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.252264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.252293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.252324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.252358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.252390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.252421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.252450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.252478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.252617] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.252676] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.252734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.253197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.253232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.253267] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.253304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.253329] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.253350] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.253372] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.253392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.253412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.253430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.253448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.253453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.253471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.253475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.253493] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.253513] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.253578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.253608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.253641] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.253671] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.253704] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.253734] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.253764] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.253798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.253833] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.253937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.253967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.253994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.254024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.254052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.254080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.254114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.254146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.254178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.254208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.254236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.254270] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.254301] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.256371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.256392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.256411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.256430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.258000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.258020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.258038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.259614] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.259635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.261509] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.264854] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.264907] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.264940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.264982] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.265091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.265133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.265194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.281999] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.282039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.282078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.282120] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.282153] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.282189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.282226] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.282267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.282309] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.282349] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.282389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.282397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.282437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.282444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.282485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.282526] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.282631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.282689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.282737] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.282781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.282828] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.282869] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.282911] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.282957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.283004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.298505] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.298588] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.298663] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.315711] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.315749] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.315789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.315822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.315852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.315881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.315920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.315959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.316002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.316043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.316085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.316124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.316161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.316225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.316270] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.316317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.316635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.316826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.316863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.316900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.316931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.316965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.316998] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.317030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.317063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.317093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.317122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.317130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.317158] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.317165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.317195] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.317224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.317254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.317282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.317315] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.317345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.317376] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.317405] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.317434] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.317467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.317501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.317629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.317867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.317896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.317924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.317952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.317981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.318012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.318042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.318071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.318098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.318124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.318155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.318185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.320265] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.320288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.320306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.320325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.321912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.321936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.321959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.323520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.323558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.325429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.328718] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.328749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.328768] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.328794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.328884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.328922] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.328983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.345829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.345868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.345908] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.345955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.345995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.346037] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.346078] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.346119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.346161] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.346201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.346241] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.346248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.346288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.346295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.346336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.346376] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.346417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.346457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.346498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.346627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.346686] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.346739] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.346788] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.346845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.346902] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.362345] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.362392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.362463] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.379510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.379578] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.379617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.379650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.379680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.379710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.379739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.379778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.379830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.379868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.379907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.379944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.379979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.380040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.380083] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.380127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.380466] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.380504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.380604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.380660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.380709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.380762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.380812] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.380865] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.380897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.380928] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.380958] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.380968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.380996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.381004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.381034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.381064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.381095] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.381124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.381158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.381187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.381218] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.381247] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.381277] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.381311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.381345] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.381430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.381461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.381491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.381542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.381572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.381602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.381636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.381669] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.381702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.381732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.381758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.381792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.381825] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.383896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.383917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.383935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.383954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.385565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.385587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.385605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.387171] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.387192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.389058] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.392298] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.392330] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.392349] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.392375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.392465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.392504] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.392622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.409435] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.409479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.409521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.409649] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.409696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.409749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.409797] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.409846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.409891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.409936] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.409976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.409988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.410029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.410039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.410084] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.410124] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.410167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.410207] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.410255] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.410294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.410340] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.410380] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.410422] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.410467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.410519] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.425938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.425985] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.426055] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.444481] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.444518] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.444643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.444690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.444738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.444782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.444826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.444870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.444921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.444971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.445020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.445061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.445104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.445189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.445243] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.445298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.445710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.445743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.445774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.445809] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.445835] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.445865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.445892] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.445920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.445946] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.445972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.445998] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.446005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.446029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.446036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.446062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.446086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.446112] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.446135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.446164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.446188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.446215] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.446238] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.446264] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.446294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.446325] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.446422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.446448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.446474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.446499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.446564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.446598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.446631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.446665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.446697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.446724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.446752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.446788] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.446817] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.448890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.448911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.448929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.448948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.450512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.450547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.450565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.452123] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.452144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.454029] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.457353] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.457406] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.457439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.457481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.457649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.457690] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.457751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.474449] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.474490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.474610] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.474668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.474712] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.474763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.474809] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.474856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.474900] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.474944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.474984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.474996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.475036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.475047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.475091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.475131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.475174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.475213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.475264] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.475304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.475349] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.475389] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.475431] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.475476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.475527] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.490968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.491019] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.491110] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.508143] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.508179] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.508219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.508252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.508283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.508313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.508343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.508374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.508408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.508439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.508470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.508498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.508601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.508683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.508731] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.508779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.509241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.509270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.509300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.509332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.509357] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.509385] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.509413] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.509440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.509465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.509490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.509561] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.509576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.509614] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.509624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.509667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.509694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.509724] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.509751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.509784] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.509811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.509842] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.509869] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.509897] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.509929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.509963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.510065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.510092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.510121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.510147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.510175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.510202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.510234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.510265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.510297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.510323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.510350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.510380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.510411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.512473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.512493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.512566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.512601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.514167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.514186] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.514204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.515770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.515790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.517659] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.520923] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.520953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.520976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.521007] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.521097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.521136] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.521197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.538038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.538082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.538125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.538171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.538212] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.538254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.538294] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.538335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.538376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.538417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.538457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.538465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.538503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.538581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.538637] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.538687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.538740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.538785] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.538839] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.538883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.538934] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.538976] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.539022] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.539076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.539127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.554523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.554603] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.554674] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.571727] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.571765] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.571804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.571836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.571866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.571895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.571933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.571972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.572015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.572063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.572095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.572123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.572149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.572208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.572251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.572295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.573038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.573086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.573120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.573156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.573184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.573216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.573246] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.573276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.573304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.573333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.573359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.573366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.573393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.573400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.573428] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.573454] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.573482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.573532] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.573566] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.573593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.573624] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.573651] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.573680] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.573715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.573750] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.574108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.574128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.574146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.574164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.574181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.574200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.574220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.574238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.574257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.574273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.574289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.574310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.574329] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.576381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.576402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.576421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.576440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.578030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.578051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.578068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.579727] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.579748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.581623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.584953] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.585005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.585038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.585080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.585221] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.585259] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.585319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.602039] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.602083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.602126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.602173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.602213] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.602254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.602295] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.602336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.602377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.602417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.602457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.602465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.602505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.602575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.602633] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.602686] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.602730] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.602767] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.602813] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.602850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.602893] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.602929] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.602968] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.603013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.603058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.618579] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.618627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.618697] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.637341] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.637383] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.637428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.637468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.637508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.637628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.637677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.637729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.637784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.637834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.637885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.637925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.637970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.638055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.638110] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.638166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.638679] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.638701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.638723] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.638747] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.638766] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.638786] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.638806] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.638825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.638843] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.638860] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.638877] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.638881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.638897] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.638901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.638918] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.638934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.638951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.638967] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.638986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.639003] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.639021] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.639037] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.639053] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.639072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.639094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.639158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.639176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.639193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.639210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.639226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.639244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.639263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.639282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.639300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.639322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.639345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.639370] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.639391] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.641454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.641475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.641494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.641572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.643145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.643167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.643186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.644753] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.644774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.646648] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.649969] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.650018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.650049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.650088] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.650226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.650287] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.650381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.667050] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.667090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.667130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.667171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.667207] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.667249] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.667291] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.667331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.667368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.667408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.667448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.667456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.667496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.667571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.667629] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.667677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.667728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.667772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.667825] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.667868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.667919] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.667962] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.668008] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.668062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.668116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.683621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.683664] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.683752] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.700782] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.700819] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.700859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.700892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.700922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.700952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.700981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.701013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.701047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.701078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.701109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.701137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.701164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.701218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.701254] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.701289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.701791] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.701854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.701885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.701911] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.701930] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.701952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.701974] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.701994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.702014] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.702033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.702051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.702057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.702074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.702079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.702097] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.702115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.702133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.702150] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.702172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.702189] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.702209] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.702226] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.702243] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.702264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.702288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.702355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.702375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.702394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.702412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.702430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.702449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.702470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.702490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.702548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.702576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.702603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.702636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.702665] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.704730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.704751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.704770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.704789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.706360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.706383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.706406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.707970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.707992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.709904] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.713142] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.713173] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.713195] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.713226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.713317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.713356] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.713416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.730274] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.730314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.730354] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.730396] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.730429] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.730465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.730501] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.730614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.730660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.730705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.730752] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.730764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.730806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.730818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.730865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.730911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.730957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.731003] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.731054] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.731100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.731139] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.731167] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.731194] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.731229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.731265] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.746771] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.746818] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.746889] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.763930] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.763966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.764006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.764039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.764069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.764099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.764127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.764158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.764192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.764223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.764254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.764282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.764310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.764363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.764399] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.764434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.764997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.765033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.765071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.765109] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.765139] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.765178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.765204] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.765230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.765256] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.765282] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.765307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.765314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.765338] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.765343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.765369] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.765395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.765418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.765443] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.765470] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.765495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.765550] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.765581] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.765609] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.765641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.765673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.765757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.765789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.765820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.765849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.765880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.765911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.765945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.765976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.765998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.766016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.766034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.766057] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.766078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.768128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.768149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.768168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.768187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.769752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.769772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.769790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.771337] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.771358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.773221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.776447] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.776478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.776556] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.776587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.776679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.776722] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.776786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.793564] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.793606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.793647] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.793691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.793729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.793770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.793809] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.793848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.793888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.793926] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.793965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.793972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.794011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.794017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.794057] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.794096] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.794135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.794174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.794213] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.794252] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.794293] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.794332] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.794371] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.794412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.794453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.810042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.810092] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.810180] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.827223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.827265] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.827309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.827350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.827389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.827429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.827468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.827516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.827630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.827681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.827726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.827755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.827782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.827834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.827875] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.827920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.828267] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.828305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.828344] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.828385] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.828421] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.828459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.828497] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.828569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.828601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.828630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.828658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.828666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.828693] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.828701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.828729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.828756] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.828783] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.828809] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.828840] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.828866] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.828894] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.828920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.828948] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.828980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.829016] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.829120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.829151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.829182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.829212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.829241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.829273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.829306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.829331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.829353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.829371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.829390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.829412] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.829432] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.831473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.831509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.831527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.831547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.833126] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.833147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.833165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.834734] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.834755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.836633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.839878] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.839911] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.839930] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.839956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.840038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.840065] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.840105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.856997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.857040] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.857083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.857130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.857170] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.857212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.857252] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.857293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.857334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.857374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.857414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.857422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.857461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.857468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.857509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.857630] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.857677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.857723] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.857772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.857815] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.857861] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.857905] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.857946] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.857994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.858048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.873499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.873581] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.873653] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.890702] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.890739] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.890778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.890811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.890849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.890889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.890928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.890967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.891010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.891051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.891092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.891131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.891169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.891233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.891279] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.891325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.891784] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.891821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.891856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.891881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.891901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.891924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.891946] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.891967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.891986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.892006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.892024] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.892029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.892046] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.892051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.892069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.892087] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.892105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.892123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.892144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.892162] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.892181] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.892198] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.892216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.892236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.892259] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.892316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.892336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.892355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.892373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.892392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.892411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.892432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.892451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.892471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.892518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.892547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.892579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.892608] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.894672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.894693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.894712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.894731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.896291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.896311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.896329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.897892] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.897913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.899785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.903089] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.903121] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.903140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.903166] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.903256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.903294] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.903354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.920189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.920233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.920276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.920323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.920363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.920405] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.920447] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.920488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.920605] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.920654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.920701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.920715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.920761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.920773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.920816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.920859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.920901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.920946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.920998] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.921044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.921092] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.921137] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.921181] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.921235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.921274] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.936699] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  297.936745] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  297.936817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  297.953851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  297.953888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  297.953927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.953967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.954007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.954046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.954085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.954124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.954175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.954211] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.954244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.954272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.954298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.954349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.954384] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.954418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.954987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.955031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.955080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.955132] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.955172] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.955215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.955245] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.955274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.955302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.955330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.955356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.955364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.955391] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.955398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.955427] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.955452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.955480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.955537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.955567] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.955597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.955629] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.955655] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.955685] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.955719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.955754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  297.955842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  297.955872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  297.955901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  297.955927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  297.955955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  297.955982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  297.956015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  297.956046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  297.956078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.956103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  297.956130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  297.956160] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  297.956190] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  297.958259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  297.958279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  297.958297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.958316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  297.959896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  297.959916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  297.959933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  297.961492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  297.961529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  297.963407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  297.966723] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  297.966769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  297.966797] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  297.966834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  297.966964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  297.967022] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  297.967110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  297.983821] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  297.983861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  297.983901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  297.983942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  297.983982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  297.984024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  297.984066] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  297.984107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  297.984148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  297.984188] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  297.984228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  297.984236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.984274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  297.984281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  297.984322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  297.984363] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  297.984403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  297.984443] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  297.984484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  297.984603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  297.984654] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  297.984705] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  297.984749] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  297.984809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  297.984845] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.000338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.000385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.000455] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.017562] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.017604] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.017648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.017688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.017728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.017767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.017806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.017845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.017888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.017929] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.017970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.018009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.018047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.018112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.018157] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.018204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.018614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.018646] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.018683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.018720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.018750] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.018784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.018817] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.018843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.018864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.018883] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.018901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.018907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.018925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.018930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.018948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.018966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.018984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.019002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.019023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.019041] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.019059] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.019077] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.019094] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.019115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.019138] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.019207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.019227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.019245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.019264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.019281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.019300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.019321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.019341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.019360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.019378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.019402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.019429] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.019456] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.021538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.021560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.021579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.021598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.023178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.023200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.023219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.024785] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.024806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.026676] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.029967] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.030010] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.030037] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.030072] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.030197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.030251] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.030335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.047102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.047142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.047182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.047223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.047256] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.047292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.047328] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.047362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.047394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.047425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.047455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.047462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.047491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.047570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.047615] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.047659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.047702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.047743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.047791] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.047832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.047881] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.047924] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.047966] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.048019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.048060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.063644] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.063691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.063779] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.080809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.080846] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.080886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.080919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.080950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.080980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.081010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.081041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.081075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.081106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.081137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.081165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.081193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.081246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.081281] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.081317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.081867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.081909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.081933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.081958] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.081978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.082000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.082025] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.082052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.082078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.082103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.082128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.082135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.082159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.082164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.082190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.082215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.082242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.082266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.082293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.082318] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.082346] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.082371] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.082397] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.082424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.082452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.082573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.082604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.082636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.082667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.082695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.082728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.082762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.082795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.082828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.082859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.082888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.082923] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.082950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.084989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.085012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.085035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.085059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.086645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.086666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.086684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.088243] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.088264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.090131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.093420] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.093468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.093568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.093630] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.093771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.093831] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.093917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.110580] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.110618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.110658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.110703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.110741] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.110782] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.110822] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.110861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.110901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.110940] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.110978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.110986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.111024] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.111031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.111071] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.111110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.111149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.111188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.111227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.111265] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.111306] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.111345] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.111384] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.111425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.111466] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.127072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.127120] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.127190] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.144213] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.144250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.144290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.144322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.144353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.144382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.144410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.144441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.144474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.144591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.144643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.144687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.144733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.144820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.144875] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.144931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.145354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.145374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.145398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.145425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.145447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.145472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.145541] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.145576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.145606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.145636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.145663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.145672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.145700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.145708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.145738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.145765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.145794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.145820] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.145853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.145879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.145908] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.145934] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.145962] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.145994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.146027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.146129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.146159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.146186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.146214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.146240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.146269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.146301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.146332] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.146363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.146388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.146415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.146445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.146477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.148569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.148589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.148607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.148626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.150185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.150205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.150223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.151786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.151806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.153669] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.156991] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.157043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.157075] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.157117] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.157228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.157271] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.157331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.174085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.174123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.174161] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.174199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.174237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.174278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.174318] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.174357] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.174397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.174436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.174474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.174553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.174606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.174618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.174672] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.174717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.174764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.174807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.174859] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.174901] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.174959] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.174985] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.175016] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.175046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.175080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.190639] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.190686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.190757] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.207795] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.207832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.207872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.207905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.207935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.207965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.207994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.208025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.208058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.208090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.208129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.208169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.208207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.208272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.208317] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.208364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.208863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.208894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.208928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.208964] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.208992] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.209024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.209053] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.209084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.209112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.209141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.209167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.209174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.209202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.209209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.209238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.209264] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.209292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.209317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.209348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.209373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.209403] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.209428] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.209456] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.209511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.209545] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.209650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.209677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.209707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.209733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.209760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.209787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.209820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.209852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.209883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.209908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.209937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.209967] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.209998] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.212080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.212101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.212119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.212139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.213716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.213737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.213755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.215305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.215326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.217197] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.220542] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.220595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.220628] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.220669] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.220776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.220818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.220879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.237665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.237705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.237744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.237785] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.237818] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.237854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.237889] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.237923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.237956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.237987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.238017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.238024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.238054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.238060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.238090] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.238120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.238149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.238188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.238230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.238271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.238313] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.238356] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.238380] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.238405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.238431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.254152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.254200] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.254289] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.271306] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.271343] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.271383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.271416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.271446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.271475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.271585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.271636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.271686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.271739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.271791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.271837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.271883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.271949] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.271986] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.272022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.272297] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.272318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.272341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.272365] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.272385] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.272406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.272426] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.272446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.272465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.272528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.272555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.272563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.272589] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.272598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.272625] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.272651] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.272677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.272703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.272734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.272762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.272793] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.272821] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.272848] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.272882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.272916] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.273004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.273035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.273065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.273094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.273114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.273133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.273155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.273175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.273196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.273214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.273232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.273254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.273275] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.275320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.275340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.275357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.275376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.276954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.276973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.276990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.278590] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.278610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.280473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.283835] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.283888] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.283920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.283962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.284099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.284165] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.284264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.300960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.300998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.301036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.301075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.301112] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.301152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.301191] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.301231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.301270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.301309] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.301347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.301354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.301393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.301400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.301439] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.301478] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.301601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.301648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.301697] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.301740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.301771] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.301798] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.301825] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.301857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.301890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.317466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.317546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.317634] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.334575] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.334612] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.334652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.334686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.334716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.334746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.334774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.334805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.334838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.334869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.334900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.334928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.334965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.335030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.335075] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.335122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.335471] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.335554] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.335587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.335625] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.335653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.335689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.335720] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.335752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.335781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.335811] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.335838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.335848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.335875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.335882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.335912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.335939] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.336241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.336268] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.336300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.336327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.336357] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.336384] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.336412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.336441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.336476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.336804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.336832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.336861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.336886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.336912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.336938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.336968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.336997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.337027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.337051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.337077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.337107] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.337133] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.339210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.339231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.339249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.339273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.340839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.340860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.340878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.342472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.342509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.344374] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.347684] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.347726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.347745] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.347770] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.347854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.347881] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.347921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.364812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.364849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.364887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.364925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.364955] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.364989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.365028] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.365067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.365107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.365146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.365184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.365192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.365230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.365237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.365277] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.365316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.365355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.365393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.365433] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.365471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.365598] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.365645] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.365691] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.365742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.365793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.381298] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.381343] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.381410] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.398454] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.398524] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.398564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.398597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.398627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.398656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.398685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.398715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.398749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.398781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.398812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.398840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.398867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.398916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.398936] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.398958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.399163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.399182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.399203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.399226] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.399244] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.399267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.399290] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.399314] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.399337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.399360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.399383] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.399387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.399410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.399414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.399438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.399461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.399537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.399567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.399598] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.399627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.399657] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.399684] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.399711] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.399741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.399774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.399877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.399906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.399935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.399965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.399994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.400024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.400058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.400091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.400124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.400155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.400185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.400219] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.400251] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.402304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.402327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.402350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.402374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.403951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.403971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.403989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.405607] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.405628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.407516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.410858] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.410910] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.410943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.410984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.411092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.411120] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.411160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.427969] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.428005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.428041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.428080] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.428114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.428155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.428195] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.428234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.428274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.428313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.428352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.428359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.428398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.428405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.428445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.428483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.428603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.428648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.428695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.428739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.428785] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.428827] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.428868] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.428914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.428965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.444534] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.444586] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.444661] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.461656] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.461693] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.461732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.461766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.461797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.461827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.461856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.461887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.461920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.461952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.461982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.462010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.462038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.462090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.462125] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.462161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.462393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.462412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.462433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.462455] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.462538] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.462569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.462600] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.462629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.462658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.462685] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.462712] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.462720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.462746] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.462754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.462781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.462807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.462834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.462863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.462895] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.462922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.462955] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.462984] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.463013] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.463046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.463080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.463183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.463214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.463244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.463271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.463291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.463311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.463333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.463353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.463373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.463391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.463409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.463431] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.463452] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.465536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.465557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.465575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.465594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.467167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.467187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.467204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.468757] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.468778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.470651] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.473962] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.474012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.474045] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.474088] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.474194] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.474236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.474297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.491067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.491108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.491148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.491189] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.491222] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.491258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.491295] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.491329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.491362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.491393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.491423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.491430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.491460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.491539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.491584] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.491627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.491670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.491711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.491760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.491801] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.491846] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.491891] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.491919] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.491953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.491988] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.507565] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.507616] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.507707] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.524742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.524779] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.524818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.524852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.524883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.524912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.524941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.524972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.525005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.525036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.525067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.525095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.525122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.525175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.525210] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.525246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.525759] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.525789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.525823] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.525860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.525888] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.525920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.525951] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.525981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.526009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.526037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.526063] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.526071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.526098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.526104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.526133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.526159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.526187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.526212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.526243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.526268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.526297] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.526323] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.526350] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.526380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.526412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.526520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.526553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.526581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.526610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.526638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.526669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.526703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.526735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.526768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.526795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.526823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.526855] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.526885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.528978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.528999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.529017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.529041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.530707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.530728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.530746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.532305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.532327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.534214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.537569] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.537622] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.537654] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.537696] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.537800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.537842] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.537903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.554727] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.554767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.554806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.554848] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.554881] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.554918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.554960] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.555001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.555042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.555082] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.555122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.555130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.555170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.555177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.555218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.555258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.555299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.555340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.555381] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.555416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.555439] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.555458] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.555525] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.555564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.555595] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.571191] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.571237] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.571309] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.588331] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.588368] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.588407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.588439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.588478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.588594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.588638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.588672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.588714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.588757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.588801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.588841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.588882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.588947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.588993] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.589040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.589311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.589337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.589364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.589392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.589417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.589442] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.589501] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.589531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.589561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.589589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.589616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.589625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.589651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.589659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.589686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.589713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.589740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.589766] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.589798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.589824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.589852] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.589878] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.589906] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.589938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.589973] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.590076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.590108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.590138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.590168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.590199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.590230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.590264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.590297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.590319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.590337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.590356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.590378] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.590403] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.592478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.592523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.592542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.592561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.594145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.594167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.594186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.595756] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.595777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.597656] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.600975] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.601025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.601058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.601099] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.601201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.601243] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.601304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.618064] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.618103] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.618145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.618192] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.618232] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.618274] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.618315] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.618356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.618397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.618437] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.618477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.618557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.618608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.618620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.618669] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.618714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.618759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.618805] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.618852] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.618880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.618912] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.618941] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.618971] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.619004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.619039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.634610] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.634657] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.634729] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.651765] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.651802] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.651842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.651874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.651904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.651934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.651972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.652013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.652055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.652097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.652139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.652177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.652214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.652280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.652325] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.652371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.652820] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.652843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.652868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.652894] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.652915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.652937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.652959] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.652979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.652999] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.653018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.653057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.653065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.653093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.653099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.653128] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.653156] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.653183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.653210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.653242] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.653270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.653299] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.653326] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.653354] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.653386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.653419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.653545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.653574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.653603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.653631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.653659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.653688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.653720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.653750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.653781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.653808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.653835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.653867] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.653898] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.655964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.655985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.656008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.656032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.657622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.657646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.657668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.659217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.659241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.661110] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.664405] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.664455] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.664559] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.664627] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.664790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.664831] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.664903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.681538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.681578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.681618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.681659] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.681691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.681727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.681762] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.681796] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.681829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.681860] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.681890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.681898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.681927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.681934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.681964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.681994] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.682023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.682052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.682087] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.682116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.682147] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.682176] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.682204] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.682235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.682257] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.698036] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.698086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.698175] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.715205] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.715242] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.715281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.715313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.715343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.715372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.715400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.715431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.715595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.715648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.715699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.715745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.715790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.715875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.715932] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.715990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.716329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.716349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.716371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.716394] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.716412] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.716432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.716452] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.716525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.716556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.716588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.716618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.716628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.716657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.716665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.716696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.716726] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.716756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.716786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.716820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.716850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.716882] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.716912] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.716938] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.716970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.717006] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.717110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.717141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.717171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.717200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.717230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.717261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.717295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.717327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.717359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.717388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.717416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.717450] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.717510] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.719576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.719597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.719615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.719634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.721208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.721228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.721246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.722806] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.722827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.724699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.728002] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.728056] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.728095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.728146] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.728261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.728301] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.728345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.745125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.745165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.745204] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.745246] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.745279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.745315] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.745351] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.745391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.745433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.745473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.745587] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.745605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.745664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.745675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.745721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.745764] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.745808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.745850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.745897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.745939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.745985] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.746347] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.746390] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.746437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.746521] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.761637] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.761684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.761755] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.778758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.778796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.778836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.778870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.778901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.778931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.778960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.778992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.779025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.779057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.779088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.779117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.779154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.779219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.779265] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.779312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.779776] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.779811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.779846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.779884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.779916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.779949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.779982] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.780013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.780045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.780075] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.780104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.780112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.780141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.780148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.780178] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.780207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.780237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.780265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.780298] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.780327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.780359] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.780388] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.780418] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.780450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.780508] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.780612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.780643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.780674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.780704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.780734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.780765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.780799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.780832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.780864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.780894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.780923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.780957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.780988] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.783061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.783082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.783100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.783119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.784699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.784719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.784742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.786302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.786324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.788197] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.791509] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.791560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.791592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.791633] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.791743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.791770] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.791810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.808622] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.808660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.808697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.808736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.808766] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.808800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.808839] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.808878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.808919] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.808958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.808996] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.809004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.809043] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.809050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.809089] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.809128] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.809167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.809207] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.809245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.809284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.809325] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.809364] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.809403] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.809444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.809549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.825136] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.825183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.825254] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.842241] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.842279] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.842320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.842354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.842385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.842415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.842451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.842577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.842634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.842687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.842738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.842786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.842834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.842905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.842941] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.842978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.843274] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.843294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.843315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.843338] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.843356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.843376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.843396] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.843414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.843432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.843505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.843533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.843543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.843572] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.843580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.843611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.843641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.843672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.843701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.843734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.843764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.843798] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.843828] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.843857] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.843890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.843925] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.844031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.844062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.844092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.844122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.844151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.844182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.844216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.844248] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.844280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.844310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.844339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.844372] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.844403] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.846506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.846526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.846544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.846562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.848130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.848154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.848174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.849738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.849760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.851636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.854686] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.854718] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.854736] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.854762] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.854842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.854869] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.854909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.871810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.871850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.871889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.871931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.871964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.872000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.872036] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.872070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.872103] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.872134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.872174] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.872182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.872222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.872229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.872271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.872312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.872353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.872393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.872434] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.872563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.872601] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.872635] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.872667] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.872703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.872738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.888311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.888358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.888428] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.905531] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.905569] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.905609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.905641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.905672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.905701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.905730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.905762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.905796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.905827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.905858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.905886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.905913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.905966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.906001] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.906046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.906387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.906415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.906445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.906553] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.906590] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.906631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.906671] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.906710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.906747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.906784] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.906818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.906829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.906866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.906876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.906914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.906949] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.906984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.907021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.907064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.907102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.907143] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.907180] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.907219] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.907263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.907308] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.907410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.907430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.907478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.907506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.907532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.907560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.907592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.907623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.907655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.907682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.907709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.907743] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.907775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.909844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.909865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.909883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.909902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.911514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.911536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.911554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.913112] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.913133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.915008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.918325] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.918377] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.918410] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.918452] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.918783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.918811] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.918854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.935461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.935534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.935574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.935619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.935657] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.935698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.935737] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.935776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.935816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.935855] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.935893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.935901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.935938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.935945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.935990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.936021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.936057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.936093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.936130] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.936166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.936204] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.936241] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.936274] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.936312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.936351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.951930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  298.951979] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  298.952051] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  298.969078] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  298.969115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  298.969155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.969188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.969220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.969250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.969279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.969317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.969360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.969402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.969443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.969617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.969662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.969749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.969804] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.969841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.970174] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.970195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.970216] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.970239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.970257] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.970280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.970304] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.970327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.970349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.970372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.970395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.970400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.970422] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.970426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.970494] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.970527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.970559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.970588] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.970622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.970650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.970682] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.970709] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.970738] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.970772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  298.970807] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  298.970908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  298.970935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  298.970964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  298.970990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  298.971018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  298.971044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  298.971076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  298.971107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  298.971138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.971164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  298.971192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  298.971222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  298.971252] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  298.973323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  298.973344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  298.973363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.973382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  298.974979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  298.974998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  298.975016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  298.976585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  298.976609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  298.978496] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  298.981835] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  298.981888] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  298.981920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  298.981965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  298.982045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  298.982072] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  298.982113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  298.998993] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  298.999034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  298.999075] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  298.999119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  298.999158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  298.999198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  298.999238] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  298.999277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  298.999316] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  298.999355] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  298.999393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  298.999401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.999439] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  298.999518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  298.999571] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  298.999620] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  298.999666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  298.999710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  298.999758] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  298.999800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  298.999851] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  298.999897] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  298.999940] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  298.999992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.000031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.015496] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.015540] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.015607] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.032608] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.032645] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.032685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.032718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.032749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.032788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.032827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.032866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.032909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.032950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.032991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.033037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.033067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.033116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.033149] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.033180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.033439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.033535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.033577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.033623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.033660] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.033700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.033739] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.033777] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.033814] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.033851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.033888] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.034127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.034148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.034152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.034172] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.034191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.034210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.034228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.034249] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.034268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.034288] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.034306] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.034324] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.034346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.034369] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.034438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.034492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.034521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.034548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.034575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.034602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.034634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.034664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.034695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.034721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.034748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.034781] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.034992] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.037050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.037071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.037089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.037107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.038687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.038707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.038725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.040285] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.040306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.042177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.045382] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.045412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.045431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.045521] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.045747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.045773] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.045811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.062575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.062613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.062649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.062688] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.062718] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.062752] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.062786] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.062817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.062855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.062895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.062934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.062941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.062980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.062987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.063027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.063066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.063105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.063144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.063183] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.063221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.063262] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.063301] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.063340] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.063381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.063422] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.079001] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.079045] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.079114] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.096142] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.096184] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.096229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.096268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.096308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.096347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.096387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.096426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.096545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.096602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.096657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.096691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.096720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.096775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.096813] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.096850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.097197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.097230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.097266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.097304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.097335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.097377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.097405] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.097430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.097495] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.097531] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.097567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.097578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.097613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.097623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.097660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.097695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.097730] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.097764] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.097805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.097839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.097877] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.097915] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.097950] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.097988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.098034] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.098124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.098150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.098175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.098200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.098223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.098248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.098275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.098302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.098326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.098351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.098373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.098407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.098427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.100512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.100532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.100551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.100570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.102143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.102163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.102181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.103744] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.103765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.105627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.108915] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.108961] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.108991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.109030] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.109131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.109170] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.109227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.126082] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.126119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.126156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.126194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.126224] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.126257] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.126296] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.126336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.126376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.126414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.126453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.126531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.126581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.126593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.126641] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.126685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.126733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.126777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.126824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.126872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.126916] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.126946] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.126976] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.127009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.127044] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.142568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.142613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.142681] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.159685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.159722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.159761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.159794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.159825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.159854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.159883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.159914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.159947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.159978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.160009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.160037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.160064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.160118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.160152] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.160188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.160640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.160674] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.160710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.160747] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.160778] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.160811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.160834] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.160859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.160885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.160911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.160937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.160942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.160967] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.160972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.160998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.161024] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.161050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.161075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.161102] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.161127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.161154] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.161180] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.161206] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.161233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.161261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.161334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.161360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.161387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.161412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.161440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.161610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.161648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.161683] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.161717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.161747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.161778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.161809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.161831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.163868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.163889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.163907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.163926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.165492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.165512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.165530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.167085] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.167106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.168979] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.172257] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.172307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.172338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.172379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.172564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.172629] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.172728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.189393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.189431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.189559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.189621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.189669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.189717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.189769] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.189819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.189868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.189916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.189962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.189975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.190020] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.190031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.190078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.190124] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.190166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.190196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.190228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.190258] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.190289] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.190319] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.190348] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.190381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.190415] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.205855] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.205900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.205966] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.224395] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.224432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.224561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.224614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.224800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.224840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.224889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.224910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.224932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.224951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.224970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.224987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.225003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.225034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.225056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.225078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.225289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.225309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.225330] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.225355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.225378] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.225402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.225426] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.225500] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.225532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.225565] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.225596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.225605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.225634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.225642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.225673] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.225703] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.225733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.225763] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.225797] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.225828] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.225860] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.225889] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.225919] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.225953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.225989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.226404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.226438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.226490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.226523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.226554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.226588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.226748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.226778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.226808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.226835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.226862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.226893] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.226922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.229033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.229054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.229072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.229091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.230670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.230689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.230707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.232264] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.232284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.234146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.237402] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.237508] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.237554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.237615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.237735] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.237772] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.237824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.254556] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.254594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.254631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.254670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.254701] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.254734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.254768] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.254800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.254830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.254859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.254887] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.254895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.254923] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.254929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.254958] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.254986] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.255013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.255040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.255073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.255100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.255129] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.255156] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.255182] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.255215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.255249] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.271017] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.271061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.271129] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.288155] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.288192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.288231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.288263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.288294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.288323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.288352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.288383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.288424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.288542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.288602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.288650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.288699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.288786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.288843] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.288901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.289358] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.289378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.289399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.289425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.289498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.289531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.289567] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.289599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.289632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.289663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.289693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.289702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.289730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.289737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.289766] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.289796] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.289823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.289852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.289884] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.289912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.289939] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.289967] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.289996] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.290026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.290060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.290163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.290194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.290224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.290253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.290280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.290310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.290344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.290376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.290408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.290437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.290487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.290523] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.290556] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.292621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.292641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.292660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.292679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.294251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.294271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.294289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.295841] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.295861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.297733] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.301029] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.301078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.301117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.301168] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.301282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.301330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.301398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.318198] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.318240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.318281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.318325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.318363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.318403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.318442] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.318567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.318623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.318676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.318726] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.318740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.318787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.318798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.318845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.318893] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.318942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.318972] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.319002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.319031] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.319062] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.319090] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.319117] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.319149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.319183] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.334657] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.334702] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.334768] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.351766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.351803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.351843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.351876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.351907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.351937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.351967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.351999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.352033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.352066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.352097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.352135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.352174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.352238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.352284] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.352331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.352882] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.352916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.352952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.352989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.353021] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.353054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.353087] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.353119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.353151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.353181] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.353210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.353218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.353247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.353255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.353284] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.353314] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.353344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.353373] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.353403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.353432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.353487] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.353518] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.353549] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.353584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.353619] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.353724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.353755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.353786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.353816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.353846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.353877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.353911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.353944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.353976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.354005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.354034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.354068] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.354099] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.356161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.356182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.356201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.356220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.357796] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.357817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.357840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.359430] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.359467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.361336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.364627] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.364677] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.364709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.364750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.364856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.364898] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.364969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.381773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.381810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.381848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.381887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.381917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.381951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.381985] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.382016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.382046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.382075] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.382102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.382110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.382137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.382143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.382171] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.382199] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.382226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.382263] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.382303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.382342] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.382383] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.382409] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.382507] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.382556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.382604] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.398259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.398303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.398370] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.415387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.415425] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.415557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.415744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.415777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.415808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.415838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.415869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.415904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.415936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.415968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.415997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.416024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.416079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.416100] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.416121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.416329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.416348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.416368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.416391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.416409] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.416481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.416513] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.416546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.416577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.416608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.416637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.416647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.416675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.416683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.416712] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.416742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.416772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.416801] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.416835] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.416865] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.416898] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.416927] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.416958] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.416991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.417320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.417424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.417485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.417517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.417549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.417580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.417711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.417742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.417773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.417803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.417830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.417856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.417888] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.417917] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.420028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.420048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.420067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.420085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.421687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.421709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.421728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.423288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.423310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.425172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.428412] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.428462] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.428482] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.428508] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.428589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.428616] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.428656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.445632] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.445670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.445708] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.445747] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.445778] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.445811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.445845] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.445877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.445908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.445937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.445966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.445973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.446001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.446007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.446035] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.446062] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.446089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.446115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.446148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.446176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.446204] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.446231] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.446257] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.446290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.446324] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.462048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.462094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.462185] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.479183] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.479220] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.479260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.479292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.479323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.479353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.479382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.479413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.479536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.479592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.479645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.479693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.479741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.479827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.479883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.479941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.480370] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.480413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.480487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.480527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.480559] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.480593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.480628] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.480660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.480691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.480720] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.480749] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.480758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.480786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.480794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.480823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.480852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.480881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.480907] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.480939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.480968] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.480998] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.481025] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.481053] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.481086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.481120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.481222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.481253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.481283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.481313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.481342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.481373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.481406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.481463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.481496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.481525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.481556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.481591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.481623] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.483686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.483707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.483725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.483743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.485316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.485336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.485354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.486917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.486938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.488837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.492138] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.492191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.492230] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.492281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.492396] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.492509] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.492614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.509296] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.509335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.509373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.509411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.509528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.509577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.509630] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.509681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.509731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.509777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.509823] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.509836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.509879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.509891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.509937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.509982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.510023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.510076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.510109] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.510138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.510169] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.510198] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.510224] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.510256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.510291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.525758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.525802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.525869] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.544377] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.544415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.544545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.544730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.544763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.544795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.544824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.544860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.544881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.544901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.544920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.544936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.544952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.544984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.545005] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.545027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.545238] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.545257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.545278] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.545301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.545319] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.545343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.545366] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.545389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.545416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.545492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.545523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.545533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.545563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.545571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.545602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.545633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.545664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.545694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.545728] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.545758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.545791] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.545822] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.545852] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.545887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.545922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.546390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.546431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.546493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.546528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.546559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.546591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.546722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.546752] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.546782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.546809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.546835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.546867] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.546896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.549001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.549022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.549040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.549059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.550652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.550677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.550699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.552263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.552285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.554157] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.557486] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.557535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.557566] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.557605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.557706] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.557746] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.557804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.574668] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.574706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.574742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.574781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.574812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.574845] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.574878] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.574909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.574939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.574968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.574995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.575002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.575030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.575036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.575064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.575092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.575119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.575145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.575177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.575214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.575256] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.575295] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.575334] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.575376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.575417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.591073] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.591120] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.591190] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.608235] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.608272] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.608310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.608343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.608373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.608403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.608512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.608563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.608619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.608672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.608724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.609036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.609084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.609170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.609229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.609264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.609547] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.609581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.609609] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.609634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.609654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.609675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.609697] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.609717] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.609737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.609761] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.609787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.609792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.609817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.609822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.609847] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.609873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.609898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.609923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.609948] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.609973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.609999] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.610025] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.610050] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.610076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.610103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.610177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.610203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.610229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.610254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.610280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.610305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.610332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.610359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.610385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.610410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.610470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.610507] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.610540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.612615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.612636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.612658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.612682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.614256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.614277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.614296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.615858] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.615879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.617748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.621088] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.621141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.621173] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.621215] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.621361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.621426] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.621575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.638221] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.638261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.638300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.638341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.638374] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.638409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.638528] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.638574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.638625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.638668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.638715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.638728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.638772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.638782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.638834] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.638870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.638909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.638947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.638985] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.639022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.639062] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.639096] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.639131] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.639169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.639213] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.654737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.654786] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.654874] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.671869] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.671907] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.671947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.671980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.672011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.672041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.672069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.672100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.672133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.672164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.672194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.672221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.672248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.672308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.672354] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.672401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.672884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.672914] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.672949] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.672986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.673014] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.673046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.673076] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.673106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.673134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.673163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.673188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.673196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.673223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.673229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.673259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.673285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.673313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.673338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.673369] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.673395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.673451] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.673478] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.673508] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.673542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.673577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.673678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.673708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.673735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.673763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.673789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.673818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.673851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.673883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.673914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.673940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.673968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.673998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.674028] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.676095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.676116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.676135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.676153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.677730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.677749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.677767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.679318] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.679339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.681211] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.684521] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.684576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.684615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.684667] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.684822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.684863] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.684922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.701641] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.701682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.701722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.701764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.701797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.701833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.701869] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.701903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.701943] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.701984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.702024] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.702031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.702072] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.702079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.702120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.702161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.702202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.702243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.702281] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.702304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.702326] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.702345] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.702364] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.702385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.702408] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.718150] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.718197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.718285] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.735245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.735281] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.735321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.735354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.735384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.735412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.735522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.735569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.735626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.735679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.735988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.736020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.736049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.736104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.736141] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.736175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.736380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.736400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.736468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.736508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.736537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.736570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.736600] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.736632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.736660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.736690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.736963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.736970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.736998] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.737004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.737032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.737057] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.737083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.737106] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.737136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.737160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.737188] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.737211] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.737237] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.737267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.737298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.737394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.737514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.737704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.737724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.737744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.737764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.737786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.737807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.737827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.737845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.737869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.737896] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.737920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.740002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.740023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.740041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.740060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.741636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.741660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.741680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.743232] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.743255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.745130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.748386] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.748470] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.748501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.748546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.748743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.748783] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.748843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.765532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.765576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.765619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.765665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.765706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.765747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.765788] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.765829] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.765870] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.765910] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.765950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.765957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.765996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.766003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.766043] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.766084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.766125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.766165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.766206] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.766246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.766288] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.766328] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.766369] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.766412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.766505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.781995] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.782046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.782121] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.800511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.800548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.800587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.800620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.800650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.800679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.800708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.800738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.800772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.800803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.800834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.800863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.800891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.800945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.800980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.801016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.801365] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.801397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.801500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.801558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.801612] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.801645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.801679] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.801711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.801744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.801774] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.801805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.801814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.801842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.801850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.801880] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.801910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.801940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.801969] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.802003] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.802032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.802063] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.802093] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.802123] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.802155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.802191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.802280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.802310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.802340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.802371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.802400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.802453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.802485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.802520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.802551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.802581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.802610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.802644] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.802676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.804749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.804770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.804788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.804808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.806428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.806468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.806487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.808051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.808073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.809947] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.813261] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.813311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.813344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.813386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.813744] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.813789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.813850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.830328] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.830372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.830415] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.830547] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.830588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.830628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.830663] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.830696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.830727] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.830757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.830786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.830794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.830822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.830828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.830858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.830886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.830916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.830944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.830978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.831006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.831038] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.831065] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.831094] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.831127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.831164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.846864] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.846910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.846981] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.864023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.864061] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.864105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.864145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.864185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.864224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.864264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.864303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.864345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.864386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.864508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.864566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.864616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.864706] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.864765] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.864824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.865199] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.865222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.865247] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.865273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.865296] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.865320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.865343] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.865367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.865391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.865465] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.865497] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.865508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.865538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.865547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.865579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.865610] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.865641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.865671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.865705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.865735] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.865768] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.865799] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.865825] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.865858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.865894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.865998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.866029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.866060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.866090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.866120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.866150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.866183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.866216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.866248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.866277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.866306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.866340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.866371] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.868468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.868490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.868510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.868529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.870089] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.870109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.870128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.871691] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.871712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.873583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.876914] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.876966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.876999] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.877041] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.877153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.877180] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.877221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.894008] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.894048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.894088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.894129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.894162] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.894198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.894234] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.894268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.894301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.894332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.894363] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.894371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.894401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.894478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.894527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.894570] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.894622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.894659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.894704] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.894742] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.894786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.894823] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.894863] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.894910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.894955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.910515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.910562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.910636] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.927669] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.927705] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.927745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.927778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.927808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.927838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.927866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.927897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.927930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.927962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.928001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.928040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.928078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.928143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.928189] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.928236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.928544] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.928578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.928613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.928651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.928681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.928714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.928747] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.928779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.928810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.928840] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.928869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.928877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.928905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.928912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.928941] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.928972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.929001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.929029] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.929060] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.929089] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.929120] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.929151] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.929180] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.929213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.929247] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.929350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.929381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.929411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.929466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.929496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.929529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.929564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.929598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.929631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.929661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.929691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.929726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.929759] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.931829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.931850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.931868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.931887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.933571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.933595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.933618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.935180] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.935222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  299.937100] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  299.940418] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  299.940501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  299.940529] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  299.940564] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  299.940689] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.940742] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.940826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.957591] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.957635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.957678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.957724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.957765] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.957806] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.957847] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.957888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.957929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.957969] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.958008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.958016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.958054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.958061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.958101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.958141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.958182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.958223] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.958263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.958303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.958345] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.958386] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.958478] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.958534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.958592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.974081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  299.974128] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  299.974200] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  299.991248] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  299.991285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  299.991325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.991358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.991389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.991513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.991564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.991623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.991675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.991723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.991772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.991815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.991858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.991935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  299.991988] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  299.992042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.992520] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  299.992553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  299.992587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  299.992629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  299.992652] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  299.992677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  299.992702] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  299.992726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  299.992748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  299.992769] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  299.992790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  299.992796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.992816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  299.992821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  299.992842] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  299.992863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  299.992883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.992903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  299.992928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  299.992949] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  299.992971] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  299.992991] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  299.993012] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  299.993036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  299.993063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  299.993146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  299.993177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  299.993208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  299.993238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  299.993268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  299.993298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  299.993330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  299.993362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  299.993393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  299.993469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  299.993508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  299.993553] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  299.993593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  299.995678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  299.995699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  299.995716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.995735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  299.997300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  299.997320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  299.997338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  299.998927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  299.998947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.000825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.004139] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.004186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.004215] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.004252] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.004351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.004390] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.004532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.021294] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.021336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.021376] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.021504] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.021554] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.021611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.021664] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.021714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.021763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.021810] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.021856] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.021868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.021912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.021924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.021970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.022016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.022061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.022106] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.022158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.022210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.022241] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.022267] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.022296] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.022330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.022363] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.037748] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.037792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.037860] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.056350] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.056387] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.056516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.056704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.056737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.056768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.056803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.056830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.056859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.056887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.056913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.056945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.056978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.057032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.057070] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.057110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.057385] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.057474] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.057524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.057577] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.057619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.057665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.057709] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.057752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.057802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.057832] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.057862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.057872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.057901] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.057909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.057939] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.058221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.058253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.058284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.058317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.058347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.058378] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.058407] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.058459] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.058494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.058530] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.058774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.058804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.058832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.058860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.058888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.058917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.058949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.058979] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.059008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.059035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.059062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.059093] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.059122] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.061213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.061237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.061260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.061285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.062868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.062889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.062911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.064524] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.064545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.066405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.069788] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.069841] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.069874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.069915] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.070023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.070072] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.070121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.086899] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.086940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.086979] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.087020] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.087054] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.087090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.087127] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.087161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.087194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.087225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.087255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.087262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.087292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.087299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.087329] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.087359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.087388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.087506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.087551] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.087592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.087635] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.087674] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.087713] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.087758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.087805] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.103418] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.103496] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.103567] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.120569] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.120607] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.120646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.120686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.120726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.120765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.120805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.120844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.120886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.120927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.120968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.121007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.121045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.121110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.121155] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.121210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.121501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.121616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.121641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.121667] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.121688] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.121710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.121732] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.121752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.121772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.121791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.121809] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.121814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.121832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.121836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.121854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.121872] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.121891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.121908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.121930] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.121948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.121967] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.121985] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.122002] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.122023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.122047] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.122113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.122133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.122152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.122171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.122189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.122208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.122229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.122249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.122269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.122287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.122305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.122327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.122352] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.124438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.124459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.124478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.124497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.126069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.126090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.126112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.127677] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.127698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.129576] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.132916] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.132968] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.133001] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.133044] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.133150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.133192] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.133252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.150046] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.150087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.150127] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.150168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.150204] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.150247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.150289] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.150330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.150371] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.150412] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.150529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.150542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.150590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.150602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.150648] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.150692] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.150739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.150782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.150829] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.150859] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.150891] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.150920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.150950] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.150983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.151018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.166545] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.166597] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.166688] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.183733] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.183775] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.183819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.183859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.183899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.183938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.183977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.184016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.184059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.184100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.184142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.184180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.184219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.184283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.184329] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.184375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.184760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.184785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.184809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.184834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.184855] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.184876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.184898] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.184919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.184939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.184958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.184976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.184982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.184999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.185004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.185022] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.185039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.185057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.185075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.185096] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.185114] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.185133] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.185150] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.185176] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.185203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.185231] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.185306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.185332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.185358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.185384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.185441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.185473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.185506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.185537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.185568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.185595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.185622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.185654] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.185684] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.187746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.187768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.187786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.187806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.189392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.189428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.189446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.191012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.191034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.192931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.196219] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.196269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.196301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.196343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.196548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.196615] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.196689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.213349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.213390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.213541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.213600] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.213651] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.213705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.213755] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.213805] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.213854] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.213901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.213947] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.213959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.214005] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.214016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.214063] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.214116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.214146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.214175] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.214207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.214237] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.214268] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.214295] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.214324] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.214357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.214391] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.229848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.229894] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.229980] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.248717] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.248755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.248794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.248827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.248858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.248888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.248926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.248965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.249008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.249049] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.249091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.249129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.249168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.249233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.249278] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.249325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.249937] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.249967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.249998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.250032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.250058] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.250088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.250115] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.250143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.250169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.250196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.250220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.250226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.250251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.250257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.250284] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.250308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.250333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.250357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.250386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.250458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.250491] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.250519] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.250549] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.250579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.250613] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.250719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.250746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.250776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.250802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.250830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.250859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.250891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.250922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.250954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.250979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.251007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.251038] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.251069] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.253134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.253157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.253176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.253197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.254754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.254774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.254792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.256391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.256429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.258298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.261598] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.261649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.261681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.261722] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.261830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.261872] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.261933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.278683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.278724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.278764] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.278804] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.278838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.278873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.278910] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.278944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.278978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.279009] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.279040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.279047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.279077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.279083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.279114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.279144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.279173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.279208] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.279249] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.279290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.279333] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.279374] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.279484] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.279517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.279549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.295212] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.295258] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.295345] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.312379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.312448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.312487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.312519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.312549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.312578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.312606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.312637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.312671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.312702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.312733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.312760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.312787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.312840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.312876] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.312910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.313253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.313295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.313318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.313345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.313368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.313391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.313466] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.313497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.313526] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.313553] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.313581] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.313589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.313615] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.313623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.313650] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.313677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.313704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.313730] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.313761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.313788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.313817] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.313843] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.313870] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.313901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.313936] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.314041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.314074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.314104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.314134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.314164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.314195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.314229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.314261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.314289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.314308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.314326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.314348] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.314369] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.316452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.316473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.316492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.316511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.318081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.318104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.318127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.319693] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.319714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.321585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.324911] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.324961] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.324992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.325030] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.325132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.325176] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.325241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.342015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.342055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.342095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.342136] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.342168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.342204] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.342245] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.342287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.342325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.342366] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.342405] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.342484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.342535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.342547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.342600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.342645] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.342695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.342740] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.342789] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.342836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.342874] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.342903] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.342934] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.342956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.342979] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.358553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.358599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.358670] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.375668] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.375705] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.375745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.375778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.375810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.375840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.375870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.375902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.375935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.375966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.375998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.376026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.376053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.376107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.376142] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.376177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.376675] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.376722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.376754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.376779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.376804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.376831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.376857] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.376883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.376909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.376935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.376960] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.376966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.376990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.376995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.377021] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.377047] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.377073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.377098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.377123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.377148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.377176] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.377201] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.377228] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.377254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.377283] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.377358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.377385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.377443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.377475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.377505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.377535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.377568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.377598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.377629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.377656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.377682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.377714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.377743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.379807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.379828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.379846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.379865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.381436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.381459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.381482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.383050] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.383072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.384945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.388203] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.388248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.388276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.388314] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.388477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.388519] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.388575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.405287] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.405327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.405367] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.405496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.405553] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.405606] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.405661] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.405703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.405735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.405766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.405794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.405804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.405832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.405838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.405869] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.405897] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.405926] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.405953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.405993] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.406033] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.406076] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.406116] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.406157] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.406199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.406242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.421833] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.421879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.421950] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.438962] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.438999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.439039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.439073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.439111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.439151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.439190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.439229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.439272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.439313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.439355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.439394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.439503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.439596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.439658] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.439724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.440103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.440124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.440148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.440173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.440193] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.440214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.440237] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.440257] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.440278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.440296] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.440315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.440320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.440338] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.440343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.440362] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.440379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.440435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.440462] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.440493] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.440519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.440547] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.440573] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.440600] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.440631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.440663] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.440766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.440797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.440827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.440856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.440885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.440915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.440950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.440975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.440996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.441013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.441031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.441053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.441074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.443119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.443140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.443157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.443176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.444752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.444772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.444790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.446385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.446422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.448292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.451567] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.451611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.451640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.451677] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.451772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.451809] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.451863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.468702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.468747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.468790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.468836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.468877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.468919] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.468960] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.469001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.469042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.469082] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.469122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.469131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.469171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.469177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.469218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.469259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.469300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.469340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.469381] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.469476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.469531] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.469585] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.469613] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.469645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.469679] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.485157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.485208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.485300] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.502308] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.502345] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.502385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.502506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.502558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.502608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.502657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.502699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.502735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.502769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.502800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.502829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.502857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.502912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.502948] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.502984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.503291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.503332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.503355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.503379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.503430] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.503461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.503490] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.503518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.503547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.503573] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.503600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.503609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.503634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.503642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.503669] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.503695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.503721] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.503748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.503777] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.503802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.503831] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.503860] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.503889] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.503919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.503954] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.504060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.504092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.504122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.504152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.504182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.504214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.504237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.504257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.504284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.504310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.504335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.504362] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.504414] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.506478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.506499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.506518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.506537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.508108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.508129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.508151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.509715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.509736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.511607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.514937] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.514987] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.515018] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.515057] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.515159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.515198] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.515255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.532025] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.532065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.532105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.532146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.532179] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.532215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.532251] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.532285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.532318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.532349] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.532379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.532457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.532500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.532513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.532557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.532599] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.532640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.532681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.532732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.532775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.532826] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.532872] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.532919] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.532971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.533005] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.548550] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.548599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.548675] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.565677] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.565714] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.565754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.565787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.565817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.565847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.565875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.565907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.565940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.565972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.566003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.566031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.566059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.566112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.566147] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.566183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.566701] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.566734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.566759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.566785] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.566805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.566827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.566849] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.566869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.566889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.566907] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.566925] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.566931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.566949] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.566953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.566971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.566989] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.567007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.567025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.567046] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.567064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.567083] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.567102] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.567119] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.567141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.567164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.567233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.567253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.567271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.567296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.567323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.567349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.567378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.567434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.567466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.567492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.567519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.567552] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.567581] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.569642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.569663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.569682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.569701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.571264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.571284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.571302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.572863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.572884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.574787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.578022] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.578052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.578071] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.578097] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.578177] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.578204] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.578244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.595114] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.595154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.595193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.595234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.595267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.595303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.595339] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.595373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.595485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.595528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.595572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.595585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.595632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.595646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.595688] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.595730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.595772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.595817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.595868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.595913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.595962] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.596007] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.596046] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.596083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.596117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.611601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.611648] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.611735] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.628748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.628785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.628825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.628858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.628889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.628919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.628949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.628980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.629021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.629063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.629113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.629142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.629175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.629233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.629274] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.629316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.629809] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.629852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.629899] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.629949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.629989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.630034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.630077] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.630128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.630155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.630184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.630209] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.630217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.630244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.630250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.630279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.630304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.630332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.630358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.630415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.630443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.630474] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.630501] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.630530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.630561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.630596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.630683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.630710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.630739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.630766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.630794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.630821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.630853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.630884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.630916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.630941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.630969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.630999] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.631030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.633105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.633127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.633145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.633164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.634731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.634751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.634770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.636319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.636341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.638260] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.641495] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.641529] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.641552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.641584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.641672] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.641701] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.641742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.658665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.658706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.658749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.658796] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.658836] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.658878] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.658919] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.658959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.659000] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.659041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.659081] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.659088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.659129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.659136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.659176] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.659217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.659257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.659297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.659338] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.659378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.659484] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.659532] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.659577] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.659627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.659680] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.675124] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.675175] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.675266] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.692301] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.692343] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.692388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.692514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.692567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.692618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.692667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.692711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.692747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.692781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.692813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.692841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.692869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.692924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.692961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.692997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.693350] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.693383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.693480] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.693517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.693546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.693577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.693608] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.693637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.693666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.693693] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.693720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.693729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.693755] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.693762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.693792] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.693819] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.693846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.693872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.693906] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.693936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.693967] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.693996] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.694026] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.694059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.694093] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.694171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.694190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.694210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.694228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.694247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.694266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.694288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.694308] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.694328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.694346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.694364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.694423] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.694452] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.696514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.696535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.696553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.696576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.698140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.698161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.698179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.699743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.699764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.701635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.704882] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.704914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.704933] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.704958] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.705038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.705066] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.705106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.721986] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.722026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.722066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.722107] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.722141] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.722177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.722212] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.722247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.722280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.722310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.722339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.722347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.722376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.722453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.722498] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.722541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.722582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.722623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.722670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.722711] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.722760] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.722805] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.722846] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.722899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.722952] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.738525] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.738572] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.738658] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.755718] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.755755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.755794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.755827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.755857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.755885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.755913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.755944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.755977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.756008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.756039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.756067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.756094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.756147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.756182] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.756218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.756762] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.756798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.756840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.756865] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.756884] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.756907] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.756928] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.756950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.756970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.756995] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.757020] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.757027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.757052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.757057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.757083] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.757108] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.757134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.757159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.757185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.757210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.757237] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.757263] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.757288] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.757315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.757343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.757471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.757503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.757534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.757566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.757597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.757628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.757664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.757697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.757730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.757760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.757785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.757808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.757829] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.759867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.759887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.759905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.759929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.761502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.761522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.761540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.763097] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.763118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.764990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.768272] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.768316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.768344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.768449] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.768595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.768651] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.768707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.785363] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.785441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.785481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.785522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.785556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.785592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.785628] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.785669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.785711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.785751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.785791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.785799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.785839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.785846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.785887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.785928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.785969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.786010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.786051] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.786091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.786133] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.786174] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.786209] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.786252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.786295] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.801853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.801900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.801988] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.819059] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.819096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.819135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.819168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.819198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.819227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.819255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.819286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.819320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.819352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.819475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.819521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.819564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.819644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.819682] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.819718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.820071] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.820104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.820140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.820178] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.820210] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.820243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.820277] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.820297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.820317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.820335] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.820354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.820382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.820410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.820418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.820445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.820472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.820498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.820525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.820555] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.820581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.820610] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.820636] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.820662] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.820692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.820727] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.820816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.820836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.820854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.820872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.820890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.820909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.820929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.820949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.820969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.820987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.821004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.821027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.821047] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.823100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.823121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.823139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.823157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.824721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.824741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.824759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.826318] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.826339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.828244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.831537] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.831570] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.831589] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.831615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.831695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.831722] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.831763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.848662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.848701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.848741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.848783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.848818] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.848860] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.848901] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.848942] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.848983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.849024] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.849064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.849072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.849112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.849119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.849160] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.849201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.849241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.849281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.849322] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.849362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.849462] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.849511] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.849557] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.849608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.849659] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.865175] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.865222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.865308] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.882337] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.882374] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.882509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.882741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.882775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.882807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.882836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.882868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.882902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.882934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.882965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.882993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.883020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.883072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.883107] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.883143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.883780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.883810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.883842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.883877] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.883906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.883936] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.883966] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.883995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.884024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.884051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.884077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.884084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.884111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.884117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.884144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.884171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.884198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.884221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.884250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.884276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.884305] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.884329] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.884355] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.884423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.884462] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.884773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.884796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.884816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.884835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.884854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.884874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.884896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.884917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.884937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.884955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.884973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.884995] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.885015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.887086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.887108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.887127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.887147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.888723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.888744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.888762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.890364] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.890402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.892276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.895623] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.895674] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.895712] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.895763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.895864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.895892] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.895933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.912754] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.912794] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.912834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.912876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.912909] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.912946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.912982] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.913016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.913049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.913080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.913111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.913118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.913148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.913154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.913185] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.913215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.913250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.913291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.913332] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.913372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.913502] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.913554] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.913605] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.913661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.913717] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.929244] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.929291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.929379] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  300.948175] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  300.948217] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  300.948262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.948302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.948342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.948381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.948501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.948549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.948605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.948656] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.948706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.948749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.948794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.948879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.948935] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.948994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.949275] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.949296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.949317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.949340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.949358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.949425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.949460] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.949489] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.949521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.949549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.949579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.949588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.949617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.949625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.949655] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.949682] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.949711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.949737] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.949769] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.949796] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.949827] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.949853] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.949880] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.949910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.949943] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.950031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.950058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  300.950087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  300.950113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  300.950140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  300.950167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  300.950199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  300.950230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  300.950260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.950286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  300.950313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  300.950343] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  300.950397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  300.952465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.952486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.952505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.952524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.954095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  300.954115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  300.954134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.955697] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.955718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  300.957592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.960925] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  300.960980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  300.961020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  300.961071] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.961185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  300.961236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  300.961279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  300.978032] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  300.978073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.978113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  300.978154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  300.978187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  300.978223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.978259] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  300.978293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  300.978326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  300.978357] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.978459] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.978472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.978514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.978527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  300.978570] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  300.978612] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  300.978660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.978700] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.978746] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  300.978783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.978827] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  300.978867] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  300.978908] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  300.978953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.979001] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  300.994560] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  300.994606] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  300.994693] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.011737] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.011774] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.011813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.011846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.011877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.011907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.011936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.011974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.012016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.012058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.012100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.012138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.012177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.012241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.012286] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.012333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.012796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.012838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.012870] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.012905] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.012934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.012965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.012995] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.013024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.013053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.013081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.013108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.013115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.013141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.013148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.013175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.013202] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.013229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.013255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.013282] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.013309] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.013337] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.013375] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.013433] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.013468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.013505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.013594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.013624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.013655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.013686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.013715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.013746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.013780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.013812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.013844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.013873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.013902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.013936] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.013967] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.016049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.016071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.016090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.016109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.017684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.017704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.017723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.019282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.019303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.021174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.024519] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.024571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.024604] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.024655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.024736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.024763] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.024803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.041690] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.041731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.041771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.041812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.041845] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.041880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.041917] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.041950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.041983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.042013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.042043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.042051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.042080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.042086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.042117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.042146] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.042176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.042215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.042257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.042297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.042340] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.042431] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.042480] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.042531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.042581] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.058141] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.058188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.058275] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.075295] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.075332] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.075372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.075494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.075545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.075594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.075642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.075686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.075722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.075755] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.075787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.075816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.075845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.075894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.075917] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.075940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.076144] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.076164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.076187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.076211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.076231] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.076252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.076274] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.076293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.076313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.076332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.076349] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.076381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.076409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.076416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.076443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.076470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.076497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.076522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.076553] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.076579] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.076608] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.076634] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.076661] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.076692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.076724] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.076827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.076858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.076888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.076918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.076948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.076978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.077012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.077044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.077076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.077105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.077130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.077153] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.077174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.079214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.079234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.079252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.079271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.080834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.080853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.080871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.082464] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.082485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.084354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.087709] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.087762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.087794] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.087836] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.087944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.087985] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.088046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.104830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.104872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.104912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.104957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.104995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.105035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.105075] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.105114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.105154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.105193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.105232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.105239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.105278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.105285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.105325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.105364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.105482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.105521] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.105564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.105601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.105640] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.105676] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.105712] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.105752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.105799] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.121359] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.121437] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.121508] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.138511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.138549] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.138589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.138621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.138652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.138690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.138729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.138769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.138811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.138852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.138894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.138932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.138971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.139036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.139081] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.139128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.139354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.139440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.139473] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.139510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.139539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.139570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.139600] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.139630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.139658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.139685] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.139715] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.139723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.139751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.139760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.139787] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.139817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.139846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.139875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.139907] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.139936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.139967] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.139995] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.140025] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.140056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.140080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.140149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.140169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.140188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.140207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.140224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.140244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.140265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.140284] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.140303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.140328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.140354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.140410] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.140439] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.142505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.142526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.142548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.142572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.144146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.144167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.144185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.145748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.145769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.147640] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.150951] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.151001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.151034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.151075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.151182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.151224] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.151284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.168055] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.168095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.168134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.168175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.168211] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.168253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.168295] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.168336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.168451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.168499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.168542] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.168556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.168601] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.168613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.168656] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.168699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.168742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.168789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.168838] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.168867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.168898] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.168928] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.168958] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.168987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.169012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.184579] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.184626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.184698] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.201705] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.201741] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.201781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.201815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.201846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.201876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.201905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.201936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.201969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.202001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.202031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.202059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.202087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.202140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.202175] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.202211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.202670] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.202700] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.202725] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.202750] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.202771] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.202792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.202818] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.202844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.202870] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.202895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.202920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.202926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.202951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.202956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.202982] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.203007] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.203033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.203058] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.203085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.203110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.203137] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.203162] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.203188] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.203215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.203243] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.203316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.203342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.203398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.203430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.203458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.203488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.203521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.203551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.203582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.203609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.203635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.203667] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.203697] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.205759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.205780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.205798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.205817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.207438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.207458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.207476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.209035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.209056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.210927] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.214241] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.214294] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.214327] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.214452] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.214800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.214828] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.214866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.231346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.231421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.231461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.231502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.231534] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.231570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.231606] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.231640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.231672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.231703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.231733] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.231741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.231771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.231778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.231818] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.231859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.231900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.231941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.231982] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.232022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.232065] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.232106] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.232150] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.232174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.232198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.247871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.247918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.247989] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.264992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.265029] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.265068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.265101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.265132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.265162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.265191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.265222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.265256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.265287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.265318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.265346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.265453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.265541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.265598] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.265659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.266055] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.266077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.266100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.266129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.266154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.266181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.266207] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.266233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.266259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.266284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.266310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.266315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.266340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.266372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.266406] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.266437] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.266466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.266493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.266525] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.266552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.266581] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.266607] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.266634] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.266666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.266698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.266802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.266833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.266863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.266893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.266922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.266953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.266986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.267008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.267028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.267047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.267064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.267088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.267108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.269152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.269172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.269190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.269210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.270783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.270803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.270821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.272397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.272418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.274277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.277601] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.277652] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.277684] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.277725] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.277831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.277873] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.277934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.294662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.294702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.294742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.294788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.294829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.294871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.294912] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.294953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.294990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.295030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.295070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.295078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.295118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.295125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.295166] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.295207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.295247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.295288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.295329] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.295443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.295494] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.295548] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.295578] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.295610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.295643] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.311216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.311263] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.311334] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.328428] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.328466] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.328506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.328539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.328570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.328609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.328649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.328688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.328730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.328772] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.328813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.328852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.328890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.328955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.329000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.329047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.329320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.329341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.329428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.329467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.329497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.329532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.329563] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.329595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.329624] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.329654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.329681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.329690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.329718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.329725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.329755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.329782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.329812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.329838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.329869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.329895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.329926] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.329951] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.329979] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.330008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.330041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.330145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.330172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.330200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.330226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.330254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.330281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.330313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.330345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.330401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.330428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.330457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.330492] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.330521] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.332590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.332614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.332637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.332661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.334236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.334259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.334282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.335870] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.335892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.337777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.341126] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.341178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.341210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.341252] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.341368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.341477] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.341538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.358241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.358278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.358315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.358354] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.358467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.358516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.358572] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.358618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.358669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.358711] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.358757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.358770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.358813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.358826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.358880] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.358917] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.358953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.358986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.359028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.359061] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.359099] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.359132] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.359168] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.359206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.359248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.374744] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.374791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.374863] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.393320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.393356] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.393481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.393528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.393577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.393620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.393665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.393718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.393766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.393812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.393858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.393896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.393936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.394015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.394066] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.394118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.394645] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.394692] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.394734] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.394763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.394787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.394812] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.394842] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.394872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.394902] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.394932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.394961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.394967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.394996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.395001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.395031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.395061] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.395091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.395120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.395150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.395180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.395210] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.395240] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.395270] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.395301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.395332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.395488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.395528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.395568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.395606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.395643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.395680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.395722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.395765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.395798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.395827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.395853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.395887] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.395915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.398007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.398030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.398053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.398077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.399655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.399676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.399694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.401252] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.401273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.403144] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.406459] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.406509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.406540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.406581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.406726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.406791] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.406890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.423575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.423616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.423655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.423697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.423730] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.423765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.423801] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.423835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.423872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.423913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.423953] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.423961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.424001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.424008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.424050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.424090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.424131] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.424171] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.424212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.424252] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.424295] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.424335] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.424420] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.424455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.424491] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.440086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.440132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.440218] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.457181] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.457223] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.457267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.457307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.457346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.457468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.457516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.457569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.457624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.457674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.457725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.457766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.457810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.457892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.457946] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.458002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.458446] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.458479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.458512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.458540] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.458558] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.458582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.458606] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.458629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.458653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.458676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.458699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.458703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.458726] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.458730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.458754] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.458777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.458800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.458823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.458845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.458868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.458892] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.458915] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.458939] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.458963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.458988] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.459057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.459081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.459105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.459128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.459151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.459175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.459200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.459225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.459249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.459272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.459294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.459319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.459342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.461444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.461465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.461484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.461503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.463064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.463085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.463102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.464665] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.464685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.466557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.469826] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.469870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.469899] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.469937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.470067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.470124] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.470212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.486933] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.486973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.487012] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.487053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.487086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.487122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.487158] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.487198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.487239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.487279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.487319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.487328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.487445] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.487458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.487510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.487557] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.487606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.487649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.487701] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.487745] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.487794] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.487837] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.487884] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.487945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.487978] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.503441] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.503492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.503582] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.520593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.520630] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.520670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.520703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.520733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.520763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.520792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.520824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.520857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.520888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.520919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.520947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.520974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.521027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.521063] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.521098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.521507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.521848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.521883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.521920] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.521948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.521980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.522010] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.522040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.522067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.522096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.522121] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.522129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.522155] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.522162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.522190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.522216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.522244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.522269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.522300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.522325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.522380] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.522407] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.522436] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.522470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.522505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.522820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.522850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.522875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.522902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.522927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.522955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.522986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.523015] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.523044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.523068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.523093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.523124] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.523151] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.525220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.525241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.525260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.525279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.526867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.526887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.526904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.528557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.528578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.530441] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.533735] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.533786] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.533825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.533876] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.534015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.534055] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.534116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.550861] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.550902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.550942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.550983] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.551015] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.551053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.551095] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.551136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.551178] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.551218] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.551258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.551266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.551305] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.551312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.551352] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.551471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.551517] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.551564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.551611] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.551657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.551706] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.551747] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.551791] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.551843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.551897] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.567405] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.567451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.567540] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.584570] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.584607] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.584646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.584679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.584710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.584739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.584768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.584800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.584833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.584865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.584895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.584923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.584951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.585003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.585047] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.585095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.585324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.585410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.585444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.585482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.585511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.585545] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.585576] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.585608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.585637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.585667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.585693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.585703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.585732] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.585739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.585769] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.585797] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.585827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.585857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.585889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.585919] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.585951] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.585980] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.586008] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.586041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.586075] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.586178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.586207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.586236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.586262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.586291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.586318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.586375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.586407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.586440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.586467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.586496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.586531] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.586560] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.588629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.588650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.588669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.588688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.590264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.590284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.590306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.591904] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.591925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.593814] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.597152] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.597204] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.597237] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.597279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.597429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.597472] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.597537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.614275] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.614313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.614349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.614476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.614526] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.614579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.614632] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.614682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.614732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.614779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.614824] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.614836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.614881] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.614892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.614938] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.614983] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.615029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.615075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.615126] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.615171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.615220] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.615266] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.615312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.615398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.615452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.630794] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.630840] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.630911] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.649758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.649796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.649836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.649870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.649901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.649930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.649960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.649992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.650026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.650057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.650088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.650116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.650144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.650198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.650233] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.650269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.650703] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.650732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.650756] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.650781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.650801] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.650823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.650845] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.650866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.650885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.650905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.650923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.650930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.650947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.650951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.650971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.650988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.651007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.651024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.651046] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.651063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.651083] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.651100] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.651119] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.651140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.651168] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.651231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.651258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.651284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.651310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.651338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.651392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.651428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.651460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.651491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.651518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.651545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.651579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.651608] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.653664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.653686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.653706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.653727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.655277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.655300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.655323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.657011] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.657032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.658907] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.662193] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.662248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.662287] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.662339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.662561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.662628] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.662721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.679329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.679402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.679440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.679478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.679509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.679543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.679577] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.679608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.679647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.679686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.679725] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.679733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.679771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.679778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.679818] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.679858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.679897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.679936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.679973] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.680011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.680052] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.680091] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.680138] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.680161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.680184] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.695828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.695873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.695958] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.713008] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.713045] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.713085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.713118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.713148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.713177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.713206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.713237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.713271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.713302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.713333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.713446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.713489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.713576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.713633] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.713690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.714131] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.714151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.714173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.714199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.714222] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.714246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.714270] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.714293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.714316] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.714387] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.714422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.714431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.714462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.714470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.714502] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.714531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.714562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.714589] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.714622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.714649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.714681] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.714707] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.714735] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.714766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.714800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.714887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.714916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.714945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.714972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.715000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.715027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.715059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.715091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.715120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.715148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.715173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.715205] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.715234] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.717302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.717323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.717396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.717432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.718991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.719010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.719032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.720598] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.720619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.722495] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.725838] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.725890] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.725923] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.725965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.726074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.726116] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.726184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.742949] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.742989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.743029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.743070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.743105] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.743147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.743189] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.743229] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.743271] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.743311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.743430] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.743444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.743493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.743507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.743557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.743608] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.743649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.743685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.743729] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.743764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.743804] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.743845] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.743883] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.743928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.743972] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.759489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.759540] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.759616] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.776621] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.776658] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.776698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.776731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.776762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.776792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.776823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.776854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.776888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.776920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.776952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.776981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.777008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.777071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.777116] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.777163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.777585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.777616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.777650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.777686] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.777714] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.777748] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.777778] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.777808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.777836] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.777865] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.777890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.777898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.777925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.777931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.777960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.777986] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.778013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.778038] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.778070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.778096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.778125] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.778150] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.778178] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.778207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.778240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.778364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.778393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.778425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.778452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.778482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.778511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.778544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.778577] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.778609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.778636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.778664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.778699] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.778728] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.780814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.780835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.780853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.780872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.782447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.782467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.782484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.784037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.784058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.785920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.789233] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.789289] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.789329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.789459] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.789611] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.789652] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.789715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.806340] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.806412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.806452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.806494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.806526] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.806563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.806599] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.806632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.806665] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.806697] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.806727] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.806734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.806764] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.806771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.806801] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.806841] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.806883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.806923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.806968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.807004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.807041] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.807077] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.807114] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.807151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.807190] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.822836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.822883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.822954] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.839887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.839925] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.839964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.839998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.840029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.840059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.840088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.840119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.840153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.840184] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.840215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.840242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.840270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.840323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.840450] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.840509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.840959] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.840989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.841022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.841056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.841085] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.841115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.841137] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.841156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.841174] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.841191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.841207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.841212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.841228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.841232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.841248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.841265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.841281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.841296] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.841315] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.841381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.841416] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.841443] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.841470] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.841503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.841539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.841645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.841673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.841701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.841728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.841756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.841783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.841814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.841845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.841876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.841902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.841930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.841964] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.841992] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.844072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.844094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.844112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.844131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.845715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.845737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.845756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.847327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.847365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.849236] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.851952] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.851988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.852007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.852033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.852118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.852146] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.852187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.869006] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.869046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.869085] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.869127] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.869159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.869195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.869231] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.869265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.869298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.869329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.869449] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.869463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.869513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.869526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.869575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.869623] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.869672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.869721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.869774] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.869821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.869870] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.869917] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.869959] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.870009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.870062] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.885558] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.885606] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.885678] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.902717] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.902755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.902795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.902835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.902875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.902914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.902953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.902992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.903035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.903076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.903118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.903160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.903188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.903237] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.903269] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.903301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.903844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.903887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.903932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.903981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.904022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.904066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.904110] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.904151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.904190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.904217] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.904244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.904251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.904277] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.904284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.904311] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.904379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.904408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.904439] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.904473] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.904503] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.904533] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.904563] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.904593] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.904628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.904664] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.904768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.904798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.904829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.904859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.904889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.904920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.904954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.904986] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.905018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.905048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.905076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.905110] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  301.905141] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  301.907214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  301.907234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  301.907253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.907271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  301.908858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  301.908880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  301.908899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  301.910460] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  301.910482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  301.912370] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  301.915692] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  301.915742] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  301.915772] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  301.915811] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  301.915950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.916011] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.916105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.932797] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.932840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.932883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.932929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.932969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.933011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.933052] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  301.933093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  301.933134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.933174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.933214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.933221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.933261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.933268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.933309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.933429] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.933477] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.933528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.933578] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.933626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.933679] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  301.933723] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  301.933770] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  301.933827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.933863] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  301.949314] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  301.949393] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  301.949481] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  301.966509] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  301.966551] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  301.966596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.966636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.966676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.966715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.966754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.966793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.966836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.966877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.966918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.966957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.966995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.967059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.967104] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.967151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.967583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.967692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  301.967721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  301.967754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  301.967781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  301.967810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  301.967838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  301.967872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  301.967904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  301.967936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  301.967968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  301.967993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  301.968021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  301.968061] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  301.968396] [drm:drm_mode_addfb2] [FB:76]
>[  301.968447] [drm:drm_mode_addfb2] [FB:78]
>[  301.997743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  301.997848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  301.997917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  301.997978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  301.997990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  301.998055] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  301.998078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  301.998103] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  301.998128] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  301.998148] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  301.998170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  301.998192] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  301.998212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  301.998231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  301.998249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  301.998267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  301.998272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.998289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  301.998293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  301.998311] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  301.998388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  301.998419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  301.998451] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  301.998484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  301.998514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  301.998545] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  301.998574] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  301.998604] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  301.998639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  301.998676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.002095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.002117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.002136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.002153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.002176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.002200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.002226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.002251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.002275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.002298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.002321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.002409] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.002440] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.004524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.004546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.004566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.004585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.006147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.006167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.006186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.007749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.007773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.009645] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.012982] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.013036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.013069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.013111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.029860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.029913] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.029985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.063508] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.063550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.063591] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.063636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.063674] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.063715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.063754] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.063793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.063833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.063872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.063911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.063918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.063956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.063963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.064004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.064043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.064081] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.064120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.064158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.064196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.064237] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.064275] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.064314] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.064408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.064471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.079997] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.080044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.080132] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.097131] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.097168] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.097207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.097240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.097271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.097301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.097412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.097458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.097513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.097566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.097876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.097918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.097963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.098047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.098104] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.098161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.098583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.098604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.098626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.098648] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.098667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.098686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.098706] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.098724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.098742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.098758] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.098775] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.098779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.098795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.098799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.098816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.098831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.098848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.098870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.098893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.098916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.098941] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.098964] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.098984] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.099009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.099033] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.099101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.099125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.099148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.099171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.099194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.099217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.099243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.099267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.099292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.099315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.099382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.099423] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.099453] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.101521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.101543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.101562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.101581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.103156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.103176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.103194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.104757] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.104777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.106648] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.109910] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.109956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.109989] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.110033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.110160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.110218] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.110303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.127002] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.127042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.127082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.127123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.127156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.127191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.127227] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.127260] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.127293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.127323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.127432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.127445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.127491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.127504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.127552] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.127595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.127641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.127684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.127735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.127777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.127825] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.128215] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.128243] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.128276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.128311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.143529] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.143577] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.143648] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.160699] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.160735] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.160774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.160807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.160845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.160886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.160925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.160964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.161007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.161048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.161090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.161128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.161165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.161227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.161272] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.161320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.161917] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.161948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.161980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.162015] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.162041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.162072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.162100] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.162129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.162155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.162182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.162205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.162212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.162237] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.162243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.162270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.162294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.162359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.162388] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.162421] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.162448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.162478] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.162504] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.162533] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.162567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.162602] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.162707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.162737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.162767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.162797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.162826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.162856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.162890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.162922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.162954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.162982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.163011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.163044] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.163075] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.165154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.165185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.165214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.165243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.166856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.166885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.166913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.168480] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.168504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.170354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.173662] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.173716] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.173749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.173792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.173898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.173941] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.174006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.190789] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.190829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.190868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.190909] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.190942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.190977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.191013] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.191047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.191080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.191111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.191141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.191149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.191183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.191191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.191232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.191274] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.191315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.191446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.191495] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.191540] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.191585] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.191628] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.191669] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.191715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.191761] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.207283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.207408] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.207515] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.225803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.225840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.225880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.225913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.225944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.225974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.226003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.226034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.226075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.226117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.226158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.226197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.226236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.226291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.226371] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.226410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.226702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.226724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.226749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.226773] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.226793] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.226815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.226840] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.226867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.226893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.226919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.226944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.226950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.226975] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.226980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.227006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.227032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.227058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.227084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.227110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.227135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.227163] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.227188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.227214] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.227241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.227269] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.227384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.227415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.227445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.227473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.227501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.227530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.227562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.227596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.227628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.227657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.227686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.227720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.227753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.229815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.229838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.229861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.229885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.231456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.231477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.231496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.233047] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.233068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.234942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.238262] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.238316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.238431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.238495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.238593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.238644] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.238705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.255395] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.255435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.255475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.255516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.255549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.255585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.255621] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.255654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.255687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.255718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.255747] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.255755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.255784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.255791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.255821] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.255851] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.255880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.255908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.255950] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.255976] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.256004] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.256030] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.256055] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.256086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.256118] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.271882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.271929] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.272017] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.289023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.289060] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.289100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.289132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.289164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.289194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.289223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.289255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.289289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.289402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.289455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.289497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.289541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.289628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.289684] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.289743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.290007] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.290027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.290048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.290071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.290089] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.290108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.290128] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.290146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.290169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.290192] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.290215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.290219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.290242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.290246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.290270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.290293] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.290366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.290396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.290428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.290457] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.290487] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.290515] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.290542] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.290574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.290607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.290710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.290741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.290771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.290801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.290830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.290861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.290895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.290919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.290939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.290958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.290976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.290999] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.291019] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.293066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.293087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.293105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.293124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.294702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.294722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.294740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.296298] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.296329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.298198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.301513] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.301568] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.301607] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.301658] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.301812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.301881] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.301986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.318610] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.318650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.318690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.318732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.318764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.318801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.318836] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.318870] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.318903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.318933] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.318963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.318971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.319000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.319006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.319036] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.319065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.319094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.319123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.319163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.319204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.319247] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.319287] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.319413] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.319454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.319496] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.335137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.335184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.335272] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.352514] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.352551] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.352590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.352623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.352654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.352684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.352714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.352745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.352778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.352809] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.352839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.352867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.352895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.352948] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.352982] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.353018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.353283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.353302] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.353386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.353423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.353452] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.353486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.353518] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.353549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.353578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.353608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.353634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.353643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.353670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.353678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.353707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.353734] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.353763] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.353788] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.353818] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.353847] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.353879] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.353904] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.353932] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.353963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.353996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.354098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.354127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.354156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.354182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.354210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.354237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.354268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.354300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.354357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.354383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.354412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.354447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.354476] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.356542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.356562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.356581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.356599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.358173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.358193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.358211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.359764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.359785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.361658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.364994] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.365047] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.365079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.365121] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.365267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.365401] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.365630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.382129] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.382169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.382209] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.382250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.382289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.382407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.382457] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.382507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.382552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.382601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.382897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.382905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.382931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.382937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.382964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.382989] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.383015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.383039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.383068] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.383092] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.383119] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.383143] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.383169] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.383198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.383229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.398649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.398700] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.398791] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.415839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.415876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.415916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.415948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.415979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.416010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.416039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.416071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.416104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.416144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.416186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.416225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.416264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.416399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.416459] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.416522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.416924] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.416956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.416989] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.417021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.417044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.417068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.417092] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.417115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.417138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.417162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.417184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.417189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.417212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.417216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.417239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.417263] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.417286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.417355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.417394] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.417424] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.417458] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.417487] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.417517] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.417552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.417587] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.417691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.417719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.417748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.417775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.417804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.417832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.417863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.417894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.417926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.417951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.417978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.418009] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.418038] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.420115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.420137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.420156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.420175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.421755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.421775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.421793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.423352] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.423373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.425239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.428554] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.428605] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.428637] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.428679] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.428787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.428823] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.428876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.445637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.445677] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.445717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.445759] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.445792] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.445829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.445864] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.445898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.445931] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.445962] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.445992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.446000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.446029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.446036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.446066] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.446101] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.446142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.446182] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.446223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.446263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.446306] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.446428] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.446474] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.446524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.446576] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.462169] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.462216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.462287] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.479391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.479428] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.479468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.479501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.479532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.479562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.479591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.479622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.479655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.479686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.479717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.479745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.479773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.479826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.479861] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.479897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.480127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.480147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.480167] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.480190] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.480208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.480227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.480246] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.480264] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.480282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.480367] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.480397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.480406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.480436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.480444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.480475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.480505] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.480535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.480565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.480598] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.480628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.480660] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.480689] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.480720] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.480754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.480788] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.481256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.481287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.481352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.481386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.481416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.481448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.481483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.481619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.481649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.481677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.481703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.481735] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.481764] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.483878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.483900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.483919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.483938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.485529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.485553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.485576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.487140] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.487163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.489039] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.492349] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.492392] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.492418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.492454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.492579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.492635] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.492720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.509553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.509594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.509635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.509680] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.509718] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.509758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.509797] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.509837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.509876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.509915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.509954] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.509961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.510000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.510007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.510045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.510084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.510123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.510163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.510202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.510240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.510281] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.510373] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.510431] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.510481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.510536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.525973] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.526020] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.526091] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.543147] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.543184] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.543223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.543256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.543286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.543397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.543441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.543491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.543545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.543595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.543645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.543685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.543727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.543809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.543862] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.543917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.544505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.544535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.544566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.544599] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.544626] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.544656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.544683] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.544712] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.544738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.544764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.544788] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.544795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.544819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.544825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.544851] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.544875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.544900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.544923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.544952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.544975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.545002] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.545026] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.545051] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.545080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.545111] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.545208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.545234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.545260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.545284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.545347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.545380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.545412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.545445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.545478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.545504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.545534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.545569] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.545598] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.547663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.547687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.547710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.547734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.549304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.549343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.549366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.550941] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.550963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.552841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.556137] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.556188] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.556221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.556262] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.556477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.556544] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.556644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.573250] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.573291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.573414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.573475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.573699] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.573735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.573770] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.573801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.573831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.573859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.573886] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.573894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.573920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.573927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.573955] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.573982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.574009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.574036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.574068] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.574096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.574129] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.574145] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.574161] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.574180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.574200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.589768] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.589815] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.589885] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.608252] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.608290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.608422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.608609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.608643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.608674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.608704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.608742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.608785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.608827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.608868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.608912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.608931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.608965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.608988] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.609010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.609217] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.609237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.609258] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.609281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.609352] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.609384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.609420] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.609452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.609485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.609515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.609546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.609554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.609582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.609591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.609621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.609650] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.609681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.609710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.609744] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.609773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.609806] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.609835] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.610143] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.610177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.610212] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.610341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.610374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.610529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.610558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.610586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.610615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.610646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.610676] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.610705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.610732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.610758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.610790] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.610818] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.612905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.612928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.612947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.612966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.614554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.614576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.614597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.616161] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.616184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.618059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.621332] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.621364] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.621387] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.621418] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.621510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.621550] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.621611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.638485] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.638523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.638563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.638608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.638646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.638687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.638727] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.638766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.638806] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.638844] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.638882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.638890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.638928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.638935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.638975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.639014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.639053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.639092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.639129] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.639167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.639208] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.639247] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.639285] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.639386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.639439] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.654934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.654982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.655052] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.672102] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.672139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.672178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.672217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.672257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.672297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.672408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.672457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.672512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.672560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.672603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.672643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.672683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.672749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.672795] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.672843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.673169] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.673204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.673241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.673278] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.673468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.673491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.673522] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.673540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.673558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.673575] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.673591] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.673596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.673612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.673616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.673633] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.673649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.673665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.673681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.673703] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.673726] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.673751] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.673774] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.673797] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.673822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.673847] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.673915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.673939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.673963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.673986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.674009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.674032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.674057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.674082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.674106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.674129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.674151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.674175] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.674196] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.676255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.676277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.676355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.676379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.677956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.677978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.678001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.679566] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.679588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.681459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.684707] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.684739] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.684758] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.684784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.684873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.684912] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.684972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.701809] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.701851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.701895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.701943] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.701983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.702025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.702066] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.702107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.702148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.702188] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.702228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.702236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.702276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.702346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.702402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.702450] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.702497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.702541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.702589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.702632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.702679] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.702721] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.702768] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.703044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.703068] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.718377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.718424] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.718512] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.735545] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.735582] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.735622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.735655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.735685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.735715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.735745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.735776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.735809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.735840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.735879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.735918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.735957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.736022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.736067] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.736114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.736829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.736860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.736892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.736925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.736951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.736980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.737008] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.737035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.737068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.737102] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.737135] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.737143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.737176] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.737182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.737217] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.737250] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.737285] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.737360] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.737402] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.737442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.737484] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.737521] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.737557] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.737599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.737642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.737944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.737968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.737991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.738012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.738032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.738055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.738078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.738101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.738129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.738157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.738185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.738213] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.738242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.740336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.740357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.740375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.740395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.741973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.741993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.742011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.743577] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.743598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.745457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.748755] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.748810] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.748849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.748900] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.749029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.749069] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.749130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.765886] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.765927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.765966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.766007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.766039] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.766075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.766111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.766145] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.766179] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.766218] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.766259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.766267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.766307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.766387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.766446] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.766489] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.766531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.766572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.766616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.766656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.766704] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.766746] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.766786] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.766837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.766875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.782393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.782440] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.782528] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.799533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.799570] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.799611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.799644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.799675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.799706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.799736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.799767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.799801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.799832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.799863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.799892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.799919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.799971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.800007] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.800043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.800354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.800384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.800417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.800452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.800481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.800511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.800543] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.800573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.800602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.800632] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.800661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.800669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.800698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.800705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.800735] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.800764] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.800792] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.800821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.800853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.800872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.800891] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.800909] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.800926] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.800947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.800970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.801039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.801060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.801078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.801098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.801115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.801135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.801157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.801176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.801196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.801214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.801231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.801253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.801273] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.803357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.803378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.803397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.803417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.805001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.805022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.805039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.806595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.806615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.808486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.811784] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.811835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.811872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.811920] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.812062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.812127] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.812220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.828883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.828921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.828958] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.828997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.829028] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.829068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.829108] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.829147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.829187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.829225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.829264] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.829272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.829368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.829384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.829434] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.829478] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.829524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.829566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.829613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.829655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.829701] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.829745] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.829791] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.830027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.830052] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.845460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.845507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.845596] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.862596] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.862633] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.862673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.862706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.862737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.862767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.862796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.862828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.862861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.862893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.862924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.862962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.863001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.863066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.863111] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.863158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.863775] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.863802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.863829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.863858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.863883] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.863910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.863936] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.863962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.863986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.864012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.864037] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.864043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.864068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.864073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.864099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.864125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.864151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.864176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.864202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.864226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.864255] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.864280] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.864335] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.864368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.864402] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.864672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.864694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.864714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.864734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.864753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.864774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.864796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.864816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.864836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.864855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.864872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.864895] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.864920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.866977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.867000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.867019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.867038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.868618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.868638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.868656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.870208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.870228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.872106] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.875452] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.875505] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.875537] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.875579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.875688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.875737] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.875808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.892606] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.892649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.892692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.892739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.892779] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.892821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.892862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.892903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.892944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.892984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.893024] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.893032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.893072] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.893079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.893120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.893160] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.893208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.893241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.893275] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.893358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.893402] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.893442] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.893481] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.893524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.893570] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.909086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.909132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.909203] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.926244] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.926286] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.926421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.926608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.926642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.926674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.926703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.926735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.926769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.926801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.926841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.926880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.926919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.926971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.926998] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.927026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.927242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.927266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.927343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.927383] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.927415] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.927451] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.927485] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.927518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.927550] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.927581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.927611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.927620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.927649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.927657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.927687] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.927717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.927748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.927777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.928060] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.928092] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.928125] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.928155] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.928185] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.928219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.928254] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.928508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.928539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.928568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.928596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.928624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.928653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.928685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.928715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.928744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.928771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.928797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.928828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.928857] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.930939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.930960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.930978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.930997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.932575] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.932594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.932612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.934175] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.934195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.936076] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.939317] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  302.939350] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  302.939373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  302.939404] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  302.939484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.939512] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.939554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.956502] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.956542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.956581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.956622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.956654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.956690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.956727] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.956761] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.956795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.956826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.956856] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.956864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.956894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.956901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.956932] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.956962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.956992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.957021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.957056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.957086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.957128] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.957169] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.957210] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.957253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.957296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.972955] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  302.973003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  302.973075] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  302.990133] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  302.990170] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  302.990210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.990243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.990273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.990387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.990431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.990481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.990534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.990584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.990634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.990675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.990721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.990801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  302.990855] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  302.990910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.991409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  302.991430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  302.991453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  302.991478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  302.991507] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  302.991527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  302.991546] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  302.991564] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  302.991582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  302.991599] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  302.991615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  302.991620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.991636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  302.991639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  302.991656] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  302.991672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  302.991689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  302.991705] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  302.991724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  302.991740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  302.991758] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  302.991774] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  302.991790] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  302.991809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.991830] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  302.991893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  302.991911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  302.991929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  302.991945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  302.991962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  302.991979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  302.991998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  302.992016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  302.992035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  302.992051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  302.992067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  302.992087] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  302.992106] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  302.994172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.994194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.994213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.994232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.995811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  302.995834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  302.995857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.997428] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.997449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  302.999336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.002653] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.002685] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.002704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.002730] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.002808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.002836] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.002880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.019747] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.019785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.019822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.019861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.019891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.019926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.019959] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.019991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.020021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.020050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.020077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.020085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.020112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.020118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.020147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.020184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.020224] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.020263] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.020382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.020427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.020476] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.020518] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.020560] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.020606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.020656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.036268] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.036350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.036425] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.054887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.054924] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.054963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.054996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.055027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.055065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.055105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.055144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.055187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.055228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.055269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.055389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.055437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.055526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.055584] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.055643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.056101] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.056133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.056165] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.056194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.056213] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.056233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.056253] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.056272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.056339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.056373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.056399] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.056410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.056437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.056445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.056475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.056502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.056531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.056557] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.056589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.056616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.056645] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.056671] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.056700] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.056733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.056766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.056853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.056881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.056909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.056935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.056963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.056990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.057021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.057052] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.057082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.057108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.057135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.057165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.057195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.059280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.059326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.059349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.059373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.060949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.060970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.060989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.062552] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.062576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.064449] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.067787] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.067840] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.067872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.067914] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.068062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.068129] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.068232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.084929] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.084969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.085009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.085050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.085082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.085118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.085154] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.085188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.085221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.085256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.085364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.085379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.085426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.085439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.085488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.085531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.085580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.085607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.085641] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.085668] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.085699] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.085725] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.085754] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.085787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.085820] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.101442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.101489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.101578] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.118587] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.118629] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.118674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.118714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.118754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.118794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.118833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.118872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.118914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.118956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.118997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.119036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.119074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.119139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.119184] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.119231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.119665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.119696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.119730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.119768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.119796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.119828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.119858] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.119888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.119916] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.119945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.119970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.119978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.120005] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.120011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.120040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.120066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.120093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.120118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.120149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.120174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.120203] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.120229] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.120256] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.120310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.120345] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.120448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.120479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.120506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.120534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.120559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.120588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.120621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.120652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.120682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.120708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.120735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.120768] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.120796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.122881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.122901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.122920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.122939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.124509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.124529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.124547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.126097] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.126118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.127984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.131280] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.131368] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.131407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.131458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.131582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.131613] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.131669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.148440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.148482] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.148523] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.148567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.148605] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.148646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.148685] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.148724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.148764] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.148803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.148841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.148849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.148887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.148894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.148933] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.148973] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.149011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.149057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.149089] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.149117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.149145] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.149170] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.149194] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.149222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.149251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.164908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.164952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.165019] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.183232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.183269] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.183391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.183439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.183488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.183530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.183575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.183619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.183670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.183720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.183769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.183817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.183845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.183901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.183935] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.183971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.184241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.184266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.184336] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.184377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.184406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.184440] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.184470] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.184502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.184531] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.184561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.184588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.184597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.184624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.184632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.184663] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.184691] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.184720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.184746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.184778] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.184804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.184835] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.184862] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.184890] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.184919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.184952] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.185055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.185083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.185112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.185138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.185166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.185193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.185224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.185256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.185313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.185340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.185369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.185404] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.185433] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.187503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.187525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.187543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.187563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.189125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.189145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.189163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.190726] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.190747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.192621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.195960] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.196025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.196048] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.196074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.196156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.196183] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.196224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.213086] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.213130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.213173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.213219] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.213259] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.213373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.213425] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.213477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.213523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.213571] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.213613] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.213627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.213670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.214044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.214080] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.214119] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.214159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.214198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.214238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.214276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.214371] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.214426] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.214472] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.214526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.214562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.229610] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.229657] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.229728] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.248227] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.248264] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.248387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.248579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.248612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.248644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.248673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.248705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.248747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.248790] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.248831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.248870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.248909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.248972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.249017] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.249064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.249646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.249668] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.249691] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.249718] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.249741] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.249765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.249788] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.249811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.249835] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.249858] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.249881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.249886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.249909] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.249913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.249937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.249960] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.249983] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.250006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.250030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.250052] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.250077] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.250100] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.250123] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.250147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.250173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.250240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.250264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.250333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.250369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.250398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.250431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.250465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.250498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.250531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.250558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.250587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.250623] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.250654] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.253043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.253066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.253085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.253106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.254664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.254687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.254710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.256267] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.256305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.258174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.261533] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.261577] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.261604] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.261640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.261733] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.261769] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.261822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.278643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.278683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.278723] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.278766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.278807] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.278849] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.278890] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.278931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.278972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.279013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.279052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.279061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.279101] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.279107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.279148] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.279189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.279230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.279270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.279381] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.279431] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.279480] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.279526] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.279569] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.279620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.279671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.295139] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.295186] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.295273] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.312399] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.312441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.312486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.312526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.312565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.312604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.312644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.312683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.312725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.312767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.312808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.312847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.312885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.312950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.312995] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.313042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.313870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.313902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.313935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.313970] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.313998] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.314029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.314060] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.314089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.314118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.314146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.314173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.314180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.314206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.314212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.314240] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.314277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.314335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.314367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.314402] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.314432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.314464] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.314494] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.314524] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.314556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.314592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.315011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.315032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.315052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.315070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.315087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.315106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.315126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.315144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.315163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.315179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.315195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.315242] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.315358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.317616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.317637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.317655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.317674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.319260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.319295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.319313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.320883] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.320906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.322822] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.326051] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.326083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.326103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.326128] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.326213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.326241] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.326343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.343180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.343218] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.343255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.343382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.343435] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.343643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.343679] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.343710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.343742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.343770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.343797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.343805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.343832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.343839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.343867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.343905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.343945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.343984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.344023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.344062] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.344103] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.344142] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.344181] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.344222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.344270] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.359645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.359690] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.359758] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.378232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.378269] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.378401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.378454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.378506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.378553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.378585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.378616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.378654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.378687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.378719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.378747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.378776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.378829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.378865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.378901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.379184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.379203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.379224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.379247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.379317] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.379347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.379378] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.379406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.379434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.379461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.379489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.379497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.379523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.379531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.379558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.379584] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.379611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.379637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.379667] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.379693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.379725] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.379753] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.379781] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.379815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.379849] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.379953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.379984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.380014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.380044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.380073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.380101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.380123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.380149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.380177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.380202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.380228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.380254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.380315] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.382377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.382400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.382423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.382447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.384019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.384039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.384057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.385620] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.385641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.387513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.390821] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.390871] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.390902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.390943] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.391050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.391092] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.391153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.407934] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.407977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.408020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.408067] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.408107] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.408149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.408190] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.408231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.408273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.408383] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.408431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.408444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.408489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.408500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.408545] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.408588] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.408638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.408896] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.408919] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.408939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.408960] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.408978] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.408997] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.409018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.409042] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.424451] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.424501] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.424575] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.441580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.441618] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.441662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.441702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.441742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.441781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.441821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.441860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.441903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.441944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.441986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.442024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.442063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.442128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.442172] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.442220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.442849] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.442873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.442897] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.442922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.442942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.442967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.442993] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.443018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.443044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.443069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.443093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.443099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.443123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.443128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.443153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.443178] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.443204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.443229] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.443254] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.443314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.443348] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.443377] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.443405] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.443437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.443471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.443712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.443733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.443754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.443773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.443799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.443825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.443853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.443881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.443909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.443935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.443961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.443988] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.444014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.446067] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.446089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.446108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.446127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.447696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.447716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.447734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.449317] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.449338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.451202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.454519] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.454568] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.454598] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.454637] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.454740] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.454781] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.454826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.471582] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.471626] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.471670] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.471716] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.471756] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.471798] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.471839] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.471880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.471922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.471962] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.472002] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.472010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.472050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.472057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.472098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.472138] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.472179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.472225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.472261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.472364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.472417] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.472462] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.472506] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.472556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.472606] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.488132] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.488183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.488273] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.505547] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.505584] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.505624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.505656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.505686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.505715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.505743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.505775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.505808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.505840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.505871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.505900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.505927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.505980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.506022] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.506053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.506815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.506862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.506910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.506961] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.507011] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.507042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.507072] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.507101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.507130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.507158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.507185] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.507192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.507218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.507224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.507252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.507324] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.507352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.507382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.507416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.507447] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.507481] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.507511] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.507541] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.507573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.507609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.507921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.507942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.507960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.507978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.507996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.508014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.508035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.508058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.508083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.508106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.508129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.508154] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.508174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.510221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.510244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.510315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.510353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.512011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.512031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.512049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.513612] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.513632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.515506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.518810] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.518860] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.518892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.518934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.519041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.519084] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.519145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.535909] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.535949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.535989] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.536031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.536064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.536100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.536135] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.536169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.536201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.536232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.536263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.536334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.536387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.536400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.536449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.536498] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.536546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.536590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.536625] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.536655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.536688] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.536719] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.536749] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.537055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.537087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.552448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.552496] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.552567] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.569571] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.569608] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.569648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.569681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.569712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.569742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.569770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.569802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.569836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.569868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.569899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.569927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.569955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.570008] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.570043] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.570088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.570767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.570799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.570831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.570866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.570894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.570926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.570957] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.570986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.571015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.571043] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.571071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.571078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.571104] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.571111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.571138] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.571164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.571191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.571214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.571243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.571310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.571342] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.571374] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.571404] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.571438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.571473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.571752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.571774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.571795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.571814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.571832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.571852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.571873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.571894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.571919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.571945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.571969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.571996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.572022] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.574075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.574097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.574116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.574136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.575715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.575737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.575760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.577354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.577376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.579249] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.582595] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.582639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.582661] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.582692] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.582800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.582840] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.582901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.599720] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.599761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.599801] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.599842] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.599875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.599911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.599947] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.599981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.600013] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.600045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.600075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.600083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.600113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.600119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.600149] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.600179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.600208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.600237] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.600346] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.600389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.600435] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.600476] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.600516] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.600564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.600614] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.616240] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.616318] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.616408] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.634945] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.634983] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.635022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.635055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.635094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.635134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.635174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.635213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.635255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.635387] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.635445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.635495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.635545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.635633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.635691] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.635750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.636147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.636167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.636190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.636213] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.636231] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.636251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.636323] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.636353] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.636387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.636418] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.636449] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.636458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.636488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.636496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.636526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.636557] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.636587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.636615] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.636646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.636675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.636706] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.636735] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.636761] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.636793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.636827] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.636931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.636961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.636991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.637020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.637049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.637077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.637110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.637142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.637174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.637202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.637231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.637288] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.637318] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.639383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.639404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.639422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.639441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.641008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.641028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.641046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.642609] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.642630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.644506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.647840] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.647894] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.647926] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.647968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.648076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.648119] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.648181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.665024] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.665062] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.665099] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.665138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.665169] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.665202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.665235] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.665346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.665395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.665445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.665493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.665507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.665553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.665568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.665615] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.665665] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.665930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.665959] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.665990] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.666019] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.666048] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.666075] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.666102] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.666133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.666164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.681479] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.681524] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.681589] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.698594] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.698631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.698670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.698704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.698734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.698773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.698813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.698852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.698894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.698935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.698977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.699015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.699054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.699119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.699164] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.699211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.699862] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.699884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.699906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.699930] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.699948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.699968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.699988] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.700006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.700024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.700041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.700057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.700061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.700077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.700081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.700098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.700113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.700129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.700145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.700164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.700179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.700196] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.700212] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.700227] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.700246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.700320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.700423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.700658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.700689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.700720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.700751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.700783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.700818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.700851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.700883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.700912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.700940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.700975] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.701005] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.703073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.703094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.703113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.703137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.704714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.704735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.704754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.706473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.706495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.708369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.711665] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.711717] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.711744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.711779] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.711870] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.711905] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.711957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.728823] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.728860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.728900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.728945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.728983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.729024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.729064] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.729103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.729143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.729182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.729220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.729228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.729343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.729357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.729415] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.729466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.729519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.729567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.729621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.729670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.729724] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.729772] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.729821] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.729875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.730241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.745319] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.745364] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.745431] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.762435] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.762473] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.762513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.762546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.762578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.762608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.762638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.762670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.762703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.762743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.762785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.762824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.762863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.762914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.762938] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.762961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.763172] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.763191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.763212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.763235] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.763315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.763349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.763383] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.763416] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.763448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.763479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.763509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.763519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.763547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.763555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.763585] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.763615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.763645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.763674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.763708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.763737] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.763770] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.763799] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.763829] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.763862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.764197] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.764411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.764442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.764471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.764499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.764527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.764552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.764583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.764613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.764643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.764670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.764696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.764727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.764756] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.766857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.766878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.766896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.766915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.768485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.768509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.768529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.770068] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.770089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.771967] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.775244] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.775311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.775338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.775374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.775490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.775545] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.775630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.792430] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.792470] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.792510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.792552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.792585] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.792621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.792662] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.792703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.792745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.792785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.792825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.792833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.792873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.792880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.792921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.792962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.793003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.793043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.793084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.793124] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.793167] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.793207] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.793247] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.793359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.793412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.808895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.808943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.809031] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.826089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.826126] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.826166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.826199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.826229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.826343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.826504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.826537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.826570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.826600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.826630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.826656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.826683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.826732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.826767] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.826800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.827097] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.827127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.827160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.827195] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.827223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.827307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.827353] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.827395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.827445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.827473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.827499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.827509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.827534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.827542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.827569] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.827596] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.827622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.827648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.827679] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.827707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.827914] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.827939] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.827966] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.827993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.828021] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.828094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.828120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.828146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.828171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.828197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.828222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.828278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.828312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.828344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.828371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.828398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.828431] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.828460] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.830680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.830703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.830725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.830749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.832356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.832377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.832399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.833958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.833980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.835851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.839173] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.839226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.839326] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.839399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.839566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.839611] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.839682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.856339] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.856378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.856415] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.856454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.856484] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.856517] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.856550] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.856581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.856612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.856640] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.856668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.856676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.856703] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.856710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.856738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.856765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.856792] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.856819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.856853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.856892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.856933] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.856972] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.857012] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.857061] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.857092] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.872769] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.872817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.872906] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.889947] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.889983] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.890023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.890056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.890087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.890116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.890144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.890175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.890209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.890240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.890356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.890400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.890448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.890536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.890779] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.890817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.891102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.891122] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.891143] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.891166] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.891184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.891204] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.891223] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.891295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.891326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.891358] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.891388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.891398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.891427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.891435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.891466] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.891496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.891527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.891557] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.891590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.891856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.891886] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.891914] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.891942] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.891972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.892004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.892100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.892129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.892156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.892183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.892210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.892239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.892317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.892353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.892386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.892416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.892446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.892481] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.892651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.894688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.894709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.894728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.894746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.896351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.896371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.896389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.897949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.897971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.899842] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.903117] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.903148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.903167] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.903193] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.903315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.903451] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.903518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.920186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.920226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.920342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.920406] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.920595] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.920631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.920665] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.920696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.920726] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.920754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.920782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.920789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.920816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.920822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.920850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.920878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.920904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.920931] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.920963] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.920991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.921020] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.921046] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.921073] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.921105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.921140] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.936731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  303.936777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  303.936846] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  303.953877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  303.953915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  303.953955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.953989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.954019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.954049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.954079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.954110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.954143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.954174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.954205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.954233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.954344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.954422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.954472] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.954525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.955020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.955050] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.955082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.955116] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.955142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.955172] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.955206] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.955242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.955332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.955367] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.955400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.955409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.955439] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.955448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.955479] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.955509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.955542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.955572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.955606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.955635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.955664] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.955694] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.955723] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.955756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.955791] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  303.955894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  303.955926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  303.955956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  303.955985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  303.956015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  303.956046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  303.956080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  303.956112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  303.956144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.956173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  303.956202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  303.956235] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  303.956293] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  303.958356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.958376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.958394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.958413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.959973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  303.959996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.960019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.961584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.961605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  303.963475] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.966757] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  303.966799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  303.966826] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  303.966861] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.966953] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  303.966989] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  303.967040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  303.983844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  303.983888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.983931] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  303.983978] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.984019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.984061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.984101] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  303.984142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  303.984183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.984223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.984350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.984367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.984419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.984432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  303.984484] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  303.984533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.984583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.984631] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.984684] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  303.984732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.984784] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  303.984830] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  303.984873] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  303.984920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.984954] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.000390] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.000437] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.000508] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.017509] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.017546] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.017585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.017618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.017649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.017679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.017708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.017740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.017773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.017805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.017836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.017863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.017891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.017943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.017978] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.018013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.018536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.018589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.018647] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.018684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.018715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.018748] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.018781] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.018812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.018844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.018874] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.018903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.018911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.018939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.018946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.018975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.019006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.019035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.019064] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.019094] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.019123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.019154] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.019184] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.019212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.019244] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.019300] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.019404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.019435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.019466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.019495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.019521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.019552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.019585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.019618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.019650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.019678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.019707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.019740] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.019772] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.021851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.021874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.021893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.021912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.023492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.023513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.023531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.025084] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.025105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.026979] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.030288] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.030339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.030371] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.030412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.030550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.030615] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.030716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.047384] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.047421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.047459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.047499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.047530] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.047564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.047597] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.047629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.047659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.047687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.047716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.047723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.047751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.047757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.047786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.047813] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.047841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.047868] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.047900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.047928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.047957] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.047984] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.048010] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.048043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.048077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.063910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.063957] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.064045] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.081071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.081108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.081148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.081180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.081210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.081239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.081356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.081403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.081459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.081494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.081525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.081555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.081582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.081637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.081674] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.081710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.082047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.082073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.082100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.082129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.082154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.082180] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.082205] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.082230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.082293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.082324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.082352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.082361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.082387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.082395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.082423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.082450] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.082477] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.082504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.082534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.082560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.082589] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.082618] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.082646] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.082677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.082711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.082815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.082847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.082877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.082907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.082936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.082967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.082996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.083018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.083038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.083057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.083075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.083098] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.083118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.085192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.085214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.085291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.085329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.086898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.086918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.086936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.088500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.088520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.090510] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.093859] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.093912] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.093945] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.093988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.094098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.094140] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.094208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.111033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.111071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.111108] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.111146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.111177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.111210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.111249] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.111366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.111424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.111474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.111525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.111540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.111587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.111600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.111647] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.111912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.111942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.111969] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.112000] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.112028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.112057] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.112084] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.112111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.112141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.112173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.127475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.127522] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.127609] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.144684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.144720] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.144760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.144792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.144822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.144850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.144878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.144909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.144943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.144974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.145005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.145033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.145060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.145114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.145149] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.145185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.145840] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.145861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.145883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.145908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.145931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.145955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.145978] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.146002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.146025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.146048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.146071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.146076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.146099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.146103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.146126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.146149] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.146173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.146196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.146219] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.146293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.146326] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.146361] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.146392] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.146428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.146464] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.146832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.146862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.146891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.146919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.146947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.146976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.147008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.147038] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.147068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.147095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.147122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.147153] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.147182] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.149286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.149307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.149326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.149345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.150916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.150936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.150954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.152518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.152538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.154410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.157729] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.157761] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.157781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.157806] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.157887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.157914] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.157955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.174818] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.174862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.174905] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.174952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.174992] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.175034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.175075] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.175116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.175157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.175197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.175237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.175319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.175377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.175391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.175445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.175497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.175546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.175595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.175649] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.175698] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.175750] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.175798] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.175839] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.175894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.175946] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.191377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.191424] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.191495] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.208497] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.208534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.208574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.208607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.208638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.208668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.208697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.208728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.208761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.208793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.208832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.208871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.208910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.208968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.208999] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.209031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.209461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.209504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.209550] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.209598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.209639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.209683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.209726] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.209767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.209808] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.209847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.209885] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.209895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.209939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.209947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.209977] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.210006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.210035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.210061] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.210093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.210122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.210153] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.210182] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.210211] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.210264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.210301] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.210408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.210439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.210469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.210496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.210526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.210553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.210587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.210619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.210651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.210680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.210708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.210742] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.210773] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.212852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.212874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.212894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.212913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.214491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.214511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.214529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.216080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.216101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.217974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.221213] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.221261] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.221280] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.221306] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.221411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.221450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.221511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.238394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.238432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.238470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.238509] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.238539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.238573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.238606] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.238637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.238668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.238697] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.238725] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.238733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.238760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.238767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.238795] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.238823] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.238861] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.238900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.238940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.238978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.239020] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.239059] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.239098] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.239138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.239179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.254843] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.254888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.254985] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.272050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.272087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.272126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.272159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.272197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.272236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.272357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.272409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.272465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.272518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.272570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.272601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.272629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.272683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.272720] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.272756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.273064] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.273096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.273131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.273169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.273199] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.273232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.273320] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.273349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.273377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.273446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.273475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.273483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.273512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.273519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.273548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.273577] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.273606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.273632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.273654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.273672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.273692] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.273710] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.273729] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.273750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.273773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.273841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.273862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.273880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.273899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.273917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.273936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.273957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.273983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.274011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.274036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.274062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.274089] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.274116] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.276176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.276199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.276222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.276301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.277887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.277911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.277935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.279503] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.279526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.281399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.284673] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.284706] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.284726] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.284751] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.284832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.284860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.284900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.301810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.301852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.301893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.301937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.301975] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.302016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.302055] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.302094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.302133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.302172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.302210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.302285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.302344] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.302357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.302412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.302463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.302513] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.302563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.302616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.302666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.302718] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.302765] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.302806] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.303127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.303163] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.318318] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.318365] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.318451] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.335497] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.335534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.335573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.335607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.335636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.335665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.335693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.335723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.335757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.335788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.335829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.335868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.335906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.335971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.336017] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.336064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.336635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.336694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.336730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.336768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.336799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.336833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.336866] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.336898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.336929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.336959] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.336988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.336997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.337025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.337032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.337062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.337091] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.337120] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.337149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.337181] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.337211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.337264] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.337296] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.337323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.337358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.337394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.337498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.337529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.337560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.337590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.337621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.337651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.337685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.337717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.337749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.337778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.337807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.337841] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.337872] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.339934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.339954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.339972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.339991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.341567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.341587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.341605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.343164] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.343185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.345100] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.348444] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.348496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.348528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.348578] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.348691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.348734] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.348796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.365571] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.365611] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.365651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.365693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.365727] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.365763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.365798] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.365832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.365864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.365894] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.365924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.365932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.365962] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.365968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.365999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.366029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.366058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.366088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.366122] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.366152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.366183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.366212] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.366332] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.366367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.366404] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.382083] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.382130] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.382218] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.399329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.399366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.399405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.399438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.399469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.399498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.399526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.399557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.399590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.399629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.399671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.399710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.399749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.399813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.399859] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.399906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.400168] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.400190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.400211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.400305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.400338] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.400374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.400408] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.400441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.400473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.400505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.400535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.400545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.400573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.400581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.400611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.400641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.400672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.400700] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.400734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.400764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.400794] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.400823] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.400852] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.400885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.400920] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.401024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.401055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.401085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.401115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.401142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.401172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.401205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.401261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.401293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.401322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.401352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.401388] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.401423] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.403497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.403518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.403537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.403556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.405119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.405139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.405157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.406711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.406731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.408634] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.411955] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.412011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.412051] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.412102] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.412255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.412344] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.412413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.429050] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.429088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.429125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.429164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.429194] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.429228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.429344] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.429390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.429442] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.429485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.429532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.429546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.429591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.429602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.429647] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.429694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.429736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.429773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.429815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.429851] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.429892] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.429928] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.429966] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.430006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.430052] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.445563] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.445610] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.445698] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.462781] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.462818] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.462858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.462891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.462921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.462950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.462978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.463009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.463043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.463075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.463106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.463134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.463162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.463215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.463342] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.463404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.463751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.463778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.463805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.463835] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.463859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.463885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.463910] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.463936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.463962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.463988] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.464013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.464019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.464044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.464050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.464075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.464101] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.464126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.464152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.464178] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.464203] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.464261] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.464292] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.464320] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.464351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.464384] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.464491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.464523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.464554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.464584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.464615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.464646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.464680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.464703] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.464723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.464741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.464759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.464782] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.464807] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.466869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.466893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.466916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.466941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.468521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.468543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.468562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.470111] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.470132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.472006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.475355] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.475409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.475441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.475483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.475589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.475632] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.475693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.492474] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.492515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.492555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.492597] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.492630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.492666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.492702] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.492736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.492769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.492799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.492829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.492837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.492867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.492873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.492904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.492934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.492963] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.492992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.493026] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.493055] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.493086] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.493115] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.493145] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.493165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.493187] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.508987] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.509033] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.509120] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.526140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.526177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.526216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.526339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.526390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.526440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.526488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.526530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.526567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.526600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.526632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.526661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.526689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.526743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.526780] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.526817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.527092] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.527112] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.527134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.527157] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.527179] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.527203] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.527275] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.527304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.527334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.527363] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.527389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.527398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.527424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.527432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.527459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.527485] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.527512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.527538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.527569] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.527595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.527624] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.527650] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.527679] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.527712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.527748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.527852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.527883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.527913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.527943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.527972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.528002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.528029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.528051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.528070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.528089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.528107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.528130] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.528151] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.530188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.530208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.530282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.530320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.531889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.531912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.531935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.533499] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.533520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.535390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.538727] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.538779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.538812] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.538854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.538962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.539004] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.539066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.555866] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.555906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.555945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.555989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.556029] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.556072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.556112] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.556153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.556195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.556305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.556352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.556365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.556409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.556421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.556466] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.556509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.556557] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.556758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.556781] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.556802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.556822] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.556841] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.556859] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.556881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.556904] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.572381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.572433] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.572508] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.589509] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.589548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.589587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.589620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.589650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.589680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.589709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.589740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.589773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.589805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.589835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.589864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.589891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.589944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.589979] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.590015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.590549] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.590571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.590596] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.590620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.590640] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.590663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.590684] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.590705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.590725] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.590745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.590762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.590769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.590786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.590790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.590809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.590826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.590844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.590861] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.590883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.590907] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.590935] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.590961] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.590987] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.591014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.591042] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.591113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.591139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.591166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.591191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.591220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.591275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.591312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.591343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.591374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.591401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.591427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.591461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.591490] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.593822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.593843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.593862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.593880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.595457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.595478] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.595496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.597053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.597074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.598945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.602226] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.602303] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.602335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.602376] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.602482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.602524] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.602585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.619378] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.619416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.619454] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.619493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.619524] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.619558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.619592] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.619623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.619653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.619681] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.619709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.619716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.619743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.619750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.619778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.619805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.619832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.619859] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.619892] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.619919] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.619948] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.619975] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.620001] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.620039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.620060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.635880] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.635931] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.636023] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.653067] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.653120] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.653177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.653226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.653345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.653393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.653439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.653488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.653539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.653587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.653636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.653679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.653721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.653804] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.653840] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.653876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.654258] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.654283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.654309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.654339] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.654363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.654389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.654414] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.654440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.654466] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.654491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.654516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.654522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.654547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.654552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.654578] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.654603] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.654628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.654653] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.654686] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.654709] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.654733] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.654756] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.654779] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.654803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.654828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.654896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.654920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.654944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.654967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.654991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.655014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.655039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.655063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.655088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.655110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.655132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.655156] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.655177] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.657282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.657304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.657323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.657345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.658917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.658937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.658956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.660520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.660541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.662410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.665744] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.665799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.665839] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.665891] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.665996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.666025] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.666067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.682887] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.682927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.682966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.683009] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.683041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.683078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.683114] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.683148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.683181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.683212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.683320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.683338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.683386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.683398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.683447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.683494] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.683542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.683588] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.683642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.683688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.683739] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.684145] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.684193] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.684280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.684338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.699399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.699447] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.699518] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.716521] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.716558] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.716598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.716631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.716662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.716692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.716721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.716752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.716793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.716835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.716876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.716915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.716954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.717018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.717064] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.717105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.717647] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.717679] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.717712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.717747] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.717776] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.717808] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.717838] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.717868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.717897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.717924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.717951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.717958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.717985] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.717991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.718018] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.718045] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.718070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.718096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.718126] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.718154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.718183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.718221] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.718278] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.718315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.718352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.718651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.718674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.718694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.718713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.718732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.718752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.718774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.718794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.718814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.718832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.718849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.718872] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.718893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.720944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.720966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.720985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.721004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.722593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.722615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.722634] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.724202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.724234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.726103] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.729414] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.729445] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.729465] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.729490] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.729573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.729605] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.729650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.746521] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.746561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.746600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.746641] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.746674] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.746710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.746747] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.746780] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.746813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.746845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.746875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.746882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.746911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.746918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.746948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.746978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.747007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.747036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.747070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.747100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.747136] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.747177] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.747218] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.747334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.747396] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.763040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.763087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.763158] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.780171] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.780208] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.780340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.780392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.780442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.780489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.780535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.780585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.780638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.780690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.780741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.780786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.780832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.780917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.780974] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.781032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.781522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.781543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.781565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.781589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.781607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.781627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.781647] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.781665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.781682] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.781700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.781716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.781720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.781736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.781740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.781757] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.781774] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.781790] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.781806] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.781825] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.781841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.781859] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.781875] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.781891] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.781910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.781931] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.781993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.782012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.782029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.782046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.782062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.782080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.782104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.782129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.782154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.782177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.782199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.782271] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.782303] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.784378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.784399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.784418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.784437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.786006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.786026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.786044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.787606] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.787627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.789502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.792769] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.792799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.792818] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.792843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.792923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.792950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.792990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.809877] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.809917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.809957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.809998] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.810031] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.810067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.810103] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.810136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.810169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.810200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.810308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.810325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.810373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.810386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.810435] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.810483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.810532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.810580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.810634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.810681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.810731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.811076] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.811132] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.811166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.811200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.826366] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.826416] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.826506] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.843555] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.843592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.843635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.843676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.843715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.843755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.843794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.843834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.843876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.843918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.843959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.843998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.844036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.844100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.844145] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.844192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.844965] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.844987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.845009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.845032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.845050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.845070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.845090] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.845109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.845131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.845154] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.845177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.845182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.845205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.845251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.845287] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.845324] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.845356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.845387] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.845423] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.845456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.845486] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.845517] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.845547] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.845582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.845617] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.845965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.845995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.846023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.846051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.846079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.846108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.846140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.846170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.846200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.846270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.846300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.846338] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.846370] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.848590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.848611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.848630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.848648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.850206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.850251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.850269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.851841] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.851865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.853748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.857045] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.857078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.857097] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.857123] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.857264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.857308] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.857374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.874166] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.874206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.874321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.874378] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.874421] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.874472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.874519] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.874565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.874608] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.874653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.874693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.874705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.874745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.874756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.874800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.874859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.874898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.874943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.874989] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.875031] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.875074] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.875117] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.875155] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.875205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.875298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.890675] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.890722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.890810] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.907862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.907904] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.907949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.907989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.908028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.908068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.908107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.908146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.908189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.908307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.908364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.908410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.908458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.908545] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.908601] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.908659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.909140] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.909161] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.909182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.909256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.909286] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.909321] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.909352] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.909385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.909414] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.909445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.909471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.909480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.909507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.909514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.909542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.909568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.909595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.909620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.909651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.909676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.909706] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.909731] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.909758] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.909787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.909819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.909922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.909949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.909977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.910003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.910031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.910058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.910089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.910120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.910151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.910177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.910205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.910260] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.910289] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.912365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.912387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.912406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.912425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.913996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.914019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.914042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.915596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.915618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.917488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.920793] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.920844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.920876] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.920918] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.921025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.921067] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.921129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.937887] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.937926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.937966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.938012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.938053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.938095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.938136] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.938176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.938218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.938343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.938396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.938411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.938461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.938474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.938525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.938574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.938622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.938669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.938727] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.938757] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.938788] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.938818] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.938846] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.938877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.938910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.954404] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  304.954451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  304.954538] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  304.971603] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  304.971641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  304.971681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.971713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.971744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.971772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.971800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.971830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.971864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.971895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.971926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.971953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.971981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.972034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.972070] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.972105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.972601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  304.972634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.972669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  304.972706] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.972737] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.972769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.972802] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  304.972833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  304.972864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.972894] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.972923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.972931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.972959] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.972966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  304.972996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  304.973025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.973055] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.973083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.973116] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  304.973144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.973172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  304.973201] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  304.973253] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  304.973288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.973324] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  304.973430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  304.973462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  304.973492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  304.973522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  304.973550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  304.973578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  304.973611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  304.973643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  304.973676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  304.973705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  304.973733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  304.973767] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  304.973798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  304.975871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.975892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.975910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.975929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.977504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  304.977524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  304.977541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.979099] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.979120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  304.980992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.984341] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  304.984394] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  304.984426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  304.984468] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  304.984579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  304.984607] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  304.984647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.001498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.001540] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.001579] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.001621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.001654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.001690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.001726] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.001760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.001792] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.001823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.001853] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.001861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.001890] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.001897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.001927] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.001956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.001986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.002015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.002049] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.002089] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.002131] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.002173] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.002213] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.002314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.002368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.017984] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.018030] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.018102] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.035103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.035141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.035181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.035305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.035358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.035409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.035458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.035508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.035560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.035610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.035668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.035697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.035726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.035781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.035817] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.035855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.036105] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.036125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.036146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.036172] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.036195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.036294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.036329] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.036362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.036396] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.036428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.036458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.036467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.036496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.036504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.036534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.036563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.036590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.036620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.036654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.036682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.036710] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.036738] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.036767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.036797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.036832] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.036933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.036964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.036994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.037024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.037054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.037086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.037119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.037152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.037185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.037243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.037270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.037306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.037338] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.039401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.039421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.039440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.039459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.041031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.041054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.041077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.042633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.042654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.044526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.047823] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.047882] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.047909] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.047944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.048035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.048071] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.048124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.064913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.064954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.064993] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.065037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.065077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.065119] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.065160] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.065201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.065319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.065378] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.065428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.065444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.065493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.065505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.065557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.065605] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.065654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.066042] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.066094] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.066143] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.066193] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.066279] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.066309] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.066345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.066380] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.081466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.081512] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.081583] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.100146] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.100184] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.100313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.100498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.100531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.100562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.100591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.100622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.100657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.100689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.100721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.100749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.100776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.100828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.100863] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.100900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.101162] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.101186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.101262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.101302] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.101334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.101368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.101402] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.101435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.101467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.101499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.101529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.101538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.101567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.101575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.101606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.101636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.101667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.101696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.101980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.102013] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.102046] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.102077] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.102107] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.102141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.102176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.102432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.102462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.102492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.102520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.102547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.102576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.102607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.102636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.102666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.102693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.102719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.102750] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.102779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.104862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.104883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.104901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.104920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.106494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.106514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.106533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.108090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.108111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.109984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.113293] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.113323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.113342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.113367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.113448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.113475] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.113515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.130437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.130478] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.130518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.130558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.130594] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.130637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.130679] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.130720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.130761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.130801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.130842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.130850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.130890] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.130897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.130938] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.130979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.131019] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.131060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.131100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.131140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.131183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.131283] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.131338] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.131395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.131454] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.146904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.146953] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.147041] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.164032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.164069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.164109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.164142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.164172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.164295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.164345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.164405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.164457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.164504] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.164553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.164595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.164637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.164719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.164772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.164827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.165258] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.165293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.165332] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.165376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.165411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.165435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.165458] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.165488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.165520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.165552] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.165582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.165590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.165619] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.165627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.165658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.165687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.165717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.165740] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.165764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.165789] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.165816] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.165841] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.165866] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.165893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.165920] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.165995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.166021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.166047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.166072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.166097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.166122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.166149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.166176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.166240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.166271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.166304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.166341] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.166374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.168447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.168468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.168487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.168506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.170075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.170095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.170117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.171677] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.171698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.173601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.176777] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.176822] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.176849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.176885] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.176977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.177012] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.177064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.193853] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.193893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.193935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.193981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.194022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.194064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.194105] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.194146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.194188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.194305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.194362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.194376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.194426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.194438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.194489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.194538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.194588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.194636] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.194690] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.194737] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.195129] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.195158] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.195186] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.195260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.195298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.210365] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.210412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.210498] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.227552] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.227589] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.227628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.227661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.227691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.227719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.227747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.227778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.227811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.227842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.227872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.227900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.227927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.227979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.228014] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.228050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.228870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.228902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.228935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.228969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.228998] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.229028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.229059] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.229089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.229118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.229145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.229172] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.229217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.229248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.229258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.229290] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.229320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.229350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.229380] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.229414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.229445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.229476] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.229506] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.229537] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.229571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.229607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.229877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.229907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.229926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.229949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.229972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.229995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.230021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.230046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.230070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.230093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.230116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.230140] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.230161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.232260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.232281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.232300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.232319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.233876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.233899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.233921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.235474] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.235495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.237367] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.240702] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.240755] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.240787] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.240829] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.240939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.240981] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.241045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.257848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.257888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.257928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.257974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.258015] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.258057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.258098] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.258139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.258180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.258298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.258356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.258370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.258420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.258433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.258487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.258530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.258573] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.258615] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.258662] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.258705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.259059] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.259101] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.259143] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.259189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.259279] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.274359] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.274406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.274479] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.292767] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.292806] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.292851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.292891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.292930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.292969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.293009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.293048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.293090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.293132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.293173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.293279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.293310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.293367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.293399] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.293426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.293629] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.293652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.293675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.293704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.293729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.293755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.293781] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.293807] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.293833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.293859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.293884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.293891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.293915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.293921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.293946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.293972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.293999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.294024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.294050] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.294075] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.294102] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.294128] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.294154] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.294180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.294237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.294326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.294359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.294389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.294417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.294447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.294472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.294495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.294520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.294548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.294574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.294600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.294626] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.294652] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.296700] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.296722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.296740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.296760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.298349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.298369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.298387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.299940] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.299960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.301837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.305152] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.305282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.305331] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.305399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.305517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.305565] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.305627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.322316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.322354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.322392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.322431] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.322462] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.322495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.322529] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.322560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.322590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.322619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.322647] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.322654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.322682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.322689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.322717] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.322745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.322772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.322799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.322831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.322860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.322896] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.322920] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.322944] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.322973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.323004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.338773] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.338822] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.338912] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.357291] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.357328] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.357368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.357401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.357432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.357462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.357491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.357522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.357555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.357586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.357617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.357653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.357679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.357729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.357761] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.357795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.358123] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.358154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.358187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.358315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.358364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.358414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.358463] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.358512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.358558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.358604] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.358654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.358665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.358701] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.358710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.358746] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.358782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.358818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.358853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.358893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.358929] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.358967] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.359005] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.359040] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.359081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.359121] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.359273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.359310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.359346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.359381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.359416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.359449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.359490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.359529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.359568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.359603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.359639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.359685] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.359717] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.361788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.361808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.361831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.361855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.363433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.363454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.363472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.365031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.365052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.366923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.370262] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.370315] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.370352] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.370400] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.370509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.370554] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.370619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.387423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.387463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.387504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.387545] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.387578] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.387613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.387649] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.387683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.387716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.387746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.387776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.387783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.387813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.387820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.387850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.387880] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.387909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.387938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.387972] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.388007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.388050] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.388091] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.388131] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.388174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.388277] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.403888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.403935] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.404005] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.421039] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.421081] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.421125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.421165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.421295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.421349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.421400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.421452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.421507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.421558] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.421609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.421655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.421702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.421788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.421844] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.421903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.422264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.422289] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.422316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.422344] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.422369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.422402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.422423] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.422443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.422461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.422478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.422494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.422499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.422514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.422518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.422535] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.422551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.422567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.422582] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.422601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.422617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.422635] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.422650] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.422672] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.422697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.422722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.422789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.422813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.422837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.422860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.422883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.422906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.422931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.422956] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.422980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.423003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.423025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.423049] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.423070] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.425140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.425161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.425231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.425267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.426838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.426858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.426876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.428438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.428459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.430327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.433617] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.433662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.433691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.433727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.433859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.433919] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.434007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.450753] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.450797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.450840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.450887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.450927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.450969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.451010] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.451051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.451093] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.451133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.451173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.451259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.451315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.451328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.451382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.451433] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.451483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.451533] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.451586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.451636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.451687] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.451740] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.451766] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.451800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.451835] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.467276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.467324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.467395] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.484450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.484491] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.484536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.484575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.484615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.484655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.484694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.484734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.484776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.484817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.484859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.484898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.484936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.485001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.485046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.485093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.485650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.485685] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.485720] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.485758] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.485789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.485823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.485856] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.485888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.485920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.485950] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.485979] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.485987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.486015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.486023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.486052] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.486082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.486111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.486137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.486170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.486228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.486257] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.486289] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.486319] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.486354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.486390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.486495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.486526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.486556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.486585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.486612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.486643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.486677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.486709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.486742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.486771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.486800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.486834] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.486866] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.488941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.488963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.488982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.489001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.490591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.490613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.490632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.492181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.492222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.494083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.497442] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.497493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.497525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.497567] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.497720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.497773] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.497852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.514515] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.514555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.514594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.514635] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.514667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.514703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.514739] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.514781] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.514823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.514863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.514902] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.514910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.514950] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.514957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.514998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.515039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.515080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.515128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.515163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.515275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.515327] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.515372] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.515416] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.515465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.515515] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.531046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.531093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.531164] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.548290] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.548327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.548367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.548400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.548431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.548460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.548489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.548521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.548561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.548603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.548645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.548683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.548722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.548787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.548832] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.548879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.549103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.549124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.549145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.549168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.549252] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.549283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.549314] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.549346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.549375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.549405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.549432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.549442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.549469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.549477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.549507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.549534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.549563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.549589] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.549622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.549649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.549680] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.549706] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.549735] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.549767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.549801] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.549907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.549935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.549964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.549990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.550018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.550046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.550077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.550108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.550140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.550165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.550217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.550253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.550282] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.552350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.552370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.552388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.552407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.553978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.554001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.554025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.555580] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.555602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.557471] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.560817] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.560870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.560903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.560946] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.561092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.561160] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.561497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.577943] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.577984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.578023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.578064] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.578097] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.578133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.578169] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.578282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.578328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.578380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.578425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.578441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.578483] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.578496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.578542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.578586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.578623] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.578658] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.578699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.578733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.578772] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.578805] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.578841] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.578885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.578925] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.594462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.594509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.594595] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.611599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.611636] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.611676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.611709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.611741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.611771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.611801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.611832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.611866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.611897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.611929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.611957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.611984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.612037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.612081] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.612128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.612598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.612628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.612662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.612698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.612726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.612758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.612788] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.612818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.612846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.612875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.612901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.612908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.612935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.612942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.612972] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.612998] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.613026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.613051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.613082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.613107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.613136] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.613162] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.613215] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.613245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.613280] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.613384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.613411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.613441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.613467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.613495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.613522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.613553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.613585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.613616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.613642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.613669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.613700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.613730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.615790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.615813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.615836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.615860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.617442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.617463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.617481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.619039] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.619060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.620931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.624239] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.624289] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.624320] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.624361] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.624507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.624578] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.624638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.641329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.641367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.641407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.641452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.641490] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.641530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.641570] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.641608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.641648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.641687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.641725] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.641733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.641771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.641778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.641817] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.641856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.641895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.641933] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.641973] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.642014] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.642044] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.642070] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.642094] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.642123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.642152] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.657853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.657900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.657971] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.675034] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.675071] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.675115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.675156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.675276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.675325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.675376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.675422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.675478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.675532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.675584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.675630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.675675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.675731] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.675765] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.675801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.676136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.676156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.676226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.676266] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.676295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.676328] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.676359] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.676391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.676420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.676450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.676476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.676485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.676511] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.676518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.676548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.676618] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.676648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.676677] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.676709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.676738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.676765] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.676793] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.676818] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.676849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.676883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.676985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.677015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.677044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.677069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.677097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.677124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.677155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.677209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.677241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.677268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.677297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.677333] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.677361] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.679430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.679451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.679470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.679489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.681049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.681069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.681086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.682647] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.682668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.684571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.687888] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.687920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.687940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.687965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.688056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.688095] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.688156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.704997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.705038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.705077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.705119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.705151] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.705269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.705316] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.705369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.705419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.705467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.705843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.705851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.705882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.705889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.705920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.705949] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.705978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.706006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.706039] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.706067] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.706096] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.706134] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.706173] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.706263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.706321] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.721487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.721534] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.721604] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.738635] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.738673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.738713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.738752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.738792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.738831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.738870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.738909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.738952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.738993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.739034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.739079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.739109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.739160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.739253] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.739306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.739643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.739673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.739706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.739746] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.739781] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.739818] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.739854] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.739891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.739927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.739963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.739997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.740006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.740040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.740047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.740088] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.740111] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.740132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.740151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.740204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.740232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.740263] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.740290] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.740317] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.740348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.740381] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.740468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.740492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.740512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.740536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.740562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.740587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.740615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.740642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.740668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.740693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.740719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.740746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.740772] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.742826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.742848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.742866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.742886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.744468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.744488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.744505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.746053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.746073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.747950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.751265] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.751307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.751326] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.751352] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.751429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.751457] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.751497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.768406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.768447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.768486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.768528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.768560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.768596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.768632] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.768666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.768706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.768746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.768787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.768794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.768834] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.768841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.768883] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.768924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.768964] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.769004] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.769045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.769085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.769128] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.769168] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.769273] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.769323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.769377] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.784874] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.784921] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.784992] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.803116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.803154] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.803277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.803329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.803380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.803429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.803469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.803507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.803550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.803579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.803606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.803630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.803655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.803700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.803731] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.803769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.804082] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.804116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.804150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.804241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.804281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.804326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.804366] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.804406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.804445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.804482] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.804517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.804528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.804569] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.804577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.804607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.804636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.804668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.804699] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.804732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.804761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.804795] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.804827] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.804858] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.804895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.804934] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.805047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.805081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.805103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.805123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.805143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.805195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.805230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.805263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.805295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.805324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.805355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.805390] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.805421] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.807503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.807526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.807544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.807563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.809162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.809199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.809217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.810789] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.810810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.812706] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.815928] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.815959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.815978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.816004] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.816094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.816134] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.816357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.833012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.833050] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.833088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.833126] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.833157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.833270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.833318] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.833369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.833414] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.833462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.833508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.833522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.833567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.833578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.833624] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.833669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.833715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.833760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.833810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.833854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.833901] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.833941] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.833984] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.834030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.834080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.849546] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.849593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.849682] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.866707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.866749] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.866794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.866835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.866874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.866913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.866953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.866992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.867036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.867077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.867122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.867151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.867240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.867321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.867668] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.867723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.868053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.868083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.868121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.868143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.868209] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.868245] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.868275] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.868308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.868337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.868368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.868395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.868403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.868430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.868648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.868676] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.868695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.868713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.868730] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.868750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.868767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.868785] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.868801] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.868824] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.868848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.868874] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.868942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.868966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.868989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.869013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.869036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.869059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.869084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.869109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.869133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.869156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.869223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.869262] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.869292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.871357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.871378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.871396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.871415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.872975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.872996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.873014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.874576] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.874596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.876467] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.879765] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.879815] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.879846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.879888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.880035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.880101] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.880255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.896884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.896924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.896963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.897009] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.897050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.897091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.897132] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.897173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.897290] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.897338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.897388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.897402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.897449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.897461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.897509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.897552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.897598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.897955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.897985] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.898013] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.898044] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.898069] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.898096] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.898127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.898169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.913408] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.913455] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.913543] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.931839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.931876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.931915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.931948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.931978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.932008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.932036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.932067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.932100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.932140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.932259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.932312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.932360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.932448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.932504] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.932571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.932910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.932930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.932951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.932974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.932992] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.933012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.933032] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.933050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.933068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.933085] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.933102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.933106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.933122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.933126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.933143] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.933212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.933241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.933272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.933306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.933336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.933370] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.933400] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.933430] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.933465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.933500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.933590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.933620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.933651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.933681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.933707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.933738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.933771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.933803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.933836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.933865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.933894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.933928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.933959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.936031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.936053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.936071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.936090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.937682] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  305.937702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.937719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.939279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.939299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  305.941160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.944521] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.944576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  305.944616] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  305.944667] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.944773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.944802] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.944843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.961647] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.961687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.961726] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.961768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.961801] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.961837] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.961873] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.961907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.961941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.961972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.962003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.962010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.962040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.962047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.962077] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.962108] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.962137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.962259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.962313] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.962362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.962415] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.962462] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.962508] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.962562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.962617] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.978156] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  305.978236] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  305.978308] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  305.995338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  305.995376] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  305.995416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.995449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.995479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.995509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.995538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.995569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.995602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.995633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.995664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.995692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.995718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.995772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  305.995806] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  305.995841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.996119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  305.996138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  305.996228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  305.996267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.996301] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.996335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.996369] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  305.996402] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.996433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.996464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  305.996494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.996503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.996532] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.996540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  305.996570] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  305.996600] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.996630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.996659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.996955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  305.996988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.997021] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  305.997051] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  305.997081] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  305.997114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.997149] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  305.997376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  305.997407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  305.997435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  305.997463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  305.997491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  305.997520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  305.997552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  305.997581] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  305.997611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  305.997638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  305.997664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  305.997695] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  305.997724] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  305.999802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.999823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.999841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.999863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.001434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.001454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.001472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.003024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.003044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.004911] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.008255] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.008288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.008307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.008333] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.008422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.008461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.008522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.025439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.025481] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.025521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.025566] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.025605] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.025645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.025684] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.025723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.025763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.025801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.025840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.025847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.025885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.025892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.025932] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.025971] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.026010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.026048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.026088] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.026126] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.026167] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.026260] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.026318] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.026367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.026422] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.041895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.041944] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.042019] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.059079] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.059120] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.059165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.059285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.059335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.059386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.059429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.059476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.059528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.059580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.059622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.059656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.059692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.059763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.059809] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.059855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.060409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.060451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.060484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.060517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.060542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.060580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.060604] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.060626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.060647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.060667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.060686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.060692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.060711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.060715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.060735] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.060754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.060774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.060792] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.060815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.060834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.060854] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.060873] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.060892] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.060914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.060938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.061013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.061034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.061055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.061074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.061101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.061129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.061158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.061221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.061261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.061291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.061323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.061362] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.061393] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.063467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.063488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.063506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.063526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.065085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.065105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.065124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.066718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.066739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.068626] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.071887] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.071920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.071939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.071965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.072056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.072094] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.072155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.088960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.089000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.089040] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.089081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.089115] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.089151] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.089264] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.089310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.089364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.089408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.089458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.089471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.089514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.089856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.089898] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.089930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.089960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.089988] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.090022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.090051] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.090081] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.090109] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.090136] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.090217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.090255] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.105515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.105563] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.105650] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.122685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.122723] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.122762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.122794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.122824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.122853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.122882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.122913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.122946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.122977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.123008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.123036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.123063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.123116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.123151] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.123262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.124033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.124054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.124075] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.124098] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.124116] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.124136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.124203] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.124238] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.124266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.124296] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.124323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.124333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.124360] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.124368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.124397] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.124655] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.124681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.124708] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.124736] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.124762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.124791] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.124815] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.124841] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.124871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.124902] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.124998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.125024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.125051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.125075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.125101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.125126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.125192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.125227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.125260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.125286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.125315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.125350] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.125379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.127653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.127674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.127692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.127711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.129371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.129391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.129409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.130959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.130980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.132846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.136188] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.136220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.136240] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.136266] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.136357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.136397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.136457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.153355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.153396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.153435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.153476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.153509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.153544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.153580] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.153612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.153645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.153675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.153705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.153712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.153742] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.153748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.153778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.153818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.153859] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.153900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.153941] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.153981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.154024] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.154065] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.154106] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.154148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.154243] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.169837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.169884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.169973] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.188484] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.188522] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.188562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.188595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.188625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.188654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.188683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.188713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.188747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.188778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.188809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.188837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.188864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.188916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.188951] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.188996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.189473] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.189506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.189542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.189579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.189610] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.189643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.189676] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.189707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.189738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.189768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.189797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.189805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.189834] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.189841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.189871] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.189900] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.189930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.189956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.189988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.190017] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.190048] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.190077] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.190106] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.190136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.190197] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.190305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.190336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.190366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.190393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.190423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.190451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.190485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.190517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.190549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.190578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.190607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.190640] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.190672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.192752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.192777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.192800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.192824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.194405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.194427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.194446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.196000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.196022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.197899] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.201259] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.201311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.201344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.201386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.201530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.201605] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.201685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.218387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.218430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.218473] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.218519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.218559] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.218601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.218642] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.218683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.218724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.218764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.218804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.218812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.218852] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.218859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.218900] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.218940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.218981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.219023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.219047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.219069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.219090] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.219109] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.219127] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.219200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.219233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.234890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.234936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.235023] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.251978] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.252016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.252056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.252090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.252121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.252151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.252262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.252308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.252365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.252417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.252738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.252770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.252809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.252844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.252868] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.252892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.253119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.253140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.253204] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.253238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.253267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.253297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.253326] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.253357] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.253630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.253658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.253688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.253695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.253724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.253730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.253759] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.253785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.253813] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.253838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.253869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.253895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.253925] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.253951] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.253979] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.254009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.254041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.254189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.254222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.254250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.254279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.254305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.254336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.254369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.254401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.254432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.254458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.254487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.254517] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.254549] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.256635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.256656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.256675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.256694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.258283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.258303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.258321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.259879] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.259900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.261772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.265034] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.265065] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.265083] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.265109] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.265361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.265401] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.265460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.282142] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.282219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.282258] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.282299] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.282332] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.282369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.282411] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.282452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.282493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.282533] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.282573] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.282581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.282621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.282628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.282669] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.282710] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.282751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.282791] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.282832] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.282871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.282913] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.282954] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.282994] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.283036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.283079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.298662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.298709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.298796] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.315799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.315837] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.315876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.315909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.315939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.315969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.315997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.316028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.316062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.316102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.316144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.316242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.316291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.316365] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.316417] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.316472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.316915] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.316957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.317003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.317052] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.317091] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.317134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.317226] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.317275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.317311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.317343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.317376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.317386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.317419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.317428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.317463] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.317496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.317531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.317564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.317602] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.317635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.317669] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.317702] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.317734] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.317768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.317806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.317922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.317953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.317986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.318015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.318047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.318077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.318113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.318149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.318212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.318253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.318280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.318314] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.318343] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.320409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.320430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.320448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.320466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.322038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.322058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.322080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.323666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.323687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.325564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.328890] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.328940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.328971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.329019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.329130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.329255] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.329346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.345952] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.345990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.346027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.346066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.346096] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.346129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.346246] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.346290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.346324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.346353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.346384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.346392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.346419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.346427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.346456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.346483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.346513] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.346540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.346574] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.346602] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.346633] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.346660] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.346688] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.346721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.346764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.362509] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.362556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.362627] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.379688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.379725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.379764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.379797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.379828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.379858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.379887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.379918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.379952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.379984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.380015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.380044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.380071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.380124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.380237] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.380294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.380705] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.380727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.380751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.380776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.380796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.380818] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.380839] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.380861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.380880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.380900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.380918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.380924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.380942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.380946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.380965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.380983] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.381001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.381018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.381040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.381057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.381076] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.381094] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.381111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.381133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.381192] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.381296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.381327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.381357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.381386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.381415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.381446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.381480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.381513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.381535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.381560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.381586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.381614] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.381639] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.383708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.383729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.383747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.383765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.385335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.385355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.385373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.386921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.386942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.388807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.392101] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.392150] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.392256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.392319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.392452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.392493] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.392548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.409251] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.409289] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.409326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.409364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.409394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.409428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.409461] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.409492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.409521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.409550] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.409577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.409585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.409612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.409618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.409646] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.409673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.409700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.409726] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.409758] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.409785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.409814] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.409841] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.409867] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.409899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.409933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.425731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.425775] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.425843] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.442854] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.442891] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.442931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.442964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.442995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.443025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.443054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.443085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.443119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.443231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.443284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.443327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.443373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.443457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.443511] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.443568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.444058] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.444080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.444102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.444125] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.444191] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.444227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.444257] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.444291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.444321] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.444351] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.444378] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.444387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.444414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.444421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.444450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.444477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.444506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.444531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.444563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.444588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.444617] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.444643] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.444671] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.444703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.444737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.444840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.444868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.444896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.444923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.444950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.444977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.445008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.445039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.445070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.445096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.445123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.445178] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.445210] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.447275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.447295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.447314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.447333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.448907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.448928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.448946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.450503] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.450524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.452388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.455697] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.455749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.455781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.455822] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.455934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.455977] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.456038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.472850] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.472888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.472928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.472973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.473012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.473052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.473092] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.473131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.473259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.473306] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.473339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.473348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.473378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.473386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.473416] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.473444] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.473472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.473500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.473536] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.473564] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.473595] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.473623] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.473653] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.473686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.473733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.489309] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.489354] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.489421] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.506432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.506469] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.506508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.506541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.506571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.506600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.506629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.506660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.506694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.506725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.506756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.506785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.506822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.506887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.506933] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.506980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.507539] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.507581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.507606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.507635] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.507661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.507687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.507714] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.507739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.507766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.507791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.507817] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.507822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.507848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.507852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.507879] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.507905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.507931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.507956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.507981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.508006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.508034] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.508059] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.508085] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.508112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.508169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.508260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.508291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.508321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.508353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.508383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.508416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.508450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.508484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.508517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.508547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.508571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.508594] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.508620] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.510659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.510679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.510697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.510716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.512286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.512306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.512324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.513882] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.513905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.515779] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.519047] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.519089] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.519115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.519220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.519346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.519401] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.519487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.536092] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.536130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.536254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.536313] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.536362] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.536416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.536458] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.536492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.536523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.536554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.536582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.536590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.536618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.536625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.536657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.536685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.536714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.536742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.536776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.536814] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.536857] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.536897] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.536938] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.536980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.537022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.552670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.552722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.552814] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.569818] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.569855] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.569895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.569928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.569958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.569987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.570017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.570048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.570081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.570112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.570228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.570270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.570318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.570405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.570463] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.570522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.570889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.570922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.570959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.570997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.571027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.571062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.571101] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.571129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.571204] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.571240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.571275] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.571287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.571321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.571331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.571367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.571402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.571437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.571471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.571515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.571554] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.571596] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.571636] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.571673] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.571717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.571762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.571888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.571915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.571940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.571965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.571989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.572014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.572042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.572069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.572103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.572123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.572180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.572216] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.572247] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.574317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.574338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.574356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.574375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.575944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.575964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.575982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.577544] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.577564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.579433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.582745] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.582796] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.582828] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.582869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.583015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.583081] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.583367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.599854] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.599898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.599941] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.599987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.600028] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.600070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.600111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.600236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.600285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.600335] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.600379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.600393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.600436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.600447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.600492] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.600534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.600579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.600619] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.600668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.600708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.600755] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.600790] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.600823] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.600859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.600900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.616348] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.616398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.616473] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.635368] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.635405] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.635445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.635478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.635509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.635538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.635568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.635599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.635632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.635664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.635695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.635732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.635771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.635836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.635881] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.635928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.636626] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.636658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.636693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.636729] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.636757] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.636789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.636819] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.636849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.636877] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.636906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.636932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.636939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.636966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.636973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.637003] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.637029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.637057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.637083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.637114] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.637164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.637196] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.637223] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.637253] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.637287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.637322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.637677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.637698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.637717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.637735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.637752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.637771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.637795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.637821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.637845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.637869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.637891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.637915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.637936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.639991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.640012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.640031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.640050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.641622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.641643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.641661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.643272] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.643293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.645238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.648559] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.648611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.648644] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.648686] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.648777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.648815] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.648877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.665637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.665678] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.665717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.665758] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.665791] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.665827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.665862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.665896] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.665929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.665960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.665990] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.665998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.666027] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.666034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.666064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.666094] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.666123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.666236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.666284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.666332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.666383] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.666425] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.666475] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.666524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.666577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.682208] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.682255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.682343] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.699370] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.699408] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.699447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.699480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.699511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.699541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.699570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.699608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.699651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.699693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.699735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.699774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.699813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.699864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.699888] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.699911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.700117] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.700200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.700239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.700277] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.700306] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.700340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.700370] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.700401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.700430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.700460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.700486] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.700495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.700523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.700530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.700559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.700888] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.700916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.700947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.700977] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.701005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.701033] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.701062] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.701087] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.701119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.701174] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.701446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.701473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.701501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.701526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.701553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.701579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.701608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.701638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.701668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.701693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.701718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.701749] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.701775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.703865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.703885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.703904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.703923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.705501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.705521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.705539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.707121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.707158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.709030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.712312] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.712354] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.712381] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.712416] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.712540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.712596] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.712679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.729434] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.729474] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.729514] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.729555] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.729587] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.729623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.729659] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.729692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.729724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.729754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.729784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.729791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.729821] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.729827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.729858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.729887] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.729916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.729945] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.729980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.730010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.730042] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.730072] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.730100] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.730134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.730225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.745917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.745965] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.746052] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.762998] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.763035] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.763075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.763108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.763221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.763266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.763315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.763361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.763422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.763464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.763505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.763540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.763576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.763648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.763694] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.763742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.764083] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.764117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.764197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.764252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.764289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.764334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.764375] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.764417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.764462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.764495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.764524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.764534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.764564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.764572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.764603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.764633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.764664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.764693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.764727] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.764756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.764788] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.764816] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.764846] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.764881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.764918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.765029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.765059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.765090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.765119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.765176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.765209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.765247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.765282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.765316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.765345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.765377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.765414] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.765452] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.767517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.767537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.767555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.767575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.769133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.769179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.769197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.770772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.770793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.772672] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.775946] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.775993] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.776023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.776062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.776427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.776492] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.776566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.793036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.793076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.793116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.793237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.793283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.793337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.793385] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.793435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.793486] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.793528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.793571] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.793583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.793625] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.793636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.793680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.793720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.793763] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.793803] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.793851] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.793890] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.793936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.793976] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.794024] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.794053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.794085] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.809560] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.809606] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.809694] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.826694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.826731] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.826771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.826803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.826833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.826862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.826900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.826939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.826982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.827024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.827065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.827103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.827220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.827309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.827572] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.827632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.827970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.827993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.828017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.828044] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.828066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.828090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.828123] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.828181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.828214] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.828243] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.828274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.828283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.828312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.828320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.828351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.828378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.828407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.828434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.828467] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.828766] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.828797] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.828823] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.828849] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.828880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.828912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.829008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.829038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.829057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.829076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.829094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.829113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.829194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.829227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.829414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.829438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.829464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.829490] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.829513] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.831552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.831573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.831591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.831610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.833182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.833202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.833224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.834787] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.834808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.836686] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.839968] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.840021] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.840040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.840066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.840335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.840377] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.840422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.857121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.857197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.857238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.857279] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.857312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.857348] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.857384] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.857418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.857451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.857490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.857531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.857539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.857579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.857586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.857628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.857669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.857710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.857750] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.857791] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.857831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.857874] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.857914] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.857954] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.857997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.858040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.873626] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.873673] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.873761] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.890769] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.890806] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.890845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.890879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.890910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.890940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.890970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.891001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.891035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.891067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.891098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.891204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.891249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.891339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.891396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.891455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.891979] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.892032] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.892074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.892096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.892114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.892181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.892217] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.892246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.892278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.892308] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.892338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.892346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.892376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.892382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.892411] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.892439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.892469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.892498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.892532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.892562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.892592] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.892621] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.892650] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.892683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.892715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.892815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.892845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.892872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.892900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.892926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.892955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.892987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.893018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.893049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.893074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.893102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.893157] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.893189] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.895256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.895277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.895298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.895322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.896895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.896916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.896934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.898488] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.898509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.900380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.903680] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.903735] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.903775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.903826] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.903977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.904047] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.904209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.920798] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.920838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.920876] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.920923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.920963] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.921006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.921046] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.921088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.921129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.921246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.921293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.921308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.921357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.921370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.921420] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.921463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.921510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.921552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.921603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.921917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.921947] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.921973] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.922000] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.922031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.922062] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.937320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  306.937367] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  306.937455] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.954464] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  306.954501] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  306.954542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.954575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.954606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.954636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.954665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.954696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.954729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.954760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.954790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.954817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.954845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.954897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.954932] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.954969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.955436] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.955458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.955481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.955507] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.955527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.955548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.955574] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.955600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.955626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.955652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.955677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.955684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.955709] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.955713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.955740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.955765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.955791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.955816] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.955843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.955867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.955894] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.955920] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.955945] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.955971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.955999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  306.956073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.956099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  306.956153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  306.956185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  306.956214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  306.956243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  306.956276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  306.956307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  306.956338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.956364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  306.956391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  306.956425] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  306.956454] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  306.958516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.958537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.958555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.958574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.960223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  306.960243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.960262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.961820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.961841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  306.963715] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.966989] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  306.967036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  306.967066] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  306.967106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.967526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  306.967570] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  306.967629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  306.984065] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  306.984105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.984226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  306.984286] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.984334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.984388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.984429] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  306.984461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  306.984501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.984542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.984581] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.984591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.984630] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.984638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  306.984678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  306.984718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.984759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.984798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.984839] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  306.984879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.984917] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  306.984956] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  306.984997] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  306.985039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.985089] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.000603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.000649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.000722] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.019072] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.019114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.019240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.019300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.019352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.019400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.019438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.019472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.019508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.019541] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.019573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.019601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.019630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.019685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.019722] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.019758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.020045] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.020064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.020086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.020108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.020178] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.020207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.020238] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.020267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.020296] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.020324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.020350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.020359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.020385] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.020392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.020419] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.020446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.020473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.020498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.020529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.020555] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.020587] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.020616] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.020643] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.020677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.020712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.020814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.020845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.020875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.020904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.020933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.020955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.020977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.020997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.021016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.021034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.021052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.021074] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.021094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.023177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.023198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.023216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.023237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.024813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.024833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.024851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.026414] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.026434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.028304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.031619] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.031669] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.031701] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.031751] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.031866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.031915] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.031984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.048727] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.048768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.048807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.048848] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.048881] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.048917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.048952] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.048987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.049020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.049050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.049080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.049087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.049117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.049192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.049239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.049281] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.049323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.049365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.049412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.049454] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.049501] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.049547] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.049589] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.049623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.049658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.065277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.065326] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.065401] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.082404] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.082441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.082481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.082520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.082560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.082599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.082639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.082678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.082720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.082761] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.082803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.082842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.082880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.082945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.082990] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.083037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.083462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.083486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.083511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.083537] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.083558] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.083580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.083603] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.083623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.083643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.083662] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.083680] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.083686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.083704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.083708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.083726] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.083744] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.083769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.083795] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.083820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.083846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.083872] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.083898] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.083923] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.083950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.083978] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.084052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.084078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.084101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.084156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.084186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.084217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.084249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.084281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.084311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.084337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.084363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.084395] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.084425] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.086487] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.086519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.086539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.086559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.088218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.088239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.088257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.089820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.089841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.091715] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.095009] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.095058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.095090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.095218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.095533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.095560] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.095598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.112096] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.112171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.112211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.112252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.112285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.112322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.112362] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.112404] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.112445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.112485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.112525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.112533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.112573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.112580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.112621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.112662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.112702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.112742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.112783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.112823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.112866] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.112912] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.112935] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.112960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.112986] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.128654] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.128701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.128773] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.145808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.145845] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.145885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.145918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.145950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.145980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.146009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.146040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.146073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.146105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.146215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.146257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.146301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.146387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.146445] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.146505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.146839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.146861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.146884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.146912] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.146937] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.146963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.146989] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.147014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.147039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.147064] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.147089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.147126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.147158] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.147166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.147197] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.147226] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.147254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.147281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.147312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.147339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.147367] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.147394] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.147421] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.147454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.147487] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.147591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.147624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.147654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.147683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.147712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.147739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.147762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.147782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.147802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.147820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.147838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.147861] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.147881] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.149925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.149947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.149965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.149984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.151561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.151581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.151599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.153155] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.153176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.155044] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.158357] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.158408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.158440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.158489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.158606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.158655] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.158724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.175472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.175512] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.175552] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.175594] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.175627] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.175663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.175699] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.175733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.175765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.175796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.175826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.175833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.175863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.175869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.175899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.175929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.175958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.175986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.176021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.176055] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.176099] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.176204] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.176248] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.176296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.176355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.191983] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.192030] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.192100] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.209368] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.209406] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.209445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.209484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.209524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.209564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.209603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.209642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.209685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.209726] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.209767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.209806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.209844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.209909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.209954] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.210001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.210355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.210389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.210424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.210461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.210493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.210526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.210559] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.210590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.210621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.210651] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.210681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.210689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.210717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.210724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.210754] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.210783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.210813] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.210842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.210874] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.210903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.210934] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.210963] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.210992] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.211025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.211059] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.211186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.211219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.211249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.211280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.211313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.211344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.211379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.211412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.211444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.211473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.211502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.211536] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.211567] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.213630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.213651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.213673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.213697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.215282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.215303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.215321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.216880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.216903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.218777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.222068] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.222118] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.222228] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.222297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.222398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.222427] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.222468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.239216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.239256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.239296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.239337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.239370] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.239407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.239443] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.239477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.239510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.239540] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.239570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.239578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.239607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.239614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.239644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.239674] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.239703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.239732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.239767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.239797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.239829] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.239858] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.239886] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.239921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.239958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.255720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.255771] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.255847] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.272875] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.272913] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.272953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.272986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.273018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.273048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.273078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.273109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.273236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.273291] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.273349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.273387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.273428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.273501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.273548] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.273598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.273999] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.274027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.274058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.274090] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.274175] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.274217] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.274264] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.274307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.274355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.274386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.274417] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.274426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.274454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.274461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.274492] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.274522] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.274549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.274577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.274609] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.274639] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.274670] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.274700] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.274729] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.274762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.274797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.274900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.274930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.274960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.274990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.275020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.275051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.275084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.275142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.275173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.275203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.275233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.275268] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.275301] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.277367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.277387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.277405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.277424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.278995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.279016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.279034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.280594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.280614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.282527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.285766] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.285797] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.285816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.285842] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.285924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.285952] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.285992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.302901] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.302942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.302981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.303023] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.303057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.303094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.303220] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.303272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.303325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.303373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.303422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.303435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.303479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.303491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.303539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.303586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.303632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.303675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.303722] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.303767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.303815] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.303860] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.303901] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.303951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.304004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.319391] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.319438] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.319509] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.336532] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.336569] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.336609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.336641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.336672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.336702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.336730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.336761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.336794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.336825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.336856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.336884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.336911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.336963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.336998] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.337034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.337459] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.337493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.337529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.337569] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.337601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.337634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.337668] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.337699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.337740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.337789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.337811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.337816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.337836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.337840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.337859] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.337878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.337896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.337914] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.337935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.337954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.337973] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.337991] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.338009] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.338030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.338053] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.338141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.338169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.338196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.338223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.338250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.338277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.338308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.338337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.338367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.338393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.338419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.338450] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.338480] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.340545] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.340566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.340584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.340604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.342228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.342250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.342269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.343832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.343853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.345717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.349000] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.349033] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.349057] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.349088] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.349405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.349433] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.349472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.366090] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.366168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.366212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.366259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.366299] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.366341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.366382] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.366423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.366464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.366505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.366545] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.366552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.366592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.366599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.366640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.366680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.366721] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.366761] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.366802] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.366841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.366884] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.366924] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.366965] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.367007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.367050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.382607] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.382655] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.382726] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.399729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.399766] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.399806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.399839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.399869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.399899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.399928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.399960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.399993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.400025] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.400064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.400091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.400204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.400283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.400337] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.400393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.400937] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.400985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.401035] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.401089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.401166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.401199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.401234] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.401266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.401297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.401329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.401359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.401367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.401396] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.401403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.401433] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.401461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.401488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.401516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.401548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.401578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.401611] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.401641] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.401671] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.401704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.401738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.401842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.401872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.401903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.401932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.401961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.401993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.402026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.402058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.402090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.402143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.402173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.402210] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.402242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.404305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.404326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.404344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.404363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.405934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.405954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.405972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.407537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.407561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.409433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.412738] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.412788] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.412820] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.412861] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.412967] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.413009] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.413070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.429843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.429884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.429923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.429964] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.429997] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.430033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.430069] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.430104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.430225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.430276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.430324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.430338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.430385] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.430400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.430448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.430495] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.430543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.430835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.430866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.430895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.430925] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.430952] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.430979] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.431009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.431041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.446347] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.446394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.446466] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.465040] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.465078] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.465208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.465245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.465279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.465309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.465340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.465372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.465415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.465443] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.465471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.465496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.465531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.465589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.465630] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.465673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.465988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.466025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.466062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.466105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.466196] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.466244] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.466288] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.466329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.466369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.466417] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.466444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.466453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.466479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.466487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.466514] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.466540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.466566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.466592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.466622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.466652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.466683] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.466710] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.466739] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.466772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.466806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.466895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.466926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.466957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.466986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.467016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.467046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.467074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.467127] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.467158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.467184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.467210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.467243] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.467271] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.469336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.469357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.469375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.469394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.470953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.470974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.470997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.472565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.472586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.474459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.477774] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.477817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.477843] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.477877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.477995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.478047] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.478173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.494882] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.494922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.494962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.495003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.495036] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.495072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.495182] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.495231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.495284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.495328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.495375] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.495388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.495435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.495446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.495492] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.495532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.495579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.495620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.495670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.495710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.495757] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.495796] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.495839] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.495884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.495934] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.511398] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.511445] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.511533] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.528543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.528581] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.528622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.528654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.528693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.528733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.528773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.528812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.528863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.528898] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.528930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.528957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.528983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.529034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.529069] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.529176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.529722] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.529766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.529815] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.529876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.529904] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.529936] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.529965] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.529995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.530022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.530051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.530076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.530110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.530139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.530146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.530177] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.530204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.530233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.530260] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.530292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.530319] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.530350] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.530376] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.530403] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.530437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.530471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.530573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.530601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.530630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.530656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.530684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.530711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.530742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.530773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.530804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.530830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.530857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.530887] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.530917] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.532981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.533002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.533021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.533040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.534636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.534656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.534674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.536325] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.536348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.538218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.541530] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.541582] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.541614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.541656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.541758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.541800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.541869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.558643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.558684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.558725] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.558770] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.558808] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.558849] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.558888] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.558927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.558967] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.559006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.559044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.559052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.559091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.559163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.559218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.559264] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.559310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.559353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.559401] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.559443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.559495] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.559525] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.559554] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.559587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.559622] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.575178] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.575224] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.575291] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.592326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.592364] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.592403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.592436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.592467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.592496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.592524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.592555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.592589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.592621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.592652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.592680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.592708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.592761] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.592796] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.592832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.593317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.593353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.593387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.593425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.593456] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.593481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.593504] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.593524] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.593544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.593563] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.593582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.593587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.593606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.593610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.593629] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.593647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.593665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.593683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.593704] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.593722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.593741] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.593759] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.593777] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.593798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.593821] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.593889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.593910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.593928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.593947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.593965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.593984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.594006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.594026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.594045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.594070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.594119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.594152] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.594181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.596252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.596273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.596291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.596310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.597885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.597904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.597922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.599490] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.599511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.601389] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.604668] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.604709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.604734] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.604767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.604850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.604884] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.604932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.621814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.621852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.621889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.621927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.621957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.621990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.622024] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.622055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.622094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.622199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.622243] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.622256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.622298] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.622310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.622358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.622627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.622657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.622687] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.622722] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.622751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.622782] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.622810] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.622838] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.622872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.622907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.638264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.638315] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.638390] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.655331] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.655368] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.655408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.655440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.655471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.655500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.655529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.655560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.655594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.655625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.655655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.655702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.655736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.655794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.655834] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.655876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.656315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.656348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.656382] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.656416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.656444] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.656475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.656505] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.656540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.656576] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.656613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.656648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.656656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.656690] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.656696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.656734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.656756] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.656775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.656794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.656816] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.656835] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.656854] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.656872] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.656890] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.656912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.656935] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.657005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.657025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.657044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.657063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.657081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.657137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.657169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.657198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.657229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.657255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.657281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.657312] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.657342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.659405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.659426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.659445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.659463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.661023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.661043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.661061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.662661] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.662682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.664560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.667887] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.667941] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.667967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.668000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.668161] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.668216] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.668297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.684957] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.684997] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.685037] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.685078] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.685192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.685244] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.685298] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.685344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.685676] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.685709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.685739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.685747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.685776] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.685782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.685812] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.685842] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.685870] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.685898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.685931] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.685959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.685989] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.686016] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.686043] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.686076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.686165] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.701499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.701546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.701634] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.718662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.718699] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.718739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.718772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.718803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.718833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.718863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.718894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.718927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.718958] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.718990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.719018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.719052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.719171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.719222] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.719274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.719758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.719788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.719820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.719854] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.719881] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.719910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.719939] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.719966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.719993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.720018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.720051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.720056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.720071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.720114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.720147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.720174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.720204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.720230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.720263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.720290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.720322] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.720349] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.720378] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.720411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.720446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.720548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.720576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.720605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.720631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.720659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.720686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.720718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.720750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.720781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.720806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.720835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.720865] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.720895] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.722959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.722980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.722999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.723018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.724609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.724630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.724648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.726220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.726241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.728121] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.731417] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.731452] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.731481] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.731507] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.731596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.731635] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.731696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.748544] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.748585] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.748625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.748666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.748700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.748736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.748772] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.748806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.748838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.748870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.748900] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.748907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.748947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.748954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.748995] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.749037] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.749077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.749190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.749243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.749289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.749342] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.749386] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.749433] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.749488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.749542] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.765039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.765086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.765249] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.782150] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.782187] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.782226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.782259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.782290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.782320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.782349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.782380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.782422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.782452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.782480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.782506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.782532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.782582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.782614] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.782648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.782936] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.782972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.783010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.783052] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.783088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.783178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.783234] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.783278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.783325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.783366] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.783410] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.783432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.783460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.783468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.783498] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.783525] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.783554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.783580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.783614] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.783640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.783672] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.783699] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.783728] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.783762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.783797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.783885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.783912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.783942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.783968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.783996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.784023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.784055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.784087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.784141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.784167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.784196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.784232] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.784260] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.786336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.786357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.786375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.786395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.787955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.787975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.787993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.789546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.789566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.791439] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.794736] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.794770] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.794793] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.794824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.794917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.794958] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.795019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.811857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.811898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.811937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.811978] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.812011] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.812047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.812089] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.812205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.812252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.812301] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.812344] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.812359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.812403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.812415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.812461] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.812502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.812549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.812590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.812640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.812680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.812727] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.812766] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.812810] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.812861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.812912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.828377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.828425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.828512] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.845518] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.845556] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.845595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.845629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.845660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.845689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.845719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.845751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.845784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.845816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.845848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.845884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.845910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.845960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.846001] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.846045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.846889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.846911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.846933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.846955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.846973] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.846993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.847013] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.847032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.847050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.847067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.847131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.847143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.847171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.847178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.847208] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.847236] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.847266] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.847292] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.847324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.847350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.847381] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.847631] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.847659] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.847691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.847725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.847832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.847857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.847884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.847908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.847934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.847959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.847988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.848017] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.848046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.848070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.848134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.848172] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.848201] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.850485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.850506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.850524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.850543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.852149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.852169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.852188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.853743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.853765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.855640] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.858919] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.858970] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.859001] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.859042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.859315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.859350] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.859388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.876019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.876060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.876173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.876331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.876363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.876399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.876440] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.876480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.876521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.876561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.876601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.876611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.876650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.876657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.876699] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.876739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.876780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.876819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.876861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.876901] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.876943] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.876982] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.877021] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.877063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.877152] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.892528] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.892575] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.892647] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.909645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.909682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.909721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.909754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.909785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.909815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.909845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.909876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.909909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.909941] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.909972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.910000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.910028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.910087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.910211] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.910261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.910572] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.910594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.910620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.910649] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.910675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.910702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.910728] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.910754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.910780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.910805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.910830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.910836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.910861] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.910865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.910892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.910918] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.910944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.910969] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.910996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.911020] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.911048] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.911075] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.911134] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.911168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.911202] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.911307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.911340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.911371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.911401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.911431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.911463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.911492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.911514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.911535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.911554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.911572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.911595] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.911616] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.913694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.913717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.913736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.913755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.915331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.915353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.915372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.916922] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.916943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.918817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.922136] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.922187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.922218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.922260] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.922371] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.922414] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.922476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.939246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.939282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.939319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.939358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.939389] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.939422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.939456] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.939487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.939518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.939555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.939595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.939602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.939641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.939648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.939688] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.939727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.939766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.939805] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.939853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.939885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.939919] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.939952] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.939985] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.940019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.940054] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.955739] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  307.955784] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  307.955851] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  307.972892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  307.972930] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  307.972970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.973003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.973034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.973064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.973177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.973224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.973278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.973329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.973379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.973422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.973467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.973560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.973596] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.973633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.973921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  307.973940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.973962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  307.973984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.974006] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.974030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.974054] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  307.974121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  307.974157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.974184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.974214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.974223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.974252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.974260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  307.974290] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  307.974317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.974347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.974374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.974406] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  307.974433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.974461] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  307.974487] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  307.974516] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  307.974549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.974583] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  307.974685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  307.974713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  307.974742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  307.974769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  307.974797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  307.974824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  307.974856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  307.974887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  307.974918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  307.974946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  307.974973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  307.975003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  307.975033] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  307.977123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.977143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.977161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.977180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.978742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  307.978762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.978780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.980347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.980367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  307.982237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.985571] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  307.985623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  307.985656] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  307.985697] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.985793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  307.985821] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  307.985861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.002687] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.002727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.002767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.002813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.002854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.002896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.002937] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.002978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.003020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.003060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.003169] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.003183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.003229] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.003242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.003288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.003332] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.003375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.003422] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.003725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.003761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.003794] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.003826] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.003855] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.003890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.003927] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.019226] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.019272] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.019344] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.036380] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.036417] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.036458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.036498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.036538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.036577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.036616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.036655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.036698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.036740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.036781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.036828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.036859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.036908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.036942] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.036974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.037459] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.037499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.037531] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.037565] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.037592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.037621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.037650] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.037676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.037702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.037726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.037751] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.037758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.037783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.037788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.037813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.037836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.037871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.037897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.037923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.037948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.037975] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.038001] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.038026] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.038052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.038110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.038217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.038250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.038281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.038311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.038341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.038373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.038405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.038434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.038462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.038487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.038513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.038539] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.038562] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.040602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.040625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.040648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.040672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.042241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.042263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.042281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.043828] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.043848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.045720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.049039] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.049152] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.049185] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.049231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.049343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.049382] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.049442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.066181] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.066221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.066260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.066301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.066334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.066370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.066406] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.066439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.066472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.066503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.066533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.066541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.066571] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.066577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.066608] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.066637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.066667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.066696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.066730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.066760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.066792] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.066821] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.066850] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.066884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.066921] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.082656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.082707] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.082798] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.099824] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.099861] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.099901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.099941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.099980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.100020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.100059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.100178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.100235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.100288] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.100333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.100363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.100393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.100443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.100467] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.100492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.100729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.100749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.100771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.100797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.100820] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.100844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.100867] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.100891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.100914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.100937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.100960] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.100965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.100987] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.100992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.101015] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.101038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.101061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.101137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.101170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.101200] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.101231] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.101260] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.101287] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.101319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.101351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.101454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.101485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.101516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.101545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.101574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.101605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.101639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.101671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.101703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.101725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.101743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.101765] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.101786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.103829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.103850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.103868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.103887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.105450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.105469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.105487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.107068] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.107107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.108965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.112273] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.112323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.112354] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.112396] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.112543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.112617] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.112696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.129335] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.129372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.129409] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.129448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.129478] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.129517] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.129557] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.129597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.129636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.129675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.129713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.129721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.129759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.129766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.129806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.129845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.129884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.129922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.129961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.129999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.130041] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.130069] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.130164] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.130206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.130248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.145905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.145952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.146039] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.164648] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.164685] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.164725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.164764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.164804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.164843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.164883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.164922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.164964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.165005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.165047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.165167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.165215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.165306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.165363] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.165422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.165926] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.165946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.165968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.165990] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.166008] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.166027] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.166047] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.166112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.166148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.166175] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.166205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.166214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.166242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.166250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.166280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.166307] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.166336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.166362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.166395] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.166421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.166451] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.166477] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.166505] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.166537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.166572] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.166675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.166703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.166732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.166758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.166786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.166813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.166845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.166876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.166908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.166933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.166961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.166991] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.167022] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.169105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.169126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.169144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.169164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.170735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.170754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.170772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.172335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.172355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.174224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.177561] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.177614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.177646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.177688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.177833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.177899] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.177999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.194697] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.194737] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.194777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.194818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.194851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.194887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.194924] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.194957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.194990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.195021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.195051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.195122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.195166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.195178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.195221] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.195263] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.195304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.195346] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.195392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.195437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.195660] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.195680] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.195699] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.195722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.195749] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.211217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.211264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.211335] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.228378] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.228415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.228454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.228487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.228517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.228545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.228573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.228603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.228644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.228686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.228728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.228767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.228805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.228870] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.228915] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.228962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.229419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.229443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.229468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.229494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.229514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.229536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.229558] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.229578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.229598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.229617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.229635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.229640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.229658] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.229662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.229681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.229700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.229717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.229735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.229757] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.229775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.229794] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.229813] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.229830] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.229853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.229875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.229945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.229965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.229985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.230003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.230021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.230041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.230092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.230124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.230154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.230181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.230208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.230240] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.230269] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.232333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.232353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.232371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.232391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.233960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.233981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.234003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.235597] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.235618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.237487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.240791] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.240836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.240864] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.240899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.240995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.241032] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.241148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.257921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.257959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.257996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.258034] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.258065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.258186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.258230] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.258263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.258295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.258325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.258353] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.258362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.258389] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.258395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.258423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.258452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.258479] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.258509] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.258541] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.258571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.258600] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.258630] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.258657] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.258691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.258726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.274411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.274457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.274524] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.291536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.291573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.291612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.291645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.291676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.291706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.291735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.291766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.291800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.291832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.291862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.291890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.291917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.291970] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.292005] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.292041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.292522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.292557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.292593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.292633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.292664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.292697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.292731] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.292762] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.292793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.292822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.292860] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.292865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.292882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.292887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.292906] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.292923] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.292942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.292959] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.292980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.292998] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.293018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.293035] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.293053] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.293115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.293150] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.293252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.293280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.293307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.293337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.293359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.293378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.293399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.293419] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.293439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.293457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.293475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.293497] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.293517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.295561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.295582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.295602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.295627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.297206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.297227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.297245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.298802] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.298823] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.300694] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.304011] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.304044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.304119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.304167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.304288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.304327] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.304388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.321154] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.321194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.321234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.321275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.321308] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.321344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.321379] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.321413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.321445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.321477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.321506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.321514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.321543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.321550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.321580] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.321610] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.321638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.321667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.321701] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.321731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.321762] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.321791] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.321820] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.321854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.321890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.337637] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.337685] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.337773] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.354780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.354817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.354857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.354890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.354921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.354950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.354989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.355028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.355071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.355204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.355251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.355288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.355325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.355400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.355450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.355501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.355801] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.355830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.355860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.355893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.355919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.355948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.355976] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.356003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.356029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.356054] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.356126] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.356138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.356173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.356183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.356224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.356253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.356282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.356310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.356342] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.356371] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.356402] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.356431] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.356459] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.356494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.356531] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.356630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.356663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.356696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.356729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.356761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.356792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.356817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.356838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.356860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.356880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.356900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.356924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.356947] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.359004] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.359025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.359044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.359110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.360774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.360793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.360811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.362380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.362400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.364294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.367546] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.367578] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.367598] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.367624] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.367715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.367754] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.367815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.384664] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.384703] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.384743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.384783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.384823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.384866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.384907] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.384948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.384990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.385030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.385070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.385157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.385211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.385225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.385279] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.385330] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.385380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.385430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.385482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.385531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.385582] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.385628] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.385670] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.385721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.385774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.401212] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.401258] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.401346] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.418352] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.418389] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.418429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.418462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.418501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.418540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.418579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.418618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.418660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.418702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.418743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.418782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.418821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.418885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.418930] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.418977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.419597] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.419632] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.419668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.419706] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.419737] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.419770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.419804] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.419836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.419868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.419899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.419929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.419936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.419965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.419972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.420002] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.420032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.420060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.420115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.420148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.420179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.420212] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.420242] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.420273] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.420307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.420343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.420446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.420478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.420508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.420538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.420567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.420596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.420629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.420662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.420694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.420723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.420751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.420786] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.420817] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.422892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.422915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.422933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.422953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.424531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.424550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.424568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.426179] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.426199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.428073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.431435] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.431488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.431520] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.431561] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.431662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.431706] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.431770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.448559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.448599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.448639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.448681] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.448714] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.448750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.448787] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.448826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.448868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.448908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.448949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.448956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.448996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.449003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.449045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.449166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.449212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.449264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.449310] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.449347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.449387] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.449423] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.449459] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.449504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.449547] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.465071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.465154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.465229] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.482265] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.482302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.482342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.482381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.482421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.482462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.482501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.482540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.482583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.482624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.482666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.482704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.482743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.482808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.482853] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.482903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.483217] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.483252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.483288] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.483326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.483352] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.483376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.483399] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.483420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.483440] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.483458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.483477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.483482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.483500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.483504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.483523] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.483541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.483560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.483577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.483599] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.483616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.483637] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.483654] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.483672] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.483693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.483716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.483801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.483821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.483840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.483860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.483878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.483898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.483920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.483940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.483960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.483985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.484010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.484037] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.484090] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.486163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.486184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.486202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.486221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.487785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.487805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.487822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.489390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.489410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.491289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.494636] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.494688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.494721] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.494763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.494909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.494975] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.495076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.511801] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.511839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.511877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.511916] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.511947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.511986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.512027] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.512066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.512179] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.512228] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.512278] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.512291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.512338] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.512351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.512399] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.512442] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.512489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.512531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.512581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.512621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.512652] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.512677] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.512706] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.512739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.512771] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.528257] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.528301] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.528387] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.545392] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.545430] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.545469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.545502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.545532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.545562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.545591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.545622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.545656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.545688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.545718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.545747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.545774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.545827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.545863] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.545899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.546443] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.546473] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.546506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.546542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.546570] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.546601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.546630] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.546660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.546688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.546716] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.546741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.546749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.546775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.546782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.546810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.546836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.546864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.546889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.546920] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.546947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.546977] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.547002] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.547031] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.547087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.547121] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.547223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.547254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.547280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.547309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.547335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.547364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.547397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.547428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.547459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.547485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.547513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.547543] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.547573] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.549655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.549676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.549694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.549713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.551283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.551303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.551321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.552872] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.552894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.554762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.558056] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.558136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.558167] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.558209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.558323] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.558366] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.558427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.575180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.575218] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.575255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.575294] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.575324] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.575358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.575391] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.575422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.575453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.575481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.575509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.575517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.575544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.575550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.575579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.575607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.575645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.575684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.575724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.575762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.575803] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.575843] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.575881] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.575923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.575964] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.591683] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.591728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.591796] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.608840] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.608876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.608916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.608949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.608979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.609009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.609037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.609150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.609204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.609258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.609309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.609350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.609396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.609482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.609536] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.609593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.609970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.609990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.610011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.610036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.610106] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.610142] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.610173] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.610206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.610235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.610265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.610291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.610301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.610328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.610334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.610363] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.610390] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.610421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.610447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.610479] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.610504] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.610534] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.610559] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.610587] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.610620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.610655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.610755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.610785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.610812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.610840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.610866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.610895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.610927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.610957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.610988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.611014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.611042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.611100] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.611130] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.613196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.613216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.613235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.613254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.614814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.614834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.614852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.616406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.616426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.618290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.621597] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.621647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.621679] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.621721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.621832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.621874] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.621936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.638752] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.638790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.638827] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.638866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.638896] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.638929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.638963] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.638994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.639024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.639053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.639162] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.639175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.639222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.639235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.639283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.639326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.639371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.639412] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.639766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.639793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.639823] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.639848] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.639875] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.639906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.639937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.655214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.655259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.655324] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.672365] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.672402] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.672443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.672476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.672507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.672537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.672575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.672615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.672658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.672700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.672741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.672780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.672819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.672883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.672928] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.672975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.673492] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.673523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.673556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.673592] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.673619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.673651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.673681] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.673712] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.673740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.673768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.673794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.673802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.673828] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.673835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.673865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.673890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.673918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.673943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.673974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.673999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.674029] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.674086] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.674111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.674145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.674181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.674284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.674315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.674342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.674370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.674396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.674426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.674459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.674490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.674522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.674547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.674575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.674605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  308.674635] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.676703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.676724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.676743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.676762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.678341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.678362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.678380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.679939] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.679960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.681832] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.685169] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  308.685222] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.685255] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  308.685297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.685404] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.685446] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.685508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.702311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.702351] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.702390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.702432] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.702464] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.702500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.702537] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  308.702571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  308.702604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.702635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.702665] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.702673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.702702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.702709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.702739] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.702769] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.702799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.702828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.702862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.702892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.702924] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:76, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  308.702953] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  308.702987] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  308.703007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.703029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  308.718797] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  308.718843] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.718930] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  308.735916] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  308.735954] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  308.735994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.736026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.736140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.736186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.736235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.736281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.736333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.736384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.736433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.736474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.736518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.736602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.736657] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.736710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.736958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.737000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.737019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.737093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.737126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.737154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.737187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.737223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.737257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.737290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.737322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.737349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.737378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.737418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  308.740248] [IGT] kms_flip: exiting, ret=0
>[  308.770989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  308.771025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.771096] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  308.771134] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.771163] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.771196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.771229] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  308.771259] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.771288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.771316] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.771342] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.771349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.771375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.771380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.771413] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  308.771428] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.771444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.771458] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  308.771477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  308.771493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.771509] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  308.771524] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  308.771539] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  308.771557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.771578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  308.771658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  308.771675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  308.771691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  308.771707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  308.771722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  308.771744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  308.771770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  308.771794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  308.771819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.771841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  308.771861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  308.771886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  308.771908] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  308.774043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.774106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.774126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.774153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.775724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  308.775751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.775767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.777333] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.777351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  308.779221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.782742] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.782786] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  308.782811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  308.782845] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.782912] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.782937] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.799601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  308.799649] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  308.799719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  308.799948] Console: switching to colour frame buffer device 240x75
>[  308.904659] Console: switching to colour dummy device 80x25
>[  308.904773] [IGT] kms_flip: executing
>[  308.916901] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  308.916952] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  308.919090] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  308.919127] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  308.921241] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  308.921253] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  308.923370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  308.923409] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  308.925522] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  308.925533] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.925541] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  308.925571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  308.925612] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  308.926711] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  308.927641] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  308.927662] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  308.927681] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  308.927698] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  308.928719] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  308.928739] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  308.929854] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  308.929858] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  308.929958] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.929961] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.929966] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  308.929968] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  308.929973] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.929975] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.929985] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  308.929989] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  308.929992] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.929995] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.929998] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.930001] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.930004] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  308.930007] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  308.930009] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.930012] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.930015] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  308.930092] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.930099] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.930105] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  308.930111] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.930116] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.930122] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  308.930127] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.930133] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.930139] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  308.930144] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  308.930150] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  308.930156] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  308.930163] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  308.930170] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  308.930176] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.930182] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.930189] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  308.930196] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.930202] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.930207] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  308.930276] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  308.930311] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  308.932109] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.932136] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.934133] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.934144] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  308.936126] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.936164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.938127] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.938138] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.938145] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  308.938547] [IGT] kms_flip: starting subtest basic-flip-vs-modeset
>[  308.939495] [drm:drm_mode_addfb2] [FB:58]
>[  308.939540] [drm:drm_mode_addfb2] [FB:79]
>[  308.992652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  308.992716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.999761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  308.999810] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  308.999900] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.016896] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.016940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.016980] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.017025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.017148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.017207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.017258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.017306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.017347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.017386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.017420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.017452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.017501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.017521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.017539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.017583] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.017647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  309.017737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  309.017814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.017827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.017880] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.017900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.017923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.017948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.017968] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.017989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.018014] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.018074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.018104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.018132] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.018159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.018169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.018195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.018203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.018230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.018257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.018284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.018309] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.018340] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.018366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.018392] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.018418] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.018444] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.018474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.018506] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.021929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.021953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.021978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.022002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.022027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.022112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.022149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.022181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.022215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.022246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.022275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.022310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.022337] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.024381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.024402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.024420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.024439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.026027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.026064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.026082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.027634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.027656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.029553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.032842] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.032885] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.032911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.032947] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.033011] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.033107] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.049712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.049759] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.049821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.066395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.066416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.083232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.083320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.116438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.116486] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.116558] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.133711] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.133754] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.133787] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.133825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.133865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.133908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.133948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.133988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.134027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.134162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.134214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.134251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.134285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.134314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.134343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.134386] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.134479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.134491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.134547] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.134568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.134592] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.134616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.134637] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.134658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.134679] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.134699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.134718] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.134736] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.134754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.134759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.134777] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.134781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.134800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.134818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.134836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.134854] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.134875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.134893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.134911] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.134929] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.134946] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.134967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.134990] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.135086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.135116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.135144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.135170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.135198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.135225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.135255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.135284] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.135315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.135341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.135367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.135398] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.135428] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.137518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.137542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.137564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.137588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.139186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.139210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.139233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.140796] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.140818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.142691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.145996] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.146116] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.146162] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.146226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.146330] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.146373] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.162859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.162908] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.162977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.163372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.163452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.196216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.196263] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.196336] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.213367] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.213409] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.213449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.213493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.213533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.213576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.213616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.213655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.213694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.213738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.213780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.213822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.213863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.213902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.213939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.214012] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.214260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.214279] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.214369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.214400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.214433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.214469] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.214497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.214530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.214559] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.214590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.214618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.214647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.214673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.214680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.214706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.214713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.214742] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.214767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.214796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.214822] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.214853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.214879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.214907] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.214932] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.214960] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.214989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.215023] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.215128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.215157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.215188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.215215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.215244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.215273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.215305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.215337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.215369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.215394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.215423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.215456] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.215484] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.217557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.217580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.217603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.217627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.219212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.219233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.219251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.220803] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.220824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.222701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.225992] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.226115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.226153] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.226196] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.226291] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.226341] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.242856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.242902] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.242964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.243365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.243444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.276251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.276298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.276385] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.293746] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.293789] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.293821] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.293864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.293904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.293948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.293987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.294027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.294124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.294187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.294240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.294293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.294345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.294734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.294773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.294846] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.294979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.294990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.295108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.295255] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.295280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.295306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.295329] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.295353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.295376] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.295399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.295423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.295446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.295468] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.295473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.295496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.295500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.295523] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.295546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.295569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.295592] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.295616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.295639] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.295662] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.295686] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.295709] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.295733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.295758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.295825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.295848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.295872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.295895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.295918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.295941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.295966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.295991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.296015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.296083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.296120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.296152] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.296185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.298256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.298277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.298295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.298315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.299879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.299899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.299917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.301482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.301503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.303374] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.306713] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.306766] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.306798] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.306840] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.306915] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.306948] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.323588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.323638] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.323703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.323889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.323967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.357042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.357197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.357371] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.374593] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.374637] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.374669] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.374709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.374749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.374793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.374832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.374871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.374910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.374954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.374996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.375112] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.375164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.375209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.375254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.375356] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.375586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.375614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.375705] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.375739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.375775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.375815] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.375849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.375871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.375892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.375918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.375945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.375970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.375995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.376025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.376056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.376064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.376094] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.376122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.376151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.376179] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.376210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.376237] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.376265] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.376291] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.376318] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.376349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.376383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.376484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.376515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.376546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.376575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.376605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.376636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.376659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.376679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.376699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.376717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.376735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.376757] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.376777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.378820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.378841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.378859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.378877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.380453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.380473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.380490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.382067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.382088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.383957] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.387208] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.387239] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.387258] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.387283] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.387342] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.387363] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.404097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.404146] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.404212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.404414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.404497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.437430] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.437476] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.437563] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.454582] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.454640] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.454672] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.454710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.454742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.454777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.454807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.454835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.454873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.454918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.454959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.455001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.455118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.455167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.455212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.455313] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.455542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.455579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.455691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.455730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.455774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.455820] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.455857] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.455898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.455936] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.455976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.456012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.456087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.456126] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.456137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.456174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.456185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.456224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.456260] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.456300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.456335] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.456377] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.456413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.456452] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.456487] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.456523] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.456562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.456608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.456708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.456735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.456764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.456791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.456819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.456846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.456878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.456909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.456940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.456965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.456993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.457049] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.457079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.459151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.459173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.459192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.459211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.460775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.460794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.460812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.462381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.462402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.464280] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.467600] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.467652] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.467684] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.467726] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.467805] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.467834] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.484452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.484504] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.484574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.484781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.484863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.517805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.517851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.517937] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.534915] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.534959] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.534991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.535113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.535161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.535217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.535260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.535306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.535350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.535403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.535454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.535512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.535543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.535568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.535596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.535659] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.535792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.535811] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.535883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.535902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.535923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.535947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.535969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.535993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.536061] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.536098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.536128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.536158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.536185] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.536194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.536221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.536229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.536259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.536285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.536315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.536341] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.536375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.536440] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.536466] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.536495] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.536521] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.536553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.536586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.536682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.536713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.536740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.536768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.536793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.536822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.536854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.536886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.536917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.536942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.536969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.537000] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.537055] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.539131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.539153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.539172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.539191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.540764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.540784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.540802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.542354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.542375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.544245] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.547583] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.547635] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.547667] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.547709] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.547783] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.547822] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.564463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.564512] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.564577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.564762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.564841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.597805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.597852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.597920] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.614953] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.615000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.615126] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.615186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.615238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.615293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.615326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.615356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.615390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.615425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.615458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.615489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.615509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.615528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.615546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.615588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.615683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.615695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.615749] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.615770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.615792] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.615818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.615838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.615858] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.615884] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.615910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.615936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.615962] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.615987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.616017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.616048] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.616056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.616086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.616114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.616142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.616168] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.616199] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.616226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.616252] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.616278] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.616305] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.616337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.616368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.616466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.616497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.616526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.616556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.616584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.616615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.616648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.616680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.616713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.616742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.616771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.616797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.616818] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.618859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.618879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.618897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.618916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.620488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.620507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.620525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.622112] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.622133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.623996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.627345] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.627397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.627430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.627472] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.627547] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.627580] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.644222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.644270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.644335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.644533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.644612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.677567] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.677618] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.677691] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.694716] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.694758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.694790] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.694829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.694862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.694897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.694927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.694965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.695005] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.695126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.695181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.695236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.695279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.695317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.695355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.695440] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.695588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.695604] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.695676] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.695703] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.695732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.695765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.695792] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.695820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.695848] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.695873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.695898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.695922] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.695953] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.695961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.695994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.696035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.696075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.696113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.696149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.696184] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.696225] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.696261] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.696288] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.696315] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.696341] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.696372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.696405] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.696504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.696536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.696565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.696595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.696625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.696655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.696688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.696721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.696742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.696760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.696778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.696800] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.696826] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.698869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.698889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.698908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.698926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.700490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.700513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.700536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.702118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.702142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.704007] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.707373] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.707406] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.707425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.707451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.707510] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.707531] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.724233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.724283] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.724352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.724567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.724666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.757582] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.757627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.757695] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.774734] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.774777] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.774810] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.774847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.774880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.774914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.774944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.774972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.775003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.775123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.775176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.775224] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.775275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.775307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.775335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.775400] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.775547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.775566] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.775650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.775681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.775716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.775755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.775786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.775819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.775851] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.775882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.775912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.775941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.775969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.775976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.776055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.776063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.776091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.776117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.776145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.776171] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.776202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.776228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.776254] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.776280] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.776307] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.776337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.776369] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.776461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.776480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.776505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.776531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.776557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.776582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.776611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.776638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.776666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.776691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.776717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.776744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.776770] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.778824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.778848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.778871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.778895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.780474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.780498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.780521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.782098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.782120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.783987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.787334] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.787366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.787386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.787411] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.787471] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.787492] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.804167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.804216] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.804280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.804467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.804544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.837509] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.837560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.837632] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.854721] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.854764] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.854796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.854835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.854867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.854902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.854932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.854960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.854992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.855110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.855163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.855209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.855261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.855407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.855455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.855550] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.855693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.855714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.855798] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.855831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.855873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.855898] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.855918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.855939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.855961] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.855985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.856038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.856067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.856095] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.856102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.856129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.856136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.856165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.856191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.856218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.856244] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.856274] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.856300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.856326] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.856352] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.856379] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.856410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.856444] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.856545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.856577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.856607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.856637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.856666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.856695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.856720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.856747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.856774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.856800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.856825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.856853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.856879] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.858950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.858971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.858990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.859067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.860646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.860667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.860685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.862248] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.862271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.864142] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.867432] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.867480] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.867510] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.867549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.867620] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.867650] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.884308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.884358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.884422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.884617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.884695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.917651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.917698] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.917766] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.934802] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.934849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  309.934889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  309.934933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.934973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.935100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.935154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.935206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.935258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.935317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.935362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.935395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.935427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.935458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.935486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.935554] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.935698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.935716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  309.935800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  309.935833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.935881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  309.935908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.935929] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.935951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.935972] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  309.936023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.936052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.936079] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.936105] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.936113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.936139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.936147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  309.936174] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  309.936200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.936227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.936253] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  309.936282] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  309.936309] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.936336] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  309.936362] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  309.936389] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  309.936420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.936452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  309.936551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  309.936583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  309.936612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  309.936642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  309.936671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  309.936701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  309.936735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  309.936767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  309.936799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.936819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  309.936837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  309.936859] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  309.936880] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  309.938944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.938967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.938990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.939072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.940633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  309.940653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  309.940671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.942238] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.942259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  309.944137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.947448] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.947497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  309.947528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  309.947567] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  309.947637] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.947668] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.964302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  309.964351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  309.964415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  309.964613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  309.964691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.997662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  309.997709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  309.997796] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.014814] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.014857] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.014889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.014932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.014972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.015094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.015140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.015190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.015237] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.015294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.015344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.015393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.015441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.015481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.015523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.015620] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.015848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.015866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.015938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.015958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.015979] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.016053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.016084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.016118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.016149] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.016181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.016210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.016240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.016267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.016276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.016303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.016311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.016341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.016366] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.016396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.016422] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.016453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.016479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.016509] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.016534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.016562] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.016594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.016628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.016712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.016739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.016768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.016794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.016821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.016848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.016879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.016910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.016941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.016966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.016994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.017050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.017082] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.019150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.019170] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.019190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.019214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.020780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.020800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.020818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.022386] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.022407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.024283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.027589] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.027639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.027671] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.027712] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.027805] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.027855] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.044440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.044487] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.044554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.044741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.044822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.077794] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.077841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.077911] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.094940] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.094984] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.095106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.095153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.095188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.095224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.095254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.095283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.095316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.095352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.095385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.095415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.095446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.095474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.095501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.095567] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.095689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.095702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.095757] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.095777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.095799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.095824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.095844] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.095865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.095885] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.095905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.095925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.095943] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.095961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.095966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.096013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.096021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.096048] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.096075] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.096102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.096128] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.096158] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.096184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.096211] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.096237] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.096263] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.096293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.096325] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.096426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.096454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.096473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.096492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.096509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.096528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.096549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.096569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.096588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.096606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.096623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.096646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.096666] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.098714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.098735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.098753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.098773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.100353] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.100374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.100392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.101979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.102012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.103881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.107228] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.107276] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.107305] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.107342] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.107409] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.107438] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.124094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.124143] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.124208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.124405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.124483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.157438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.157487] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.157572] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.174766] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.174808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.174840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.174879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.174912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.174948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.174978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.175091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.175143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.175196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.175248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.175284] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.175316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.175344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.175371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.175436] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.175553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.175565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.175619] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.175640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.175662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.175687] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.175707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.175728] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.175749] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.175768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.175788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.175807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.175825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.175830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.175848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.175853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.175871] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.175889] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.175907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.175925] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.175946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.175965] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.176020] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.176047] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.176073] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.176103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.176135] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.176234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.176264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.176292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.176320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.176343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.176362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.176383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.176403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.176423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.176440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.176458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.176480] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.176501] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.178573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.178592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.178610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.178629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.180211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.180231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.180249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.181798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.181819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.183693] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.186997] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.187081] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.187119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.187167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.187243] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.187280] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.203909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.203959] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.204118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.204315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.204392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.237253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.237299] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.237368] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.254433] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.254477] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.254509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.254547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.254580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.254615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.254645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.254674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.254706] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.254740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.254772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.254803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.254833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.254861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.254888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.254950] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.255239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.255267] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.255386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.255409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.255432] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.255458] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.255477] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.255500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.255525] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.255551] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.255577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.255603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.255628] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.255634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.255659] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.255664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.255690] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.255715] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.255741] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.255767] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.255793] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.255818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.255844] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.255870] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.255896] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.255922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.255950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.256133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.256168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.256201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.256232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.256262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.256294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.256328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.256351] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.256372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.256391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.256409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.256434] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.256454] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.258498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.258519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.258537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.258556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.260242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.260264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.260283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.261846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.261869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.263744] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.267060] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.267110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.267142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.267184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.267259] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.267291] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.283914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.283963] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.284120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.284357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.284439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.317254] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.317305] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.317377] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.334574] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.334616] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.334648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.334687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.334720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.334755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.334794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.334834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.334873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.334917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.334958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.335076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.335128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.335172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.335221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.335305] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.335435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.335449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.335504] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.335530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.335557] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.335586] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.335611] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.335638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.335664] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.335690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.335716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.335742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.335767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.335773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.335798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.335803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.335828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.335854] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.335881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.335906] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.335932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.335958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.336013] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.336044] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.336072] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.336104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.336137] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.336236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.336269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.336299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.336330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.336361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.336392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.336424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.336447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.336467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.336486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.336504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.336528] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.336548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.338597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.338618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.338636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.338656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.340222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.340242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.340260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.341810] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.341831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.343696] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.346982] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.347066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.347105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.347157] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.347236] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.347276] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.363855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.363902] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.363964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.364287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.364373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.397207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.397253] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.397321] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.414359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.414406] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.414447] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.414490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.414530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.414574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.414614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.414652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.414691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.414735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.414777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.414818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.414860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.414899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.414937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.415109] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.415252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.415271] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.415359] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.415392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.415427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.415464] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.415496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.415528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.415561] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.415592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.415623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.415654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.415685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.415692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.415721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.415728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.415758] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.415787] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.415818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.415843] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.415875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.415904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.415933] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.415962] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.416023] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.416055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.416091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.416191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.416221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.416248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.416277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.416303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.416333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.416365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.416397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.416430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.416459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.416487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.416521] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.416552] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.418629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.418651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.418670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.418689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.420277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.420299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.420318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.421878] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.421899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.423772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.427087] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.427137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.427169] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.427211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.427290] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.427311] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.443935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.443985] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.444150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.444386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.444462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.477282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.477330] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.477399] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.494434] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.494477] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.494510] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.494548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.494580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.494615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.494645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.494674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.494705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.494739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.494771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.494801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.494831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.494858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.494886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.494925] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.495095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.495114] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.495177] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.495198] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.495221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.495246] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.495266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.495286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.495309] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.495329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.495349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.495367] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.495386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.495391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.495409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.495413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.495432] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.495449] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.495468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.495485] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.495507] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.495524] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.495543] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.495561] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.495579] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.495599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.495623] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.495688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.495708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.495726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.495744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.495762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.495782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.495803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.495823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.495842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.495860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.495878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.495904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.495930] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.498014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.498036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.498054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.498074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.499649] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.499670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.499692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.501249] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.501270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.503134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.506452] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.506502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.506532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.506572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.506647] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.506685] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.523294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.523340] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.523403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.523601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.523676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.556678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.556725] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.556792] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.573803] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.573846] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.573878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.573916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.573949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.574081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.574132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.574183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.574233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.574291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.574343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.574392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.574443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.574488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.574533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.574631] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.574812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.574828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.574881] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.574900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.574922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.574948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.575021] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.575057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.575092] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.575125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.575157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.575189] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.575219] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.575229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.575258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.575266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.575295] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.575325] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.575356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.575382] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.575416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.575445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.575473] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.575500] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.575529] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.575563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.575597] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.575696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.575727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.575757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.575787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.575816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.575847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.575880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.575913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.575945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.575997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.576025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.576061] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.576092] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.578160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.578181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.578200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.578219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.579780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.579802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.579825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.581389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.581410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.583281] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.586621] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.586673] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.586706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.586747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.586821] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.586854] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.603497] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.603547] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.603613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.603794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.603873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.636841] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.636888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.636957] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.654066] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.654108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.654139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.654177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.654210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.654249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.654289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.654328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.654368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.654412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.654456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.654486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.654514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.654546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.654579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.654640] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.654766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.654781] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.654860] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.654893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.654927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.654965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.655049] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.655095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.655137] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.655176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.655214] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.655250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.655286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.655296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.655330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.655340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.655375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.655410] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.655453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.655479] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.655509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.655535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.655562] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.655587] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.655613] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.655646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.655903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.656003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.656089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.656109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.656128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.656147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.656167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.656189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.656210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.656231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.656249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.656268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.656291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.656312] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.658355] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.658378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.658399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.658425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.660092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.660113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.660132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.661691] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.661712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.663586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.666822] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.666854] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.666874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.666899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.666959] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.667023] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.683701] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.683750] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.683815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.684115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.684231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.717045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.717091] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.717161] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.734201] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.734245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.734277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.734315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.734348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.734382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.734412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.734441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.734472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.734507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.734539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.734570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.734600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.734627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.734654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.734716] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.734857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.734876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.734957] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.735074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.735124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.735179] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.735223] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.735271] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.735317] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.735359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.735387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.735414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.735443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.735451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.735479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.735488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.735515] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.735545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.735568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.735586] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.735608] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.735625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.735644] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.735662] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.735680] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.735701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.735724] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.735791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.735811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.735830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.735848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.735866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.735885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.735906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.735925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.735944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.735990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.736017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.736049] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.736078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.738139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.738160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.738177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.738196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.739768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.739788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.739810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.741365] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.741387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.743257] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.746592] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.746624] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.746643] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.746669] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.746727] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.746748] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.763423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.763474] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.763545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.763751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.763834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.796766] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.796813] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.796883] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.814045] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.814088] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.814119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.814157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.814190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.814225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.814255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.814283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.814315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.814349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.814381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.814411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.814441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.814469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.814496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.814559] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.814688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.814707] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.814789] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.814819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.814853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.814891] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.814921] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.814953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.815056] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.815102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.815146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.815186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.815213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.815221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.815247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.815254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.815281] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.815307] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.815334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.815359] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.815389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.815415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.815441] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.815468] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.815494] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.815525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.815556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.815653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.815682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.815710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.815740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.815761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.815780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.815802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.815822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.815842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.815859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.815883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.815910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.815935] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.818008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.818029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.818047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.818066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.819630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.819651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.819668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.821221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.821242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.823111] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.826421] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.826453] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.826473] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.826498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.826556] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.826577] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.843272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.843319] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.843380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.843565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.843639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.876619] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.876664] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.876730] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.893771] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.893815] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.893848] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.893886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.893918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.893953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.894063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.894112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.894159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.894218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.894268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.894319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.894369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.894414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.894459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.894528] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.894675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.894694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.894778] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.894810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.894845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.894883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.894914] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.894947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.895031] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.895069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.895107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.895143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.895177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.895188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.895222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.895232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.895268] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.895302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.895337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.895371] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.895410] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.895444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.895479] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.895513] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.895551] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.895593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.895639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.895771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.895813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.895854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.895894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.895933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.896008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.896042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.896076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.896111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.896142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.896173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.896211] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.896247] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.898305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.898326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.898345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.898366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.899953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.899989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.900007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.901580] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.901604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.903487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.906801] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.906853] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.906886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.906928] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.907099] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.907152] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.923651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.923699] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.923763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.924014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.924133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.957025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  310.957074] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  310.957161] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.974161] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.974204] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  310.974237] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  310.974275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.974308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.974342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.974372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.974401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.974432] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  310.974466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.974499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.974530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.974560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.974587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.974614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.974677] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  310.974812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  310.974824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  310.974874] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  310.974892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  310.974912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  310.974938] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  310.975024] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  310.975055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  310.975086] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  310.975114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  310.975143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  310.975169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  310.975196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  310.975204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.975230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  310.975237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  310.975264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  310.975290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  310.975317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.975343] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  310.975372] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  310.975401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  310.975430] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  310.975458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  310.975485] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  310.975515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.975550] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  310.975618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  310.975638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  310.975656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  310.975673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  310.975691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  310.975710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  310.975730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  310.975750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  310.975770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  310.975789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  310.975806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  310.975829] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  310.975849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  310.977895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.977916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.977934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.978002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.979558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  310.979579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.979597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.981156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.981178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  310.983037] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.986349] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.986395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  310.986424] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  310.986462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.986546] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.986591] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.003203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.003252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.003316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.003515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.003594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.036547] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.036594] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.036679] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.053716] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.053743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.053762] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.053785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.053805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.053825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.053843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.053860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.053879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.053899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.053923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.053948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.054034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.054062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.054090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.054154] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.054269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.054282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.054338] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.054363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.054390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.054420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.054445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.054472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.054498] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.054521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.054547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.054573] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.054598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.054603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.054628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.054633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.054659] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.054685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.054710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.054735] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.054760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.054785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.054812] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.054837] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.054863] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.054890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.054918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.055036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.055068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.055097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.055125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.055155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.055186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.055219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.055243] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.055264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.055282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.055300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.055323] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.055344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.057379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.057399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.057417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.057436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.058998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.059017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.059035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.060587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.060608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.062484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.065801] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.065853] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.065886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.065927] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.066231] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.066252] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.082650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.082698] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.082763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.083018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.083133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.115998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.116045] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.116115] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.133146] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.133189] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.133221] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.133259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.133292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.133327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.133358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.133388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.133419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.133454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.133487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.133519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.133550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.133587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.133626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.133687] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.133775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.133787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.133836] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.133854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.133877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.133904] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.133927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.134013] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.134045] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.134077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.134106] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.134136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.134163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.134172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.134199] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.134207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.134237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.134264] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.134294] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.134320] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.134353] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.134380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.134410] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.134438] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.134467] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.134501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.134536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.134634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.134664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.134690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.134718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.134744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.134773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.134805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.134836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.134867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.134893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.134921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.134976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.135008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.137080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.137101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.137120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.137139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.138709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.138729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.138747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.140312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.140333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.142204] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.145527] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.145580] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.145617] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.145669] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.145749] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.145786] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.162370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.162420] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.162484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.162682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.162761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.195714] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.195761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.195829] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.213030] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.213074] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.213106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.213143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.213176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.213210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.213239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.213268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.213299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.213333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.213365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.213396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.213426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.213453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.213480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.213531] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.213618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.213630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.213680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.213699] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.213719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.213742] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.213760] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.213779] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.213798] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.213816] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.213834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.213851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.213867] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.213871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.213887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.213891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.213907] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.213923] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.213994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.214021] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.214051] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.214079] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.214105] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.214131] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.214157] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.214188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.214219] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.214316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.214346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.214374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.214402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.214431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.214458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.214492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.214513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.214533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.214550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.214568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.214590] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.214615] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.216648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.216669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.216687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.216710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.218286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.218306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.218324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.219873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.219894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.221767] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.225069] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.225118] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.225155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.225203] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.225276] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.225309] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.241932] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.242017] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.242087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.242293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.242375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.275277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.275324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.275394] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.293910] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.294037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.294088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.294146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.294194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.294231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.294261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.294291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.294322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.294359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.294392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.294423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.294454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.294482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.294511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.294573] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.294722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.294740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.294822] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.294853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.294890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.294935] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.295023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.295071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.295118] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.295162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.295211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.295245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.295277] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.295288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.295320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.295330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.295364] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.295396] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.295430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.295463] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.295499] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.295531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.295565] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.295597] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.295629] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.295666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.295710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.295832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.295871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.295908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.295944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.296064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.296102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.296145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.296186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.296230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.296258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.296278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.296301] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.296323] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.298366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.298387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.298405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.298424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.299990] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.300013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.300036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.301602] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.301624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.303490] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.306795] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.306844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.306875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.306914] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.307074] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.307118] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.323630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.323679] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.323748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.324002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.324290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.357000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.357044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.357111] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.374260] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.374303] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.374335] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.374373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.374405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.374440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.374470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.374499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.374530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.374565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.374596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.374627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.374658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.374685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.374712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.374776] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.374904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.374996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.375132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.375164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.375198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.375236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.375267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.375300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.375322] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.375343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.375364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.375382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.375400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.375405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.375423] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.375427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.375445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.375463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.375481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.375499] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.375521] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.375538] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.375557] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.375574] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.375592] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.375613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.375636] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.375702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.375723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.375741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.375760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.375778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.375798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.375818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.375839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.375858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.375877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.375894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.375916] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.375969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.378045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.378066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.378085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.378104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.379672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.379692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.379710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.381263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.381284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.383153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.386418] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.386450] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.386473] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.386504] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.386565] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.386586] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.403269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.403320] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.403391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.403594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.403677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.436592] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.436639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.436708] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.453741] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.453784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.453817] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.453863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.453894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.453927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.454032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.454080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.454123] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.454177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.454213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.454242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.454272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.454299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.454324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.454384] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.454521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.454539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.454618] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.454648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.454681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.454718] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.454746] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.454778] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.454809] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.454838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.454868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.454886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.454903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.454908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.454927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.454962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.454991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.455019] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.455046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.455072] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.455102] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.455128] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.455156] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.455182] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.455208] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.455237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.455270] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.455369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.455391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.455410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.455428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.455446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.455465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.455487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.455507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.455527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.455551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.455576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.455603] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.455630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.457677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.457698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.457716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.457734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.459300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.459320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.459338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.460933] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.460970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.462829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.466118] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.466148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.466168] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.466198] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.466259] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.466280] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.482996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.483045] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.483109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.483307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.483385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.516339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.516386] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.516454] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.533489] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.533532] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.533565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.533603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.533635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.533670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.533701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.533731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.533762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.533796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.533828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.533859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.533890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.533918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.534029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.534128] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.534286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.534304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.534388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.534419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.534456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.534500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.534539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.534582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.534622] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.534670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.534692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.534712] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.534737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.534742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.534767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.534772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.534798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.534823] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.534849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.534874] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.534901] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.534927] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.534983] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.535013] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.535042] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.535075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.535108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.535207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.535238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.535269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.535298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.535328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.535359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.535393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.535426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.535453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.535471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.535490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.535512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.535534] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.537728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.537751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.537774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.537798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.539363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.539384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.539402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.540977] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.540998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.542862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.546182] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.546230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.546261] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.546300] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.546370] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.546401] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.563029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.563080] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.563152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.563359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.563442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.596371] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.596418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.596490] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.613521] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.613563] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.613595] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.613633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.613665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.613699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.613728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.613756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.613786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.613828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.613871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.613913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.614034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.614079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.614123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.614223] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.614349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.614361] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.614415] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.614435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.614459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.614483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.614505] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.614532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.614558] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.614584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.614611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.614636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.614662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.614668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.614692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.614697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.614723] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.614749] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.614774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.614799] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.614825] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.614850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.614876] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.614901] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.614955] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.614988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.615022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.615122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.615154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.615185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.615216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.615247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.615277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.615312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.615345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.615378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.615408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.615437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.615461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.615482] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.617532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.617552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.617570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.617589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.619160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.619180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.619198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.620746] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.620767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.622643] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.625933] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.626012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.626044] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.626085] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.626159] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.626192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.642803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.642850] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.642912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.643258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.643336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.676152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.676196] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.676262] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.693299] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.693343] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.693375] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.693412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.693445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.693479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.693510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.693538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.693569] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.693605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.693637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.693667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.693698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.693725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.693752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.693823] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.694077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.694097] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.694189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.694221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.694256] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.694293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.694324] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.694357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.694389] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.694420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.694451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.694481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.694510] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.694518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.694545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.694552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.694581] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.694610] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.694639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.694667] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.694701] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.694730] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.694761] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.694790] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.694819] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.694851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.694886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.694995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.695028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.695059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.695091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.695122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.695150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.695185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.695218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.695250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.695281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.695310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.695344] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.695375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.697439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.697463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.697486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.697510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.699100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.699122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.699141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.700705] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.700728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.702602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.705919] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.706042] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.706075] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.706117] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.706192] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.706225] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.722867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.722916] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.723080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.723324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.723401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.756213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.756259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.756328] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.773364] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.773408] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.773440] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.773479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.773512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.773547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.773578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.773607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.773639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.773674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.773707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.773738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.773775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.773813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.773852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.773934] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.774142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.774162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.774252] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.774276] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.774300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.774325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.774345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.774367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.774389] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.774410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.774430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.774449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.774473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.774479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.774504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.774509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.774535] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.774561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.774587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.774612] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.774639] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.774664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.774690] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.774715] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.774742] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.774769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.774798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.774870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.774897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.774952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.774984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.775013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.775043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.775075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.775106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.775137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.775165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.775191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.775224] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.775253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.777317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.777338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.777360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.777384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.778974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.778995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.779017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.780582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.780603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.782477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.785759] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.785810] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.785841] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.785882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.786200] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.786223] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.802642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.802691] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.802755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.803054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.803171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.836003] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.836049] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.836121] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.853134] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.853177] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.853209] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.853248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.853280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.853315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.853344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.853373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.853404] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.853439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.853470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.853500] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.853530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.853557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.853584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.853651] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.853762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.853773] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.853824] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.853843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.853863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.853886] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.853908] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.853991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.854021] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.854054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.854083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.854112] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.854139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.854148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.854175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.854183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.854213] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.854240] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.854269] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.854296] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.854328] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.854354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.854385] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.854411] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.854440] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.854475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.854509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.854999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.855030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.855060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.855088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.855117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.855145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.855178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.855210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.855242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.855268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.855297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.855331] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.855360] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.857422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.857442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.857461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.857484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.859127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.859158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.859177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.860727] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.860749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.862614] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.865929] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.866003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.866023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.866049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.866108] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.866138] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.882824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.882871] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.883024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.883215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.883320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.916172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.916217] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.916303] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.933448] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.933492] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  311.933524] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  311.933562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.933595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.933629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.933659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.933688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.933728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.933761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.933791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.933820] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.933848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.933873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.933899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.934048] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.934205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.934222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  311.934301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  311.934332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.934367] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  311.934409] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.934447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.934485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.934524] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.934561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.934600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.934637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.934675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.934683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.934719] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.934726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  311.934761] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  311.934783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.934803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.934821] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  311.934845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  311.934864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.934883] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  311.934901] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  311.934952] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  311.934982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.935015] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  311.935115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.935147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  311.935178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  311.935209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  311.935239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  311.935270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  311.935304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  311.935336] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  311.935368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.935397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  311.935426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  311.935459] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  311.935480] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  311.937534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.937555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.937573] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.937592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.939191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  311.939213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.939236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.940798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.940820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  311.942698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.946010] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.946042] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  311.946062] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  311.946087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.946147] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.946168] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.962865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  311.962916] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.963088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  311.963331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.963410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.996209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.996256] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  311.996325] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.013475] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.013522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.013563] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.013606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.013646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.013689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.013729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.013768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.013807] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.013850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.013892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.014013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.014066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.014110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.014158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.014251] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.014395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.014413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.014499] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.014532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.014569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.014608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.014627] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.014649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.014670] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.014691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.014710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.014729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.014753] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.014759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.014784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.014789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.014814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.014840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.014867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.014892] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.014946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.014977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.015007] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.015034] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.015062] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.015094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.015127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.015225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.015246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.015265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.015290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.015315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.015340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.015368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.015395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.015422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.015447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.015472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.015499] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.015524] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.017635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.017658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.017679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.017699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.019243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.019264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.019283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.020812] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.020834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.022675] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.025892] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.025963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.025983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.026009] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.026070] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.026091] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.042789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.042839] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.042906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.043242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.043331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.076136] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.076183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.076252] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.093288] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.093332] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.093364] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.093403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.093436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.093471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.093501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.093530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.093562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.093597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.093628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.093659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.093688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.093726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.093764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.093838] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.094078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.094109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.094220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.094255] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.094292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.094337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.094365] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.094393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.094423] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.094449] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.094476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.094500] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.094525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.094531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.094554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.094560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.094584] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.094607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.094632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.094654] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.094683] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.094706] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.094730] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.094753] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.094776] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.094804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.094836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.094962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.095001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.095037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.095073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.095107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.095144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.095186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.095226] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.095265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.095300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.095334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.095379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.095412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.097506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.097527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.097545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.097564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.099138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.099158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.099176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.100724] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.100744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.102617] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.105906] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.105979] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.106008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.106045] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.106112] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.106142] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.122782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.122831] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.122896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.123195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.123293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.156126] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.156173] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.156242] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.173280] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.173323] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.173355] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.173393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.173426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.173461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.173491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.173520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.173551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.173585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.173617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.173649] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.173679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.173707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.173734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.173796] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.174029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.174059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.174197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.174256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.174290] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.174327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.174351] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.174373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.174394] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.174415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.174435] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.174454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.174472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.174478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.174495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.174500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.174519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.174537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.174556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.174573] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.174593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.174612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.174629] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.174648] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.174665] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.174686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.174709] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.174776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.174796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.174814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.174833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.174858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.174884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.174938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.174970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.175001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.175027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.175054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.175086] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.175115] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.177178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.177199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.177217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.177236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.178806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.178826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.178844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.180423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.180444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.182336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.185612] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.185644] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.185663] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.185689] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.185750] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.185771] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.202461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.202510] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.202574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.202760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.202838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.235810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.235857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.236014] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.253123] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.253184] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.253232] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.253287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.253335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.253386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.253431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.253470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.253502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.253536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.253568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.253598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.253628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.253655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.253682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.253745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.253954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.253985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.254109] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.254139] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.254170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.254205] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.254233] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.254263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.254292] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.254322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.254349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.254378] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.254404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.254411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.254437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.254444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.254472] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.254497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.254525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.254550] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.254580] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.254605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.254633] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.254658] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.254685] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.254714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.254746] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.255248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.255277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.255303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.255330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.255355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.255382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.255412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.255441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.255470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.255494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.255519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.255551] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.255577] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.257661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.257685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.257708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.257732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.259300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.259323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.259346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.260901] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.260947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.262806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.266156] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.266207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.266240] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.266284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.266343] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.266372] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.283013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.283063] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.283131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.283365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.283457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.316381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.316427] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.316499] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.333521] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.333565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.333598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.333636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.333668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.333702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.333732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.333761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.333791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.333825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.333857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.333888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.334000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.334036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.334075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.334159] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.334355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.334381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.334493] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.334533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.334576] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.334623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.334661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.334702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.334741] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.334779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.334815] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.334852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.334888] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.334932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.334972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.334979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.335011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.335038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.335067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.335094] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.335125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.335152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.335181] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.335208] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.335238] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.335271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.335305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.335406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.335436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.335466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.335496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.335525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.335554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.335586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.335617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.335648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.335674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.335701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.335731] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.335761] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.337843] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.337865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.337885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.337956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.339588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.339608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.339627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.341190] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.341210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.343083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.346339] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.346372] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.346391] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.346417] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.346475] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.346505] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.363177] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.363222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.363286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.363467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.363542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.396542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.396589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.396675] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.413700] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.413743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.413775] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.413813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.413846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.413880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.413989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.414035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.414085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.414144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.414197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.414248] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.414300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.414335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.414363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.414428] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.414569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.414588] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.414677] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.414717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.414760] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.414805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.414842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.414868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.414891] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.414945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.414975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.415002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.415028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.415036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.415062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.415069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.415097] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.415124] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.415151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.415176] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.415207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.415233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.415260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.415286] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.415311] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.415344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.415378] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.415479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.415511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.415540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.415570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.415599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.415630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.415664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.415688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.415708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.415727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.415744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.415768] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.415788] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.417840] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.417861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.417883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.417962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.419531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.419551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.419569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.421133] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.421154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.423024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.426294] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.426336] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.426363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.426398] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.426477] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.426519] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.443136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.443184] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.443249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.443442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.443520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.476485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.476532] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.476618] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.493639] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.493682] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.493714] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.493752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.493784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.493818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.493848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.493877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.493990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.494049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.494098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.494150] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.494202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.494248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.494294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.494391] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.494541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.494554] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.494609] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.494629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.494652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.494677] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.494697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.494718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.494739] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.494759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.494779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.494803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.494829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.494834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.494859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.494864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.494893] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.494951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.494980] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.495007] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.495038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.495065] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.495093] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.495119] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.495145] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.495176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.495209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.495307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.495338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.495368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.495398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.495429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.495460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.495494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.495523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.495545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.495563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.495581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.495603] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.495624] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.497673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.497694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.497712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.497731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.499305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.499325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.499342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.500899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.500935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.502805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.506136] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.506187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.506224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.506272] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.506363] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.506411] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.522959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.523006] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.523073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.523271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.523351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.556329] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.556376] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.556447] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.574843] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.574887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.575003] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.575061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.575110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.575162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.575205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.575249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.575294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.575347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.575397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.575440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.575471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.575497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.575526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.575588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.575739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.575757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.575839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.575863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.575934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.575976] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.576005] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.576039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.576070] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.576102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.576131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.576160] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.576187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.576197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.576224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.576232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.576261] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.576290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.576319] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.576344] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.576376] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.576401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.576430] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.576456] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.576484] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.576516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.576549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.576633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.576661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.576690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.576716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.576744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.576771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.576802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.576833] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.576864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.576915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.576945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.576977] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.577008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.579076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.579099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.579122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.579145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.580708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.580729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.580747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.582311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.582332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.584193] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.587524] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.587576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.587608] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.587650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.587709] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.587739] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.604358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.604407] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.604474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.604659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.604742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.637703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.637752] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.637838] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.654890] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.654966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.654999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.655037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.655070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.655104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.655133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.655161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.655193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.655228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.655261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.655300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.655342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.655381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.655419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.655492] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.655622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.655641] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.655733] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.655773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.655812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.655857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.655895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.655989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.656050] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.656097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.656151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.656188] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.656226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.656237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.656275] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.656286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.656326] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.656362] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.656400] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.656434] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.656477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.656511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.656549] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.656584] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.656621] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.656665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.656710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.657314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.657344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.657374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.657402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.657431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.657459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.657491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.657523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.657554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.657580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.657607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.657637] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.657667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.659731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.659751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.659769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.659788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.661354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.661374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.661392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.662974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.662996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.664868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.668166] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.668215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.668247] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.668293] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.668351] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.668381] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.685044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.685092] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.685156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.685353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.685431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.718387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.718434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.718519] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.735596] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.735639] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.735672] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.735710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.735742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.735776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.735806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.735835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.735866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.736043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.736089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.736133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.736177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.736213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.736252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.736338] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.736541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.736568] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.736678] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.736708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.736739] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.736773] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.736800] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.736828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.736857] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.736934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.736981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.737029] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.737062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.737072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.737104] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.737113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.737147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.737177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.737211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.737241] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.737277] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.737308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.737342] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.737372] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.737406] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.737440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.737476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.737586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.737617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.737649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.737679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.737710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.737741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.737776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.737811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.737845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.737874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.737932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.737969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.738002] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.740080] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.740101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.740119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.740143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.741705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.741726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.741744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.743307] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.743329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.745202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.748427] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.748458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.748478] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.748503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.748560] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.748589] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.765267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.765316] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.765380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.765577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.765655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.798625] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.798677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.798752] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.815809] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.815852] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.815968] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.816015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.816050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.816086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.816117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.816147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.816180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.816216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.816249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.816280] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.816311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.816340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.816368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.816433] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.816580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.816600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.816683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.816714] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.816750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.816794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.816833] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.816875] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.816957] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.816988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.817017] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.817045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.817072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.817080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.817106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.817114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.817141] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.817168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.817195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.817221] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.817252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.817279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.817307] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.817333] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.817359] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.817389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.817421] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.817505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.817537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.817567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.817597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.817627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.817658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.817691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.817724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.817756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.817785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.817814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.817845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.817866] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.819960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.819981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.819999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.820017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.821582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.821602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.821619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.823195] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.823217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.825091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.828380] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.828425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.828454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.828491] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.828575] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.828619] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.845256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.845305] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.845375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.845580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.845662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.878602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.878650] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.878735] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.895741] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.895784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.895816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.895854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.895967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.896022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.896068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.896115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.896160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.896215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.896264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.896313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.896361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.896401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.896443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.896539] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.896716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.896735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.896802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.896821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.896842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.896865] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.896930] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.896965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.896995] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.897028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.897057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.897087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.897114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.897122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.897150] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.897158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.897188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.897215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.897245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.897271] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.897302] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.897328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.897357] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.897384] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.897411] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.897443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.897476] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.897574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.897602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.897630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.897656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.897684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.897711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.897742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.897774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.897805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.897830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.897858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.897913] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.897944] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.900008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.900028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.900046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.900065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.901635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.901655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.901673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.903237] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.903257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.905130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.908439] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.908489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.908521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.908563] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.908656] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.908706] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.925283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.925329] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.925392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.925581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.925657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.958641] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  312.958688] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  312.958772] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.975788] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.975830] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  312.975862] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  312.975986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.976038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.976094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.976143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.976180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.976218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  312.976265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.976309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.976352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.976396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.976436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.976476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.976560] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  312.976653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  312.976666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  312.976724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  312.976746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.976771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  312.976795] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.976815] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.976838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.976859] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  312.976910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.976939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.976967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.976995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.977003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.977030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.977037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  312.977065] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  312.977092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.977119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.977144] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  312.977175] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  312.977201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.977228] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  312.977253] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  312.977280] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  312.977311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.977343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  312.977442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  312.977475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  312.977505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  312.977534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  312.977564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  312.977595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  312.977628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  312.977661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  312.977694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  312.977723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  312.977748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  312.977771] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  312.977792] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  312.979833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.979856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.979934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.979968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.981540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  312.981563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.981585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.983153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.983175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  312.985048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.988369] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.988422] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  312.988454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  312.988495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.988588] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.988638] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.005212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.005262] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.005327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.005521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.005599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.038559] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.038610] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.038700] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.055713] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.055756] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.055789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.055826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.055859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.055981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.056024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.056056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.056088] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.056124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.056156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.056198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.056241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.056282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.056322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.056396] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.056535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.056548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.056605] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.056627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.056651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.056681] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.056705] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.056732] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.056758] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.056784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.056810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.056836] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.056862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.056895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.056927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.056935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.056965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.056995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.057023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.057051] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.057082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.057109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.057136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.057163] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.057190] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.057220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.057252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.057352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.057374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.057393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.057411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.057430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.057449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.057470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.057489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.057509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.057527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.057544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.057566] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.057587] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.059633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.059654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.059673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.059691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.061248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.061270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.061289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.062862] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.062900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.064769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.068053] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.068099] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.068133] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.068179] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.068265] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.068309] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.084924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.084972] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.085034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.085231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.085306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.118279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.118326] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.118411] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.135435] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.135482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.135523] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.135567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.135607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.135651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.135690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.135730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.135769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.135812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.135854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.135976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.136030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.136079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.136125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.136218] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.136354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.136367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.136421] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.136442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.136465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.136491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.136511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.136533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.136554] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.136579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.136605] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.136631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.136654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.136660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.136684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.136689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.136715] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.136741] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.136768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.136793] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.136819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.136845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.136900] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.136931] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.136960] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.136993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.137025] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.137124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.137151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.137171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.137189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.137206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.137226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.137248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.137268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.137288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.137306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.137324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.137346] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.137366] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.139445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.139465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.139484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.139503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.141077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.141097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.141119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.142678] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.142699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.144572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.147908] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.147957] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.147988] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.148027] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.148115] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.148162] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.164787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.164836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.164996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.165205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.165301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.198133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.198180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.198265] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.215391] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.215434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.215466] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.215503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.215535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.215570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.215600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.215630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.215661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.215696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.215728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.215760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.215791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.215818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.215846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.215989] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.216180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.216199] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.216278] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.216300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.216323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.216348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.216373] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.216400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.216426] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.216450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.216476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.216502] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.216527] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.216533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.216557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.216562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.216588] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.216613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.216639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.216664] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.216690] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.216715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.216741] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.216766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.216792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.216819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.216847] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.216969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.217000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.217030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.217061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.217092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.217123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.217158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.217191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.217225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.217254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.217284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.217318] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.217351] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.219443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.219463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.219482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.219500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.221068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.221088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.221107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.222646] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.222668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.224535] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.227823] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.227950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.228002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.228072] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.228179] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.228229] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.244702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.244748] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.244816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.245148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.245247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.278086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.278132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.278203] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.296806] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.296849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.296963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.297021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.297067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.297118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.297161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.297206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.297250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.297304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.297354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.297403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.297452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.297493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.297538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.297635] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.297894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.297916] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.298006] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.298040] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.298076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.298100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.298122] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.298148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.298178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.298196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.298214] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.298236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.298259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.298264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.298286] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.298291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.298314] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.298338] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.298361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.298384] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.298408] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.298430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.298454] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.298477] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.298500] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.298525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.298549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.298605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.298629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.298652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.298676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.298699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.298722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.298747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.298771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.298796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.298819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.298842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.298910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.298946] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.301030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.301052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.301071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.301090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.302659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.302679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.302697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.304261] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.304281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.306152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.309422] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.309454] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.309474] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.309499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.309560] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.309581] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.326267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.326316] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.326381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.326582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.326661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.359611] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.359658] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.359726] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.376921] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.376964] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.376997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.377035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.377067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.377102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.377132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.377161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.377192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.377226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.377259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.377290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.377320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.377348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.377375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.377437] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.377566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.377584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.377666] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.377696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.377731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.377769] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.377799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.377832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.377940] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.377977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.378012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.378046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.378080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.378090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.378122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.378131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.378165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.378197] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.378231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.378263] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.378300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.378333] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.378366] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.378399] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.378431] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.378472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.378514] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.378637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.378675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.378712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.378751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.378788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.378827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.378904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.378938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.378972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.379002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.379029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.379063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.379093] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.381161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.381182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.381200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.381223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.382795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.382815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.382833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.384416] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.384437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.386312] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.389651] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.389704] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.389737] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.389779] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.389858] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.389965] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.406528] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.406577] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.406644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.406830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.407188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.439851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.439928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.440000] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.457026] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.457069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.457101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.457139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.457172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.457206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.457236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.457265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.457296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.457332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.457363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.457394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.457425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.457452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.457479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.457541] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.457681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.457700] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.457781] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.457811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.457857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.457946] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.457975] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.458010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.458040] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.458071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.458099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.458129] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.458155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.458164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.458191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.458199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.458229] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.458257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.458285] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.458311] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.458343] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.458370] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.458398] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.458424] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.458452] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.458485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.458518] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.458616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.458643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.458671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.458697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.458724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.458751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.458784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.458814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.458846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.458896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.458923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.458957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.458986] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.461055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.461076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.461095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.461115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.462686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.462707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.462725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.464287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.464308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.466179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.469500] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.469553] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.469586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.469628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.469703] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.469736] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.486344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.486393] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.486457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.486656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.486733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.519689] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.519734] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.519803] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.536941] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.536988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.537029] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.537072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.537112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.537155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.537195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.537234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.537273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.537317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.537359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.537400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.537442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.537481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.537517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.537595] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.537683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.537694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.537746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.537767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.537789] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.537812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.537830] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.537917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.537947] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.537980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.538009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.538039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.538066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.538076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.538103] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.538111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.538142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.538169] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.538199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.538225] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.538257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.538284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.538313] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.538339] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.538368] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.538402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.538436] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.538532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.538562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.538589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.538617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.538643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.538671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.538704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.538734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.538765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.538791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.538818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.538848] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.538903] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.540971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.540994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.541017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.541041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.542617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.542640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.542663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.544228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.544249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.546120] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.549430] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.549481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.549512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.549553] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.549627] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.549660] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.566286] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.566335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.566400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.566599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.566678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.599630] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.599681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.599754] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.616782] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.616826] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.616942] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.617000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.617046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.617098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.617141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.617185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.617229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.617282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.617332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.617383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.617432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.617473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.617500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.617563] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.617710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.617722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.617773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.617792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.617814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.617837] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.617903] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.617939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.617969] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.618001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.618030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.618060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.618087] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.618095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.618123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.618131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.618161] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.618189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.618219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.618245] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.618278] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.618305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.618335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.618361] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.618389] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.618423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.618457] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.618555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.618583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.618611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.618637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.618665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.618692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.618723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.618754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.618786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.618811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.618839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.618894] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.618923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.620988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.621008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.621026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.621050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.622611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.622631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.622649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.624203] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.624224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.626093] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.629400] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.629450] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.629482] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.629522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.629598] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.629630] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.646258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.646307] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.646370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.646553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.646631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.679604] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.679653] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.679727] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.696758] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.696801] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.696833] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.696960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.697000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.697037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.697067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.697098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.697130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.697168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.697201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.697233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.697264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.697304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.697322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.697364] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.697460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.697472] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.697527] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.697547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.697570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.697595] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.697615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.697636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.697657] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.697677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.697703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.697729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.697754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.697760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.697785] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.697790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.697816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.697844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.697900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.697930] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.697961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.697989] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.698017] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.698044] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.698070] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.698102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.698134] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.698232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.698263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.698290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.698320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.698341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.698361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.698382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.698402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.698421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.698438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.698456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.698478] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.698498] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.700544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.700565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.700583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.700602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.702177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.702197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.702215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.703764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.703785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.705658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.708959] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.709010] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.709042] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.709083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.709158] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.709191] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.725822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.725905] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.725971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.726165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.726243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.759167] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.759214] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.759285] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.776375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.776419] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.776451] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.776488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.776520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.776554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.776584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.776612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.776643] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.776685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.776727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.776769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.776810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.776849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.776957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.777062] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.777266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.777286] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.777352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.777374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.777398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.777423] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.777443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.777465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.777486] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.777507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.777527] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.777547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.777565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.777570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.777588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.777593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.777611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.777629] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.777647] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.777664] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.777690] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.777715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.777742] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.777767] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.777794] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.777820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.777877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.777978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.778010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.778039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.778071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.778102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.778134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.778168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.778201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.778233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.778263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.778288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.778312] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.778333] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.780372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.780393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.780411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.780430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.782002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.782023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.782040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.783599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.783620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.785482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.788738] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.788782] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.788810] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.788919] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.789186] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.789216] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.805596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.805647] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.805718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.806041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.806143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.838942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.838989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.839060] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.856095] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.856138] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.856170] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.856208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.856241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.856275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.856306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.856335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.856366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.856401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.856432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.856463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.856493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.856520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.856547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.856609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.856752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.856771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.856943] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.856991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.857048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.857083] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.857111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.857144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.857176] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.857206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.857238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.857267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.857296] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.857303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.857331] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.857338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.857368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.857397] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.857425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.857443] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.857465] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.857483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.857501] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.857518] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.857535] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.857560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.857589] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.857661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.857687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.857713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.857739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.857765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.857790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.857818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.857876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.857910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.857939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.857967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.857999] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.858030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.860095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.860116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.860135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.860154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.861724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.861744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.861762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.863323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.863343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.865235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.868514] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.868558] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.868585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.868620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.868688] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.868720] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.885350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.885399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.885463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.885646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.885724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.918695] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  313.918742] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  313.918810] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.937614] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.937658] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  313.937691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  313.937729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.937762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.937796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.937825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.937912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.937969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.938034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.938081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.938126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.938418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.938446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.938472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.938531] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.938645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.938662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  313.938736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  313.938765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.938796] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  313.938829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.938924] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.938968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.939023] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  313.939052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.939083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.939110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.939139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.939148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.939176] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.939184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  313.939214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  313.939242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.939558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.939585] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  313.939612] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  313.939640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.939665] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  313.939691] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  313.939715] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  313.939744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.939775] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  313.939906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  313.939938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  313.940113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  313.940133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  313.940152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  313.940171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  313.940193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  313.940213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  313.940233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.940251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  313.940268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  313.940291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  313.940311] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  313.942351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.942371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.942389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.942408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.944068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  313.944088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.944106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.945667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.945688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  313.947564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.950909] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.950963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  313.950995] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  313.951037] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.951114] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.951148] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.967782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  313.967831] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  313.967988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  313.968264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  313.968343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.001125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.001174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.001247] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.019775] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.019819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.019932] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.019990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.020189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.020232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.020272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.020312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.020352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.020395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.020438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.020479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.020521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.020560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.020599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.020670] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.020865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.020900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.021234] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.021262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.021293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.021327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.021353] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.021382] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.021410] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.021438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.021464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.021491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.021515] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.021522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.021546] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.021552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.021579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.021603] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.021628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.021652] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.021680] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.021704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.021730] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.021753] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.021778] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.021809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.021879] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.021979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.022232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.022253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.022278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.022304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.022329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.022357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.022384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.022410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.022435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.022460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.022486] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.022509] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.024566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.024588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.024607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.024626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.026216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.026238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.026257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.027818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.027851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.029719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.033022] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.033074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.033114] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.033165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.033236] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.033257] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.049883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.049931] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.049995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.050188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.050266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.083230] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.083282] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.083355] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.100380] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.100423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.100455] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.100493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.100525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.100560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.100591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.100620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.100651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.100685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.100717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.100748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.100793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.100827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.100912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.101005] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.101207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.101233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.101345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.101381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.101418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.101458] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.101493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.101531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.101567] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.101603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.101638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.101675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.101710] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.101716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.101751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.101757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.101797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.101821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.101876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.101905] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.101939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.101967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.101995] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.102022] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.102048] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.102079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.102111] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.102211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.102242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.102274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.102304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.102333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.102364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.102398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.102421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.102442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.102460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.102478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.102500] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.102520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.104566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.104587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.104605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.104624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.106198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.106217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.106235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.107820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.107857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.109726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.113044] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.113076] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.113095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.113121] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.113179] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.113201] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.129891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.129939] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.130004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.130202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.130281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.163236] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.163282] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.163350] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.180386] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.180430] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.180462] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.180499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.180532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.180566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.180596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.180625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.180656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.180690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.180722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.180753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.180792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.180832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.180928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.181031] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.181233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.181263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.181355] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.181395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.181435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.181481] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.181520] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.181562] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.181604] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.181626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.181647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.181666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.181684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.181689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.181707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.181712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.181730] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.181748] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.181766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.181784] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.181806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.181857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.181886] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.181912] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.181939] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.181971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.182003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.182103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.182135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.182166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.182195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.182225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.182256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.182290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.182318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.182339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.182357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.182383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.182410] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.182436] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.184487] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.184508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.184526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.184545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.186120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.186143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.186165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.187725] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.187748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.189612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.192878] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.192908] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.192931] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.192962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.193022] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.193043] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.209725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.209775] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.209923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.210172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.210249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.243072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.243118] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.243186] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.260350] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.260393] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.260425] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.260463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.260497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.260532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.260570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.260610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.260650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.260694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.260735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.260777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.260818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.260927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.260975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.261079] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.261230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.261249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.261336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.261369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.261407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.261447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.261467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.261489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.261510] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.261531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.261550] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.261569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.261588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.261593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.261611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.261615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.261635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.261653] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.261671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.261688] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.261710] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.261728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.261747] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.261764] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.261782] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.261803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.261857] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.261955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.261984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.262012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.262042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.262070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.262098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.262131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.262152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.262172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.262190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.262207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.262229] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.262255] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.264320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.264341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.264359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.264378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.265969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.265990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.266009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.267560] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.267582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.269458] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.272742] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.272774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.272793] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.272882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.272956] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.272988] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.289571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.289620] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.289685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.289999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.290108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.322917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.322969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.323042] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.340068] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.340111] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.340143] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.340181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.340215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.340250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.340280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.340309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.340340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.340375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.340407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.340439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.340470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.340498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.340525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.340588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.340730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.340748] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.340991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.341042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.341096] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.341153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.341200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.341251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.341305] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.341346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.341386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.341425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.341463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.341473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.341509] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.341518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.341556] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.341594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.341632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.341669] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.341711] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.341749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.341787] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.341857] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.341896] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.341942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.341988] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.342117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.342156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.342192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.342229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.342267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.342312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.342346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.342378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.342410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.342439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.342465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.342497] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.342528] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.344598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.344619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.344637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.344656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.346231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.346251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.346269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.347819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.347866] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.349735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.353077] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.353129] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.353161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.353211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.353292] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.353332] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.369951] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.370004] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.370074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.370279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.370361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.403296] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.403343] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.403412] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.420450] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.420493] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.420526] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.420564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.420597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.420632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.420663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.420691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.420723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.420757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.420789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.420901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.420950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.420993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.421034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.421133] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.421288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.421307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.421368] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.421395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.421422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.421451] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.421477] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.421504] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.421529] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.421555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.421580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.421606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.421631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.421637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.421662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.421667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.421690] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.421716] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.421742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.421767] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.421794] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.421849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.421881] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.421910] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.421938] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.421971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.422003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.422102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.422134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.422165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.422195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.422225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.422257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.422291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.422322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.422344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.422362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.422381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.422407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.422433] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.424491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.424513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.424535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.424559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.426142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.426162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.426180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.427734] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.427755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.429633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.432980] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.433032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.433064] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.433106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.433183] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.433216] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.449888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.449937] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.450002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.450188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.450265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.483194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.483240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.483310] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.500342] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.500389] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.500429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.500473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.500513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.500556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.500595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.500635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.500674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.500717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.500759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.500801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.500926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.500973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.501019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.501121] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.501247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.501260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.501316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.501338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.501362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.501387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.501407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.501429] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.501450] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.501471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.501491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.501510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.501528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.501534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.501551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.501555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.501574] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.501592] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.501610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.501627] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.501648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.501666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.501684] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.501702] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.501719] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.501740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.501764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.501870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.501898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.501926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.501954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.501981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.502008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.502039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.502069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.502101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.502129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.502155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.502186] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.502217] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.504256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.504277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.504295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.504314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.505908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.505928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.505946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.507505] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.507525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.509398] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.512675] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.512722] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.512752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.512791] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.512939] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.512970] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.529511] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.529560] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.529629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.529912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.530031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.562858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.562904] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.562972] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.581319] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.581346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.581365] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.581388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.581407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.581428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.581445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.581462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.581481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.581501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.581520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.581538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.581556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.581572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.581588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.581628] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.581721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.581733] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.581783] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.581865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.581899] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.581937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.581964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.581998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.582028] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.582060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.582088] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.582118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.582145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.582154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.582181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.582188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.582218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.582245] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.582275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.582300] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.582331] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.582358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.582386] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.582412] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.582440] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.582471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.582504] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.582604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.582632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.582660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.582686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.582713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.582740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.582771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.582803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.582859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.582885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.582914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.582949] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.582980] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.585054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.585075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.585094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.585113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.586684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.586704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.586726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.588294] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.588315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.590218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.593455] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.593489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.593512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.593543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.593607] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.593628] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.610333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.610382] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.610446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.610647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.610725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.643678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.643725] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.643793] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.660886] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.660928] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.660960] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.660998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.661031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.661065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.661095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.661124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.661155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.661190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.661222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.661253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.661283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.661310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.661337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.661400] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.661530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.661548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.661636] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.661676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.661716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.661760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.661798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.661918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.661951] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.661984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.662013] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.662043] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.662070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.662079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.662106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.662114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.662144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.662172] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.662201] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.662227] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.662261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.662288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.662317] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.662344] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.662373] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.662406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.662441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.662542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.662569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.662599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.662626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.662653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.662680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.662711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.662742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.662774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.662803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.662854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.662886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.662916] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.664987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.665008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.665026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.665045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.666616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.666636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.666658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.668223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.668244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.670115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.673391] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.673436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.673464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.673501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.673569] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.673603] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.690228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.690277] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.690342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.690528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.690606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.723575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.723621] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.723689] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.740726] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.740768] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.740800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.740925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.740967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.741005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.741035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.741065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.741097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.741133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.741165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.741197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.741228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.741257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.741284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.741348] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.741492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.741510] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.741597] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.741637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.741679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.741725] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.741764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.741812] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.741868] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.741898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.741928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.741955] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.741983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.741990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.742017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.742025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.742053] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.742080] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.742107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.742133] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.742164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.742190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.742216] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.742243] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.742269] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.742300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.742333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.742430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.742451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.742470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.742489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.742506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.742526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.742547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.742567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.742587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.742604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.742622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.742645] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.742665] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.744707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.744728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.744747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.744766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.746384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.746404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.746422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.747987] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.748012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.749874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.753147] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.753181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.753204] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.753235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.753298] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.753323] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.769989] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.770038] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.770103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.770300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.770378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.803335] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.803382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.803451] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.820485] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.820532] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.820573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.820617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.820657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.820700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.820740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.820779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.820880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.820941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.820995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.821043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.821095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.821130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.821159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.821223] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.821368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.821388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.821471] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.821511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.821551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.821603] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.821626] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.821649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.821671] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.821691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.821710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.821728] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.821746] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.821751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.821769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.821774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.821833] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.821860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.821887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.821913] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.821944] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.821970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.821996] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.822022] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.822049] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.822080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.822112] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.822209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.822230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.822248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.822266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.822283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.822302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.822324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.822343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.822363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.822380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.822404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.822431] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.822455] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.824502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.824523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.824542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.824561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.826136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.826157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.826180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.827740] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.827763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.829664] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.832936] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.832970] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.832991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.833048] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.833273] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.833294] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.849783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.849866] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.849931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.850129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.850207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.883165] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.883212] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.883283] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.900337] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.900385] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.900425] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.900470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.900509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.900552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.900592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.900631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.900670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.900713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.900755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.900797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.900915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.900963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.901013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.901113] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.901526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.901538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.901593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.901613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.901635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.901658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.901677] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.901696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.901716] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.901735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.901753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.901770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.901834] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.901846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.901875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.901883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.901914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.901941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.901971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.901997] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.902030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.902057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.902087] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.902114] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.902142] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.902171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.902205] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.902574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.902602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.902629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.902655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.902680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.902706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.902736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.902766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.902832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.902864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.902891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.902926] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.902955] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.905213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.905234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.905252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.905271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.906896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.906917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.906935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.908484] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.908505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.910381] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.913665] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.913698] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.913721] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.913752] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.913870] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.913903] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.930495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.930544] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.930608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.931004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.931092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.963842] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  314.963891] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  314.963967] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.980999] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.981043] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  314.981075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  314.981113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.981145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.981179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.981210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.981239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.981270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  314.981305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.981337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.981367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.981397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.981425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.981452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.981515] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  314.981656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  314.981675] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  314.981757] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  314.981788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.981907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  314.981962] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.982006] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.982053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.982099] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  314.982144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.982188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.982231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.982274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.982283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.982308] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.982316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  314.982346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  314.982374] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.982401] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.982427] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  314.982460] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  314.982489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.982518] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  314.982547] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  314.982576] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  314.982609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.982644] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  314.982729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  314.982759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  314.982779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  314.982831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  314.982859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  314.982887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  314.982919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  314.982949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  314.982979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  314.983008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  314.983035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  314.983071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  314.983104] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  314.985172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.985193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.985215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.985239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.986834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  314.986854] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.986873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.988429] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.988450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  314.990329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.993563] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.993594] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  314.993612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  314.993638] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.993697] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.993718] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.010402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.010450] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.010514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.010711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.010788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.043739] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.043785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.044171] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.062777] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.062853] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.062885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.062922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.062955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.062989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.063019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.063048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.063080] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.063124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.063154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.063192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.063231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.063267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.063303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.063371] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.063508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.063526] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.063613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.063651] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.063688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.063730] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.063766] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.063862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.063912] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.063955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.063998] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.064039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.064078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.064090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.064134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.064143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.064176] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.064207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.064239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.064270] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.064306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.064337] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.064369] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.064400] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.064431] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.064469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.064507] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.064624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.064659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.064692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.064726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.064752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.064775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.064849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.064877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.064900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.064922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.064943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.064970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.064994] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.067039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.067060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.067083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.067107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.068680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.068701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.068720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.070309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.070330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.072313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.075601] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.075645] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.075673] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.075708] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.075773] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.075876] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.092486] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.092535] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.092599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.092875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.092996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.125849] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.125896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.125965] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.142982] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.143024] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.143057] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.143095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.143128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.143163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.143193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.143222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.143254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.143289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.143321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.143353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.143383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.143411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.143439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.143501] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.143645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.143663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.143745] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.143775] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.143894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.143961] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.143990] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.144023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.144053] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.144084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.144113] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.144142] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.144169] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.144178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.144205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.144213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.144242] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.144269] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.144298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.144324] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.144357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.144384] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.144412] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.144438] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.144466] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.144499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.144533] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.144632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.144660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.144688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.144714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.144743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.144770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.144826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.144859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.144892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.144919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.144947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.144979] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.145009] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.147086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.147110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.147133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.147157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.148734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.148755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.148773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.150360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.150381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.152271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.155560] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.155610] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.155642] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.155683] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.155758] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.155859] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.172438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.172487] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.172551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.172736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.172909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.205781] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.205859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.205929] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.222957] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.223000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.223032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.223070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.223109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.223152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.223192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.223232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.223271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.223315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.223356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.223398] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.223439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.223478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.223516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.223589] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.223711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.223722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.223775] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.223862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.223895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.223933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.223962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.223997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.224028] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.224060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.224089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.224119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.224146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.224155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.224184] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.224192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.224222] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.224249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.224278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.224304] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.224335] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.224362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.224391] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.224418] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.224445] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.224477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.224510] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.224607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.224636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.224663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.224691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.224716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.224746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.224779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.224835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.224868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.224895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.224925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.224960] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.224989] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.227060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.227081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.227099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.227118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.228690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.228710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.228728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.230305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.230325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.232305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.235582] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.235631] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.235663] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.235704] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.235777] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.235888] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.252419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.252468] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.252532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.252730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.252904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.285765] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.285844] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.285913] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.302922] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.302966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.302999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.303037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.303069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.303104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.303134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.303163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.303193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.303228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.303260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.303291] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.303322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.303349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.303376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.303439] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.303587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.303603] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.303672] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.303698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.303730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.303768] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.303876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.303924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.303970] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.304012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.304054] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.304094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.304134] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.304145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.304182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.304192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.304232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.304272] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.304311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.304350] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.304394] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.304433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.304473] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.304512] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.304548] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.304595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.304629] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.304728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.304759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.304812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.304843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.304871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.304902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.304936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.304968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.305000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.305029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.305054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.305087] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.305118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.307188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.307209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.307227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.307246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.308816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.308836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.308854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.310425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.310448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.312328] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.315660] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.315712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.315745] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.315833] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.316072] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.316092] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.332492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.332543] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.332614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.332918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.333035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.365835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.365880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.365947] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.382987] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.383030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.383062] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.383101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.383134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.383168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.383198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.383227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.383258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.383292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.383324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.383354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.383394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.383431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.383455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.383508] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.383631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.383646] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.383716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.383741] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.383770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.383882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.383925] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.383970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.384015] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.384058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.384100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.384141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.384180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.384192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.384230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.384240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.384280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.384319] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.384359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.384398] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.384446] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.384476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.384506] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.384535] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.384565] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.384598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.384632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.384733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.384764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.384817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.384849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.384877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.384909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.384942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.384974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.385006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.385035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.385064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.385095] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.385127] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.387197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.387218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.387237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.387257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.388827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.388847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.388865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.390434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.390455] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.392332] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.395605] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.395636] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.395655] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.395680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.395737] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.395762] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.412446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.412494] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.412559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.412830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.413165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.445820] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.445871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.445945] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.463116] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.463159] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.463191] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.463229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.463262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.463304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.463344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.463384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.463423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.463467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.463509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.463550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.463592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.463630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.463669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.463742] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.463988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.464007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.464096] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.464133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.464171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.464210] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.464241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.464275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.464297] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.464323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.464349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.464375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.464400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.464406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.464431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.464436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.464462] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.464487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.464514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.464539] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.464564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.464590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.464615] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.464641] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.464666] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.464693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.464720] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.464824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.464856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.464885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.464913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.464940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.464970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.465002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.465033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.465064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.465092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.465118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.465150] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.465181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.467266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.467287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.467305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.467324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.468991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.469014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.469037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.470597] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.470618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.472490] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.475758] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.475829] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.475858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.475895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.475963] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.475992] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.492655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.492703] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.492768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.493089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.493181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.526000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.526048] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.526116] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.544835] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.544878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.544911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.544948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.544981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.545014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.545044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.545072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.545103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.545138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.545170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.545200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.545230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.545258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.545295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.545368] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.545511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.545530] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.545622] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.545663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.545703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.545747] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.545846] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.545902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.545951] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.546007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.546036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.546063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.546089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.546097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.546123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.546131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.546158] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.546184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.546211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.546237] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.546267] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.546294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.546321] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.546347] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.546373] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.546406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.546642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.546709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.546730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.546750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.546799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.546826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.546856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.546890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.546983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.547004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.547023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.547042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.547064] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.547085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.549121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.549142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.549160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.549179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.550757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.550795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.550818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.552385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.552407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.554314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.557600] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.557654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.557694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.557745] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.557924] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.557976] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.574481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.574530] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.574595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.574893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.574982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.607840] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.607886] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.607958] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.625007] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.625050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.625082] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.625120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.625153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.625187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.625217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.625247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.625279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.625313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.625346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.625376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.625407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.625434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.625461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.625523] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.625665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.625684] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.625767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.625856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.625888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.625925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.625954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.625984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.626014] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.626043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.626074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.626103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.626131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.626139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.626165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.626173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.626204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.626233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.626263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.626291] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.626323] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.626352] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.626382] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.626411] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.626437] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.626460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.626482] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.626548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.626568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.626586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.626604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.626622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.626641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.626662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.626682] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.626701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.626719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.626736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.626788] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.626818] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.628880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.628903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.628926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.628950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.630522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.630543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.630562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.632126] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.632148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.634017] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.637302] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.637351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.637386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.637432] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.637519] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.637564] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.654169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.654213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.654272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.654466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.654544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.687543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.687589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.687659] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.704707] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.704750] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.704867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.704925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.704971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.705022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.705064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.705108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.705152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.705205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.705255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.705305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.705353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.705393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.705436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.705532] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.705703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.705717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.705825] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.705856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.705892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.705929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.705958] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.705991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.706022] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  315.706054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.706082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.706111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.706138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.706146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.706173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.706180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.706208] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.706234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.706262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.706287] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  315.706319] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.706345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.706373] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  315.706399] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  315.706426] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  315.706455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.706487] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  315.706585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.706614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.706641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.706669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.706695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.706724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.706757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.706811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.706843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.706870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.706900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.706932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  315.706963] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.709025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.709046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.709064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.709082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.710653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.710673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.710692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.712271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.712291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.714203] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.717541] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.717593] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.717625] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  315.717667] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.717761] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.717882] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.734416] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.734465] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.734530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.734712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.734874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.767765] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  315.767886] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.767973] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.784975] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.785018] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  315.785050] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.785088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.785121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.785156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.785186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.785216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.785247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.785281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.785313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.785344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.785375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.785409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.785433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.785490] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  315.785865] [drm:drm_mode_addfb2] [FB:58]
>[  315.786166] [drm:drm_mode_addfb2] [FB:78]
>[  315.815428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  315.815530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.815600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  315.815667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.815679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.815742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.815826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.815861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.815898] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.815927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.815962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.815997] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.816029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.816060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.816090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.816120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.816127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.816151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.816156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.816176] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.816194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.816214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.816231] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.816254] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.816272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.816291] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  315.816309] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.816327] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.816348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.816373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.819745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.819794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.819813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.819831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.819848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.819867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.819888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.819907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.819926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.819943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.819960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.819981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.820000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.822062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.822084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.822106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.822131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.823695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.823716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.823735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.825332] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.825353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.827225] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.830514] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.830560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.830587] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.830623] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.847378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.847424] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.847487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.864062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.864082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.880909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.880989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.897422] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.897466] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.897535] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.914706] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.914743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.914866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.914913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.914967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.915010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.915055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.915099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.915152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.915202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.915250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.915303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.915331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.915358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.915421] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.915553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.915570] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.915653] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.915676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.915697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.915720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.915738] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.915807] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.915843] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.915872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.915903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.915932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.915961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.915970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.915998] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.916006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.916036] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.916063] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.916094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.916120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.916154] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.916181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.916211] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  315.916239] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.916267] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.916301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.916336] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.916420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.916448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.916476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.916502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.916531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.916557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.916588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.916619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.916650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.916675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.916702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.916732] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.916791] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.918861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.918882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.918901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.918920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.920495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.920515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.920532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.922101] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.922122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.923999] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.927321] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.927374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.927406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.927447] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.944161] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.944211] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.944276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.944443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.944520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.960836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.960882] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  315.960953] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.977985] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  315.978022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  315.978061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.978094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.978128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.978158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.978186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.978218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  315.978252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.978284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.978315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.978345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.978373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.978410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.978483] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  315.978629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  315.978649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  315.978722] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  315.978741] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.978828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  315.978862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.978891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.978922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.978951] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  315.978980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.979008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.979035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.979061] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.979069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.979095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.979102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  315.979131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  315.979160] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.979187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.979213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.979245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  315.979274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.979303] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  315.979331] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  315.979360] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  315.979393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.979428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  315.979523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  315.979544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  315.979563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  315.979581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  315.979599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  315.979619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  315.979640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  315.979659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  315.979679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  315.979697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  315.979714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  315.979737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  315.979796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  315.981861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.981882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.981900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.981919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.983482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  315.983502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.983520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.985084] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.985107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  315.986980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.990278] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.990326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  315.990355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.990395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.007142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.007195] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.007266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.007465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.007548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.023818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.023868] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.023941] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.040966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.041003] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.041043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.041076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.041110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.041140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.041168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.041199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.041234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.041275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.041317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.041359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.041398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.041435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.041507] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.041653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.041671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.041844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.041893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.041946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.042001] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.042046] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.042095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.042143] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.042195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.042237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.042276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.042312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.042322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.042357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.042367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.042407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.042436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.042460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.042484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.042516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.042549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.042584] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.042618] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.042652] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.042687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.042724] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.042871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.042901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.042928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.042954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.042979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.043006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.043035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.043062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.043088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.043113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.043137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.043172] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.043211] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.045252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.045273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.045292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.045311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.046989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.047011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.047029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.048592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.048616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.050491] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.053613] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.053657] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.053685] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.053719] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.070454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.070506] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.070577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.071049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.071131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.087160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.087208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.087283] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.104341] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.104379] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.104418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.104450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.104484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.104513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.104541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.104572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.104606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.104638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.104668] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.104698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.104726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.104830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.104930] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.105400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.105418] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.105505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.105538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.105574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.105614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.105632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.105652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.105672] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.105690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.105708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.105724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.105788] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.105799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.105827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.105835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.105865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.105892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.105921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.105948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.105980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.106006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.106036] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.106062] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.106091] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.106124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.106441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.106546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.106573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.106600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.106625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.106652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.106678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.106707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.106748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.106807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.106835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.106864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.106900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.106929] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.109223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.109246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.109269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.109293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.110966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.110988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.111006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.112566] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.112586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.114459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.117745] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.117824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.117847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.117878] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.134621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.134671] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.134737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.135058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.135152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.151316] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.151362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.151434] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.168475] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.168512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.168552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.168584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.168619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.168648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.168677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.168708] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.168743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.168857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.168909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.168962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.169006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.169035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.169332] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.169423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.169435] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.169491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.169515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.169539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.169565] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.169588] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.169612] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.169635] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.169659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.169682] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.169705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.169728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.169772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.169811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.169819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.169852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.169884] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.169914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.169942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.169976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.170004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.170034] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.170061] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.170089] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.170124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.170159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.170496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.170525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.170554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.170581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.170609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.170637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.170669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.170702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.170734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.170789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.170815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.170849] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.170878] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.173172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.173193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.173212] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.173230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.175951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.175978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.176001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.177576] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.177600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.179468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.182774] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.182824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.182857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.182898] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.199609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.199657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.199719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.200137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.200214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.216304] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.216353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.216439] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.233457] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.233494] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.233534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.233567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.233601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.233631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.233660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.233691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.233726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.233836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.233888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.233941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.233983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.234029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.234451] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.234538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.234549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.234602] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.234621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.234642] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.234665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.234683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.234702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.234722] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.234787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.234822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.234849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.234879] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.234887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.234916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.234924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.234954] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.234981] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.235010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.235037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.235069] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.235283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.235313] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.235340] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.235368] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.235398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.235431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.235528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.235559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.235586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.235614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.235640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.235668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.235701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.235732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.235786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.235813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.235843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.235878] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.235907] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.238224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.238245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.238263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.238282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.239958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.239979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.239997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.241545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.241566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.243439] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.246691] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.246721] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.246794] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.246838] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.263548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.263598] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.263664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.264081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.264161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.280228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.280275] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.280361] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.297377] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.297415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.297455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.297488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.297523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.297553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.297582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.297614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.297648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.297680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.297712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.297827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.297866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.297897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.297961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.298111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.298131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.298218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.298247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.298280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.298324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.298349] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.298378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.298405] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.298432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.298457] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.298484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.298508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.298514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.298539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.298545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.298571] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.298595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.298621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.298644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.298673] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.298697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.298723] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.298794] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.298823] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.298855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.298890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.298988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.299021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.299048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.299077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.299103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.299132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.299163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.299195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.299226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.299251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.299278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.299309] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.299340] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.301409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.301431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.301449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.301469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.303046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.303066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.303084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.304633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.304655] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.306520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.309840] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.309894] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.309934] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.309985] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.326678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.326726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.326886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.327077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.327153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.343356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.343400] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.343468] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.360493] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.360536] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.360580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.360621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.360664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.360704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.360744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.360877] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.360938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.360994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.361044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.361096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.361141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.361186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.361285] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.361476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.361494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.361566] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.361590] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.361614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.361640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.361663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.361687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.361710] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.361786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.361822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.361856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.361887] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.361897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.361927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.361934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.361966] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.361997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.362029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.362059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.362090] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.362120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.362151] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.362181] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.362206] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.362239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.362273] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.362375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.362407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.362434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.362463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.362492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.362523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.362556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.362588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.362621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.362650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.362679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.362712] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.362770] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.364832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.364852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.364871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.364890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.366460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.366480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.366498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.368064] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.368086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.369958] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.373296] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.373348] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.373380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.373422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.390172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.390221] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.390286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.390483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.390562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.406848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.406894] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.406961] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.423994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.424032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.424070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.424103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.424137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.424167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.424195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.424227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.424261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.424293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.424323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.424354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.424391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.424430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.424503] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.424649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.424668] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.424831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.424861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.424895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.424932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.424961] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.424996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.425021] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.425041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.425061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.425081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.425098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.425104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.425121] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.425125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.425145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.425162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.425181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.425198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.425220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.425237] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.425255] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.425273] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.425290] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.425311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.425335] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.425400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.425420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.425438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.425456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.425473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.425492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.425513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.425532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.425551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.425569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.425587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.425609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.425629] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.427676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.427697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.427715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.427795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.429356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.429376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.429394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.430958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.430979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.432851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.436143] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.436186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.436213] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.436248] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.453004] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.453054] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.453120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.453320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.453398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.469688] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.469735] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.470121] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.488689] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.488726] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.488856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.488909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.488965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.489014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.489046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.489079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.489116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.489148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.489179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.489210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.489239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.489257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.489299] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.489395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.489408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.489462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.489483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.489506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.489530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.489549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.489571] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.489592] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.489612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.489631] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.489650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.489668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.489673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.489690] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.489695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.489714] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.489775] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.489802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.489829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.489858] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.489884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.489910] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.489937] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.489963] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.489993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.490026] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.490125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.490154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.490181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.490211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.490240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.490271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.490304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.490337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.490369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.490398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.490426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.490460] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.490492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.492541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.492562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.492580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.492599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.494173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.494193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.494210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.495766] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.495787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.498741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.502109] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.502161] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.502193] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.502234] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.518977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.519027] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.519092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.519271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.519349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.535652] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.535699] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.536085] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.554688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.554726] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.554851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.554903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.554959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.555008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.555055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.555093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.555130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.555164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.555195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.555226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.555255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.555283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.555346] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.555476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.555495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.555578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.555610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.555644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.555683] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.555714] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.555800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.555831] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.555860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.555889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.555916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.555943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.555952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.555978] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.555985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.556012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.556039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.556065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.556091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.556121] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.556147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.556173] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.556199] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.556226] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.556256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.556290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.556390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.556422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.556452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.556483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.556512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.556543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.556577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.556609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.556635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.556653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.556671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.556693] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.556715] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.558804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.558825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.558843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.558861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.560441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.560461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.560479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.562033] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.562054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.563914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.567142] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.567175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.567198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.567229] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.583975] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.584025] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.584090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.584289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.584367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.600683] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.600729] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.600892] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.619697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.619770] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.619810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.619843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.619878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.619908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.619937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.619969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.620004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.620036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.620068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.620099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.620127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.620154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.620216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.620326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.620338] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.620388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.620406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.620427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.620449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.620468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.620487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.620505] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.620523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.620540] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.620557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.620573] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.620577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.620593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.620597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.620613] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.620629] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.620645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.620661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.620680] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.620696] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.620763] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.620795] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.620826] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.620860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.620895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.620995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.621026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.621056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.621086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.621116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.621147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.621181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.621213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.621244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.621273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.621302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.621335] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.621367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.623444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.623466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.623485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.623504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.625085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.625105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.625124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.626722] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.626761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.628627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.631977] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.632030] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.632062] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.632104] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.648832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.648879] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.648942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.649139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.649214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.665516] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.665567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.665655] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.682636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.682674] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.682713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.682827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.682884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.682927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.682972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.683016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.683071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.683121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.683169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.683218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.683258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.683302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.683399] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.683614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.683633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.683701] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.683767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.683804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.683842] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.683871] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.683904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.683934] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.683966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.683995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.684025] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.684052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.684061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.684088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.684096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.684126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.684152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.684179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.684206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.684238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.684263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.684291] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.684316] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.684344] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.684375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.684409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.684508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.684535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.684564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.684590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.684618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.684645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.684676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.684708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.684763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.684790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.684819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.684854] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.684883] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.686948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.686969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.686991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.687015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.688588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.688608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.688626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.690190] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.690210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.692105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.695430] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.695486] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.695526] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.695577] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.712267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.712317] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.712382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.712580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.712658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.728942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.728989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.729074] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.746091] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.746128] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.746168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.746201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.746236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.746266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.746295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.746326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.746361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.746393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.746423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.746454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.746481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.746508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.746570] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.746761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.746792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.746927] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.746972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.747023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.747076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.747103] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.747135] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.747164] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.747193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.747221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.747250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.747276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.747283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.747309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.747316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.747344] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.747370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.747397] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.747422] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.747453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.747478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.747506] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.747531] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.747558] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.747586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.747619] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.747714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.747769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.747798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.747828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.747856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.747888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.747922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.747955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.747987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.748013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.748042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.748077] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.748105] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.750196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.750217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.750235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.750254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.751854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.751876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.751894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.753473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.753494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.755370] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.758662] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.758712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.758823] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.758892] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.775540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.775592] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.775664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.776011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.776129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.792233] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.792280] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.792351] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.809385] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.809422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.809461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.809493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.809527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.809556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.809584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.809615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.809650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.809682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.809713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.809824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.809866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.809913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.810012] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.810457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.810469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.810522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.810542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.810566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.810593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.810615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.810639] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.810663] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.810687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.810710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.810780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.810816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.810823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.810854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.810863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.810894] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.810922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.810952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.810979] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.811011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.811038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.811068] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.811095] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.811124] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.811444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.811479] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.811585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.811615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.811640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.811666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.811690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.811757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.811794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.811826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.811859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.812070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.812088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.812110] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.812129] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.814203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.814225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.814243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.814262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.815947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.815967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.815985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.817532] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.817553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.821641] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.824941] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.824987] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.825020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.825064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.841783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.841830] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.841893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.842089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.842162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.858510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.858557] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.858628] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.875671] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.875709] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.875840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.875892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.875949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.875997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.876036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.876076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.876123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.876167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.876210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.876249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.876289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.876329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.876404] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.876558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.876578] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.876671] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.876712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.876802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.876858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.876905] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.876947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.876987] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.877026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.877064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.877101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.877136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.877146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.877180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.877190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.877226] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.877261] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.877299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.877336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.877377] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.877417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.877456] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.877496] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.877535] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.877578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.877623] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.877766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.877808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.877845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.877891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.877918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.877946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.877978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.878011] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.878041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.878071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.878100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.878133] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.878165] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.880235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.880257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.880276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.880296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.881907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.881928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.881950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.883510] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.883531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.885394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.888709] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.888792] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.888825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.888867] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.905607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.905657] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.905809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.906093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.906182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.922305] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.922350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.922436] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.939460] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  316.939498] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  316.939541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.939581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.939625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.939665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.939703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.939823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.939883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.939938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.939992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.940044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.940088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.940119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.940185] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.940313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.940331] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  316.940412] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  316.940433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.940456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  316.940481] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.940501] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.940522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.940544] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  316.940568] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  316.940595] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.940621] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.940646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.940652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.940677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.940681] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  316.940710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  316.940770] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.940799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.940828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.940858] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  316.940886] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.940914] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  316.940941] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  316.940967] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  316.940998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.941030] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  316.941129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.941160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  316.941190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  316.941221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  316.941251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  316.941282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  316.941315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  316.941348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  316.941380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.941404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  316.941422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  316.941445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  316.941465] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  316.943506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.943529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.943552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.943576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.945142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  316.945162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  316.945181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.946761] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.946783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  316.948643] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.951940] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  316.951984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  316.952013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  316.952050] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.968804] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  316.968851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  316.968914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  316.969120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  316.969217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.985513] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.985559] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  316.985631] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.002691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.002766] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.002805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.002838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.002873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.002902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.002930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.002962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.002996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.003028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.003058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.003098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.003137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.003175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.003248] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.003395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.003414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.003505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.003545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.003586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.003630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.003669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.003709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.003802] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.003834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.003863] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.003891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.003918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.003926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.003952] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.003959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.003987] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.004013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.004040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.004067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.004097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.004124] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.004151] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.004177] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.004204] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.004235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.004267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.004366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.004397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.004427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.004458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.004488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.004519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.004552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.004584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.004617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.004644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.004663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.004685] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.004737] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.006798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.006821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.006844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.006868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.008429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.008450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.008468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.010031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.010052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.011922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.015152] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.015183] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.015202] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.015226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.031983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.032034] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.032100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.032295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.032374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.048658] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.048705] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.048866] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.066681] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.066752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.066795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.066835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.066879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.066918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.066957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.066996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.067040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.067082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.067124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.067165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.067204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.067242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.067323] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.067411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.067423] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.067476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.067496] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.067518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.067540] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.067558] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.067578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.067598] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.067616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.067639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.067662] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.067685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.067728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.067763] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.067772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.067805] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.067836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.067868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.067896] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.067929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.067956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.067986] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.068013] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.068042] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.068077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.068112] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.068197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.068224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.068255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.068283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.068311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.068338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.068370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.068401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.068433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.068458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.068486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.068516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.068546] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.070672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.070695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.070777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.070806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.072370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.072392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.072411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.073982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.074004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.075878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.079213] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.079265] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.079304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.079355] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.096099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.096149] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.096215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.096428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.096511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.112790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.112837] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.112908] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.129948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.129985] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.130025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.130057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.130091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.130120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.130147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.130178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.130212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.130244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.130275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.130315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.130354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.130393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.130465] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.130595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.130614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.130712] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.130801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.130835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.130873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.130902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.130937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.130968] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.131000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.131030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.131061] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.131088] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.131097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.131124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.131132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.131162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.131189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.131217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.131243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.131276] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.131303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.131332] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.131358] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.131385] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.131414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.131447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.131548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.131576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.131605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.131631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.131658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.131685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.131742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.131776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.131810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.131837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.131866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.131896] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.131927] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.134001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.134022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.134040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.134059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.135629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.135649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.135670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.137253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.137274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.139163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.142516] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.142569] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.142601] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.142643] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.159376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.159429] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.159500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.159674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.159861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.176057] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.176102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.176170] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.193254] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.193291] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.193330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.193363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.193397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.193425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.193453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.193483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.193518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.193550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.193580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.193611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.193638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.193665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.193821] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.194051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.194081] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.194183] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.194214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.194245] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.194280] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.194308] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.194339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.194369] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.194398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.194426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.194454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.194479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.194486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.194513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.194519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.194549] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.194575] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.194603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.194628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.194659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.194685] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.194739] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.194766] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.194796] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.194826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.194860] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.194961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.194989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.195017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.195043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.195070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.195097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.195128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.195160] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.195191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.195217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.195244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.195274] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.195304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.197377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.197399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.197418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.197437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.199008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.199028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.199046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.200598] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.200619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.202487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.205837] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.205890] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.205922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.205963] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.222706] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.222789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.222855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.223055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.223134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.239399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.239445] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.239517] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.256533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.256571] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.256615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.256655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.256698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.256823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.256868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.256904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.256941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.256975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.257006] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.257037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.257064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.257092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.257156] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.257299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.257318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.257401] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.257432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.257468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.257506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.257545] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.257587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.257627] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.257667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.257688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.257738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.257765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.257774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.257801] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.257808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.257836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.257862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.257889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.257916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.257946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.257973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.258000] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.258026] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.258052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.258084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.258116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.258212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.258233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.258252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.258271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.258288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.258309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.258330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.258350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.258370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.258388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.258405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.258428] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.258449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.260513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.260535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.260554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.260575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.262154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.262174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.262196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.263793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.263814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.265688] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.268979] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.269012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.269036] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.269067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.285815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.285868] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.285939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.286172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.286265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.302513] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.302558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.302644] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.319641] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.319679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.319801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.319849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.319902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.319945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.319991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.320036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.320089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.320145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.320184] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.320224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.320256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.320291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.320369] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.320543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.320558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.320626] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.320651] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.320680] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.320760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.320799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.320840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.320878] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.320918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.320954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.320991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.321025] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.321036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.321070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.321079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.321118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.321156] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.321185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.321212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.321244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.321271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.321300] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.321327] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.321354] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.321383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.321416] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.321514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.321543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.321570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.321598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.321624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.321654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.321687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.321803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.321834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.321859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.321887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.321920] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.321948] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.324014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.324036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.324058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.324083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.325688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.325726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.325745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.327310] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.327331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.329215] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.332433] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.332464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.332483] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.332508] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.349275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.349325] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.349390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.349593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.349693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.365974] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.366019] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.366103] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.383106] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.383144] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.383183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.383217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.383252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.383282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.383312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.383343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.383378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.383410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.383441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.383471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.383499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.383526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.383584] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.383726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.383746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.383834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.383868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.383903] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.383940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.383971] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.384001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.384024] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.384045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.384064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.384084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.384102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.384108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.384125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.384129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.384155] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.384181] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.384207] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.384233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.384259] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.384284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.384309] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.384336] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.384361] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.384389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.384416] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.384489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.384515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.384540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.384566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.384592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.384618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.384646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.384672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.384730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.384760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.384789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.384822] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.384852] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.386919] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.386940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.386959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.386978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.388538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.388562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.388584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.390150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.390171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.392043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.395365] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.395417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.395450] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.395491] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.412206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.412256] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.412323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.412551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.412644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.428904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.428949] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.429036] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.446042] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.446079] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.446119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.446152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.446186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.446216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.446245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.446277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.446311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.446343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.446374] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.446413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.446452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.446490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.446562] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.446793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.446823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.446966] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.447019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.447073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.447111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.447141] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.447165] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.447188] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.447209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.447229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.447248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.447266] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.447271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.447289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.447293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.447312] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.447330] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.447348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.447365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.447386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.447405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.447423] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.447441] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.447459] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.447480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.447503] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.447569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.447589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.447608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.447627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.447645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.447664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.447716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.447747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.447777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.447804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.447831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.447863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.447892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.449956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.449977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.449995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.450015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.451573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.451593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.451611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.453165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.453189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.455091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.458396] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.458441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.458468] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.458503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.475262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.475314] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.475385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.475594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.475677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.491954] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.492001] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.492073] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.509096] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.509133] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.509173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.509206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.509240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.509270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.509298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.509330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.509364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.509396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.509427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.509465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.509490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.509514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.509570] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.509777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.509804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.509903] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.509939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.509976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.510016] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.510051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.510088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.510124] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.510160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.510196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.510232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.510267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.510275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.510309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.510316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.510352] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.510386] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.510422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.510457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.510493] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.510516] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.510537] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.510557] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.510576] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.510598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.510621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.510719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.510749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.510777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.510805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.510832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.510860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.510892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.510922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.510951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.510978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.511004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.511035] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.511064] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.513130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.513151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.513170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.513188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.514782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.514801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.514819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.516375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.516395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.518275] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.521570] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.521620] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.521652] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.521753] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.538442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.538493] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.538558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.538855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.538975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.555138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.555184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.555255] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.573772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.573809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.573848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.573880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.573914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.573953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.573993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.574032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.574076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.574118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.574159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.574201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.574239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.574276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.574349] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.574483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.574501] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.574593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.574633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.574673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.574774] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.574832] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.574881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.574935] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.574984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.575037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.575065] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.575094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.575103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.575131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.575139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.575169] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.575196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.575226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.575252] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.575284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.575311] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.575342] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.575369] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.575397] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.575430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.575464] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.575548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.575575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.575603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.575629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.575657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.575709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.575740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.575771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.575802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.575829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.575858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.575893] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.575921] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.577991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.578011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.578030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.578048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.579613] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.579633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.579651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.581253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.581274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.583194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.586482] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.586529] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.586562] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.586606] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.603357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.603406] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.603471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.603763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.604064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.620065] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.620112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.620184] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.637227] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.637269] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.637314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.637354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.637397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.637437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.637475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.637515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.637558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.637600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.637642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.637684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.637806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.637853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.637957] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.638106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.638126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.638212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.638248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.638283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.638324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.638355] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.638389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.638429] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.638454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.638480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.638506] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.638531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.638537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.638562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.638567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.638593] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.638618] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.638645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.638670] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.638724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.638755] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.638786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.638814] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.638841] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.638874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.638906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.638988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.639017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.639037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.639056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.639075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.639094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.639116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.639142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.639170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.639195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.639221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.639248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.639274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.641331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.641352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.641371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.641390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.642977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.642999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.643018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.644579] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.644600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.646473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.649737] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.649769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.649789] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.649814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.666584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.666634] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.666778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.667017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.667094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.683261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.683308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.683395] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.700411] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.700449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.700488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.700521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.700556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.700586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.700624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.700664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.700792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.700853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.700898] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.700941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.700979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.701018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.701089] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.701213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.701229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.701300] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.701327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.701356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.701389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.701416] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.701443] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.701471] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.701497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.701523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.701547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.701572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.701578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.701600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.701608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.701631] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.701654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.701723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.701757] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.701797] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.701832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.701868] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.701906] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.701933] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.701964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.701997] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.702094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.702126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.702155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.702186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.702215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.702246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.702279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.702312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.702344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.702367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.702386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.702408] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.702429] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.704467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.704490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.704509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.704529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.706095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.706115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.706133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.707681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.707728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.709597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.712933] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.712988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.713034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.713063] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.729808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.729858] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.729925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.730127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.730209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.746484] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.746531] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.746616] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.763630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.763668] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.763795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.763849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.763907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.763954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.763986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.764019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.764057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.764089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.764120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.764150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.764178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.764206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.764270] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.764404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.764416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.764470] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.764490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.764513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.764537] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.764557] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.764578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.764599] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.764624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.764650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.764702] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.764730] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.764739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.764766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.764773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.764801] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.764828] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.764855] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.764881] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.764912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.764938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.764966] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.764993] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.765019] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.765050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.765082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.765180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.765211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.765242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.765272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.765302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.765332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.765366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.765398] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.765430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.765459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.765486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.765509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.765530] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.767570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.767591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.767609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.767627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.769235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.769254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.769271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.770834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.770855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.772745] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.776084] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.776136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.776169] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.776212] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.792936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.792982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.793050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.793248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.793327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.809634] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.809680] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.809843] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.826837] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.826875] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.826914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.826948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.826983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.827013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.827043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.827075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.827109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.827142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.827173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.827204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.827232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.827260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.827324] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.827462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.827479] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.827560] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.827592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.827626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.827664] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.827758] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.827789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.827819] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.827847] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.827876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.827902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.827929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.827937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.827963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.827970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.827997] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.828023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.828050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.828076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.828106] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.828132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.828162] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.828405] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.828426] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.828449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.828474] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.828539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.828560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.828579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.828598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.828616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.828640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.828671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.828726] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.828757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.828785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.828811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.828842] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.828872] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.831038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.831059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.831077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.831101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.832666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.832703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.832722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.834283] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.834307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.836220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.839516] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.839568] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.839600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.839641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.856388] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.856439] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.856504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.856799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.856877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.873088] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.873137] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.873206] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.890219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.890257] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.890296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.890329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.890362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.890391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.890419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.890450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.890485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.890517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.890548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.890579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.890607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.890645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.890813] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.891026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.891039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.891096] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.891117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.891140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.891165] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.891185] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.891207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.891228] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.891248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.891268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.891287] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.891305] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.891309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.891327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.891331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.891350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.891368] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.891391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.891417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.891443] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.891468] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.891494] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.891519] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.891546] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.891572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.891600] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.891701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.891733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.891762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.891790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.891819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.891848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.891880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.891911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.891942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.891970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.891997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.892030] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.892059] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.894146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.894167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.894185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.894208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.895789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.895810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.895832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.897396] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.897419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.899300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.902621] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.902673] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.902784] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.902854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.919469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.919519] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.919584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.919906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.920024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.936162] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.936209] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.936280] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  317.953365] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  317.953403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  317.953442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.953474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.953508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.953537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.953565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.953595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.953629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.953661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.953771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.953820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.953861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.953908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.954009] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.954208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.954238] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  317.954326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  317.954359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  317.954402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  317.954427] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.954452] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.954479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.954505] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  317.954531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  317.954557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.954583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  317.954608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.954614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.954639] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.954644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  317.954700] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  317.954732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.954761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.954790] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.954821] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  317.954849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.954876] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  317.954903] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  317.954929] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  317.954961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.954993] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  317.955079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  317.955111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  317.955141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  317.955171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  317.955200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  317.955231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  317.955261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  317.955283] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  317.955302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.955321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  317.955339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  317.955362] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  317.955383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  317.957431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.957452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.957470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.957490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.959054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  317.959076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  317.959098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.960660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.960697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  317.962565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.965854] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  317.965895] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  317.965920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  317.965953] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  317.982729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  317.982779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  317.982845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  317.983048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  317.983149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.999425] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  317.999470] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  317.999556] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.016550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.016587] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.016627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.016660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.016782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.016831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.016880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.016938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.016986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.017027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.017055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.017082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.017107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.017130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.017185] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.017307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.017322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.017393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.017419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.017449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.017486] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.017519] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.017555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.017590] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.017623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.017658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.017738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.017779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.017790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.017828] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.017837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.017874] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.017910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.017956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.017982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.018012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.018039] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.018066] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.018092] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.018118] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.018148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.018181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.018280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.018312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.018342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.018372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.018402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.018433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.018467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.018499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.018532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.018551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.018569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.018591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.018612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.020702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.020723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.020742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.020761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.022335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.022355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.022377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.023944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.023966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.025838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.029173] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.029217] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.029245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.029281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.046046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.046093] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.046156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.046339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.046413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.062728] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.062773] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.062840] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.079877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.079914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.079954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.079987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.080022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.080051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.080080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.080112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.080147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.080179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.080210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.080241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.080269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.080297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.080354] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.080442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.080454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.080504] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.080522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.080545] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.080572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.080595] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.080619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.080642] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.080728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.080759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.080788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.080814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.080823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.080849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.080857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.080884] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.080911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.080940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.080966] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.080996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.081022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.081049] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.081075] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.081101] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.081132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.081167] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.081259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.081279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.081297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.081315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.081333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.081353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.081375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.081395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.081414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.081432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.081449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.081471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.081492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.083540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.083564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.083587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.083611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.085189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.085210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.085229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.086885] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.086907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.088792] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.092097] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.092148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.092180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.092222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.108929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.108974] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.109037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.109232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.109306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.125629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.125756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.125848] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.144748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.144785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.144825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.144858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.144892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.144922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.144951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.144982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.145017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.145049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.145080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.145110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.145137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.145165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.145227] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.145355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.145373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.145453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.145484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.145518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.145556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.145587] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.145617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.145649] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.145742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.145783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.145824] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.145861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.145871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.145906] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.145916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.145954] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.145991] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.146029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.146066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.146108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.146145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.146183] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.146220] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.146258] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.146300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.146343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.146448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.146486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.146523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.146556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.146591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.146626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.146697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.146742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.146774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.146804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.146833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.146866] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.146900] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.148974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.148994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.149012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.149031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.150595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.150615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.150633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.152237] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.152258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.154136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.157451] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.157503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.157535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.157577] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.174307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.174356] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.174420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.174603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.174778] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.190982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.191030] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.191099] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.208132] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.208169] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.208209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.208242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.208277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.208308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.208337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.208369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.208404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.208445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.208487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.208529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.208568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.208606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.208759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.208946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.208965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.209052] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.209086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.209127] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.209152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.209173] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.209194] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.209216] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.209237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.209257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.209277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.209295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.209301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.209318] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.209322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.209342] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.209360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.209378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.209396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.209418] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.209435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.209454] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.209472] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.209490] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.209511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.209535] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.209600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.209620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.209639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.209697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.209726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.209754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.209785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.209814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.209844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.209870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.209897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.209929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.209958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.212022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.212043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.212061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.212080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.213648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.213684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.213703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.215270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.215293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.217192] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.220447] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.220479] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.220499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.220524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.237304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.237354] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.237419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.237614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.237943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.254000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.254044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.254127] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.271216] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.271254] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.271293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.271327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.271361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.271390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.271418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.271449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.271484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.271516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.271555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.271593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.271630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.271734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.271829] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.272322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.272340] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.272423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.272455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.272489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.272525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.272554] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.272592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.272617] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.272640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.272708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.272748] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.272779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.272790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.272823] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.272832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.272868] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.272901] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.272935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.272966] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.273004] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.273036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.273337] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.273369] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.273405] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.273445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.273486] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.273605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.273633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.273687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.273714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.273744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.273773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.273806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.273838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.274091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.274117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.274144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.274176] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.274204] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.276286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.276309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.276332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.276356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.277935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.277956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.277974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.279533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.279556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.281431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.284776] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.284823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.284843] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.284868] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.301642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.301726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.301792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.301990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.302069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.318320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.318366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.318434] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.335460] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.335497] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.335537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.335569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.335604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.335633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.335744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.335792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.335849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.335906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.335947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.335988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.336024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.336060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.336141] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.336334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.336358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.336472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.336516] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.336561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.336611] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.336651] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.336735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.336782] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.336819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.336860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.336896] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.336941] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.336950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.336981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.336990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.337022] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.337051] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.337084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.337112] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.337147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.337177] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.337209] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.337238] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.337268] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.337303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.337338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.337448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.337480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.337510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.337538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.337568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.337598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.337631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.337693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.337727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.337757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.337788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.337827] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.337858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.339936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.339956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.339974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.339993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.341563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.341583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.341601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.343188] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.343209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.345081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.348386] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.348431] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.348458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.348494] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.365236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.365284] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.365346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.365516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.365590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.381918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.381963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.382030] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.399070] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.399108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.399147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.399179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.399214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.399244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.399273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.399305] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.399347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.399389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.399431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.399472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.399511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.399548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.399621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.399905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.399934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.400063] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.400099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.400137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.400176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.400207] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.400241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.400276] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.400307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.400346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.400365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.400384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.400389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.400407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.400411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.400430] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.400448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.400466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.400483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.400505] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.400530] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.400556] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.400583] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.400607] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.400635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.400697] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.400797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.400827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.400857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.400888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.400917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.400949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.400983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.401016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.401049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.401079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.401103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.401127] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.401147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.403223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.403244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.403266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.403290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.404873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.404895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.404913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.406472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.406493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.408364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.411634] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.411684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.411704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.411730] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.428525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.428577] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.428649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.428950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.429049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.445224] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.445273] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.445344] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.463543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.463580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.463620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.463738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.463787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.463818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.463849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.463881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.463916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.463949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.463982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.464014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.464043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.464081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.464156] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.464303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.464322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.464414] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.464456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.464497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.464542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.464581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.464624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.464704] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.464735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.464765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.464793] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.464821] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.464829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.464855] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.464865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.464892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.464919] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.464946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.464972] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.465003] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.465029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.465056] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.465082] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.465109] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.465139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.465174] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.465266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.465286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.465305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.465324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.465341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.465361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.465381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.465401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.465420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.465438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.465455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.465478] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.465498] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.467539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.467560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.467578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.467597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.469219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.469242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.469264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.470833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.470855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.472722] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.475998] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.476030] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.476050] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.476075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.492834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.492887] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.492958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.493194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.493287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.509531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.509576] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.509642] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.526707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.526745] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.526784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.526818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.526853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.526884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.526913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.526945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.526979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.527012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.527051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.527093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.527138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.527163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.527219] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.527340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.527356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.527426] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.527453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.527482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.527513] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.527539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.527566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.527593] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.527619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.527716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.527753] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.527787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.527797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.527832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.527842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.527877] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.527912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.527948] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.527982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.528022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.528056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.528091] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.528125] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.528164] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.528194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.528229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.528325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.528353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.528383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.528404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.528422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.528441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.528462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.528482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.528507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.528533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.528558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.528585] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.528610] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.530690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.530713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.530736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.530760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.532324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.532345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.532364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.533927] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.533948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.535820] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.539119] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.539169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.539200] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.539242] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.555982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.556032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.556097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.556297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.556400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.572717] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.572763] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.572830] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.589831] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.589868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.589908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.589940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.589975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.590004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.590034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.590065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.590099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.590139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.590181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.590223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.590262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.590300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.590373] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.590493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.590505] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.590558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.590578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.590599] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.590622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.590705] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.590737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.590768] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.590796] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.590825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.590852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.590879] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.590887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.590913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.590920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.590947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.590973] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.591000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.591025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.591058] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.591087] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.591113] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.591139] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.591166] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.591199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.591234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.591332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.591363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.591394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.591423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.591453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.591484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.591515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.591537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.591557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.591576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.591593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.591616] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.591668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.593733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.593754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.593772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.593791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.595361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.595381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.595399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.596962] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.596983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.598853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.602143] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.602193] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.602226] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.602267] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.619012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.619065] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.619136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.619365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.619460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.635716] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.635774] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.635846] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.652840] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.652882] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.652927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.652967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.653011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.653050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.653089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.653128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.653172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.653214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.653256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.653297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.653336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.653374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.653446] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.653591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.653609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.653788] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.653820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.653854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.653890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.653920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.653953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.653983] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.654013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.654042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.654070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.654096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.654103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.654130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.654136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.654165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.654191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.654218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.654244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.654274] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.654300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.654328] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.654353] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.654381] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.654409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.654442] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.654525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.654552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.654581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.654607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.654636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.654689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.654724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.654757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.654791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.654818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.654848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.654881] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.654912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.656983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.657004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.657023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.657042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.658642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.658684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.658703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.660267] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.660288] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.662179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.665494] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.665546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.665585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.665636] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.682337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.682389] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.682458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.682765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.682885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.699001] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.699046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.699132] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.716187] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.716225] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.716264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.716297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.716332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.716362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.716392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.716423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.716458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.716490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.716521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.716561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.716600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.716639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.716795] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.717031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.717051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.717137] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.717169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.717200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.717236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.717264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.717295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.717324] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.717354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.717381] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.717410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.717435] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.717442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.717468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.717475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.717503] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.717529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.717556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.717582] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.717614] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.717665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.717695] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.717722] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.717751] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.717781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.717815] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.717914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.717944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.717971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.717999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.718024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.718053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.718085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.718116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.718147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.718172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.718200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.718234] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.718262] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.720341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.720363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.720382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.720402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.721984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.722004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.722024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.723633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.723671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.725538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.728891] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.728941] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.728974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.729015] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.745752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.745801] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.745867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.746050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.746127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.762459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.762505] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.762576] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.779640] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.779710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.779750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.779783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.779818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.779847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.779886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.779925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.779969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.780011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.780052] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.780094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.780132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.780171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.780243] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.780364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.780381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.780455] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.780484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.780515] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.780547] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.780574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.780607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.780689] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.780729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.780768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.780804] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.780840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.780850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.780885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.780895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.780931] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.780966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.781002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.781036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.781076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.781111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.781147] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.781182] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.781216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.781257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.781299] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.781401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.781434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.781466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.781499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.781531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.781565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.781601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.781665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.781701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.781732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.781763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.781799] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.781830] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.783929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.783951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.783970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.783989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.785552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.785572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.785591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.787202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.787226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.789124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.792443] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.792496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.792528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.792553] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.809288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.809338] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.809403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.809598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.809884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.825963] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.826009] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.826078] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.843050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.843088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.843127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.843160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.843194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.843223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.843252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.843283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.843317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.843349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.843379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.843410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.843437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.843464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.843529] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.843757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.843774] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.843831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.843852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.843875] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.843900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.843920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.843942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.843963] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.843983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.844004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.844022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.844040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.844044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.844063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.844067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.844087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.844105] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.844122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.844140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.844161] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.844179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.844197] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.844214] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.844231] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.844253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.844275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.844341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.844362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.844380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.844399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.844416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.844436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.844458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.844478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.844497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.844516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.844533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.844556] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.844576] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.846661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.846683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.846701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.846720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.848304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.848325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.848344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.849910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.849932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.851809] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.855071] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.855104] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.855123] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.855149] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.871922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.871974] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.872045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.872245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.872327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.888628] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.888708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.888782] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.905817] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.905855] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.905894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.905927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.905969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.906009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.906048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.906088] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.906132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.906173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.906214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.906256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.906303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.906324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.906366] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.906455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.906466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.906518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.906538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.906560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.906587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.906609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.906696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.906727] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.906757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.906785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.906812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.906839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.906847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.906873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.906880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.906907] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.906933] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.906960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.906985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.907016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.907042] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.907068] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.907097] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.907126] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.907157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.907189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.907271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.907291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.907311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.907329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.907348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.907367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.907389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.907408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.907429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.907446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.907465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.907486] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.907512] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.909567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.909591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.909614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.909694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.911269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.911289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.911307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.912876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.912897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.914776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.918087] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.918141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.918180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.918231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  318.934947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.934998] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.935063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.935268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.935348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.951622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  318.951695] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  318.951774] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  318.970715] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  318.970752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  318.970792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.970828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.970872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.970911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.970951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.970990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  318.971034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.971076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.971118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.971159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.971198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.971237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.971312] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  318.971455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  318.971474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  318.971567] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  318.971608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  318.971725] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  318.971761] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.971793] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.971826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.971860] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  318.971890] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  318.971921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.971949] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  318.971978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.971987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.972015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.972023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  318.972053] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  318.972080] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.972109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.972135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.972167] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  318.972192] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.972222] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  318.972248] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  318.972277] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  318.972310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.972344] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  318.972449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  318.972477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  318.972507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  318.972533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  318.972562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  318.972589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  318.972622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  318.972703] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  318.972735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  318.972761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  318.972788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  318.972819] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  318.972849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  318.974917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.974938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.974956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.974980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.976551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  318.976571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  318.976593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.978195] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.978217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  318.980088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.983402] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  318.983458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  318.983498] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  318.983549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.000228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.000275] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.000337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.000542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.000762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.016944] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.016992] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.017060] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.034073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.034110] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.034149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.034183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.034218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.034247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.034286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.034326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.034370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.034412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.034453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.034494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.034533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.034570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.034722] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.034946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.034975] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.035088] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.035134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.035160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.035186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.035206] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.035229] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.035251] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.035271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.035292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.035311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.035329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.035334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.035359] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.035364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.035390] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.035416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.035441] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.035467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.035492] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.035518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.035543] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.035568] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.035594] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.035624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.035683] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.035783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.035814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.035843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.035875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.035905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.035936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.035970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.036003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.036035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.036065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.036091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.036116] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.036137] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.038211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.038232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.038254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.038278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.039850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.039870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.039889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.041435] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.041456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.043334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.046625] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.046690] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.046719] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.046757] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.063495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.063545] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.063609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.064037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.064115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.080174] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.080222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.080290] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.098567] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.098609] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.098740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.098794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.098985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.099017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.099048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.099080] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.099115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.099148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.099179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.099209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.099237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.099265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.099327] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.099470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.099481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.099531] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.099549] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.099570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.099592] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.099610] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.099683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.099714] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.099749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.099780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.099812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.099841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.099850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.099879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.099887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.099917] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.099946] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.099976] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.100005] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.100040] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.100069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.100100] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.100130] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.100160] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.100194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.100229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.100596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.100654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.100686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.100718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.100844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.100873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.100905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.100935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.100965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.100992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.101019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.101050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.101079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.103149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.103170] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.103188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.103207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.104798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.104820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.104838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.106403] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.106424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.108299] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.111597] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.111673] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.111693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.111723] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.128468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.128518] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.128582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.128895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.128990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.145162] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.145209] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.145279] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.162301] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.162339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.162378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.162411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.162454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.162493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.162533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.162572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.162615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.162731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.162792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.162837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.162876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.162912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.162997] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.163164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.163189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.163263] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.163291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.163322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.163354] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.163379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.163407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.163435] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.163462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.163488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.163514] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.163546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.163554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.163586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.163593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.163662] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.163699] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.163736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.163770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.163817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.163845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.163873] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.163899] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.163926] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.163957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.163989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.164088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.164119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.164150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.164180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.164210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.164241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.164276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.164300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.164321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.164339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.164357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.164379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.164400] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.166448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.166469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.166487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.166506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.168093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.168115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.168134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.169722] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.169743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.171606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.174960] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.175021] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.175048] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.175084] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.191833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.191883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.191948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.192132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.192210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.208523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.208568] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.208803] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.225840] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.225882] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.225927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.225967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.226010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.226050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.226089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.226128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.226172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.226214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.226259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.226290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.226318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.226344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.226402] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.226528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.226544] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.226618] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.226724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.226769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.226819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.226859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.226901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.226942] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.226982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.227021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.227059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.227099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.227110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.227147] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.227160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.227197] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.227247] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.227270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.227288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.227309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.227327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.227344] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.227362] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.227379] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.227400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.227423] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.227489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.227509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.227527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.227546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.227563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.227583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.227609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.227662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.227693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.227719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.227746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.227779] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.227808] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.229870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.229890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.229908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.229930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.231490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.231510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.231528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.233080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.233100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.234969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.238311] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.238364] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.238396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.238442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.255180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.255230] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.255295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.255476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.255553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.271858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.271905] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.271973] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.289007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.289044] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.289084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.289117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.289151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.289181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.289219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.289259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.289302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.289344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.289386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.289428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.289467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.289504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.289577] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.289769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.289789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.289879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.289909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.289943] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.289979] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.290007] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.290039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.290068] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.290099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.290129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.290157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.290183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.290190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.290216] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.290223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.290251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.290277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.290305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.290332] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.290363] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.290389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.290417] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.290443] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.290471] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.290500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.290532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.290614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.290670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.290698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.290728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.290754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.290785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.290819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.290851] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.290885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.290911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.290941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.290976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.291005] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.293094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.293115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.293133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.293152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.294738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.294759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.294777] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.296338] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.296361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.298236] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.301522] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.301575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.301614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.301750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.318399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.318449] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.318515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.318828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.318916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.335097] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.335143] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.335229] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.352233] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.352275] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.352320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.352360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.352403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.352443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.352482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.352521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.352565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.352607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.352721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.352784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.352813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.352844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.352910] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.353041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.353054] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.353110] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.353131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.353154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.353180] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.353200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.353225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.353251] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.353278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.353304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.353330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.353354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.353360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.353385] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.353390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.353416] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.353442] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.353468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.353494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.353519] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.353544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.353571] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.353596] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.353659] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.353693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.353726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.353826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.353854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.353883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.353912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.353942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.353973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.354008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.354041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.354073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.354103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.354133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.354157] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.354181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.356222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.356244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.356267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.356291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.357864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.357885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.357903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.359461] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.359482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.361353] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.364654] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.364705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.364736] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.364777] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.381515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.381564] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.381716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.381973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.382074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.398214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.398259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.398345] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.415354] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.415392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.415432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.415465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.415500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.415529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.415567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.415607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.415729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.415782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.415836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.415888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.415934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.415980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.416057] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.416195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.416218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.416272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.416294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.416317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.416342] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.416362] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.416383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.416404] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.416424] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.416443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.416462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.416480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.416485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.416502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.416507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.416532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.416558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.416584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.416635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.416666] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.416694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.416722] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.416748] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.416775] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.416805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.416837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.416936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.416968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.416999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.417030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.417059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.417089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.417124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.417156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.417178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.417196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.417215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.417237] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.417263] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.419310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.419330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.419348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.419367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.420942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.420962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.420979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.422536] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.422557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.424430] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.427707] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.427751] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.427779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.427816] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.444540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.444590] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.444755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.445019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.445110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.461237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.461283] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.461368] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.478368] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.478406] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.478445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.478478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.478513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.478543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.478582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.478695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.478754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.478803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.478855] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.478906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.478952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.478997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.479094] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.479240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.479259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.479344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.479380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.479421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.479466] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.479505] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.479546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.479585] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.479653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.479692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.479727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.479761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.479772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.479806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.479816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.479852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.479887] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.479922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.479956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.479996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.480030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.480066] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.480100] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.480137] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.480180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.480226] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.480359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.480400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.480439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.480479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.480514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.480541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.480579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.480630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.480659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.480685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.480712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.480744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.480773] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.482835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.482855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.482874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.482893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.484462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.484482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.484499] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.486062] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.486082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.487953] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.491264] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.491315] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.491346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.491387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.508114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.508164] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.508230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.508458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.508553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.524813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.524858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.524943] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.541950] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.541988] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.542027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.542060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.542094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.542124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.542153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.542184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.542218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.542250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.542281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.542312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.542340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.542367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.542429] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.542569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.542659] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.542797] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.542849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.542904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.542957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.542989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.543016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.543039] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.543059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.543079] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.543098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.543116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.543121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.543139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.543143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.543162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.543180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.543199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.543216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.543237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.543255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.543273] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.543290] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.543308] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.543329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.543352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.543423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.543449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.543476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.543501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.543528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.543553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.543581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.543638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.543673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.543701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.543729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.543765] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.543794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.545857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.545878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.545896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.545915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.547484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.547504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.547523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.549080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.549100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.551002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.554283] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.554323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.554348] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.554381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.571114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.571164] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.571230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.571429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.571530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.587813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.587858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.587944] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.604949] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.604986] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.605026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.605059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.605093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.605123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.605152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.605184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.605218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.605259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.605301] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.605348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.605376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.605402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.605459] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.605572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.605655] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.605775] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.605815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.605848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.605882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.605910] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.605939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.605969] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.605998] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.606032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.606069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.606104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.606112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.606146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.606153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.606189] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.606224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.606261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.606296] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.606333] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.606370] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.606392] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.606412] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.606431] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.606453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.606477] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.606543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.606564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.606583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.606630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.606658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.606686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.606717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.606747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.606778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.606804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.606830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.606862] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.606891] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.608949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.608969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.608987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.609006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.610588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.610623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.610641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.612202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.612224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.614141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.617462] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.617519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.617546] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.617580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.634310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.634360] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.634425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.634694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.634783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.651005] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.651050] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.651121] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.668219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.668255] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.668295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.668334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.668378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.668417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.668457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.668496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.668539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.668590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.668705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.668758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.668801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.668847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.668942] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.669155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.669184] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.669311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.669353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.669402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.669455] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.669495] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.669542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.669584] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.669655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.669684] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.669716] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.669743] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.669752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.669781] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.669789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.669819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.669846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.669875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.669902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.669934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.669959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.669990] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.670016] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.670043] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.670075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.670109] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.670193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.670220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.670248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.670274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.670302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.670329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.670361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.670393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.670423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.670449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.670476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.670506] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.670536] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.672644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.672665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.672683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.672702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.674323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.674345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.674364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.675943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.675963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.677857] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.681102] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.681135] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.681154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.681179] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.697967] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.698017] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.698082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.698312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.698405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.714674] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.714721] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.714792] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.731858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.731895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.731935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.731968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.732002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.732030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.732058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.732090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.732124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.732155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.732186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.732216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.732243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.732270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.732332] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.732475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.732493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.732575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.732760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.732814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.732872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.732919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.732970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.733027] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.733058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.733089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.733119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.733148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.733155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.733183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.733190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.733219] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.733248] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.733277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.733305] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.733337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.733365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.733394] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.733423] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.733452] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.733485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.733519] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.733634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.733667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.733696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.733727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.733758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.733789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.733825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.733858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.733891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.733921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.733948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.733984] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.734016] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.736083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.736104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.736122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.736141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.737749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.737771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.737790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.739352] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.739373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.741247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.744511] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.744556] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.744584] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.744697] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.761355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.761405] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.761470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.761857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.761937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.778066] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.778112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.778201] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.795271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.795313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.795358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.795398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.795441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.795481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.795520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.795559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.795682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.795744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.795799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.795853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.795901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.796245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.796342] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.796441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.796453] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.796505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.796525] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.796546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.796569] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.796640] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.796672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.796707] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.796739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.796773] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.796804] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.796836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.796845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.796875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.796882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.796912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.797104] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.797136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.797166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.797199] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.797229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.797260] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.797286] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.797316] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.797349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.797383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.797488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.797516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.797544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.797571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.797635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.797669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.797704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.797738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.797771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.797801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.797831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.797866] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.797898] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.800212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.800235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.800253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.800273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.801848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.801869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.801887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.803444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.803465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.805339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.808642] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.808675] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.808694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.808720] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.825501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.825550] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.825707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.825965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.826042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.842208] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.842255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.842343] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.859405] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.859443] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.859483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.859516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.859551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.859590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.859705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.859762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.859821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.859874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.860087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.860117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.860145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.860172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.860229] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.860318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.860329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.860379] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.860398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.860419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.860442] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.860461] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.860480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.860499] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.860517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.860535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.860551] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.860568] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.860615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.860645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.860656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.860686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.860717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.860748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.860777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.860811] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.860841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.860872] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.860902] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.860933] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.860967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.861003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.861362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.861395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.861426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.861457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.861486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.861518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.861551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.861584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.861640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.861668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.861699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.861734] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.861766] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.863996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.864016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.864035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.864054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.865729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.865749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.865768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.867326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.867346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.869219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.872506] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.872553] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.872582] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.872700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.889382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.889433] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.889498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.889888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.889967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.906089] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.906135] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.906206] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.925064] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.925101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.925141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.925180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.925223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.925263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.925302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.925340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.925384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.925425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.925472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.925505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.925533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.925559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.925705] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.925909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.925935] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.926054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.926099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.926147] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.926199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.926242] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.926288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.926334] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.926376] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.926419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.926461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.926501] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.926508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.926537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.926544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.926575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.926634] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.926666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.926696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.926729] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.926760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.926790] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.926818] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.926848] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.926882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.926918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.927018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.927049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.927079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.927106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.927135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.927165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.927199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.927231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.927263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.927293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.927322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.927356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.927387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.929451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.929472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.929490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.929509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.931106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.931126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.931144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.932717] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.932741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.934633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.937897] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  319.937929] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  319.937949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  319.937975] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  319.954743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.954793] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.954858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.955057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.955136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.971454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  319.971505] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  319.971580] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  319.988684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  319.988722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  319.988761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.988794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.988829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.988858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.988886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.988917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  319.988952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.988983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.989014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.989054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.989093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.989131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.989204] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  319.989334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  319.989353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  319.989445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  319.989485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.989525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  319.989569] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.989696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.989756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.989810] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  319.989862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  319.989913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.989963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  319.989994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.990003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.990032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.990040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  319.990070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  319.990100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.990131] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.990161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.990195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  319.990224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.990255] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  319.990284] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  319.990315] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  319.990348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.990382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  319.990484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  319.990515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  319.990546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  319.990575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  319.990629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  319.990659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  319.990690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  319.990722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  319.990754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  319.990783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  319.990814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  319.990850] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  319.990882] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  319.992956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.992977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.992999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.993023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.994614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  319.994637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  319.994660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.996229] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.996251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.998129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.001346] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.001377] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.001399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.001430] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.018192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.018242] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.018308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.018498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.018576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.034891] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.034937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.035010] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.052032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.052069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.052108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.052140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.052175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.052204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.052233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.052264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.052299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.052331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.052362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.052393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.052428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.052452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.052509] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.052742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.052768] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.052887] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.052931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.052978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.053030] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.053073] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.053118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.053163] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.053207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.053250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.053291] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.053331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.053342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.053379] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.053389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.053437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.053466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.053495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.053524] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.053554] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.053604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.053635] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.053665] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.053695] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.053729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.053764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.053863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.053893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.053923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.053953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.053979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.054009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.054042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.054075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.054107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.054136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.054164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.054198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.054229] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.056297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.056317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.056335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.056354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.057922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.057942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.057960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.059510] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.059534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.061449] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.064756] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.064798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.064825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.064860] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.081652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.081702] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.081768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.081972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.082050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.098312] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.098362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.098439] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.115496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.115534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.115573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.115698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.115757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.115805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.115853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.115908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.115958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.116003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.116049] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.116093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.116134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.116174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.116261] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.116425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.116442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.116517] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.116545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.116576] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.116670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.116716] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.116766] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.116812] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.116857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.116911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.116942] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.116972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.116981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.117009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.117018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.117048] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.117078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.117104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.117134] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.117167] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.117197] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.117226] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.117254] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.117284] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.117317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.117350] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.117448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.117479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.117510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.117539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.117568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.117622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.117657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.117691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.117724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.117753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.117783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.117817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.117848] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.119926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.119948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.119967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.119986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.121568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.121604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.121622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.123180] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.123201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.125097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.128356] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.128398] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.128425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.128460] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.145198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.145245] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.145308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.145506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.145580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.161882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.161929] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.162014] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.179037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.179075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.179115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.179148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.179183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.179213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.179242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.179273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.179307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.179339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.179369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.179400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.179427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.179455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.179518] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.179741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.179771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.179906] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.179952] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.180004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.180063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.180107] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.180156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.180202] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.180249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.180292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.180339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.180364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.180371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.180398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.180404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.180433] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.180459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.180486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.180511] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.180542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.180567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.180619] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.180647] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.180676] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.180711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.180746] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.180845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.180873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.180902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.180929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.180956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.180983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.181015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.181046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.181077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.181102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.181130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.181160] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.181190] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.183254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.183276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.183294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.183314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.184889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.184909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.184927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.186476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.186497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.188368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.191636] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.191667] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.191687] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.191712] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.208469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.208517] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.208584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.208910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.209009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.225178] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.225223] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.225307] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.242307] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.242344] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.242384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.242416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.242451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.242480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.242509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.242540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.242574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.242690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.242743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.242787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.242815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.242844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.242907] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.243053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.243072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.243163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.243192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.243223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.243256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.243282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.243311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.243338] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.243366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.243391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.243418] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.243442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.243448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.243473] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.243479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.243506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.243530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.243557] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.243623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.243654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.243683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.243711] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.243739] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.243766] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.243800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.243834] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.243934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.243964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.243990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.244018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.244044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.244074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.244107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.244139] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.244170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.244197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.244224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.244254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.244285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.246346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.246366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.246385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.246404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.247976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.247996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.248013] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.249564] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.249601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.251470] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.253744] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.253791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.253824] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.253868] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.270640] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.270690] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.270760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.270989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.271080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.287307] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.287353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.287422] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.304522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.304560] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.304677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.304724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.304779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.304828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.304875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.304924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.304980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.305031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.305080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.305129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.305169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.305219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.305281] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.305429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.305448] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.305521] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.305541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.305562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.305638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.305668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.305703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.305733] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.305767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.305796] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.305826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.305854] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.305863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.305890] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.305898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.305928] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.305955] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.305984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.306010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.306044] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.306070] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.306098] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.306127] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.306155] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.306188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.306224] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.306325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.306357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.306387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.306414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.306440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.306471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.306504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.306536] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.306568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.306623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.306649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.306684] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.306713] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.308780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.308801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.308820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.308839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.310409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.310429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.310451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.312017] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.312039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.313897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.317237] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.317292] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.317332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.317383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.334110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.334160] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.334225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.334422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.334500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.350784] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.350831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.350916] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.367938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.367975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.368014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.368047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.368082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.368113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.368142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.368174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.368209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.368241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.368273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.368304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.368332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.368359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.368422] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.368625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.368646] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.368735] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.368764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.368797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.368833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.368861] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.368894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.368923] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.368953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.368981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.369009] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.369034] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.369041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.369068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.369075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.369103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.369129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.369156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.369181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.369212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.369237] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.369265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.369290] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.369318] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.369347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.369379] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.369475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.369503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.369532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.369559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.369611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.369640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.369675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.369708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.369740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.369767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.369796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.369831] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.369860] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.371929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.371952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.371975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.372000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.373565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.373602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.373620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.375199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.375222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.377112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.380443] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.380495] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.380527] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.380568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.397276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.397326] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.397391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.397650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.397767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.413980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.414031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.414107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.431192] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.431229] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.431268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.431301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.431336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.431366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.431394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.431425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.431460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.431491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.431522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.431552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.431658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.431702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.431802] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.432217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.432229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.432282] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.432305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.432330] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.432357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.432379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.432403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.432426] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.432450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.432473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.432496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.432519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.432523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.432546] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.432590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.432628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.432660] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.432692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.432721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.432755] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.432783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.432816] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.432845] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.432875] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.432910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.432945] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.433307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.433337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.433367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.433394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.433423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.433451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.433483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.433515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.433546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.433598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.433629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.433662] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.433694] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.435933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.435954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.435973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.435992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.437556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.437593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.437612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.439176] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.439199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.441092] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.444388] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.444430] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.444457] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.444490] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.461251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.461304] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.461375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.461650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.461771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.477958] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.478005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.478077] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.495125] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.495162] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.495202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.495235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.495270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.495301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.495330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.495361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.495403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.495452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.495483] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.495512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.495538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.495652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.495749] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.495957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.495985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.496111] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.496159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.496209] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.496263] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.496309] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.496357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.496405] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.496450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.496491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.496521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.496550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.496583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.496612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.496620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.496651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.496681] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.496712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.496741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.496775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.496804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.496832] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.496861] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.496891] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.496926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.496961] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.497060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.497091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.497122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.497150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.497177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.497206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.497240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.497272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.497304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.497333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.497362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.497395] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.497426] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.499507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.499530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.499553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.499634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.501199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.501219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.501236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.502794] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.502815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.504698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.508029] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.508079] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.508109] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.508149] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.524860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.524910] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.524975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.525155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.525232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.541554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.541635] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.541705] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.558736] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.558774] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.558813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.558847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.558881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.558910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.558949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.558988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.559032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.559074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.559116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.559157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.559196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.559233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.559305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.559452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.559472] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.559563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.559697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.559758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.559797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.559829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.559864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.559898] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.559931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.559963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.559995] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.560024] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.560034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.560062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.560070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.560100] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.560130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.560159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.560189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.560222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.560251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.560280] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.560309] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.560338] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.560371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.560405] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.560505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.560536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.560587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.560619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.560649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.560680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.560714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.560748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.560781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.560810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.560836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.560870] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.560902] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.562976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.562997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.563019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.563043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.564667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.564688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.564706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.566257] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.566278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.568147] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.571442] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.571496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.571535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.571653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.588318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.588368] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.588433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.588861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.588940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.605009] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.605056] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.605127] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.622148] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.622186] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.622225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.622257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.622291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.622320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.622349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.622380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.622414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.622446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.622476] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.622507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.622534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.622656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.622757] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.622957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.622985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.623118] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.623167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.623231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.623268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.623299] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.623332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.623364] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.623395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.623426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.623457] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.623487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.623496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.623524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.623532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.623587] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.623615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.623646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.623675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.623710] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.623740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.623771] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.623801] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.623831] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.623866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.623901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.624001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.624032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.624063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.624092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.624122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.624154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.624187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.624219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.624251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.624280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.624308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.624342] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.624374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.626443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.626464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.626482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.626501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.628088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.628110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.628130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.629689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.629710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.631599] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.634929] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.634981] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.635013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.635055] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.651759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.651809] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.651874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.652073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.652151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.668436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.668483] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.668568] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.685642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.685679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.685719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.685752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.685787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.685817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.685847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.685878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.685913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.685945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.685975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.686005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.686033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.686060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.686122] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.686263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.686282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.686363] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.686394] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.686429] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.686467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.686497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.686538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.686621] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.686650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.686678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.686708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.686736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.686745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.686772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.686780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.686810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.686836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.686867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.686893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.686925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.686951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.686980] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.687007] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.687036] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.687070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.687106] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.687205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.687235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.687262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.687290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.687316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.687345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.687378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.687409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.687440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.687466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.687494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.687528] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.687586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.689653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.689674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.689693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.689712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.691282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.691302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.691320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.692884] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.692905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.694774] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.698062] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.698110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.698140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.698179] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.714936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.714986] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.715051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.715245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.715323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.731613] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.731663] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.731750] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.748764] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.748801] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.748841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.748873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.748916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.748956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.748995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.749034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.749078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.749120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.749161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.749203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.749242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.749280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.749353] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.749500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.749519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.749712] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.749761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.749814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.749870] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.749918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.749950] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.749980] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.750010] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.750038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.750067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.750093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.750100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.750127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.750133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.750162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.750188] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.750215] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.750240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.750271] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.750297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.750326] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.750352] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.750379] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.750409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.750442] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.750536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.750589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.750620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.750647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.750677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.750705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.750738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.750771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.750803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.750830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.750859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.750894] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.750923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.752989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.753009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.753028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.753046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.754644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.754664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.754682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.756246] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.756267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.758131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.761400] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.761444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.761472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.761510] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.778244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.778293] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.778359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.778642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.778758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.794918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.794964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.795034] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.812094] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.812131] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.812170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.812203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.812237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.812267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.812305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.812344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.812388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.812430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.812472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.812513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.812552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.812662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.812767] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.812969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.812999] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.813135] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.813181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.813234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.813289] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.813332] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.813377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.813406] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.813435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.813463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.813491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.813516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.813524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.813575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.813583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.813614] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.813640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.813669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.813696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.813729] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.813755] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.813785] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.813812] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.813840] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.813871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.813905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.814003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.814031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.814059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.814086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.814114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.814141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.814173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.814204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.814235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.814261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.814288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.814318] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.814348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.816410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.816430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.816448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.816467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.818057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.818077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.818095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.819655] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.819675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.821537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.824856] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.824902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.824932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.824969] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.841714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.841764] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.841834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.842030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.842110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.858389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.858436] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.858503] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.875539] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.875610] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.875649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.875689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.875733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.875772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.875811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.875851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.875894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.875936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.875980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.876038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.876088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.876119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.876186] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.876325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.876344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.876428] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.876460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.876496] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.876534] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.876629] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.876679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.876726] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.876769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.876798] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.876824] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.876851] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.876859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.876885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.876893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.876920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.876946] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.876973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.876998] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.877031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.877059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.877085] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.877112] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.877138] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.877169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.877201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.877299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.877330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.877360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.877390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.877418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.877449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.877482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.877515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.877573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.877600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.877628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.877660] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.877689] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.879758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.879779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.879801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.879825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.881386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.881407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.881429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.882995] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.883016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.884884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.888116] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.888149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.888168] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.888193] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.904944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.904994] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.905058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.905253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.905331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.921622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.921669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.921736] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.938766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  320.938804] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  320.938844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.938877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.938912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.938942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.938971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.939002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.939037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.939078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.939120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.939162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.939205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.939231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.939285] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.939404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.939419] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  320.939490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  320.939516] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.939613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  320.939661] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.939698] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.939739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.939777] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  320.939814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.939851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.939887] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  320.939921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.939932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.939966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.939976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  320.940013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  320.940050] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.940086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.940120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.940162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  320.940193] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.940218] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  320.940250] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  320.940268] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  320.940289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.940312] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  320.940378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  320.940398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  320.940417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  320.940435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  320.940452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  320.940471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  320.940492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  320.940512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  320.940531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.940582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  320.940609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  320.940641] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  320.940670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  320.942733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.942754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.942772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.942790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.944351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  320.944371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  320.944393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.945955] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.945976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  320.947846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.951155] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.951205] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  320.951236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  320.951278] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  320.968008] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  320.968057] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  320.968123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  320.968323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  320.968400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.984684] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  320.984732] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  320.984799] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.001832] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.001869] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.001909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.001941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.001975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.002005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.002033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.002065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.002099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.002131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.002162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.002193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.002221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.002248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.002310] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.002437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.002455] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.002538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.002652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.002684] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.002719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.002747] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.002777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.002807] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.002836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.002864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.002891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.002920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.002928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.002955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.002964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.002991] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.003020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.003045] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.003063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.003085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.003102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.003120] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.003137] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.003154] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.003176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.003198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.003263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.003283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.003301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.003319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.003337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.003356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.003377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.003397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.003416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.003438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.003463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.003490] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.003514] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.005599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.005622] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.005645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.005669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.007230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.007251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.007270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.008832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.008852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.010724] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.014017] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.014061] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.014088] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.014123] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.030888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.030938] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.031002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.031186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.031263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.047604] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.047649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.047715] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.064721] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.064759] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.064798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.064831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.064865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.064896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.064925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.064956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.064990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.065022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.065062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.065103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.065129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.065161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.065226] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.065357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.065374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.065457] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.065493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.065529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.065637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.065680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.065725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.065768] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.065808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.065847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.065886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.065923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.065935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.065971] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.065981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.066019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.066056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.066099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.066132] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.066412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.066438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.066463] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.066493] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.066521] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.066582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.066621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.066792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.066817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.066839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.066868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.066898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.066927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.066959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.066990] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.067021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.067049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.067079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.067115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.067138] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.069183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.069205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.069223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.069243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.070804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.070824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.070841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.072387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.072408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.074271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.077541] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.077608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.077635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.077670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.094425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.094473] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.094536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.094860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.094950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.111128] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.111176] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.111244] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.128263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.128300] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.128340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.128372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.128407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.128436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.128466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.128498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.128532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.128650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.128703] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.128756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.128798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.128843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.128942] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.129167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.129197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.129331] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.129376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.129433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.129466] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.129492] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.129521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.129587] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.129622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.129652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.129683] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.129709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.129718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.129747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.129754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.129785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.129812] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.129842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.129867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.129899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.129926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.129953] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.129979] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.130007] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.130038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.130072] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.130170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.130200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.130227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.130257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.130283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.130312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.130345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.130377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.130408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.130436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.130463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.130494] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.130525] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.132610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.132631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.132649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.132668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.134243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.134263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.134281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.135845] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.135866] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.137737] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.141066] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.141115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.141146] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.141185] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.157898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.157947] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.158012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.158210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.158289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.174605] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.174651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.174719] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.191729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.191767] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.191806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.191840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.191875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.191905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.191934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.191965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.192000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.192032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.192063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.192094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.192122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.192149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.192211] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.192340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.192358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.192440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.192471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.192505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.192623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.192669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.192723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.192770] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.192819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.192871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.192901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.192927] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.192936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.192964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.192971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.193002] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.193029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.193058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.193084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.193117] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.193143] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.193173] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.193199] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.193228] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.193261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.193292] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.193392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.193419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.193447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.193474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.193502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.193529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.193583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.193613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.193646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.193673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.193700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.193730] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.193760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.195832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.195854] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.195872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.195891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.197452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.197472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.197491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.199096] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.199117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.201017] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.204307] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.204352] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.204379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.204415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.221180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.221231] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.221297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.221478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.221763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.237888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.237935] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.238008] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.256498] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.256540] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.256670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.256706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.256744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.256774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.256805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.256836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.256872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.256914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.256957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.257001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.257041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.257081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.257156] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.257304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.257323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.257406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.257428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.257453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.257478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.257497] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.257520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.257576] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.257606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.257636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.257663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.257690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.257698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.257724] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.257732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.257759] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.257786] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.257812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.257838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.257868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.257894] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.257922] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.257948] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.257974] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.258004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.258036] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.258130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.258150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.258169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.258187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.258205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.258225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.258246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.258266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.258286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.258304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.258322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.258344] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.258364] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.260420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.260443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.260461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.260481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.262061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.262081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.262103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.263670] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.263691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.265576] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.268876] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.268921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.268947] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.268983] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.285739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.285790] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.285854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.286053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.286130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.302445] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.302492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.302854] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.321505] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.321576] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.321619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.321659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.321702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.321742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.321781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.321821] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.321865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.321907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.321948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.321989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.322028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.322067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.322139] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.322283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.322301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.322389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.322424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.322461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.322498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.322529] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.322626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.322676] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.322722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.322766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.322813] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.322840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.322848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.322874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.322881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.322908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.322935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.322961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.322987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.323017] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.323043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.323070] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.323096] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.323123] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.323153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.323188] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.323280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.323302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.323320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.323346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.323371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.323398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.323426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.323453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.323481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.323507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.323559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.323593] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.323623] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.325686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.325707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.325726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.325746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.327317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.327337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.327355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.328918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.328938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.330798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.334080] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.334112] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.334131] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.334157] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.350910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.350960] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.351026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.351223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.351301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.367586] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.367633] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.367702] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.384734] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.384771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.384811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.384844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.384878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.384908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.384937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.384968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.385011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.385053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.385095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.385136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.385177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.385203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.385259] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.385382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.385397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.385468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.385495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.385524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.385628] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.385667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.385708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.385747] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.385785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.385823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.385859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.385893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.385905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.385938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.385948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.385983] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.386022] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.386059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.386092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.386132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.386174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.386204] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.386228] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.386247] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.386268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.386291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.386357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.386377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.386395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.386413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.386430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.386449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.386476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.386503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.386554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.386582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.386609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.386640] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.386670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.388730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.388751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.388769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.388790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.390361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.390381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.390399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.391961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.391985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.393858] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.397179] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.397232] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.397264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.397306] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.414019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.414069] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.414134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.414317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.414395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.430696] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.430742] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.430810] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.447839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.447877] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.447917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.447950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.447985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.448015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.448045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.448076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.448111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.448143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.448174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.448204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.448232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.448260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.448322] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.448458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.448476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.448658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.448689] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.448724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.448752] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.448776] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.448804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.448830] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.448856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.448883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.448909] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.448934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.448940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.448965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.448970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.448995] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.449021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.449046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.449072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.449098] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.449123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.449148] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.449174] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.449199] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.449226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.449254] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.449324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.449351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.449376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.449402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.449428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.449453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.449480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.449508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.449566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.449597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.449625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.449659] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.449688] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.451768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.451789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.451807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.451827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.453388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.453409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.453427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.454979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.454999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.456869] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.460184] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.460230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.460259] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.460297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.477030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.477080] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.477145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.477341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.477419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.493710] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.493756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.493824] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.510855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.510893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.510932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.510966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.511008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.511048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.511087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.511126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.511170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.511212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.511256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.511287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.511313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.511338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.511396] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.511590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.511618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.511738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.511778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.511826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.511877] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.511916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.511960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.512000] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.512041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.512080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.512119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.512155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.512164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.512201] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.512210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.512254] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.512280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.512307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.512332] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.512363] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.512388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.512416] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.512443] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.512471] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.512500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.512557] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.512654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.512682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.512711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.512737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.512766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.512793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.512825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.512856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.512887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.512912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.512940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.512974] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.513002] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.515105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.515126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.515145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.515164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.516761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.516782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.516801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.518354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.518375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.520254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.523543] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.523576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.523595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.523620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.540423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.540473] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.540632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.540873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.540949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.557089] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.557132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.557199] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.574257] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.574294] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.574334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.574366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.574400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.574429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.574456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.574487] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.574601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.574664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.574706] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.574751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.574792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.574831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.574920] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.575079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.575096] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.575171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.575201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.575233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.575267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.575295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.575324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.575353] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.575381] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.575407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.575434] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.575458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.575466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.575490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.575530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.575570] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.575607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.575643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.575679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.575726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.575756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.575786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.575815] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.575844] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.575878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.575914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.576027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.576062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.576096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.576128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.576162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.576196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.576235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.576265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.576289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.576317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.576346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.576377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.576407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.578456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.578477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.578496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.578564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.580209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.580229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.580247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.581809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.581830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.583688] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.587003] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.587035] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.587054] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.587080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.603857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.603907] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.603972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.604175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.604278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.620598] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.620645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.620731] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.637736] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.637774] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.637813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.637847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.637881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.637911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.637941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.637972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.638007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.638039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.638070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.638101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.638129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.638156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.638215] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.638294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.638305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.638354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.638373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.638394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.638416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.638435] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.638453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.638472] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.638490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.638575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.638602] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.638629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.638637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.638663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.638670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.638698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.638724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.638751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.638777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.638807] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.638833] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.638861] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.638887] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.638913] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.638944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.638975] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.639072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.639103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.639132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.639161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.639191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.639222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.639255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.639287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.639320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.639349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.639373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.639396] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.639417] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.641454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.641475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.641498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.641566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.643254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.643277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.643300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.644864] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.644885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.646756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.650055] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.650108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.650147] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.650198] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.666919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.666969] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.667034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.667260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.667353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.683618] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.683664] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.683751] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.700755] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.700792] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.700832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.700865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.700899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.700929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.700959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.700990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.701025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.701057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.701088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.701118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.701146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.701173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.701235] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.701375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.701394] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.701476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.701507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.701630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.701666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.701694] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.701724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.701754] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.701783] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.701811] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.701838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.701864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.701872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.701898] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.701905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.701934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.701963] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.701992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.702017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.702047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.702073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.702102] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.702124] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.702148] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.702176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.702203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.702275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.702301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.702328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.702353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.702380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.702406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.702434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.702462] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.702490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.702541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.702572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.702605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.702633] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.704692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.704713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.704734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.704759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.706320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.706341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.706360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.707923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.707943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.709812] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.713097] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.713144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.713174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.713213] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.729973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.730026] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.730096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.730329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.730422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.746672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.746715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.746800] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.763803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.763841] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.763880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.763913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.763947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.763977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.764015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.764055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.764099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.764141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.764182] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.764224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.764263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.764300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.764373] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.764666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.764695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.764810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.764846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.764884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.764923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.764954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.764988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.765022] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.765053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.765073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.765092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.765111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.765116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.765134] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.765138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.765157] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.765175] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.765193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.765210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.765231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.765249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.765267] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.765285] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.765303] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.765323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.765346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.765410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.765431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.765449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.765468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.765485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.765534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.765564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.765595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.765625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.765652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.765679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.765712] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.765743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.767803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.767824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.767842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.767860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.769433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.769453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.769471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.771073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.771094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.772966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.776290] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.776323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.776345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.776377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.793107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.793154] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.793218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.793404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.793479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.809823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.809872] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.809940] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.826954] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.826991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.827030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.827064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.827098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.827129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.827157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.827188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.827222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.827253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.827284] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.827314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.827341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.827369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.827427] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.827571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.827591] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.827675] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.827697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.827721] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.827745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.827765] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.827786] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.827808] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.827828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.827848] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.827866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.827884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.827889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.827907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.827911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.827930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.827955] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.827981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.828007] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.828033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.828058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.828084] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.828111] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.828136] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.828164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.828192] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.828262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.828286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.828313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.828338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.828365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.828390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.828419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.828445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.828473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.828498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.828552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.828586] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.828616] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.830683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.830706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.830729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.830753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.832314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.832335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.832353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.833906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.833927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.835788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.839101] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.839154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.839186] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.839228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.855945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.855992] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.856055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.856277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.856369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.872645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.872693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.872760] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.889784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.889821] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.889861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.889893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.889928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.889957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.889986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.890017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.890051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.890083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.890114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.890144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.890172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.890199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.890261] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.890401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.890420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.890501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.890620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.890669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.890729] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.890777] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.890830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.890879] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.890938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.890974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.891012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.891045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.891056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.891090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.891100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.891136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.891170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.891205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.891236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.891277] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.891310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.891347] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.891379] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.891413] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.891449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.891489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.891644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.891681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.891715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.891751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.891783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.891819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.891860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.891899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.891943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.891969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.891998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.892029] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.892060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.894129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.894149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.894168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.894187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.895759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.895780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.895798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.897356] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.897376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.899249] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.902593] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.902646] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.902679] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.902721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.919461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.919511] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.919666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.919911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.919988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.936137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.936184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.936251] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.953282] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  321.953320] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  321.953360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.953393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.953428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.953458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.953487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.953600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.953657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.953706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.953758] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.953793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.953821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.953849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.953913] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.954056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.954074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  321.954156] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  321.954189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.954224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  321.954262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.954293] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.954326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.954359] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  321.954400] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.954419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.954437] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.954455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.954460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.954477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.954506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  321.954535] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  321.954562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.954589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.954614] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.954645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  321.954671] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.954698] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  321.954725] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  321.954751] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  321.954782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.954814] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  321.954912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.954933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  321.954951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  321.954970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  321.954987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  321.955007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  321.955028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  321.955048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  321.955067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.955085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  321.955102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  321.955125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  321.955145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  321.957194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.957215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.957233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.957252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.958826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  321.958845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  321.958863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.960410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.960431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.962297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.965634] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.965667] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  321.965686] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  321.965711] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.982511] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  321.982596] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  321.982662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  321.982862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  321.982941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.999186] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  321.999234] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  321.999302] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.016311] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.016349] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.016388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.016428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.016472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.016586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.016635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.016688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.016746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.016797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.016852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.016883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.016909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.016936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.016999] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.017138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.017156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.017238] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.017268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.017300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.017334] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.017353] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.017373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.017393] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.017411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.017429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.017446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.017463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.017467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.017483] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.017527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.017559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.017587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.017617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.017644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.017677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.017704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.017734] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.017761] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.017791] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.017825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.017860] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.017959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.017989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.018015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.018044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.018069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.018098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.018131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.018162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.018193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.018220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.018248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.018282] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.018310] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.020374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.020394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.020412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.020431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.022020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.022039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.022057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.023632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.023653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.025531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.028870] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.028923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.028956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.028998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.045743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.045795] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.045866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.046050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.046132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.062421] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.062468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.062824] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.081436] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.081474] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.081595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.081643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.081697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.081740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.081785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.081830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.081882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.081932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.081981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.082030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.082070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.082113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.082212] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.082379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.082391] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.082442] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.082462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.082483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.082559] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.082590] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.082624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.082654] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.082686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.082714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.082745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.082771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.082780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.082808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.082816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.082845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.082872] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.082902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.082929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.082962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.082990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.083019] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.083046] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.083073] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.083102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.083135] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.083236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.083265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.083292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.083321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.083347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.083376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.083408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.083439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.083470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.083521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.083551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.083586] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.083615] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.085677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.085698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.085721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.085745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.087306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.087329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.087352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.088916] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.088938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.090807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.094114] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.094165] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.094197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.094238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.110968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.111018] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.111084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.111279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.111358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.127645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.127691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.127760] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.144786] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.144827] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.144872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.144912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.144955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.144995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.145034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.145073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.145117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.145158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.145200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.145242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.145281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.145319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.145392] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.145637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.145666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.145786] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.145829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.145853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.145879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.145898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.145921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.145943] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.145963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.145983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.146002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.146020] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.146024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.146042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.146047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.146066] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.146083] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.146101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.146119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.146140] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.146164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.146191] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.146216] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.146242] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.146269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.146297] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.146368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.146394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.146421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.146447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.146471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.146524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.146560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.146591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.146622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.146652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.146679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.146713] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.146742] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.148804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.148825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.148843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.148862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.150433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.150453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.150471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.152158] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.152178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.154040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.157300] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.157346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.157379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.157422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.174152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.174202] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.174267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.174463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.174743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.190861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.190908] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.190980] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.208038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.208076] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.208115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.208148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.208190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.208229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.208269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.208308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.208352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.208402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.208436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.208468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.208573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.208614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.208710] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.208899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.208927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.209053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.209096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.209146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.209199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.209240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.209285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.209328] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.209371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.209412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.209458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.209488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.209530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.209562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.209575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.209611] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.209642] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.209679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.209710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.209749] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.209782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.209818] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.209849] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.209884] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.209924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.209965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.210083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.210116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.210151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.210182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.210215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.210248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.210285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.210323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.210360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.210390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.210424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.210467] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.210521] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.212582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.212603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.212622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.212641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.214209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.214230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.214248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.215813] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.215834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.217701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.221011] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.221061] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.221091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.221131] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.237864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.237914] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.237981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.238167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.238249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.254541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.254591] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.254679] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.271691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.271728] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.271767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.271800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.271835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.271866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.271895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.271926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.271960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.271992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.272022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.272052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.272080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.272107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.272170] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.272310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.272328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.272410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.272441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.272480] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.272605] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.272651] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.272705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.272752] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.272801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.272846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.272898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.272932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.272945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.272981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.272991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.273030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.273065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.273104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.273138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.273181] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.273216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.273254] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.273288] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.273324] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.273368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.273413] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.273607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.273644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.273683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.273717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.273755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.273794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.273835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.273876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.273918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.273943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.273970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.274001] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.274031] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.276110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.276133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.276156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.276181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.277752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.277775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.277798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.279359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.279381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.281248] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.283802] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.283854] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.283886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.283927] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.300659] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.300708] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.300773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.300982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.301060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.317324] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.317367] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.317432] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.334477] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.334547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.334586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.334626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.334669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.334709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.334749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.334788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.334832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.334874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.334916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.334957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.334996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.335033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.335105] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.335252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.335271] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.335363] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.335403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.335447] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.335481] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.335556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.335607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.335647] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.335690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.335728] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.335770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.335806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.335818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.335854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.335865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.335904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.335940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.335979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.336013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.336056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.336093] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.336132] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.336167] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.336205] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.336250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.336296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.336421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.336460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.336514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.336541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.336569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.336596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.336630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.336661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.336693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.336720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.336749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.336781] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.336813] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.338884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.338904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.338922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.338941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.340530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.340550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.340567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.342135] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.342156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.344043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.347358] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.347410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.347442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.347492] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.364190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.364240] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.364310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.364772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.364854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.380901] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.380947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.381033] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.398038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.398076] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.398115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.398149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.398183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.398214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.398243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.398274] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.398310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.398342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.398373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.398404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.398432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.398459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.398625] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.398781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.398800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.398882] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.398914] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.398956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.398981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.399001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.399022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.399043] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.399063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.399082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.399101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.399119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.399124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.399141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.399145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.399164] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.399182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.399200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.399224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.399251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.399276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.399302] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.399328] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.399354] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.399381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.399409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.399484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.399538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.399570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.399598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.399626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.399655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.399688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.399719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.399749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.399776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.399803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.399835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.399864] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.401923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.401944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.401963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.401982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.403584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.403604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.403624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.405183] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.405203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.407075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.410327] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.410369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.410396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.410430] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.427187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.427237] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.427302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.427561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.427660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.443893] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.443940] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.444011] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.463038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.463075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.463114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.463148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.463182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.463212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.463240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.463271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.463306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.463337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.463368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.463398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.463432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.463455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.463593] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.463778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.463802] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.463883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.463911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.463942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.463974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.464001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.464029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.464062] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.464096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.464129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.464164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.464197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.464205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.464237] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.464244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.464278] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.464312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.464346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.464379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.464414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.464450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.464474] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.464528] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.464557] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.464590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.464623] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.464723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.464754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.464785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.464814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.464844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.464874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.464909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.464941] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.464964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.464982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.465001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.465023] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.465044] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.467089] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.467110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.467128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.467147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.468729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.468749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.468767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.470323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.470344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.472215] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.475561] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.475614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.475656] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.475681] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.492428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.492479] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.492644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.492890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.492967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.509104] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.509152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.509236] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.526251] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.526288] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.526328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.526361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.526396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.526425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.526454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.526564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.526622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.526676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.526728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.526779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.526826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.526865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.526929] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.527038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.527050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.527105] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.527125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.527148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.527172] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.527192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.527213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.527234] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  322.527254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.527273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.527292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.527310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.527315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.527333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.527337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.527356] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.527374] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.527392] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.527409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.527431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.527449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.527468] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  322.527526] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  322.527552] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  322.527583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.527615] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  322.527712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.527742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.527770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.527800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.527829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.527860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.527893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.527925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.527957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.527986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.528016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.528050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  322.528078] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.530128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.530149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.530168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.530187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.531765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.531785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.531803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.533360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.533381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.535253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.538558] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.538606] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.538636] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  322.538675] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.555414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.555464] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.555624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.555897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.555974] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.572091] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  322.572138] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.572223] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.591001] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  322.591038] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.591077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.591110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.591145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.591183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.591223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.591262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.591306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.591348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.591396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.591428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.591455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.591539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.591628] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  322.591968] [drm:drm_mode_addfb2] [FB:58]
>[  322.592006] [drm:drm_mode_addfb2] [FB:78]
>[  322.621475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  322.621579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  322.621642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.621701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.621713] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.621772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.621794] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.621816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.621840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.621858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.621879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.621899] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.621917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.621935] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.621952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.621969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.621973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.621995] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.621999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.622023] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.622047] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.622070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.622093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.622117] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.622139] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.622163] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  322.622186] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.622209] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.622233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.622259] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.625553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.625576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.625596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.625615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.625634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.625654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.625677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.625697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.625717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.625735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.625752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.625778] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.625802] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.627872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.627895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.627914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.627933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.629520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.629540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.629558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.631131] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.631154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.633032] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.636309] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.636342] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.636362] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.636388] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.653138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.653188] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.653254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.669831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.669851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.686668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.686753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.703205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.703252] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.703326] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.720391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.720429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.720468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.720582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.720644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.720693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.720741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.720789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.720844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.720895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.720945] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.720994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.721039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.721084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.721181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.721330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.721342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.721396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.721420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.721444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.721522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.721559] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.721597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.721632] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.721665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.721698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.721730] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.721760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.721770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.721799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.721807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.721837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.721867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.721898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.721925] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.721958] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.721987] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.722018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  322.722048] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.722077] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.722107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.722141] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.722241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.722272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.722303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.722333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.722362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.722393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.722426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.722459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.722517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.722547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.722575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.722610] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.722642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.724712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.724732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.724750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.724774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.726338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.726358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.726377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.727954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.727976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.729873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.733201] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.733254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.733287] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.733329] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.750036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.750086] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.750151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.750378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.750471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.766743] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.766790] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.766861] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.783887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.783924] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.783963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.783996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.784030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.784060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.784087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.784119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.784153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.784185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.784215] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.784246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.784273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.784300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.784364] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.784848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.784861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.784920] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.784946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.784974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.785003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.785028] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.785055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.785081] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.785107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.785133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.785159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.785183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.785189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.785214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.785219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.785245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.785271] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.785296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.785322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.785348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.785373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.785400] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  322.785426] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.785452] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.785516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.785551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.785814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.785837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.785857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.785877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.785895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.785916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.785939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.785959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.785980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.785998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.786017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.786040] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.786061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.788101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.788121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.788139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.788157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.789720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.789740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.789759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.791319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.791340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.793212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.796531] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.796581] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.796612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.796654] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.813373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.813423] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.813577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.813781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.813873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.830072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.830117] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.830202] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.847201] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.847238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.847278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.847310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.847353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.847393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.847432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.847472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.847595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.847649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.847697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.847750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.847798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.847844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.847945] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.848076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.848094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.848171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.848197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.848224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.848253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.848278] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.848305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.848331] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.848357] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.848383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.848409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.848433] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.848440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.848497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.848505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.848536] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.848565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.848593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.848620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.848651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.848678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.848706] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  322.848732] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.848759] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.848790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.848822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.848922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.848954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.848984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.849014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.849043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.849073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.849108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.849138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.849159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.849177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.849196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.849218] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.849244] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.851284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.851305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.851323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.851342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.852906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.852927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.852947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.854514] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.854536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.856405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.859737] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.859787] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.859818] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.859857] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.876565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.876616] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.876682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.876906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.876999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.893266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.893312] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.893399] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.910388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.910425] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.910464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.910580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.910631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.910681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.910723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.910771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.910825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.910875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.910924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.910972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.911012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.911054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.911150] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.911368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.911388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.911531] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.911566] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.911598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.911635] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.911664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.911697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.911728] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.911760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.911791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.911821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.911848] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.911857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.911883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.911890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.911918] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.911945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.911975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.912001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.912033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.912059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.912087] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  322.912113] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.912140] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.912169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.912203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.912302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.912332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.912359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.912387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.912413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.912443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.912496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.912528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.912561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.912587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.912616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.912651] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.912680] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.914744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.914768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.914790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.914815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.916379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.916400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.916419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.918015] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.918036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.919924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.923254] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.923306] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.923338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.923380] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  322.940093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.940144] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.940209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.940391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.940468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.956787] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  322.956834] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  322.956905] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  322.975555] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  322.975592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  322.975632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.975665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.975700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.975730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.975768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.975807] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  322.975851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.975893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.975935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.975976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.976011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.976031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.976071] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  322.976158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  322.976169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  322.976220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  322.976239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  322.976260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  322.976283] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.976302] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.976321] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.976340] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  322.976359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  322.976377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.976394] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  322.976410] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.976415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.976431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.976435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  322.976499] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  322.976533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.976560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.976587] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.976620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  322.976646] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.976676] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  322.976703] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  322.976732] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  322.976766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.976802] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  322.977272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  322.977303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  322.977333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  322.977360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  322.977389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  322.977417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  322.977451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  322.977510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  322.977544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  322.977571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  322.977601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  322.977636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  322.977816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  322.979881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.979902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.979923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.979947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.981559] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  322.981580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  322.981602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.983155] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.983176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.985039] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.988301] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  322.988332] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  322.988355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  322.988386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.005150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.005200] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.005266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.005648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.005727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.021827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.021873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.021958] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.039000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.039037] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.039077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.039109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.039144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.039174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.039204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.039235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.039269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.039301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.039331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.039362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.039389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.039416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.039536] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.039646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.039659] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.039713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.039734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.039756] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.039781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.039801] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.039822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.039843] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.039863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.039883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.039901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.039919] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.039924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.039942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.039946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.039965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.039982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.040000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.040017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.040038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.040057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.040075] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.040093] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.040110] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.040132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.040155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.040221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.040241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.040260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.040280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.040297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.040317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.040344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.040371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.040398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.040424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.040451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.040509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.040540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.042603] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.042625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.042647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.042671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.044244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.044265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.044283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.045845] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.045865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.047737] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.051041] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.051091] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.051122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.051163] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.067899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.067950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.068015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.068208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.068286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.084572] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.084620] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.084707] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.101725] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.101763] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.101802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.101835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.101870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.101900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.101929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.101961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.101996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.102028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.102058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.102088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.102116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.102144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.102206] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.102344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.102363] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.102445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.102562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.102613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.102669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.102713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.102760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.102815] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.102844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.102872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.102899] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.102929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.102936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.102964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.102973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.103000] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.103029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.103052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.103070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.103092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.103109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.103128] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.103145] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.103162] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.103183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.103206] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.103272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.103291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.103310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.103328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.103346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.103366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.103387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.103407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.103427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.103445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.103495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.103528] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.103557] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.105616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.105636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.105654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.105673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.107242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.107262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.107280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.108832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.108853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.110725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.114029] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.114072] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.114091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.114116] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.130888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.130938] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.131004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.131197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.131276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.147562] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.147609] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.147693] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.164710] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.164747] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.164786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.164820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.164855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.164885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.164914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.164945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.164980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.165011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.165051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.165093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.165132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.165170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.165243] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.165390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.165405] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.165564] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.165606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.165653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.165689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.165715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.165744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.165774] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.165800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.165828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.165852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.165877] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.165883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.165906] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.165912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.165937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.165960] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.165984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.166016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.166051] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.166085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.166120] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.166153] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.166187] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.166222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.166258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.166350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.166387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.166409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.166429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.166477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.166507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.166539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.166570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.166601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.166628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.166655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.166688] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.166717] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.168780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.168801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.168819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.168838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.170440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.170476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.170494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.172060] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.172084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.174003] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.177301] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.177352] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.177385] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.177427] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.194173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.194223] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.194289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.194602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.194709] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.210872] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.210920] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.210990] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.228037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.228074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.228114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.228146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.228188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.228228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.228267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.228307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.228351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.228393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.228434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.228552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.228599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.228645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.228745] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.228933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.228954] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.229019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.229041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.229065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.229090] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.229110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.229133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.229154] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.229175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.229195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.229214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.229232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.229238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.229256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.229260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.229286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.229311] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.229337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.229363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.229389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.229414] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.229439] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.229496] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.229526] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.229559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.229593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.229692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.229724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.229755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.229785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.229816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.229847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.229881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.229905] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.229925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.229944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.229962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.229985] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.230005] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.232058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.232078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.232096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.232114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.233683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.233702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.233720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.235282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.235302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.237170] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.240505] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.240554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.240585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.240625] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.257378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.257428] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.257594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.257829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.257906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.274082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.274129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.274201] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.291223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.291261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.291300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.291333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.291367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.291396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.291424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.291536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.291595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.291645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.291679] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.291710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.291740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.291768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.291833] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.291977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.291996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.292080] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.292111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.292148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.292186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.292234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.292256] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.292277] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.292298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.292317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.292336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.292354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.292360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.292377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.292381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.292400] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.292417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.292436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.292491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.292522] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.292549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.292576] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.292603] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.292628] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.292659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.292691] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.292790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.292821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.292851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.292880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.292909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.292939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.292973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.293005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.293037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.293065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.293094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.293127] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.293147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.295213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.295235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.295254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.295273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.296850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.296871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.296889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.298443] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.298481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.300350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.303611] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.303644] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.303663] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.303689] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.320459] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.320540] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.320607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.320832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.320930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.337160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.337210] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.337280] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.354287] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.354324] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.354363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.354396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.354430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.354551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.354603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.354655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.354712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.354764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.354806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.354848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.354885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.354919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.355000] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.355189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.355207] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.355280] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.355314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.355348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.355386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.355418] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.355506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.355556] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.355601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.355644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.355686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.355726] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.355738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.355781] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.355790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.355823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.355856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.355889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.355921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.355954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.355986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.356018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.356051] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.356083] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.356119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.356157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.356265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.356300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.356334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.356366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.356398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.356432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.356491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.356530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.356567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.356599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.356632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.356670] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.356704] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.358778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.358799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.358821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.358845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.360433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.360470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.360489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.362052] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.362075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.363968] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.367235] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.367283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.367318] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.367364] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.384079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.384130] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.384202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.384665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.384769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.400778] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.400824] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.400891] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.417904] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.417942] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.417982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.418015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.418049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.418080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.418109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.418140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.418175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.418207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.418238] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.418269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.418306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.418345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.418417] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.418665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.418695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.418831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.418867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.418904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.418943] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.418974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.419010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.419048] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.419090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.419131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.419172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.419208] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.419214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.419234] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.419239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.419259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.419278] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.419297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.419314] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.419336] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.419355] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.419374] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.419391] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.419409] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.419432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.419489] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.419588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.419617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.419645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.419676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.419706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.419736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.419770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.419803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.419835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.419866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.419894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.419917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.419938] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.422005] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.422026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.422044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.422068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.423641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.423664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.423687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.425237] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.425258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.427120] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.430424] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.430474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.430493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.430519] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.447282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.447332] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.447398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.447731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.447809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.463958] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.464006] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.464073] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.481114] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.481151] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.481190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.481223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.481257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.481286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.481314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.481345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.481380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.481412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.481520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.481577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.481615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.481656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.481744] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.481944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.481971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.482091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.482133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.482181] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.482231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.482270] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.482314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.482354] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.482397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.482436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.482512] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.482550] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.482562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.482605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.482615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.482649] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.482680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.482713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.482743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.482780] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.482810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.482844] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.482874] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.482905] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.482943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.482982] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.483095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.483126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.483159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.483189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.483220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.483251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.483287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.483322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.483357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.483385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.483416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.483479] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.483513] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.485606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.485629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.485651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.485675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.487239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.487260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.487279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.488840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.488861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.490730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.493966] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.493997] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.494015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.494041] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.510817] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.510862] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.510925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.511113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.511188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.527518] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.527569] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.527641] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.544666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.544704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.544743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.544776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.544810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.544840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.544869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.544907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.544951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.544993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.545035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.545076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.545117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.545136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.545176] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.545261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.545273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.545323] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.545342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.545362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.545385] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.545403] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.545422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.545505] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.545534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.545563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.545590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.545616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.545624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.545650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.545658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.545685] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.545711] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.545738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.545764] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.545795] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.545821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.545847] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.545873] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.545900] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.545934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.545967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.546066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.546096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.546126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.546157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.546186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.546217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.546250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.546283] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.546315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.546335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.546353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.546376] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.546396] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.548473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.548494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.548513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.548531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.550103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.550123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.550141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.551702] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.551723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.553593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.556907] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.556957] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.556996] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.557047] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.573754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.573804] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.573869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.574064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.574145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.590431] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.590509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.590579] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.607583] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.607625] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.607670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.607710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.607753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.607793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.607831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.607870] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.607914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.607956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.607998] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.608039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.608078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.608115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.608187] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.608334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.608353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.608444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.608567] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.608619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.608668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.608696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.608727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.608758] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.608787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.608815] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.608843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.608872] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.608880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.608909] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.608918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.608946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.608976] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.609005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.609034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.609066] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.609095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.609124] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.609153] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.609182] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.609213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.609237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.609303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.609323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.609343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.609367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.609394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.609419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.609474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.609506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.609537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.609563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.609590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.609622] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.609651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.611711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.611732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.611754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.611778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.613339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.613360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.613379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.614961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.614982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.616961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.620282] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.620334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.620367] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.620408] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.637124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.637175] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.637240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.637485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.637601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.653801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.653847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.653917] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.670971] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.671009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.671048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.671081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.671116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.671145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.671174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.671206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.671240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.671273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.671303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.671334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.671362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.671389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.671538] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.671758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.671787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.671918] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.671968] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.672014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.672051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.672082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.672115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.672147] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.672178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.672210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.672239] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.672269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.672276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.672304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.672312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.672341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.672371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.672401] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.672429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.672484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.672515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.672547] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.672577] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.672607] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.672642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.672677] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.672778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.672809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.672839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.672866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.672895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.672926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.672959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.672991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.673023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.673052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.673080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.673114] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.673145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.675207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.675228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.675246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.675264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.676836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.676856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.676873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.678422] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.678458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.680325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.683305] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.683338] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.683357] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.683382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.700133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.700184] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.700249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.700506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.700627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.716808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.716855] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.716941] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.733956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.733993] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.734033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.734072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.734116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.734156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.734195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.734234] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.734277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.734319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.734360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.734404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.734503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.734540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.734628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.734768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.734784] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.734856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.734884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.734915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.734947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.734974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.735002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.735031] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.735057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.735091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.735124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.735158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.735165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.735198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.735204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.735238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.735272] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.735305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.735339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.735373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.735410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.735469] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.735501] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.735531] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.735566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.735602] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.735710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.735736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.735758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.735777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.735797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.735817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.735841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.735862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.735884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.735903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.735923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.735947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.735969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.738033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.738053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.738072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.738091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.739669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.739689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.739706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.741254] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.741274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.743147] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.746465] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.746515] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.746547] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.746589] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.763298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.763346] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.763410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.763745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.763822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.779985] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.780031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.780116] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.798578] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.798615] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.798654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.798687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.798722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.798752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.798781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.798812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.798847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.798878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.798908] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.798939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.798966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.799001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.799054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.799176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.799192] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.799261] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.799286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.799315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.799347] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.799372] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.799399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.799494] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.799534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.799576] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.799612] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.799650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.799661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.799699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.799709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.799748] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.799784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.799824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.799859] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.799902] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.799937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.799975] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.800010] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.800055] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.800089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.800124] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.800222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.800252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.800279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.800307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.800332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.800362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.800394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.800426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.800479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.800506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.800535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.800570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.800599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.802673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.802694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.802712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.802732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.804294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.804314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.804332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.805897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.805918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.807821] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.811137] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.811190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.811226] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.811252] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.827991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.828042] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.828108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.828317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.828420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.844689] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.844737] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.844805] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.862967] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.863004] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.863044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.863083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.863127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.863167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.863206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.863245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.863289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.863331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.863372] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.863414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.863511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.863541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.863609] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.863739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.863759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.863823] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.863846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.863869] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.863895] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.863916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.863937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.863959] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.863979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.863999] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.864018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.864036] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.864040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.864058] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.864063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.864080] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.864098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.864116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.864133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.864154] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.864172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.864189] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.864207] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.864224] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.864245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.864267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.864321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.864341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.864360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.864379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.864396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.864448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.864479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.864510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.864541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.864567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.864593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.864625] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.864653] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.866703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.866726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.866746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.866767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.868304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.868325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.868344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.869877] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.869899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.871740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.875082] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.875135] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.875168] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.875211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.891955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.892006] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.892071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.892275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.892353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.908660] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.908707] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.908779] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.925843] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.925880] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.925918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.925951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.925985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.926015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.926043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.926074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.926109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.926141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.926172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.926203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.926231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.926258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.926321] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.926551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.926581] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.926716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.926761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.926816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.926877] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.926906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.926937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.926966] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.926996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.927024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.927052] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.927078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.927085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.927111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.927117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.927145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.927173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.927200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.927225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.927255] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.927281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.927308] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.927334] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.927360] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.927389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.927423] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.927543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.927571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.927601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.927627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.927654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.927682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.927712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.927743] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.927774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.927799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.927827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.927859] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.927888] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.929941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.929962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.929980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.929998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.931591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.931613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.931632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.933186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.933207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  323.935087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.938383] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  323.938512] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  323.938557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  323.938622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  323.955251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.955301] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.955366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.955686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.955765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.971950] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  323.971997] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  323.972069] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  323.990200] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  323.990238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  323.990277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.990310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.990345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.990383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.990423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.990530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  323.990589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.990637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.990689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.990741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.990787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.990833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.990912] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  323.991061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  323.991080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  323.991164] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  323.991200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.991226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  323.991256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.991281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.991308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.991334] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  323.991360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.991386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.991412] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  323.991466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.991474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.991503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.991511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  323.991540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  323.991568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.991595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.991622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.991653] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  323.991680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.991707] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  323.991733] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  323.991760] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  323.991790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.991822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  323.991922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  323.991954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  323.991984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  323.992014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  323.992043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  323.992073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  323.992106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  323.992135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  323.992155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  323.992174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  323.992192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  323.992215] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  323.992235] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  323.995365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.995387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.995405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.995482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.997054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  323.997074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  323.997092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.998653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.998674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.000549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.003890] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.003943] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.003976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.004018] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.020748] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.020794] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.020857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.021054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.021127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.037480] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.037527] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.037599] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.054667] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.054704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.054743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.054783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.054826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.054865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.054904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.054944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.054988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.055029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.055071] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.055113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.055152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.055190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.055263] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.055459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.055494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.055633] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.055693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.055741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.055791] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.055832] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.055876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.055919] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.055957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.055997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.056032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.056068] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.056077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.056112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.056121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.056159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.056193] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.056231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.056264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.056304] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.056338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.056374] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.056408] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.056479] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.056524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.056569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.056708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.056739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.056770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.056800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.056829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.056859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.056892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.056924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.056955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.056980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.057008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.057038] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.057069] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.059145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.059167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.059186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.059205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.060792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.060816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.060839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.062409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.062456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.064325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.067692] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.067745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.067778] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.067827] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.084537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.084588] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.084660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.084859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.084942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.101243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.101291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.101362] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.118484] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.118521] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.118560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.118593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.118628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.118657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.118685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.118716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.118751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.118783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.118814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.118845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.118873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.118901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.118963] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.119104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.119116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.119165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.119183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.119207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.119234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.119257] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.119282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.119314] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.119337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.119356] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.119373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.119389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.119434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.119466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.119474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.119502] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.119531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.119558] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.119587] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.119617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.119645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.119672] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.119700] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.119726] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.119759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.119793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.119891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.119919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.119947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.119974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.120002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.120030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.120061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.120092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.120122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.120148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.120174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.120207] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.120235] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.122304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.122325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.122343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.122362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.123948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.123968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.123986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.125633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.125654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.127525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.130863] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.130916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.130949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.130991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.147737] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.147788] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.147854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.148050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.148126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.164480] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.164527] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.164599] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.181630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.181668] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.181708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.181741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.181775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.181804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.181832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.181864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.181898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.181930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.181961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.181992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.182020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.182047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.182109] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.182250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.182269] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.182351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.182382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.182494] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.182529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.182558] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.182588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.182618] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.182647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.182675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.182702] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.182728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.182737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.182762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.182770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.182799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.182827] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.182854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.182880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.182912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.182934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.182952] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.182969] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.182987] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.183008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.183035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.183113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.183133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.183152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.183171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.183189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.183208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.183229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.183248] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.183268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.183293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.183318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.183345] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.183372] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.185453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.185473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.185491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.185510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.187077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.187100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.187123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.188683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.188704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.190582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.193825] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.193857] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.193876] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.193902] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.210693] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.210744] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.210809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.211011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.211088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.227395] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.227476] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.227552] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.244605] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.244641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.244680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.244713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.244748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.244777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.244805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.244837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.244872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.244904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.244934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.244964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.244991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.245018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.245081] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.245204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.245222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.245303] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.245333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.245368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.245411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.245529] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.245579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.245626] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.245670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.245715] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.245756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.245797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.245809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.245849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.245861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.245903] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.245930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.245956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.245982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.246015] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.246043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.246070] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.246097] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.246122] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.246154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.246184] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.246258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.246284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.246309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.246335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.246361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.246386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.246442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.246476] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.246508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.246540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.246567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.246598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.246630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.248681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.248701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.248719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.248738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.250296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.250316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.250334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.251913] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.251934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.253922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.257205] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.257237] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.257256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.257282] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.274034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.274085] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.274151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.274334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.274411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.290722] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.290769] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.290840] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.307868] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.307905] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.307944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.307977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.308011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.308040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.308069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.308107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.308151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.308193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.308235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.308276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.308315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.308348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.308389] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.308574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.308594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.308682] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.308712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.308745] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.308781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.308809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.308841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.308870] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.308900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.308928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.308957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.308982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.308989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.309016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.309022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.309050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.309076] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.309104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.309129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.309159] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.309185] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.309213] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.309238] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.309265] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.309293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.309326] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.309444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.309474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.309504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.309532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.309561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.309589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.309623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.309656] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.309688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.309715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.309744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.309778] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.309807] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.311888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.311910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.311932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.311956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.313546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.313568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.313587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.315137] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.315159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.317033] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.320358] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.320409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.320522] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.320600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.337196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.337246] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.337310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.337640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.337759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.353871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.353917] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.353986] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.372349] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.372387] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.372516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.372703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.372741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.372773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.372803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.372843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.372871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.372897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.372922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.372947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.372970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.372992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.373041] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.373154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.373169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.373235] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.373260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.373287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.373318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.373342] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.373368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.373394] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.373471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.373509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.373549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.373586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.373596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.373632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.373642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.373680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.373717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.373756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.373792] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.373833] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.373872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.373903] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.373932] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.373963] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.373997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.374032] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.374475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.374508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.374540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.374571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.374602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.374633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.374667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.374700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.374733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.374762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.374790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.374824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.374855] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.376976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.376997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.377015] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.377034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.378624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.378648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.378671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.380226] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.380248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.382123] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.385471] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.385525] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.385557] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.385599] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.402329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.402377] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.402535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.402743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.402817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.419037] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.419084] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.419153] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.436203] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.436240] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.436280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.436313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.436347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.436376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.436486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.436537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.436595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.436648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.436698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.436748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.436794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.436837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.436901] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.437032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.437051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.437133] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.437165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.437200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.437238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.437272] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.437292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.437313] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.437332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.437352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.437370] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.437388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.437417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.437445] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.437453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.437480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.437507] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.437533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.437559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.437590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.437616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.437643] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.437670] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.437696] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.437725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.437758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.437856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.437887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.437917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.437946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.437976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.438007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.438040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.438073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.438103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.438121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.438139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.438161] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.438183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.440231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.440254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.440277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.440301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.441880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.441901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.441919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.443507] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.443528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.445397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.448717] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.448764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.448793] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.448830] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.465575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.465626] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.465692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.465875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.465952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.482270] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.482316] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.482386] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.499492] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.499529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.499569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.499608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.499652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.499692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.499731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.499770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.499814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.499856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.499897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.499938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.499977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.500016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.500089] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.500233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.500252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.500344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.500384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.500512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.500574] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.500625] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.500680] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.500733] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.500779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.500811] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.500842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.500872] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.500881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.500910] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.500918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.500950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.500979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.501010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.501040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.501074] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.501390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.501447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.501476] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.501508] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.501639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.501673] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.501765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.501794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.501822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.501850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.501877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.501905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.501937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.501967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.501996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.502023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.502049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.502081] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.502110] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.504196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.504219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.504238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.504257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.505834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.505854] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.505872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.507449] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.507471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.509344] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.512657] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.512708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.512739] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.512780] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.529508] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.529559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.529625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.529821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.529898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.546183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.546229] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.546313] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.563302] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.563339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.563378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.563494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.563549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.563753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.563784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.563816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.563852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.563884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.563915] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.563945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.563973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.564000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.564061] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.564200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.564218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.564283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.564301] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.564321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.564344] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.564366] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.564390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.564457] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.564491] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.564519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.564549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.564576] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.564585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.564612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.564620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.564651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.564678] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.564706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.564733] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.564765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.564791] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.564820] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.564846] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.564875] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.564909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.564943] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.565322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.565352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.565383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.565437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.565467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.565500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.565533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.565677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.565706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.565730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.565756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.565787] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.565813] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.567904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.567925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.567944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.567962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.569634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.569654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.569672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.571222] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.571246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.573118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.576465] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.576515] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.576535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.576560] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.593332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.593384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.593551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.593779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.593856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.610007] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.610053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.610137] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.627151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.627188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.627227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.627260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.627302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.627342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.627382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.627498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.627557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.627612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.627662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.627712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.627754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.627798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.627880] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.628037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.628055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.628127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.628146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.628167] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.628190] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.628208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.628228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.628247] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.628266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.628284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.628301] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.628317] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.628321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.628337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.628341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.628358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.628373] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.628436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.628468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.628498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.628527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.628554] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.628583] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.628609] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.628641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.628674] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.628774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.628802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.628831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.628857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.628884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.628911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.628943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.628974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.629004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.629030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.629056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.629086] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.629116] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.631183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.631204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.631222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.631242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.632816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.632835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.632853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.634427] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.634448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.636316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.639651] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.639705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.639745] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.639796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.656529] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.656582] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.656653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.656837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.656918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.673203] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.673249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.673335] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.692007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.692045] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.692084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.692118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.692153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.692183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.692213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.692245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.692280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.692312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.692343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.692374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.692496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.692544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.692646] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.692868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.692898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.693036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.693086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.693140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.693197] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.693246] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.693294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.693327] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.693358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.693389] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.693443] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.693474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.693483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.693512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.693519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.693551] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.693580] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.693611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.693641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.693671] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.693701] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.693732] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.693761] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.693787] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.693819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.693856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.693957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.693987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.694018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.694047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.694077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.694109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.694142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.694174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.694206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.694235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.694263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.694297] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.694327] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.696499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.696529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.696547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.696566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.698140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.698160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.698178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.699734] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.699757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.701637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.704952] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.705006] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.705038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.705081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.721807] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.721860] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.721931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.722136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.722219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.738501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.738549] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.738621] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.755634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.755671] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.755711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.755743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.755778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.755817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.755857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.755896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.755940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.755982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.756024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.756065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.756104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.756143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.756215] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.756358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.756456] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.756596] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.756649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.756704] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.756760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.756791] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.756825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.756857] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.756889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.756920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.756950] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.756979] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.756986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.757014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.757021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.757050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.757079] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.757108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.757137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.757170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.757199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.757229] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.757256] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.757285] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.757318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.757352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.757469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.757502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.757534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.757565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.757594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.757626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.757660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.757692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.757724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.757750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.757779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.757813] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.757844] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.759917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.759940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.759963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.759987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.761566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.761588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.761607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.763156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.763178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.765053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.768372] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.768456] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.768489] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.768532] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.785262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.785313] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.785379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.785688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.785785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.801975] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.802021] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.802093] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.819150] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.819187] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.819226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.819259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.819293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.819322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.819350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.819382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.819502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.819559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.819610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.819661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.819703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.819746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.819842] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.820070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.820100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.820219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.820239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.820261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.820287] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.820310] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.820335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.820358] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.820427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.820462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.820491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.820521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.820529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.820558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.820566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.820596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.820623] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.820652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.820679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.820713] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.820741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.820772] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.820798] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.820827] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.820857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.820890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.820990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.821017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.821047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.821073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.821101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.821128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.821159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.821190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.821221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.821247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.821275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.821305] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.821335] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.823422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.823442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.823460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.823479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.825052] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.825071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.825094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.826656] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.826677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.828546] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.831888] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.831941] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.831973] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.832015] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.848747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.848798] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.848868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.849051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.849128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.865435] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.865481] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.865566] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.882578] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.882614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.882653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.882686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.882720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.882750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.882779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.882810] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.882853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.882895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.882936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.882978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.883016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.883054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.883125] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.883255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.883273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.883363] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.883487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.883539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.883674] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.883702] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.883735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.883765] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.883796] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.883824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.883852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.883878] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.883885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.883912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.883918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.883947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.883972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.884001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.884026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.884057] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.884083] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.884110] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.884136] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.884163] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.884192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.884224] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.884322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.884350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.884379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.884559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.884586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.884616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.884649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.884680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.884711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.884736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.884764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.884797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.884825] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.886889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.886910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.886928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.886947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.888532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.888553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.888572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.890121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.890141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.892004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.895298] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.895348] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.895380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.895485] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.912165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.912218] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.912290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.912602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.912682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.928872] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.928919] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.928990] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.947339] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  324.947376] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  324.947497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.947544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.947597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.947640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.947684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.947728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.947780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.947830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.947879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.947927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.947967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.948010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.948090] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.948233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.948246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  324.948297] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  324.948316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  324.948337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  324.948359] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.948427] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.948462] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.948492] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  324.948523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.948551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.948581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  324.948608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.948616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.948643] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.948653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  324.948683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  324.948710] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.948739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.948765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.948798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  324.948824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.948853] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  324.948880] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  324.948908] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  324.948937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.948970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  324.949068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  324.949098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  324.949125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  324.949153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  324.949178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  324.949208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  324.949240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  324.949271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  324.949301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.949327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  324.949354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  324.949414] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  324.949443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  324.951505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.951526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.951545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.951569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.953141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  324.953161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  324.953180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.954741] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.954764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.956637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.959984] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.960036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  324.960069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  324.960111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  324.976847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  324.976900] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  324.976972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  324.977171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  324.977254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.993537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  324.993584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  324.993656] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.010704] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.010746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.010790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.010831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.010874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.010914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.010953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.010993] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.011036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.011078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.011120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.011162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.011200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.011239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.011311] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.011581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.011601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.011691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.011722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.011755] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.011791] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.011819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.011851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.011880] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.011910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.011938] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.011966] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.011992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.011999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.012026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.012032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.012062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.012088] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.012115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.012141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.012171] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.012197] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.012225] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.012251] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.012278] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.012307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.012340] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.012462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.012491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.012519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.012547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.012576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.012604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.012635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.012666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.012698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.012724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.012752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.012785] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.012813] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.014878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.014899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.014917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.014935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.016525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.016545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.016564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.018111] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.018131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.020001] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.023302] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.023351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.023453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.023525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.040141] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.040190] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.040261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.040677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.040789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.056868] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.056914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.056986] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.074047] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.074085] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.074125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.074158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.074192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.074221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.074259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.074299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.074342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.074463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.074524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.074579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.074627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.074675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.074776] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.074978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.075007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.075114] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.075154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.075185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.075219] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.075247] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.075278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.075308] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.075337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.075376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.075436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.075468] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.075478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.075507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.075515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.075546] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.075577] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.075607] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.075637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.075670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.075700] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.075732] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.075759] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.075789] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.075822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.075858] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.075943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.075974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.076004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.076034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.076064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.076094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.076127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.076159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.076191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.076220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.076249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.076283] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.076314] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.078425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.078446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.078464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.078483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.080049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.080071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.080090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.081644] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.081666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.083542] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.086882] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.086935] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.086968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.087010] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.103755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.103805] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.103872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.104071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.104153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.120461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.120508] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.120597] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.137652] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.137688] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.137727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.137761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.137795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.137825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.137854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.137886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.137928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.137970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.138011] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.138053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.138092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.138130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.138202] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.138344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.138441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.138567] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.138602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.138637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.138676] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.138707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.138740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.138773] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.138805] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.138834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.138864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.138890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.138898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.138924] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.138931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.138959] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.138985] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.139013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.139038] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.139070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.139096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.139123] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.139149] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.139176] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.139208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.139242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.139341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.139371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.139425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.139453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.139483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.139511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.139544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.139577] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.139610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.139636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.139665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.139700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.139729] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.141798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.141819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.141837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.141856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.143424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.143445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.143463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.145013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.145034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.146906] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.150200] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.150251] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.150283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.150324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.167065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.167116] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.167182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.167449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.167562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.183775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.183822] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.183893] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.202426] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.202463] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.202502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.202535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.202568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.202597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.202624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.202655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.202689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.202721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.202751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.202782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.202809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.202836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.202898] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.203028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.203039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.203089] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.203107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.203127] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.203150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.203168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.203187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.203205] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.203223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.203240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.203256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.203272] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.203276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.203292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.203296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.203312] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.203328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.203350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.203419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.203454] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.203482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.203513] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.203539] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.203568] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.203602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.203636] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.203734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.203765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.203795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.203823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.203851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.203878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.203909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.203942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.203973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.203999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.204026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.204056] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.204086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.206154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.206178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.206201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.206225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.207804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.207827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.207850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.210510] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.210544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.212416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.215763] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.215819] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.215859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.215911] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.232629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.232679] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.232745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.232941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.233019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.249334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.249464] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.249573] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.266628] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.266665] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.266704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.266738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.266773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.266802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.266831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.266863] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.266898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.266930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.266961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.266992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.267020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.267047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.267109] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.267232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.267250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.267331] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.267363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.267459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.267497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.267527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.267561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.267591] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.267622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.267653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.267682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.267709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.267718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.267745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.267753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.267784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.267811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.267840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.267866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.267898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.267923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.267951] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.267976] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.268005] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.268038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.268071] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.268154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.268182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.268210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.268236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.268264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.268295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.268327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.268360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.268413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.268441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.268470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.268500] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.268532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.270596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.270616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.270639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.270663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.272235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.272256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.272275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.273826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.273846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.275703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.279019] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.279068] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.279099] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.279138] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.295866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.295917] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.295988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.296177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.296259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.312541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.312588] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.312657] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.331492] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.331530] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.331569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.331602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.331635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.331670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.331710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.331750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.331794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.331836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.331882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.331914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.331941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.331966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.332023] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.332147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.332164] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.332238] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.332265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.332297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.332330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.332357] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.332459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.332512] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.332556] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.332602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.332644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.332686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.332698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.332737] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.332748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.332790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.332831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.332881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.332910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.332944] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.332974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.333004] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.333034] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.333064] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.333098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.333133] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.333216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.333247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.333277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.333307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.333336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.333389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.333423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.333453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.333486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.333516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.333545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.333579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.333612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.335685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.335705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.335723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.335741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.337365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.337407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.337427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.338989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.339010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.340894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.344170] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.344202] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.344222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.344247] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.361005] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.361056] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.361126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.361307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.361468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.377679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.377726] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.377794] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.394831] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.394868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.394907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.394941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.394975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.395013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.395053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.395093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.395136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.395178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.395219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.395261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.395298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.395320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.395424] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.395573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.395593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.395682] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.395712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.395746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.395781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.395809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.395840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.395870] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.395900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.395929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.395957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.395983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.395990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.396017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.396024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.396053] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.396079] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.396107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.396133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.396163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.396189] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.396217] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.396242] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.396270] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.396298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.396330] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.396451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.396480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.396510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.396537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.396567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.396595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.396627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.396658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.396690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.396716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.396744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.396777] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.396806] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.398870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.398890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.398908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.398927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.400508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.400530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.400548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.402101] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.402122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.404001] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.407325] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.407444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.407502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.407572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.424160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.424210] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.424276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.424665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.424743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.440845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.440889] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.440956] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.459112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.459149] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.459188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.459221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.459255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.459284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.459313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.459344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.459473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.459528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.459580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.459632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.459677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.459715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.459778] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.459894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.459906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.459960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.459981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.460003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.460032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.460057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.460084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.460110] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.460136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.460162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.460187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.460211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.460217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.460238] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.460243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.460270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.460295] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.460322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.460348] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.460410] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.460444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.460474] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.460503] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.460530] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.460561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.460594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.460678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.460708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.460736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.460765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.460795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.460827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.460860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.460893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.460925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.460954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.460983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.461018] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.461045] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.463098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.463120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.463139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.463158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.464731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.464751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.464769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.466342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.466376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.468242] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.471606] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.471659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.471691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.471733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.488456] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.488506] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.488572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.488754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.488831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.505162] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.505213] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.505290] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.522361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.522433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.522472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.522504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.522538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.522567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.522595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.522633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.522677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.522718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.522760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.522801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.522840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.522879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.522951] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.523107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.523126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.523218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.523258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.523299] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.523323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.523345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.523415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.523453] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.523483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.523515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.523543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.523572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.523581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.523609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.523617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.523647] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.523673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.523703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.523729] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.523761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.523787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.523817] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.523843] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.523873] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.523904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.523938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.524038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.524066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.524094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.524120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.524147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.524174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.524206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.524237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.524268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.524294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.524321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.524352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.524407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.526472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.526495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.526518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.526541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.528115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.528138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.528161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.529717] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.529738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.531607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.534915] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.534966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.534998] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.535039] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.551769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.551819] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.551885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.552079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.552156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.568443] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.568490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.568574] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.587535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.587573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.587613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.587646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.587680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.587709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.587738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.587770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.587805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.587836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.587876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.587918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.587957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.587995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.588068] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.588214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.588233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.588324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.588450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.588503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.588559] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.588604] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.588652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.588699] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.588746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.588791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.588835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.588864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.588872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.588899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.588908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.588936] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.588965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.588990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.589008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.589030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.589048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.589066] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.589084] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.589101] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.589123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.589146] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.589214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.589233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.589251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.589270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.589288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.589307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.589333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.589387] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.589418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.589445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.589472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.589504] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.589533] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.591619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.591641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.591660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.591680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.593252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.593272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.593290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.594885] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.594907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.596818] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.600096] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.600128] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.600148] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.600173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.616938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.616989] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.617054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.617266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.617451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.633636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.633684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.633752] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.650799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.650836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.650876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.650909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.650942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.650971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.651000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.651032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.651066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.651099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.651130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.651161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.651188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.651216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.651287] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.651457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.651470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.651526] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.651547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.651571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.651596] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.651615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.651638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.651659] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.651680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.651700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.651719] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.651737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.651743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.651760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.651764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.651784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.651801] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.651827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.651853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.651879] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.651905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.651931] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.651960] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.651991] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.652024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.652058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.652156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.652186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.652215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.652243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.652270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.652300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.652332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.652391] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.652422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.652449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.652476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.652510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.652540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.654719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.654743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.654766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.654790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.656392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.656414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.656432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.658004] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.658025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.659887] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.663183] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.663234] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.663266] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.663308] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.680034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.680084] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.680150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.680397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.680514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.696758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.696809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.696885] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.713966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.714004] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.714043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.714076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.714109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.714148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.714187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.714227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.714271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.714312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.714354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.714478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.714524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.714570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.714670] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.714867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.714887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.714948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.714974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.715001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.715031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.715056] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.715082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.715108] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.715134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.715160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.715186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.715210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.715217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.715241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.715246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.715273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.715298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.715325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.715383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.715416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.715446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.715475] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.715503] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.715529] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.715560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.715593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.715693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.715726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.715756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.715785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.715814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.715845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.715879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.715908] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.715929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.715953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.715980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.716007] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.716033] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.718095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.718117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.718135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.718154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.719720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.719741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.719759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.721396] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.721417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.723287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.726638] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.726691] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.726723] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.726765] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.743500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.743550] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.743617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.743810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.743888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.760175] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.760221] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.760289] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.777324] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.777395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.777435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.777468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.777502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.777540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.777580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.777619] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.777663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.777705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.777746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.777788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.777827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.777863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.777936] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.778078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.778097] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.778188] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.778228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.778270] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.778295] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.778314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.778335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.778409] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.778439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.778468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.778496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.778522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.778531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.778557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.778564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.778592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.778618] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.778645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.778672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.778702] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.778728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.778755] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.778782] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.778808] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.778839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.778871] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.778968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.778991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.779010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.779029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.779046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.779066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.779086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.779106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.779125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.779143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.779160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.779183] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.779202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.781239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.781260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.781278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.781297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.782910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.782930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.782952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.784509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.784530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.786391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.789657] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.789691] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.789714] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.789746] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.806503] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.806553] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.806618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.806815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.806893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.823177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.823224] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.823292] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.840326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.840398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.840437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.840470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.840504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.840534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.840563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.840594] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.840629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.840660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.840691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.840721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.840749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.840778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.840816] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.840904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.840915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.840965] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.840983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.841004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.841026] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.841044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.841063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.841082] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.841104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.841127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.841151] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.841173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.841178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.841200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.841204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.841228] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.841251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.841275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.841298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.841321] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.841397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.841428] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.841456] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.841484] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.841516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.841549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.841647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.841677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.841705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.841732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.841758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.841788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.841815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.841836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.841856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.841874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.841892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.841914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.841934] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.844096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.844117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.844136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.844155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.845732] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.845752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.845769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.847323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.847360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.849219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.852545] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.852596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.852628] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.852669] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.869408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.869459] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.869524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.869705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.869782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.886055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.886103] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.886187] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.903201] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.903238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.903278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.903311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.903425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.903471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.903519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.903566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.903621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.903671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.903720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.903768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.903809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.903854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.903951] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.904148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.904177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.904274] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.904293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.904314] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.904390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.904420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.904454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.904485] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.904517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.904547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.904577] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.904604] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.904613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.904641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.904648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.904678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.904706] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.904733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.904760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.904792] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.904818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.904847] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.904873] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.904901] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.904933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.904966] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.905066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.905094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.905123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.905148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.905176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.905203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.905234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.905265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.905297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.905322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.905373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.905405] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.905437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.907498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.907519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.907537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.907556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.909126] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.909147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.909165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.910729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.910750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.912620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.915924] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.915975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.916013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.916064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.932780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.932831] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.932897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.933089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.933167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.949457] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  325.949503] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  325.949587] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.966611] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  325.966649] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  325.966688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.966721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.966756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.966786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.966816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.966848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.966883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.966915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.966946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.966977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.967004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.967041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.967114] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.967257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.967276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  325.967451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  325.967500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.967556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  325.967613] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.967658] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.967720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.967751] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  325.967781] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.967809] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.967839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  325.967865] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.967873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.967900] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.967907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  325.967938] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  325.967964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.967991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.968016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.968047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  325.968073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.968100] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  325.968126] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  325.968153] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  325.968182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.968214] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  325.968313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  325.968365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  325.968396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  325.968424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  325.968453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  325.968482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  325.968515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  325.968549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  325.968582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.968609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  325.968636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  325.968666] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  325.968697] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  325.970765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.970785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.970804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.970822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.972430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  325.972454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  325.972477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.974017] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.974041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  325.975894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.979162] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.979206] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  325.979235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  325.979273] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  325.996007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  325.996060] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  325.996131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  325.996568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  325.996649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.012681] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.012728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.012813] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.029864] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.029901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.029941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.029973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.030007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.030038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.030067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.030102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.030154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.030187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.030217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.030255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.030292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.030329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.030472] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.030688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.030716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.030843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.030889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.030937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.030990] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.031031] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.031077] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.031120] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.031170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.031202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.031236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.031267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.031275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.031306] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.031342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.031380] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.031414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.031450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.031481] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.031520] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.031552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.031587] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.031624] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.031659] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.031698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.031739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.031857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.031890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.031924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.031955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.031988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.032020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.032058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.032095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.032132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.032163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.032199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.032233] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.032261] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.034368] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.034389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.034407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.034426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.035994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.036014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.036033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.037590] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.037611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.039487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.042812] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.042862] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.042892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.042932] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.059644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.059693] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.059761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.059950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.060029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.076325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.076418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.076488] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.093513] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.093550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.093589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.093622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.093657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.093686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.093715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.093747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.093782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.093814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.093845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.093875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.093903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.093930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.093993] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.094121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.094139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.094221] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.094252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.094287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.094324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.094441] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.094488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.094535] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.094580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.094634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.094661] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.094687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.094696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.094722] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.094729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.094756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.094783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.094809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.094835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.094865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.094891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.094921] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.094949] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.094975] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.095006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.095040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.095108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.095128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.095148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.095166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.095185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.095204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.095225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.095245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.095271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.095296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.095323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.095378] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.095408] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.097473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.097494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.097512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.097531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.099090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.099110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.099127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.100679] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.100700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.102573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.105867] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.105899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.105919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.105949] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.122730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.122781] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.122851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.123053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.123132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.139410] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.139454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.139524] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.156570] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.156612] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.156656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.156696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.156740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.156779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.156818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.156857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.156900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.156942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.156988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.157019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.157045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.157069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.157124] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.157240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.157256] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.157326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.157437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.157486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.157535] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.157577] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.157623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.157666] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.157711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.157753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.157794] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.157832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.157843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.157882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.157892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.157931] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.157969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.158010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.158040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.158073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.158102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.158131] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.158160] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.158189] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.158222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.158256] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.158378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.158407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.158438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.158469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.158496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.158526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.158559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.158591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.158623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.158651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.158677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.158710] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.158742] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.160833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.160856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.160879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.160903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.162490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.162512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.162531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.164090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.164111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.165973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.169226] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.169257] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.169276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.169302] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.186087] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.186138] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.186204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.186518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.186625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.202760] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.202811] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.202886] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.219911] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.219948] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.219987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.220020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.220055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.220084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.220113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.220144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.220178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.220210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.220241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.220271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.220299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.220397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.220461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.220580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.220592] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.220646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.220667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.220690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.220715] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.220735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.220756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.220777] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.220797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.220816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.220835] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.220853] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.220858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.220876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.220880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.220899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.220916] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.220935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.220952] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.220975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.220999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.221025] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.221051] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.221077] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.221104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.221132] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.221202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.221229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.221255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.221282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.221306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.221360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.221393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.221426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.221457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.221484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.221511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.221545] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.221574] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.223635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.223656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.223674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.223693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.225263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.225284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.225302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.226978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.226999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.228872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.232162] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.232211] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.232243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.232284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.249033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.249084] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.249154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.249448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.249567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.265711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.265758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.265827] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.282855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.282893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.282932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.282965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.283000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.283029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.283058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.283089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.283124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.283155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.283187] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.283217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.283245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.283272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.283425] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.283625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.283655] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.283796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.283829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.283863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.283900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.283931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.283963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.283996] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.284027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.284058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.284088] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.284117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.284125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.284153] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.284160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.284190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.284219] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.284250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.284278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.284311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.284367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.284398] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.284429] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.284459] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.284494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.284529] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.284629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.284660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.284690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.284720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.284749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.284780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.284813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.284845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.284877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.284906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.284935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.284968] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.285000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.287063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.287084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.287102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.287121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.288696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.288716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.288734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.290312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.290350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.292219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.295524] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.295574] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.295613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.295664] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.312381] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.312431] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.312497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.312679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.312756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.329058] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.329104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.329171] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.346208] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.346245] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.346285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.346318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.346449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.346500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.346548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.346597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.346653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.346704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.346753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.346803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.346849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.346896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.346992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.347190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.347209] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.347273] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.347292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.347313] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.347390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.347423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.347459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.347493] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.347527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.347560] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.347591] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.347621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.347629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.347659] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.347667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.347697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.347727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.347759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.347789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.347822] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.347850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.347882] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.347911] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.347936] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.347968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.348003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.348100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.348130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.348160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.348190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.348220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.348251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.348283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.348316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.348373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.348401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.348431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.348467] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.348499] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.350563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.350587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.350609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.350633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.352196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.352217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.352235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.353795] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.353816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.355729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.359050] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.359102] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.359134] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.359175] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.375891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.375941] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.376007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.376199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.376276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.392598] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.392647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.392725] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.411268] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.411306] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.411430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.411484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.411541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.411590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.411628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.411660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.411698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.411731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.411771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.411804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.411823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.411841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.411882] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.411981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.411994] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.412049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.412074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.412101] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.412130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.412156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.412182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.412208] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.412234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.412259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.412284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.412310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.412339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.412372] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.412380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.412411] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.412440] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.412469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.412496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.412526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.412553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.412581] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.412607] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.412633] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.412663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.412695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.412779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.412807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.412835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.412865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.412895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.412926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.412959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.412992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.413024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.413053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.413081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.413115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.413148] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.415194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.415215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.415233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.415252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.416844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.416864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.416881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.418543] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.418566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.420429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.423766] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.423818] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.423857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.423908] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.440642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.440692] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.440757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.440956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.441033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.457363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.457411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.457482] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.474531] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.474568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.474608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.474640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.474675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.474704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.474733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.474764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.474798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.474831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.474862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.474902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.474940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.474979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.475051] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.475193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.475204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.475256] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.475277] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.475298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.475386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.475415] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.475447] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.475477] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.475506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.475534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.475562] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.475588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.475596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.475622] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.475630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.475657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.475687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.475716] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.475742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.475772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.475801] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.475825] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.475844] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.475861] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.475882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.475906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.475972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.475992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.476011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.476029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.476046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.476066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.476086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.476106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.476125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.476143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.476161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.476184] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.476204] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.479425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.479461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.479492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.479523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.481127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.481156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.481182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.482730] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.482751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.484621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.487965] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.488017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.488050] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.488092] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.504833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.504883] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.504949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.505133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.505210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.521540] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.521585] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.521656] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.538671] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.538708] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.538749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.538782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.538816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.538846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.538876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.538908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.538949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.538991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.539033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.539074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.539113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.539152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.539224] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.539468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.539494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.539584] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.539619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.539655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.539698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.539720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.539742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.539763] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.539784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.539804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.539823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.539841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.539846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.539863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.539868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.539886] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.539904] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.539922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.539939] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.539960] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.539978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.539996] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.540013] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.540030] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.540051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.540074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.540140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.540160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.540179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.540197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.540215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.540240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.540267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.540294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.540348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.540377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.540404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.540436] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.540466] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.542552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.542573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.542592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.542616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.544188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.544209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.544227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.545791] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.545812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.547714] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.550959] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.550992] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.551015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.551046] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.567806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.567857] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.567927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.568125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.568205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.584500] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.584547] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.584632] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.601655] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.601692] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.601732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.601765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.601800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.601830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.601859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.601891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.601926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.601958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.601989] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.602020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.602049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.602076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.602132] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.602219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.602231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.602281] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.602300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.602383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.602422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.602451] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.602484] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.602514] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.602545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.602574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.602603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.602630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.602639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.602666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.602674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.602704] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.602731] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.602759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.602786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.602818] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.603195] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.603224] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.603254] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.603281] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.603338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.603375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.603589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.603616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.603643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.603668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.603694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.603719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.603749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.603778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.603808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.603832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.603858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.603888] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.603915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.605994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.606017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.606040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.606064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.607631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.607652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.607670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.609221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.609242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.611115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.614428] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.614469] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.614495] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.614528] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.631277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.631405] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.631501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.631699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.631774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.647930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.647977] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.648064] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.665098] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.665135] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.665174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.665207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.665249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.665289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.665405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.665453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.665511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.665565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.665615] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.665664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.665704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.665746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.665809] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.665964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.665982] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.666056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.666076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.666097] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.666123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.666146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.666171] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.666194] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.666218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.666241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.666264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.666287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.666331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.666369] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.666377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.666411] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.666441] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.666473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.666501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.666535] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.666562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.666593] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.666620] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.666649] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.666684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.666719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.666817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.666849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.666876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.666905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.666930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.666960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.666992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.667024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.667056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.667082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.667109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.667140] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.667170] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.669242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.669262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.669281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.669343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.670913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.670934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.670952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.672511] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.672532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.674391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.677726] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.677778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.677811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.677853] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.694605] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.694656] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.694722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.694904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.694982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.711278] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.711358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.711443] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.728449] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.728487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.728526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.728559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.728601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.728641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.728681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.728721] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.728764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.728806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.728848] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.728889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.728928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.728967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.729039] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.729145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.729156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.729209] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.729229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.729251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.729274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.729292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.729374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.729405] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.729438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.729467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.729497] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.729524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.729533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.729560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.729568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.729599] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.729627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.729656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.729682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.729714] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.729741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.729770] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.729797] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.729825] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.729859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.729894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.730384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.730415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.730445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.730473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.730502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.730530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.730562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.730593] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.730624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.730650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.730678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.730708] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.730738] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.732798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.732818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.732837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.732856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.734457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.734481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.734505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.736055] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.736078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.737954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.741284] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.741335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.741354] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.741380] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.758167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.758217] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.758283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.758667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.758759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.774864] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.774910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.774995] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.792000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.792037] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.792077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.792110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.792145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.792175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.792204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.792235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.792270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.792302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.792417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.792469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.792517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.792554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.792632] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.792812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.792836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.792944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.792980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.793021] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.793065] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.793099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.793138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.793174] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.793210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.793244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.793281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.793346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.793357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.793391] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.793401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.793438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.793472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.793515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.793542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.793577] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.793605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.793637] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.793665] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.793694] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.793724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.793758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.793861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.793891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.793918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.793948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.793974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.794006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.794039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.794071] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.794103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.794129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.794157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.794188] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.794219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.796307] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.796353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.796371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.796390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.797969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.797993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.798013] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.799557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.799578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.801474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.804754] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.804786] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.804806] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.804831] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.821576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.821625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.821688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.821917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.822009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.838269] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.838392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.838480] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.856636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.856673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.856713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.856747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.856782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.856813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.856842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.856873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.856908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.856939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.856970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.857001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.857029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.857057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.857120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.857264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.857333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.857689] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.857725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.857762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.857802] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.857839] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.857862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.857883] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.857905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.857924] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.857944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.857962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.857968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.857985] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.857989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.858009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.858033] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.858060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.858085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.858112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.858137] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.858163] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.858188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.858213] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.858240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.858268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.858388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.858608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.858631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.858652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.858673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.858693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.858717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.858738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.858760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.858778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.858798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.858824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.858850] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.860895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.860915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.860933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.860953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.862531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.862551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.862569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.864118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.864139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.866003] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.869236] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.869269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.869288] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.869382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.886057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.886105] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.886169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.886430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.886538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.902760] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.902808] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.902896] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.919946] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.919983] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.920022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.920055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.920089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.920119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.920148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.920179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.920213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.920245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.920276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.920393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.920429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.920464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.920546] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.920659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.920675] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.920746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.920772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.920802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.920835] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.920861] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.920895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.920929] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.920963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.920997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.921031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.921064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.921071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.921104] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.921110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.921144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.921174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.921208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.921242] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.921275] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.921345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.921387] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.921428] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.921460] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.921496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.921532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.921639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.921673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.921706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.921738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.921770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.921804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.921841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.921877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.921912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.921943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.921967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.921991] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.922015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.924064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.924085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.924103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.924122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.925695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.925715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.925735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.927290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.927324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.929195] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.932562] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.932596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.932619] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.932650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.949408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.949459] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.949524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.949720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.949798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.966082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  326.966129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  326.966197] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.983233] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  326.983271] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  326.983398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.983451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.983510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.983557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.983590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.983622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  326.983667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.983711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.983754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.983792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.983812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.983832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.983874] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  326.983967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  326.983980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  326.984033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  326.984055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.984077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  326.984106] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.984131] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.984158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.984184] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  326.984207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.984233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.984259] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.984284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.984319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.984350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.984358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  326.984388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  326.984417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.984445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.984472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.984502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  326.984529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.984556] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  326.984583] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  326.984609] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  326.984640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.984672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  326.984771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.984800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  326.984827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  326.984859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  326.984888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  326.984919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  326.984953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  326.984986] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  326.985018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  326.985047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  326.985076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  326.985110] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  326.985138] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  326.987178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.987201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.987224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.987248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.988857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  326.988880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  326.988902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.990465] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.990487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  326.992351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.995687] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.995740] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  326.995773] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  326.995814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.012564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.012614] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.012680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.012876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.012954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.029271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.029357] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.029430] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.046481] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.046519] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.046558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.046592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.046626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.046655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.046684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.046715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.046749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.046782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.046812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.046842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.046870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.046897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.046967] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.047112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.047131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.047214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.047241] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.047270] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.047370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.047408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.047449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.047488] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.047526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.047563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.047598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.047634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.047647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.047681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.047691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.047730] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.047768] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.047804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.047841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.047884] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.047921] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.047960] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.047997] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.048035] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.048077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.048122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.048233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.048254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.048272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.048320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.048348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.048376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.048407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.048437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.048467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.048493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.048520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.048555] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.048584] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.050646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.050667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.050689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.050713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.052274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.052322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.052343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.053896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.053917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.055815] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.059146] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.059199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.059232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.059274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.075978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.076028] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.076093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.076385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.076499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.092654] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.092702] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.092772] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.109830] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.109872] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.109917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.109957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.110001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.110040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.110079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.110118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.110162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.110204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.110246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.110287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.110399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.110448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.110553] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.110726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.110746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.110842] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.110869] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.110900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.110933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.110960] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.110989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.111017] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.111044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.111070] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.111096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.111120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.111127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.111151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.111157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.111184] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.111208] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.111234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.111257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.111297] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.111353] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.111381] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.111410] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.111437] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.111470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.111505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.111602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.111630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.111658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.111685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.111712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.111739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.111770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.111801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.111832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.111858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.111885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.111915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.111945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.114018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.114039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.114058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.114077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.115645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.115665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.115685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.117279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.117315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.119174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.122555] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.122608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.122641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.122682] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.139387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.139438] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.139505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.139696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.139773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.156061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.156108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.156175] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.173211] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.173248] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.173287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.173402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.173459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.173502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.173547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.173591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.173647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.173697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.173745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.173794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.173834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.173877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.173973] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.174187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.174202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.174270] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.174340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.174387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.174434] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.174471] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.174513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.174551] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.174590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.174627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.174666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.174699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.174711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.174745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.174754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.174790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.174822] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.174858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.174890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.174929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.174961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.174996] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.175027] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.175061] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.175101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.175142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.175253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.175282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.175338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.175367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.175397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.175427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.175462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.175495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.175528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.175555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.175584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.175616] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.175647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.177720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.177741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.177763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.177788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.179390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.179411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.179429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.180987] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.181008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.182882] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.186176] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.186226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.186258] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.186356] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.203046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.203097] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.203163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.203482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.203593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.219722] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.219769] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.219839] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.236865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.236902] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.236942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.236975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.237010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.237039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.237068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.237099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.237133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.237165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.237195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.237226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.237254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.237281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.237444] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.237656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.237670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.237725] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.237746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.237769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.237794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.237814] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.237836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.237857] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.237877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.237897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.237915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.237933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.237938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.237955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.237959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.237977] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.237995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.238013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.238030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.238052] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.238069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.238087] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.238104] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.238122] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.238142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.238166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.238231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.238250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.238269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.238328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.238358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.238386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.238418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.238447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.238478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.238504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.238531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.238563] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.238593] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.240660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.240682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.240700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.240719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.242282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.242319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.242337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.243891] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.243912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.245835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.249154] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.249201] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.249230] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.249267] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.265996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.266046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.266112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.266392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.266508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.282701] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.282747] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.282818] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.301422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.301460] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.301500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.301533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.301567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.301597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.301626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.301658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.301693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.301724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.301756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.301786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.301814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.301841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.301903] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.302028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.302046] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.302125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.302144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.302165] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.302192] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.302215] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.302239] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.302262] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.302344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.302375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.302406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.302433] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.302442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.302470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.302478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.302508] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.302535] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.302564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.302591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.302623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.302650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.302679] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.302705] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.302735] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.302766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.302800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.303264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.303319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.303352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.303381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.303516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.303545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.303578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.303610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.303641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.303667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.303695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.303725] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.303756] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.305880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.305900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.305918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.305937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.307527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.307549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.307568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.309122] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.309144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.311017] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.314343] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.314377] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.314401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.314432] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.331188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.331238] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.331399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.331578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.331654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.347881] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.347927] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.347998] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.365018] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.365056] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.365095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.365128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.365163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.365192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.365230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.365270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.365397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.365453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.365507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.365559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.365613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.365653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.365716] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.365837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.365853] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.365923] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.365950] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.365981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.366019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.366052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.366088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.366121] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.366155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.366189] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.366224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.366256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.366300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.366343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.366352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.366394] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.366432] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.366470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.366506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.366547] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.366583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.366628] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.366657] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.366686] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.366721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.366756] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.366863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.366897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.366929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.366961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.366993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.367026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.367062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.367097] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.367131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.367152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.367171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.367196] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.367218] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.369320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.369342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.369360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.369380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.370962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.370982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.371000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.372564] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.372585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.374455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.377802] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.377833] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.377852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.377877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.394641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.394686] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.394748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.394970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.395063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.411366] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.411412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.411477] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.428498] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.428535] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.428575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.428608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.428642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.428681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.428720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.428760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.428804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.428845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.428887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.428928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.428967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.429003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.429045] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.429131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.429143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.429194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.429214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.429236] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.429259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.429344] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.429376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.429406] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.429435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.429464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.429491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.429517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.429526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.429552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.429559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.429586] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.429613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.429640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.429666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.429699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.429727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.429755] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.429781] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.429808] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.429841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.429867] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.429932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.429952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.429971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.429989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.430007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.430027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.430047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.430067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.430087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.430105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.430122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.430145] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.430165] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.432221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.432241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.432259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.432336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.433910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.433930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.433948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.435511] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.435532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.437405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.440732] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.440785] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.440820] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.440871] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.457548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.457598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.457668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.457899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.457988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.474266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.474344] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.474412] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.491400] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.491438] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.491477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.491510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.491544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.491574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.491603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.491641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.491685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.491727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.491768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.491810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.491848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.491887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.491959] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.492090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.492109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.492200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.492241] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.492281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.492408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.492456] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.492501] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.492532] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.492561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.492590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.492617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.492643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.492652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.492678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.492685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.492713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.492742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.492770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.492796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.492826] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.492853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.492884] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.492914] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.492943] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.492976] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.493011] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.493109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.493140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.493170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.493198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.493218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.493238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.493260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.493317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.493347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.493373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.493400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.493433] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.493461] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.495523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.495546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.495569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.495593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.497164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.497184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.497203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.498787] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.498807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.500693] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.504016] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.504063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.504091] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.504129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.520855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.520906] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.520975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.521178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.521280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.537553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.537599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.537665] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.554685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.554727] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.554771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.554811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.554855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.554894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.554933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.554972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.555016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.555058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.555099] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.555140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.555179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.555217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.555369] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.555590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.555618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.555730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.555770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.555812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.555861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.555884] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.555909] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.555931] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.555954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.555973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.555993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.556010] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.556015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.556033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.556037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.556056] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.556074] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.556093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.556110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.556132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.556156] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.556183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.556208] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.556235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.556263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.556323] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.556424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.556454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.556483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.556515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.556545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.556577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.556610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.556644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.556676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.556706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.556731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.556756] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.556781] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.558855] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.558875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.558893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.558911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.560479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.560499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.560517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.562076] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.562096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.563970] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.567188] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.567218] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.567241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.567333] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.584030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.584081] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.584147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.584544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.584629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.600738] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.600785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.600857] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.619215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.619252] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.619374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.619420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.619474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.619517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.619562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.619606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.619662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.619713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.619762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.619811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.619851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.619894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.619992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.620211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.620231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.620378] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.620408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.620443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.620479] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.620509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.620542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.620571] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.620601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.620629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.620657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.620683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.620690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.620719] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.620725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.620755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.620780] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.620808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.620833] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.620864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.620890] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.620917] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.620943] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.620970] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.620999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.621032] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.621115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.621142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.621171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.621197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.621224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.621251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.621307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.621340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.621373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.621400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.621429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.621464] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.621492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.623569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.623591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.623610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.623630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.625190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.625211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.625229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.626836] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.626856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.628745] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.632065] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.632120] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.632160] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.632211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.648916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.648966] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.649032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.649230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.649403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.665609] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.665655] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.665726] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.682745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.682782] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.682821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.682854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.682889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.682919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.682949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.682980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.683015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.683046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.683086] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.683128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.683167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.683206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.683344] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.683572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.683601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.683730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.683763] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.683788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.683813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.683834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.683855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.683877] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.683898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.683919] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.683937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.683957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.683962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.683980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.683985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.684003] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.684029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.684055] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.684080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.684107] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.684131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.684158] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.684184] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.684210] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.684236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.684293] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.684395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.684425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.684455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.684486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.684516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.684549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.684583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.684616] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.684649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.684674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.684692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.684715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.684741] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.686783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.686804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.686821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.686840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.688428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.688448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.688469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.690036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.690060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.691948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.695256] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.695336] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.695366] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.695406] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.712161] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.712212] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.712423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.712638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.712715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.728814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.728857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.728923] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.745963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.746000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.746039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.746072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.746107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.746137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.746166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.746197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.746231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.746263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.746375] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.746428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.746472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.746518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.746616] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.746834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.746863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.746996] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.747041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.747095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.747128] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.747154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.747182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.747209] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.747236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.747305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.747335] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.747364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.747373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.747402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.747410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.747440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.747466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.747496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.747522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.747554] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.747581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.747609] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.747635] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.747664] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.747697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.747732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.747831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.747861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.747890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.747916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.747943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.747971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.748002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.748033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.748064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.748089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.748116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.748146] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.748176] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.751408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.751449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.751488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.751528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.753132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.753172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.753194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.754748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.754769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.756661] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.759974] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.760025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.760057] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.760098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.776823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.776874] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.776939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.777132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.777209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.793501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.793548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.793617] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.810648] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.810685] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.810725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.810758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.810793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.810824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.810854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.810886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.810921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.810954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.810985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.811016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.811044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.811082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.811155] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.811624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.811644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.811734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.811766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.811800] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.811837] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.811866] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.811898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.811927] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.811958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.811987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.812016] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.812042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.812049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.812075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.812082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.812110] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.812136] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.812164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.812189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.812220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.812247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.812301] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.812328] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.812358] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.812392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.812427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.812761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.812792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.812818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.812845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.812870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.812897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.812928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.812957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.812986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.813010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.813036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.813067] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.813093] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.815160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.815181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.815200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.815219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.816827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.816847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.816865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.818447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.818470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.820354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.823689] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.823721] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.823741] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.823766] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.840517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.840570] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.840643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.840840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.840921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.857225] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.857350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.857670] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.876218] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.876254] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.876376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.876422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.876476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.876517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.876561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.876605] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.876658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.876708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.876759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.876807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.876846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.876890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.876953] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.877103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.877121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.877195] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.877216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.877237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.877314] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.877345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.877380] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.877411] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.877444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.877473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.877503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.877530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.877539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.877566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.877574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.877604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.877631] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.877660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.877687] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.877720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.877746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.877775] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.877800] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.877828] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.877860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.877895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.877998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.878025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.878056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.878082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.878110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.878137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.878169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.878200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.878231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.878284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.878313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.878345] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.878377] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.880445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.880465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.880483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.880502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.882064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.882084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.882102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.883658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.883681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.885561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.888895] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.888947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.888979] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.889021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.905776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.905826] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.905894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.906081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.906163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.922466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.922517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.922594] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.939618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  327.939655] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  327.939695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.939727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.939762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.939792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.939821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.939852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.939887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.939919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.939950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.939981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.940018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.940057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.940129] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.940340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.940371] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  327.940477] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  327.940499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.940524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  327.940552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.940578] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.940605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.940631] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  327.940655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.940680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.940707] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.940732] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.940738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.940762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.940767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  327.940793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  327.940818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.940845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.940870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.940896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  327.940921] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.940947] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  327.940972] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  327.940998] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  327.941025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.941053] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  327.941124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  327.941151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  327.941176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  327.941203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  327.941228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  327.941282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  327.941315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  327.941348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  327.941379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.941407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  327.941434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  327.941466] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  327.941495] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  327.943564] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.943585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.943603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.943622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.945184] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  327.945207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.945230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.946921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.946942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.948829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.952150] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.952203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  327.952236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  327.952366] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.968991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  327.969042] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  327.969107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  327.969496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  327.969576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.985697] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  327.985744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  327.985833] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.004600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.004638] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.004678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.004711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.004745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.004776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.004805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.004843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.004887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.004929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.004970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.005014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.005042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.005070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.005127] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.005329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.005356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.005477] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.005521] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.005568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.005619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.005661] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.005707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.005751] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.005795] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.005838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.005879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.005920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.005930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.005969] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.005979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.006022] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.006052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.006081] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.006110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.006143] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.006173] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.006203] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.006233] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.006285] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.006321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.006353] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.006455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.006486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.006516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.006545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.006571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.006602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.006635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.006667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.006700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.006729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.006758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.006792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.006824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.008911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.008933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.008951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.008970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.010548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.010568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.010586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.012145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.012166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.014038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.017282] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.017313] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.017332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.017357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.034151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.034201] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.034352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.034623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.034700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.050825] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.050871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.050939] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.067970] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.068007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.068046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.068080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.068114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.068153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.068193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.068232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.068354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.068415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.068460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.068504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.068543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.068583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.068664] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.068787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.068803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.068874] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.068901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.068930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.068963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.068990] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.069018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.069046] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.069072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.069098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.069123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.069155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.069162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.069195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.069201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.069236] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.069310] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.069349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.069385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.069430] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.069460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.069490] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.069519] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.069547] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.069581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.069616] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.069723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.069757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.069791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.069823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.069855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.069889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.069925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.069960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.069996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.070022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.070042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.070067] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.070089] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.072132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.072153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.072175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.072199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.073807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.073827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.073845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.075402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.075423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.077294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.079892] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.079939] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.079967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.080004] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.096756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.096807] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.096873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.097088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.097184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.113454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.113502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.113572] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.130595] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.130632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.130672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.130704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.130738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.130767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.130796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.130827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.130861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.130893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.130924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.130954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.130981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.131008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.131069] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.131196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.131214] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.131409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.131460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.131515] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.131572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.131619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.131663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.131697] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.131737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.131778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.131815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.131840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.131847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.131870] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.131876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.131899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.131922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.131946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.131968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.131996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.132018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.132041] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.132062] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.132084] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.132110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.132138] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.132220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.132281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.132316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.132350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.132384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.132418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.132458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.132495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.132532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.132565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.132598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.132638] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.132675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.134758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.134779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.134797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.134816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.136390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.136410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.136428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.138002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.138025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.139900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.143196] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.143238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.143327] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.143382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.160063] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.160114] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.160180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.160512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.160590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.176738] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.176784] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.176854] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.193876] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.193914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.193954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.193988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.194030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.194070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.194109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.194148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.194192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.194234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.194340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.194374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.194402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.194430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.194497] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.194632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.194645] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.194702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.194727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.194754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.194784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.194809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.194836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.194862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.194888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.194914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.194940] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.194964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.194971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.194995] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.195000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.195025] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.195051] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.195077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.195103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.195128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.195153] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.195179] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.195205] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.195231] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.195292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.195328] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.195428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.195458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.195486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.195517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.195547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.195578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.195612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.195645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.195677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.195707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.195735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.195759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.195779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.197859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.197881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.197900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.197923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.199512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.199533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.199553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.201104] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.201126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.202997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.206314] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.206365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.206398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.206439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.223160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.223211] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.223371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.223619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.223696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.239834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.239885] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.239958] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.256979] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.257017] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.257056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.257089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.257123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.257152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.257181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.257219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.257349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.257405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.257458] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.257509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.257555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.257601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.257677] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.257785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.257797] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.257851] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.257872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.257895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.257920] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.257939] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.257961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.257981] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.258001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.258020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.258039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.258057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.258062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.258080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.258084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.258103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.258121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.258140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.258157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.258179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.258196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.258214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.258232] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.258289] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.258320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.258352] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.258450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.258480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.258509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.258539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.258568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.258599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.258632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.258666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.258698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.258726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.258755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.258789] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.258816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.260862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.260883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.260901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.260920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.262482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.262501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.262519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.264067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.264087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.265961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.269292] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.269339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.269368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.269405] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.286124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.286175] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.286243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.286581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.286660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.302831] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.302878] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.302951] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.320008] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.320050] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.320094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.320134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.320177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.320217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.320344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.320390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.320431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.320465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.320496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.320527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.320556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.320584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.320649] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.320778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.320796] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.320880] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.320913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.320948] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.320992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.321031] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.321072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.321113] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.321153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.321194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.321215] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.321267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.321276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.321304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.321311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.321339] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.321366] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.321395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.321421] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.321452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.321479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.321506] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.321532] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.321558] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.321588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.321621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.321715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.321736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.321755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.321775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.321793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.321813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.321834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.321854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.321874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.321892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.321916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.321944] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.321969] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.324013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.324034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.324052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.324070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.325633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.325652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.325670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.327221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.327254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.329121] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.332460] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.332491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.332511] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.332537] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.349336] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.349386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.349454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.349640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.349718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.366009] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.366055] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.366139] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.383151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.383188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.383228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.383343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.383398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.383443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.383490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.383537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.383592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.383643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.383691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.383722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.383748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.383775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.383838] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.383978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.383989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.384040] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.384059] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.384080] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.384103] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.384121] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.384141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.384160] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.384178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.384196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.384213] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.384276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.384288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.384315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.384323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.384353] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.384380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.384410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.384436] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.384469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.384496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.384526] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.384552] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.384581] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.384615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.384650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.384747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.384777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.384803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.384830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.384856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.384885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.384917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.384948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.384980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.385006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.385034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.385064] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.385094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.387176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.387197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.387215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.387279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.388849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.388869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.388887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.390448] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.390469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.392329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.395673] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.395726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.395758] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.395800] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.412520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.412567] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.412630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.412822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.412898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.429216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.429294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.429378] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.446383] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.446421] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.446460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.446495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.446539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.446579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.446618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.446657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.446701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.446742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.446784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.446825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.446864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.446903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.446975] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.447119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.447130] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.447183] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.447207] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.447293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.447331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.447361] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.447396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.447427] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.447459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.447488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.447519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.447546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.447555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.447582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.447590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.447620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.447647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.447677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.447704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.447736] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.447762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.447791] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.447817] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.447846] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.447879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.447913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.448012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.448039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.448068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.448094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.448122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.448149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.448181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.448213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.448266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.448293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.448323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.448356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.448387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.450454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.450475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.450497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.450521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.452087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.452112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.452137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.453683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.453706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.455578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.458873] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.458923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.458955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.458996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.475739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.475789] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.475855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.476051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.476131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.492417] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.492468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.492557] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.509569] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.509607] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.509646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.509679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.509713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.509744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.509773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.509805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.509840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.509872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.509903] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.509933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.509960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.509987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.510049] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.510176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.510194] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.510379] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.510424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.510480] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.510516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.510544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.510575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.510604] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.510634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.510661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.510690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.510717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.510724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.510751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.510757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.510785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.510811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.510840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.510866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.510897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.510923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.510951] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.510976] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.511004] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.511033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.511065] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.511160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.511190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.511216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.511268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.511295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.511327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.511361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.511393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.511427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.511454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.511483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.511518] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.511547] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.513617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.513639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.513658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.513677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.515264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.515285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.515303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.516877] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.516899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.518777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.522095] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.522147] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.522186] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.522237] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.538948] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.538999] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.539065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.539322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.539434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.555645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.555694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.555762] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.572810] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.572847] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.572886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.572919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.572953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.572983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.573011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.573042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.573077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.573108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.573139] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.573170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.573198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.573235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.573386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.573605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.573634] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.573767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.573802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.573838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.573876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.573907] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.573944] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.573966] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.573991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.574017] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.574043] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.574069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.574074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.574099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.574104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.574130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.574155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.574181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.574206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.574261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.574294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.574323] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.574351] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.574379] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.574412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.574444] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.574545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.574577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.574607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.574637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.574666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.574697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.574725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.574745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.574766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.574783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.574802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.574824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.574846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.576910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.576931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.576950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.576969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.578538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.578559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.578577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.580128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.580149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.582021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.585287] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.585319] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.585339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.585364] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.602135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.602185] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.602341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.602601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.602679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.618841] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.618887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.618959] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.635983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.636020] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.636059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.636092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.636126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.636156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.636184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.636216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.636347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.636392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.636441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.636490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.636533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.636576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.636668] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.636809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.636827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.636910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.636949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.636988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.637031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.637068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.637108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.637146] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.637183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.637223] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.637313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.637343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.637352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.637380] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.637387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.637416] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.637443] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.637470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.637497] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.637527] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.637553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.637580] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.637606] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.637632] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.637662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.637698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.637797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.637828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.637858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.637888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.637917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.637948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.637976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.637998] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.638018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.638037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.638054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.638078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.638098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.640151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.640172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.640190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.640209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.641799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.641819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.641842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.643400] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.643421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.645289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.648593] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.648625] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.648644] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.648670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.665435] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.665483] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.665547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.665754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.665850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.682146] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.682195] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.682350] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.699378] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.699415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.699454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.699487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.699521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.699550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.699579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.699609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.699644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.699676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.699715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.699757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.699802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.699828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.699883] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.700004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.700020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.700090] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.700117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.700147] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.700185] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.700217] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.700320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.700359] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.700397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.700434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.700469] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.700503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.700514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.700547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.700557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.700592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.700627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.700662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.700695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.700735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.700768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.700814] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.700842] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.700869] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.700900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.700934] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.701033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.701064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.701093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.701124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.701153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.701183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.701216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.701274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.701304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.701332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.701358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.701393] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.701424] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.703489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.703510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.703528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.703547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.705105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.705125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.705143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.706694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.706715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.708609] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.711926] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.711978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.712019] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.712054] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.728763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.728810] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.728873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.729079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.729177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.745466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.745514] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.745582] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.762604] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.762642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.762682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.762715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.762749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.762778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.762807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.762838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.762880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.762922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.762964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.763005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.763044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.763074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.763115] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.763273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.763293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.763382] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.763415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.763449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.763486] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.763516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.763550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.763582] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.763613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.763644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.763674] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.763703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.763710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.763738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.763745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.763774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.763803] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.763832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.763861] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.763894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.763923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.763954] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.763983] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.764012] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.764044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.764079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.764157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.764187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.764217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.764269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.764300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.764332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.764367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.764400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.764433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.764462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.764492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.764528] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.764560] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.766622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.766643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.766661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.766680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.768258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.768278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.768296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.769856] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.769879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.771749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.775068] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.775120] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.775152] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.775194] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.791904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.791952] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.792016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.792293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.792545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.808613] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.808659] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.808748] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.825801] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.825839] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.825878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.825911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.825945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.825974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.826003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.826034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.826068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.826100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.826131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.826161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.826189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.826215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.826374] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.826602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.826622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.826690] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.826711] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.826735] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.826763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.826788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.826815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.826841] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.826868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.826894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.826920] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.826945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.826950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.826975] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.826980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.827006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.827032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.827058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.827083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.827110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.827134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.827160] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.827186] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.827212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.827270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.827305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.827405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.827435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.827464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.827494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.827524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.827557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.827592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.827625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.827657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.827687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.827713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.827737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.827757] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.829807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.829827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.829845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.829864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.831453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.831475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.831494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.833051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.833073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.834975] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.838308] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.838360] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.838392] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.838434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.855140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.855191] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.855360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.855605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.855682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.871815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.871862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.871931] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.888957] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.888994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.889034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.889067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.889102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.889131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.889161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.889192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.889317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.889370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.889423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.889474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.889520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.889565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.889663] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.889813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.889831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.889914] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.889940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.889967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.889997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.890021] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.890048] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.890073] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.890099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.890125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.890151] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.890176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.890182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.890206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.890239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.890272] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.890302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.890331] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.890358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.890390] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.890417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.890444] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.890471] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.890497] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.890529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.890562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.890661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.890693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.890723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.890753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.890782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.890814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.890847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.890880] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.890910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.890929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.890947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.890970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.890991] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.893033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.893056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.893079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.893103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.894679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.894700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.894718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.896302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.896323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.898196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.901542] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.901594] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.901626] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.901668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.918417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.918471] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.918542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.918728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.918811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.935125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.935171] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.935332] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  328.952578] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  328.952616] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  328.952656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.952689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.952723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.952753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.952781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.952812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.952847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.952879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.952909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.952940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.952968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.952995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.953057] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.953185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.953273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  328.953612] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  328.953643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.953676] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  328.953712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  328.953741] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  328.953773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.953802] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  328.953832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  328.953861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  328.953890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.953916] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.953923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.953950] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.953956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  328.953986] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  328.954012] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  328.954039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.954065] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.954096] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  328.954121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.954149] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  328.954174] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  328.954202] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  328.954259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.954294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  328.954635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  328.954662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  328.954690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  328.954715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  328.954742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  328.954768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  328.954797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  328.954827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  328.954856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.954880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  328.954906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  328.954937] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  328.954963] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  328.957039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.957059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.957077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.957097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.958665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  328.958685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.958702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.960262] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.960282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.962156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.965458] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  328.965489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  328.965509] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  328.965535] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.982301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  328.982349] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  328.982413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  328.982607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  328.982683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.998996] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  328.999043] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  328.999112] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.016141] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.016179] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.016301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.016355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.016411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.016460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.016494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.016526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.016563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.016597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.016637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.016680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.016713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.016732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.016776] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.016871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.016885] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.016938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.016958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.016980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.017008] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.017033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.017061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.017087] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  329.017112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  329.017138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.017164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.017189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.017219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.017251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.017259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.017289] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.017318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.017347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.017374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.017405] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.017433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.017460] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  329.017487] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  329.017513] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  329.017544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.017576] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  329.017674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.017705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.017735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.017765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.017794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.017824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.017858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.017891] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.017924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.017952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.017972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.017995] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  329.018020] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.020062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.020082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.020101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.020119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.021683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.021705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.021728] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.023304] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.023326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.025196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.028552] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  329.028604] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.028636] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  329.028678] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.045394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.045439] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.045502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.045692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.045766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.062096] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  329.062142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.062210] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.079416] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.079454] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.079493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.079526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.079560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.079589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.079618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.079648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.079683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.079715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.079745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.079775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.079813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.079851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.079925] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.080069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.080088] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.080157] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.080177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.080198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.080290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.080319] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.080352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.080382] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  329.080411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  329.080439] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.080467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.080494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.080502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.080530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.080737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.080764] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.080784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.080803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.080821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.080843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.080862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.080880] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  329.080898] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  329.080915] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  329.080937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.080960] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  329.081025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.081045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.081063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.081082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.081099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.081120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.081147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.081174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.081203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.081254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.081284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.081317] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  329.081345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.083652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.083674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.083696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.083720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.085315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.085335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.085354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.086899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.086920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.088782] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.092129] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  329.092180] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.092269] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  329.092340] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.108996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.109046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.109112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.109434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.109521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.125694] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  329.125739] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.125824] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.142832] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.142870] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.142909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.142949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.142993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.143033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.143072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.143110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.143155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.143196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.143310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.143364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.143407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.143455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.143658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.143743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.143756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.143811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.143832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.143855] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.143880] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.143902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.143930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.143956] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  329.143980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  329.144001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.144021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.144039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.144045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.144063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.144067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.144086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.144104] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.144123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.144140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.144163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.144180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.144229] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  329.144256] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  329.144283] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  329.144314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.144346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  329.144605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.144626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.144646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.144665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.144684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.144704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.144726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.144746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.144766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.144785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.144803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.144825] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  329.144846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.146886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.146907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.146925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.146945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.148519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.148539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.148557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.150115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.150136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.151996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.155305] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  329.155355] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.155387] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  329.155428] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.172147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.172194] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.172360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.172622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.172713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.188856] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  329.188901] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.188986] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.206004] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.206041] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.206080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.206114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.206149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.206179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.206287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.206339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.206396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.206449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.206501] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.206553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.206599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.206636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.206701] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.206837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.206849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.206904] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.206924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.206947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.206972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.206991] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.207012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.207037] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  329.207063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  329.207090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.207116] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.207141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.207147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.207172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.207177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.207235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.207265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.207293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.207320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.207350] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.207377] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.207405] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  329.207432] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  329.207458] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  329.207488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.207520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  329.207619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.207650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.207681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.207710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.207740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.207770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.207804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.207837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.207869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.207893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.207912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.207938] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  329.207963] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.210006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.210029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.210052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.210076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.211652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.211673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.211691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.213247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.213270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.215130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.218460] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  329.218511] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.218543] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  329.218585] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.235294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.235345] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.235411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.235635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.235729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.251979] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  329.252025] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.252110] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.269111] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.269148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.269187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.269301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.269356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.269402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.269448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.269494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.269552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.269604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.269654] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.269703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.269743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.269786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.269881] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.270094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.270113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.270177] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.270243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.270279] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.270315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.270346] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.270382] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.270412] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  329.270444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  329.270473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.270503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.270529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.270538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.270564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.270571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.270599] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.270625] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.270652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.270678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.270709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.270734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.270762] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  329.270788] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  329.270815] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  329.270844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.270877] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  329.270973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.271003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.271030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.271058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.271084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.271113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.271145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.271176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.271229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.271258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.271284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.271319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  329.271348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.273412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.273432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.273451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.273470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.275040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.275060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.275078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.276640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.276660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.278529] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.281478] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  329.281509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.281528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  329.281554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.298337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.298388] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.298454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.298684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.298775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.315036] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  329.315081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.315166] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.332260] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.332302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.332346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.332387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.332430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.332470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.332508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.332547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.332600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.332638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.332671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.332702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.332729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.332756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.332817] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.332936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.332953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.333031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.333061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.333094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.333130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.333159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.333189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.333274] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  329.333326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  329.333368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.333413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.333452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.333465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.333504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.333515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.333559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.333598] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.333640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.333666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.333700] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.333727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.333756] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  329.333783] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  329.333811] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  329.333845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.333880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  329.333977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.334007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.334034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.334062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.334087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.334116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.334148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.334180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.334306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.334332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.334360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.334391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  329.334421] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.336489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.336510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.336528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.336547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.338117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.338138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.338158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.339757] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.339778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.341668] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.344919] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  329.344952] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.344976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  329.345007] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.361780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.361830] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.361896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.362097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.362198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.378487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  329.378534] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.378605] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  329.396795] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  329.396832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.396872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.396911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.396955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.396994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.397033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.397072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.397116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.397158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.397199] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.397325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.397371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.397416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.397518] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  329.400465] [IGT] kms_flip: exiting, ret=0
>[  329.420085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.420126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.420169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.420244] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.420283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.420324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.420365] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.420404] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.420444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.420484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.420522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.420539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.420562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.420565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.420586] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.420604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.420622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.420645] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.420670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.420693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.420716] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.420740] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.420763] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.420788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.420814] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.420902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.420927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.420951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.420974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.420998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.421022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.421048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.421074] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.421099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.421122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.421142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.421167] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.421214] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.423285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.423307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.423329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.423352] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.424927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.424946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.424964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.426526] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.426545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.428417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.431650] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.431702] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.431732] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.431773] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.431835] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.431862] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.448540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.448588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.448657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.448898] Console: switching to colour frame buffer device 240x75
>[  329.553903] Console: switching to colour dummy device 80x25
>[  329.554016] [IGT] kms_flip: executing
>[  329.566030] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  329.566082] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  329.567620] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  329.567657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  329.569282] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  329.569293] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  329.571275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  329.571313] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  329.573285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  329.573297] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  329.573304] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  329.573335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  329.573380] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  329.574487] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  329.575411] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  329.575432] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  329.575451] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  329.575469] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  329.576485] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  329.576505] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  329.577610] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  329.577613] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  329.577711] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  329.577714] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  329.577719] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  329.577721] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  329.577726] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  329.577728] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  329.577738] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  329.577741] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.577744] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.577747] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.577750] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  329.577753] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  329.577756] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  329.577759] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  329.577762] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.577765] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  329.577768] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  329.577771] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  329.577774] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  329.577777] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  329.577780] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  329.577783] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  329.577786] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  329.577789] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  329.577792] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  329.577794] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  329.577797] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  329.577800] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  329.577803] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  329.577806] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  329.577809] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  329.577812] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  329.577815] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  329.577818] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  329.577821] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  329.577824] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  329.577827] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  329.577863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  329.577886] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  329.579233] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  329.579256] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  329.581286] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  329.581297] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  329.583273] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  329.583311] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  329.585272] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  329.585283] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  329.585290] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  329.585690] [IGT] kms_flip: starting subtest basic-flip-vs-wf_vblank
>[  329.586609] [drm:drm_mode_addfb2] [FB:76]
>[  329.586653] [drm:drm_mode_addfb2] [FB:79]
>[  329.639876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.639936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.648680] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.648725] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  329.648795] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.665825] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.665869] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  329.665901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  329.665939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.665972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.666006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.666036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.666065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.666096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.666131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.666162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.666254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.666309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.666351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.666398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.666497] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.666609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  329.666760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  329.666886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  329.666899] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  329.666950] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  329.666970] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.666992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  329.667018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  329.667041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  329.667065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.667089] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  329.667112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.667136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  329.667159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.667227] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.667239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.667269] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.667277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  329.667309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  329.667337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  329.667367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.667394] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  329.667427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  329.667454] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.667484] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  329.667510] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  329.667539] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  329.667574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.667608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  329.670886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  329.670908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  329.670926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  329.670944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  329.670962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  329.670980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  329.671000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  329.671019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  329.671037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  329.671054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  329.671070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  329.671091] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  329.671110] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  329.673228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.673249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.673272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.673296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.674871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  329.674892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.674910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.676476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.676497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  329.678369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.681680] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.681733] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  329.681765] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.681813] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.681873] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.681894] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.698536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  329.698586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  329.698651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.335203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.351546] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  333.351704] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  333.352637] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.369781] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.369883] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  333.369927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  333.369973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.370006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.370123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.370169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.370218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.370260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.370295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.370532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.370552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.370572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.370589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.370606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.370661] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  333.370892] [drm:drm_mode_addfb2] [FB:76]
>[  333.370919] [drm:drm_mode_addfb2] [FB:78]
>[  333.403863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  333.403971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  333.404112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  333.404223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  333.404236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  333.404305] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  333.404327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.404349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  333.404373] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  333.404392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  333.404413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.404433] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  333.404453] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.404471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  333.404493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.404517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.404521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.404544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.404548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  333.404572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  333.404595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  333.404619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.404642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.404666] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  333.404688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.404712] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  333.404735] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  333.404755] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  333.404780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.404805] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  333.408204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  333.408231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  333.408256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  333.408281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  333.408306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  333.408331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  333.408357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  333.408383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  333.408409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  333.408433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  333.408456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  333.408482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  333.408507] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  333.410621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.410643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.410661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.410680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.412269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  333.412291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.412310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.413863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.413884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.415764] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.419113] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.419167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  333.419208] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.419244] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.435983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  333.436033] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  333.436200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.072509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.072679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  337.072772] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  337.072913] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  337.090102] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  337.090141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  337.090182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.090216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.090252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.090282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.090311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.090342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.090377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.090409] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.090440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.090471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.090509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.090542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.090601] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  337.090943] [drm:drm_mode_addfb2] [FB:76]
>[  337.091009] [drm:drm_mode_addfb2] [FB:78]
>[  337.120705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  337.120802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  337.120938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  337.121060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  337.121074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  337.121141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  337.121166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.121191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  337.121218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  337.121239] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  337.121262] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.121284] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  337.121305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.121326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  337.121345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.121364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.121368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.121386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.121390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  337.121409] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  337.121427] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  337.121444] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.121461] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.121481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  337.121499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.121516] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  337.121533] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  337.121556] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  337.121581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  337.121608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  337.124914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  337.124938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  337.124958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  337.124977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  337.124996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  337.125015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  337.125038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  337.125058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  337.125086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  337.125105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  337.125123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  337.125147] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  337.125168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  337.127233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.127255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.127274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.127294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.129978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  337.130004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.130026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.131578] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.131599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.133473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.136792] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.136846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  337.136878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.137017] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.153638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  337.153689] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  337.153756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.790192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.790362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  340.790454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.790598] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  340.807855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  340.807894] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  340.807934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.807967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.808002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.808031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.808060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.808091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.808126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.808159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.808190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.808222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.808250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.808277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.808342] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  340.811327] [IGT] kms_flip: exiting, ret=0
>[  340.830631] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  340.830671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.830710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  340.830776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.830808] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.830843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.830878] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  340.830909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  340.830928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.830946] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  340.830964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.830968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.830985] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.830988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.831006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  340.831023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.831040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.831056] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  340.831076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  340.831093] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.831110] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  340.831127] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  340.831143] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  340.831163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.831186] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  340.831257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  340.831276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  340.831294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  340.831311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  340.831329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  340.831347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  340.831368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  340.831387] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  340.831405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.831422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  340.831442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  340.831467] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  340.831491] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  340.833567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.833588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.833606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.833628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.835238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  340.835257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  340.835282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.836856] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.836875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.838762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.842206] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  340.842242] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  340.842264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  340.842297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  340.842363] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  340.842384] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  340.859085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  340.859134] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  340.859203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  340.859444] Console: switching to colour frame buffer device 240x75
>[  340.966216] Console: switching to colour dummy device 80x25
>[  340.966328] [IGT] kms_flip: executing
>[  340.977568] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  340.977619] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  340.979162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  340.979202] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  340.980801] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  340.980813] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  340.982801] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  340.982840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  340.984803] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  340.984814] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  340.984821] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  340.984851] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  340.984893] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  340.986010] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  340.986942] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  340.986963] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  340.986982] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  340.986999] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  340.988017] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  340.988037] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  340.989153] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  340.989156] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  340.989257] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  340.989259] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  340.989264] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  340.989267] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  340.989271] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  340.989274] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  340.989283] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  340.989286] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  340.989289] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  340.989292] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  340.989295] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  340.989298] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  340.989301] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  340.989304] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  340.989307] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  340.989310] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  340.989313] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  340.989316] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  340.989319] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  340.989322] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  340.989325] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  340.989328] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  340.989331] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  340.989334] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  340.989337] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  340.989340] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  340.989342] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  340.989345] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  340.989348] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  340.989351] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  340.989354] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  340.989357] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  340.989360] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  340.989363] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  340.989366] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  340.989369] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  340.989372] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  340.989414] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  340.989436] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  340.990764] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  340.990786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  340.992805] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  340.992815] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  340.994800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  340.994839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  340.996800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  340.996811] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  340.996818] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  340.997211] [IGT] kms_flip: starting subtest basic-plain-flip
>[  340.998173] [drm:drm_mode_addfb2] [FB:58]
>[  340.998218] [drm:drm_mode_addfb2] [FB:79]
>[  341.051618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  341.051716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.059244] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  341.059292] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  341.059367] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  341.076437] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  341.076481] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  341.076514] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  341.076552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.076585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.076619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.076650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.076679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.076710] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.076815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.076870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.076922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.076974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.077024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.077054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.077120] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  341.077205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  341.077353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  341.077440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  341.077452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  341.077504] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  341.077524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  341.077545] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  341.077568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.077586] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.077605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.077624] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  341.077643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  341.077660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.077677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  341.077693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.077736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.077766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.077775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  341.077805] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  341.077833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.077862] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.077888] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  341.077921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  341.077948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.077977] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  341.078005] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  341.078034] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  341.078068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.078102] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  341.081496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  341.081517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  341.081540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  341.081564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  341.081588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  341.081611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  341.081637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  341.081662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  341.081686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  341.081769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  341.081799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  341.081835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  341.081865] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  341.083936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.083956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.083974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.083993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.085571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  341.085593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  341.085612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.087177] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.087199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.089105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.092403] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  341.092435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  341.092455] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  341.092481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  341.092542] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  341.092566] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  341.109269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  341.109318] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  341.109383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.462048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.478621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  344.478672] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  344.478747] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  344.495743] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  344.495787] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  344.495820] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  344.495858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.495891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.495926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.495965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.496005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.496045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.496089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.496132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.496174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.496216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.496255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.496293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.496369] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  344.496827] [drm:drm_mode_addfb2] [FB:58]
>[  344.496898] [drm:drm_mode_addfb2] [FB:78]
>[  344.529842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  344.529935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  344.530005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  344.530070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  344.530084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  344.530142] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  344.530163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  344.530186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  344.530210] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.530228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.530249] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.530269] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  344.530288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  344.530307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.530324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  344.530341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.530345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.530361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.530365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  344.530382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  344.530405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.530429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.530452] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.530476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  344.530499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.530523] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  344.530546] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  344.530619] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  344.530654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.530691] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  344.534087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  344.534109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  344.534128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  344.534146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  344.534163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  344.534181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  344.534202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  344.534221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  344.534239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  344.534256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  344.534272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  344.534293] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  344.534312] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  344.536375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.536396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.536415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.536434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.540305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  344.540346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  344.540384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.543044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.543076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.546108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.549407] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  344.549459] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  344.549491] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  344.549533] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  344.566273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  344.566323] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  344.566388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.919038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.919123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  347.919169] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.919243] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  347.936254] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  347.936291] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  347.936332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.936365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.936400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.936509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.936559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.936605] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.936671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.936718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.936764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.936809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.936841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.936866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.936927] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  347.937217] [drm:drm_mode_addfb2] [FB:58]
>[  347.937257] [drm:drm_mode_addfb2] [FB:78]
>[  347.966626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  347.966719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  347.966787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.966853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  347.966866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  347.966924] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  347.966948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.966973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  347.967000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.967022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.967046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.967070] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  347.967093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.967117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.967140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  347.967163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.967167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.967190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.967194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  347.967218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  347.967241] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.967264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.967287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.967311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  347.967333] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.967357] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  347.967380] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  347.967403] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  347.967484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.967520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  347.970837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  347.970861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  347.970881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  347.970900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  347.970919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  347.970939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  347.970961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  347.970981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  347.971001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  347.971019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  347.971037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  347.971059] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  347.971079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  347.973144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.973166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.973185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.973204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.974768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  347.974788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  347.974810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.976361] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.976383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  347.978294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.981637] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.981682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  347.981709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  347.981745] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  347.998502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  347.998550] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  347.998614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  351.351276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.351396] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  351.351441] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  351.351515] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  351.368534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  351.368572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  351.368612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  351.368645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  351.368680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  351.368709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  351.368738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  351.368770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  351.368805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  351.368839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  351.368870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  351.368901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  351.368929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  351.368962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  351.369038] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  351.372384] [IGT] kms_flip: exiting, ret=0
>[  351.395226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  351.395264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.395347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  351.395389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  351.395423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  351.395464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.395505] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  351.395544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.395585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  351.395624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.395663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.395671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  351.395709] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.395715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  351.395756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  351.395795] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  351.395835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.395874] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  351.395914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  351.395953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.395995] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  351.396016] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  351.396036] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  351.396057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.396081] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  351.396153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  351.396172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  351.396195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  351.396219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  351.396243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  351.396277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  351.396317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  351.396347] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  351.396367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  351.396385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  351.396402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  351.396424] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  351.396443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  351.398511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.398532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.398554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.398578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.400161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  351.400181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.400198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.401764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.401783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  351.403725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.407221] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.407254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  351.407273] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.407313] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.407376] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.407396] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.424104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  351.424152] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  351.424222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  351.424496] Console: switching to colour frame buffer device 240x75
>[  351.529847] Console: switching to colour dummy device 80x25
>[  351.529951] [IGT] kms_force_connector_basic: executing
>[  351.541240] [IGT] kms_force_connector_basic: exiting, ret=77
>[  351.574433] Console: switching to colour frame buffer device 240x75
>[  351.677802] Console: switching to colour dummy device 80x25
>[  351.677906] [IGT] kms_force_connector_basic: executing
>[  351.702643] [IGT] kms_force_connector_basic: exiting, ret=77
>[  351.724511] Console: switching to colour frame buffer device 240x75
>[  351.829925] Console: switching to colour dummy device 80x25
>[  351.830029] [IGT] kms_force_connector_basic: executing
>[  351.854657] [IGT] kms_force_connector_basic: exiting, ret=77
>[  351.874613] Console: switching to colour frame buffer device 240x75
>[  351.978671] Console: switching to colour dummy device 80x25
>[  351.978774] [IGT] kms_force_connector_basic: executing
>[  352.003659] [IGT] kms_force_connector_basic: exiting, ret=77
>[  352.024739] Console: switching to colour frame buffer device 240x75
>[  352.137190] Console: switching to colour dummy device 80x25
>[  352.137495] [IGT] kms_frontbuffer_tracking: executing
>[  352.159594] [drm:drm_mode_addfb2] [FB:58]
>[  352.159693] [drm:drm_mode_addfb2] [FB:79]
>[  352.159802] [drm:drm_mode_addfb2] [FB:80]
>[  352.162199] [drm:drm_mode_addfb2] [FB:81]
>[  352.176055] [drm:drm_mode_addfb2] [FB:82]
>[  352.176701] [IGT] kms_frontbuffer_tracking: starting subtest basic
>[  352.181650] [drm:drm_mode_addfb2] [FB:58]
>[  352.181744] [drm:drm_mode_addfb2] [FB:79]
>[  352.181850] [drm:drm_mode_addfb2] [FB:80]
>[  352.184183] [drm:drm_mode_addfb2] [FB:81]
>[  352.200045] [drm:drm_mode_addfb2] [FB:82]
>[  352.200068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.200131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.208040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.208091] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  352.208165] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.226098] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.226142] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  352.226176] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  352.226214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.226246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  352.226379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  352.226430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  352.226479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  352.226528] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  352.226587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  352.226638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  352.226687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  352.226737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.226781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  352.226825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  352.226925] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.227069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  352.227292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  352.232616] [drm:drm_mode_addfb2] [FB:78]
>[  352.235785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.235798] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  352.235861] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  352.235883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.235907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  352.235934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  352.235957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  352.235982] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.236005] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  352.236029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.236050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  352.236073] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.236096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.236100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  352.236123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.236127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  352.236151] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  352.236174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  352.236198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.236221] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  352.236245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  352.236321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.236358] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  352.236392] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  352.236424] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  352.236461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.236498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  352.239828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.239852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  352.239876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  352.239900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  352.239923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  352.239947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  352.239972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  352.239997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  352.240021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.240044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  352.240067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  352.240093] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  352.240113] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  352.242201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.242223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.242242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.242309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.243877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  352.243897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.243915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.245480] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.245501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  352.247384] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.250720] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.250753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  352.250773] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.250798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.250862] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.250885] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.267594] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  352.267643] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.267708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.317899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.317990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.334301] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.334347] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  352.334417] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.351422] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.351468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  352.351500] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  352.351538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.351571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  352.351606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  352.351637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  352.351666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  352.351698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  352.351733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  352.351764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  352.351796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  352.351826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.351863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  352.351902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  352.351977] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.352068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  352.352212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  352.357792] [drm:drm_mode_addfb2] [FB:78]
>[  352.364133] [drm:drm_mode_addfb2] [FB:83]
>[  352.369188] [drm:drm_mode_addfb2] [FB:96]
>[  352.374249] [drm:drm_mode_addfb2] [FB:97]
>[  352.533058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.533073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  352.533139] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  352.533160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.533184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  352.533211] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  352.533234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  352.533308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.533340] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  352.533371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.533399] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  352.533427] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.533454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.533462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  352.533491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.533498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  352.533527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  352.533554] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  352.533581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.533610] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  352.533644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  352.533672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.533701] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  352.533730] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  352.533758] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  352.533791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.533819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  352.537230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.537277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  352.537298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  352.537317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  352.537336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  352.537356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  352.537379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  352.537399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  352.537420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.537438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  352.537456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  352.537478] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  352.537499] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  352.539559] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.539582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.539602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.539623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.541176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  352.541197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.541215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.542807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.542828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  352.544718] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.548025] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.548058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  352.548077] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.548103] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.548164] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.548194] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.564913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  352.564963] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.565033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.614944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.614964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  352.681660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.681679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  352.748374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.748393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  352.815147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.815231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.831749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.831796] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  352.831866] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.848893] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.848938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  352.848970] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  352.849008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.849041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  352.849075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  352.849105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  352.849134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  352.849165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  352.849200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  352.849328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  352.849372] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  352.849417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.849453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  352.849491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  352.849574] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.849712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  352.849915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  352.850873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  352.850887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  352.850949] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  352.850974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.850999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  352.851024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  352.851044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  352.851066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.851087] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  352.851108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.851128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  352.851147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.851164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.851169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  352.851187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.851191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  352.851209] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  352.851651] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  352.851672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.851697] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  352.851723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  352.851748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.851774] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  352.851799] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  352.851824] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  352.851852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.851880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  352.855817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  352.855841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  352.855862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  352.855881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  352.855900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  352.855920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  352.855941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  352.855961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  352.855981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.855999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  352.856016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  352.856038] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  352.856059] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  352.858110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.858133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.858153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.858178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.860774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  352.860796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.860815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.863344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.863368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  352.865308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.868358] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.868395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  352.868421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.868454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.868522] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.868555] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.885319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  352.885370] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  352.885439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  352.990797] [drm:drm_mode_addfb2] [FB:78]
>[  353.719394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.735871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.735920] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  353.735993] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.753832] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.753881] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  353.753922] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  353.753967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  353.754007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  353.754051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  353.754091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  353.754131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  353.754171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  353.754304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  353.754363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  353.754417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  353.754471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  353.754518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  353.754565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  353.754666] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  353.755023] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  353.789593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  353.789646] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.789684] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  353.789724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  353.789755] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  353.789789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.789823] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  353.789855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.789885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  353.789914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.789941] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.789950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  353.789977] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.789984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  353.790012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  353.790040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  353.790067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.790093] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  353.790126] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  353.790153] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.790181] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  353.790278] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  353.790327] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  353.790383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.790448] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  353.790611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  353.790652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  353.790693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  353.790729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  353.790768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  353.790808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  353.790854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  353.790897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  353.790940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  353.790980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  353.791019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  353.791080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  353.791138] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  353.793393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.793415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.793434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.793458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.795032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  353.795056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.795078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.796643] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.796664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  353.798543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.801835] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.801869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  353.801889] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.801926] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.802170] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.802276] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.818727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  353.818779] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  353.818853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  353.835562] Console: switching to colour frame buffer device 240x75
>[  353.953317] Console: switching to colour dummy device 80x25
>[  353.953434] [IGT] kms_pipe_crc_basic: executing
>[  353.964074] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  353.964126] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  353.966240] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  353.966275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  353.968280] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  353.968291] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  353.970263] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  353.970302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  353.972266] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  353.972277] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  353.972284] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  353.972314] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  353.972358] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  353.973485] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  353.974420] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  353.974443] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  353.974462] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  353.974481] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  353.975501] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  353.975522] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  353.976639] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  353.976643] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  353.976743] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  353.976745] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  353.976750] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  353.976753] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  353.976757] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  353.976760] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  353.976769] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  353.976773] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  353.976776] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.976779] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.976782] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  353.976785] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  353.976788] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  353.976791] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  353.976793] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.976796] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.976799] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  353.976802] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  353.976805] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  353.976808] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  353.976811] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  353.976814] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  353.976817] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  353.976820] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.976823] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.976826] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  353.976829] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  353.976832] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  353.976835] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  353.976838] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  353.976840] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  353.976843] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.976846] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.976849] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  353.976852] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.976855] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.976858] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  353.976896] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  353.976918] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  353.978205] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  353.978227] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  353.980244] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  353.980253] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  353.982265] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  353.982307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  353.984419] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  353.984429] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  353.984436] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  353.997418] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  353.997443] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  353.999561] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  353.999599] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.001716] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.001727] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.003848] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.003887] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.006003] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.006014] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.006021] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.006647] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.006688] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.007793] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.008721] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.008743] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.008761] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.008778] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.009817] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.009838] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.010963] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.010967] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.011066] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.011068] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.011074] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.011076] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.011081] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.011083] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.011092] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.011096] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.011099] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.011102] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.011105] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.011108] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.011111] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.011114] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.011117] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.011120] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.011123] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.011126] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.011128] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.011131] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.011134] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.011137] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.011140] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.011143] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.011146] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.011149] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.011152] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.011209] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.011214] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.011221] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.011227] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.011233] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.011240] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.011246] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.011252] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.011259] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.011266] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.011626] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.011652] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.013277] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.013316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.015280] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.015291] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.017411] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.017451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.019549] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.019559] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.019566] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.020123] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-1
>[  354.020360] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  354.020640] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  354.035726] Console: switching to colour frame buffer device 240x75
>[  354.144874] Console: switching to colour dummy device 80x25
>[  354.145044] [IGT] kms_pipe_crc_basic: executing
>[  354.157067] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.157118] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.159257] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.159293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.161407] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.161419] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.163536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.163578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.165694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.165705] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.165713] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.165744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.165785] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.166901] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.167828] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.167850] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.167869] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.167887] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.168918] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.168940] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.170051] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.170055] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.170207] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.170211] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.170222] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.170227] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.170237] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.170242] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.170260] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.170266] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.170272] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.170278] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.170284] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.170289] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.170295] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.170300] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.170306] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.170312] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.170317] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.170323] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.170329] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.170334] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.170340] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.170346] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.170351] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.170357] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.170363] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.170369] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.170374] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.170380] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.170385] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.170391] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.170396] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.170402] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.170407] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.170413] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.170419] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.170424] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.170430] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.170497] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.170531] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.172635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.172671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.174786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.174796] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.176914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.176953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.179067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.179078] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.179085] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.192224] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.192249] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.194369] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.194410] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.196527] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.196538] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.198659] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.198698] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.200815] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.200826] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.200833] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.201513] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.201555] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.202650] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.203572] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.203594] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.203612] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.203630] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.204650] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.204671] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.205788] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.205791] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.205890] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.205893] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.205898] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.205900] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.205905] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.205907] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.205916] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.205920] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.205923] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.205926] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.205929] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.205932] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.205935] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.205938] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.205941] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.205944] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.205946] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.205949] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.205952] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.205955] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.205958] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.205961] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.205964] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.205967] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.205970] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.205973] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.205976] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.205979] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.205982] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.205985] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.205988] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.205991] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.205993] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.205996] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.205999] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.206002] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.206005] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.206471] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.206507] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.208256] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.208295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.210263] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.210274] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.212268] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.212306] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.214256] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.214267] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.214274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.214834] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-3
>[  354.214961] [drm:display_crc_ctl_write [i915]] too many words, allowed <= 3
>[  354.214992] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  354.215120] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  354.235892] Console: switching to colour frame buffer device 240x75
>[  354.343767] Console: switching to colour dummy device 80x25
>[  354.343944] [IGT] kms_pipe_crc_basic: executing
>[  354.361059] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.361111] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.363252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.363288] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.365403] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.365414] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.367532] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.367571] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.369685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.369696] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.369704] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.369734] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.369776] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.370896] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.371826] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.371848] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.371867] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.371885] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.372901] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.372921] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.374042] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.374045] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.374218] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.374223] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.374229] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.374232] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.374237] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.374240] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.374250] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.374254] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.374257] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.374260] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.374264] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.374267] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.374270] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.374274] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.374278] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.374281] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.374285] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.374288] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.374291] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.374294] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.374298] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.374302] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.374305] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.374308] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.374311] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.374315] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.374318] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.374322] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.374326] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.374329] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.374332] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.374335] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.374339] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.374342] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.374345] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.374350] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.374353] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.374396] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.374421] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.376208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.376229] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.378255] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.378266] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.380249] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.380288] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.382249] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.382259] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.382267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.395155] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.395180] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.397301] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.397340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.399439] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.399449] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.401571] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.401609] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.403726] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.403736] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.403744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.404413] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.404454] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.405542] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.406465] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.406487] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.406506] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.406523] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.407546] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.407567] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.408673] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.408676] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.408777] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.408779] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.408784] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.408787] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.408792] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.408794] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.408803] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.408806] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.408809] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.408812] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.408815] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.408818] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.408821] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.408824] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.408827] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.408830] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.408833] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.408835] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.408838] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.408841] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.408844] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.408847] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.408850] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.408853] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.408856] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.408859] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.408862] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.408865] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.408868] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.408871] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.408874] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.408876] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.408879] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.408882] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.408885] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.408888] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.408891] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.409270] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.409305] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.411237] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.411273] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.413250] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.413261] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.415362] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.415398] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.417512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.417522] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.417530] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.418088] [IGT] kms_pipe_crc_basic: starting subtest bad-pipe
>[  354.418312] [drm:display_crc_ctl_write [i915]] unknown pipe D
>[  354.418585] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  354.436027] Console: switching to colour frame buffer device 240x75
>[  354.543870] Console: switching to colour dummy device 80x25
>[  354.544063] [IGT] kms_pipe_crc_basic: executing
>[  354.557025] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.557078] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.558595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.558632] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.560240] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.560251] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.562239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.562279] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.564239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.564250] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.564258] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.564289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.564333] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.565422] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.566340] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.566362] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.566381] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.566399] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.567416] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.567437] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.568548] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.568552] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.568650] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.568653] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.568658] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.568660] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.568665] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.568668] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.568676] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.568680] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.568683] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.568686] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.568689] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.568692] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.568695] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.568697] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.568700] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.568703] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.568706] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.568709] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.568712] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.568715] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.568718] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.568721] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.568724] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.568727] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.568730] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.568733] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.568736] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.568738] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.568741] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.568744] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.568747] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.568750] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.568753] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.568756] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.568759] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.568762] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.568765] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.568807] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.568829] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.570208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.570234] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.572240] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.572251] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.574221] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.574258] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.576239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.576250] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.576257] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.589425] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.589451] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.591571] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.591610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.593727] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.593737] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.595857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.595896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.598014] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.598025] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.598032] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.598758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.598799] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.599895] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.600821] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.600843] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.600861] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.600878] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.601900] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.601920] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.603029] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.603032] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.603174] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.603179] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.603189] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.603193] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.603202] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.603207] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.603223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.603229] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.603237] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.603243] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.603249] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.603255] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.603262] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.603269] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.603275] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.603281] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.603288] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.603296] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.603301] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.603307] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.603313] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.603320] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.603327] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.603333] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.603339] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.603345] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.603353] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.603359] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.603365] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.603370] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.603377] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.603384] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.603390] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.603395] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.603401] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.603408] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.603415] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.603995] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.604028] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.606137] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.606205] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.608310] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.608321] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.610441] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.610480] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.612576] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.612586] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.612593] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.613195] [IGT] kms_pipe_crc_basic: starting subtest bad-source
>[  354.613519] [drm:intel_crtc_set_crc_source [i915]] unknown source foo
>[  354.613622] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  354.636221] Console: switching to colour frame buffer device 240x75
>[  354.744414] Console: switching to colour dummy device 80x25
>[  354.744655] [IGT] kms_pipe_crc_basic: executing
>[  354.756972] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.757025] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.758613] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.758653] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.760235] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.760246] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.762232] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.762274] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.764235] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.764246] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.764253] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.764283] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.764324] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.765426] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.766365] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.766392] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.766416] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.766438] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.767464] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.767486] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.768597] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.768601] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.768699] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.768702] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.768707] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.768709] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.768714] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.768716] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.768725] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.768729] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.768732] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.768735] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.768738] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.768741] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.768744] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.768746] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.768749] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.768752] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.768755] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.768758] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.768761] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.768764] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.768767] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.768770] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.768773] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.768776] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.768779] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.768782] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.768785] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.768788] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.768791] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.768793] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.768796] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.768799] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.768802] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.768805] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.768808] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.768811] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.768814] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.768851] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.768873] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.770204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.770225] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.772234] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.772245] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.774231] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.774270] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.776231] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.776242] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.776249] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.789092] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  354.789117] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  354.791261] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.791303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.793400] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  354.793410] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  354.795529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.795568] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  354.797685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  354.797695] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.797702] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  354.798351] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  354.798393] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  354.799481] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  354.800404] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.800426] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  354.800448] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.800471] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.801492] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  354.801513] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  354.802619] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  354.802623] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  354.802721] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.802724] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.802729] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  354.802731] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  354.802736] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  354.802738] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  354.802747] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  354.802750] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.802753] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.802756] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.802759] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.802762] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  354.802765] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.802768] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  354.802771] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.802774] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.802777] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.802780] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.802783] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  354.802786] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  354.802789] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.802792] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.802795] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.802798] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.802800] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.802803] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.802806] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  354.802809] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.802812] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  354.802815] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.802818] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.802821] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.802824] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.802827] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  354.802830] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.802833] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.802836] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.803119] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  354.803203] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  354.805244] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.805284] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.807231] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  354.807242] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  354.809363] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.809402] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  354.811499] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  354.811509] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  354.811516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  354.812080] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-A
>[  354.812870] [drm:drm_mode_addfb2] [FB:78]
>[  354.820305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  354.820319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  354.852857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  354.853029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  354.936406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.952928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  354.952982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  354.953060] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  354.970074] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  354.970118] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  354.970246] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  354.970308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  354.970360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  354.970416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  354.970464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  354.970512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  354.970561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  354.970618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  354.970670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  354.970721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  354.970772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  354.970818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  354.970863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  354.970964] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  354.971781] [drm:drm_mode_addfb2] [FB:58]
>[  354.980757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  354.980777] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  354.980870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  354.980901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.980933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  354.980968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  354.980995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  354.981025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.981055] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  354.981083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  354.981111] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  354.981184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.981216] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.981224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.981253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.981261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  354.981292] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  354.981321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  354.981350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.981379] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  354.981413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  354.981442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.981470] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  354.981498] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  354.981526] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  354.981559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.981594] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  354.985086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  354.985110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  354.985142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  354.985220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  354.985253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  354.985285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  354.985321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  354.985350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  354.985371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  354.985390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  354.985408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  354.985431] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  354.985456] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  354.987503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.987523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.987541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.987560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.989118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  354.989163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.989181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.990735] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.990756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  354.992619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.995923] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  354.995975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  354.996012] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  354.996061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.996151] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  354.996328] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  355.012777] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  355.012824] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.012886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.113002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.129526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  355.129571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  355.129639] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  355.147986] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  355.148030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  355.148063] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  355.148102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.148218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  355.148276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  355.148325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  355.148373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  355.148428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  355.148466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  355.148496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  355.148524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  355.148554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.148579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  355.148604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  355.148664] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.149945] [drm:drm_mode_addfb2] [FB:58]
>[  355.158382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  355.158396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  355.158464] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  355.158487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.158511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  355.158536] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  355.158556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  355.158577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.158599] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  355.158619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  355.158638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  355.158657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.158675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.158679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  355.158697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.158701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  355.158719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  355.158737] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  355.158754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.158771] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  355.158792] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  355.158810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.158827] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  355.158845] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  355.158862] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  355.158883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.158906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  355.162405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.162428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  355.162449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  355.162468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  355.162486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  355.162507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  355.162529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  355.162549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  355.162570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.162588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  355.162606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  355.162629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  355.162649] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  355.164755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.164778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.164797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.164816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.166389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  355.166409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.166427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.167992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.168015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  355.169884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.173191] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  355.173238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  355.173267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  355.173305] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.173377] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  355.173406] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  355.190038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  355.190087] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.190240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.290289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.306780] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  355.306828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  355.306900] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  355.325869] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  355.325913] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  355.325946] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  355.325984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.326024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  355.326068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  355.326108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  355.326225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  355.326273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  355.326342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  355.326389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  355.326436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  355.326483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.326523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  355.326564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  355.326630] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.327669] [drm:drm_mode_addfb2] [FB:58]
>[  355.337201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  355.337221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  355.337317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  355.337355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.337394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  355.337436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  355.337471] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  355.337509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.337545] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  355.337581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  355.337618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  355.337654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.337689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.337696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  355.337730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.337736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  355.337772] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  355.337808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  355.337845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.337880] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  355.337917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  355.337952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.337988] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  355.338024] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  355.338055] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  355.338094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.338853] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  355.342387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.342414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  355.342440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  355.342466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  355.342491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  355.342517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  355.342544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  355.342571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  355.342598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.342623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  355.342648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  355.342675] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  355.342700] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  355.344859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.344886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.344909] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.344932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.346549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  355.346581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.346608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.348209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.348235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  355.350177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.353505] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  355.353559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  355.353592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  355.353634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.353714] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  355.353747] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  355.370309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  355.370352] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  355.370414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.470547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.487107] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  355.487180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  355.487252] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  355.506229] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  355.506273] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  355.506306] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  355.506344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  355.506377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  355.506412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  355.506442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  355.506471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  355.506503] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  355.506538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  355.506571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  355.506602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  355.506633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  355.506660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  355.506687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  355.506753] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  359.703153] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  364.702422] [drm] GPU HANG: ecode 8:0:0xe757fffe, in kms_pipe_crc_ba [8879], reason: Hang on render ring, action: reset
>[  364.702613] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  364.702682] drm/i915: Resetting chip after gpu hang
>[  364.703856] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8879]/0 marked guilty (score 10) banned? no
>[  364.703886] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x179fe4
>[  364.704052] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  364.707530] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  364.707567] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x179fe4, 0x0]
>[  364.707604] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  364.707644] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  364.707681] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  364.707721] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  364.707847] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  364.709181] [drm:drm_mode_addfb2] [FB:58]
>[  364.719221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  364.719235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  364.719296] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  364.719318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.719340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  364.719364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  364.719382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  364.719402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.719422] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  364.719442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  364.719460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  364.719477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.719493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.719497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  364.719513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.719517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  364.719533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  364.719550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  364.719566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.719582] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  364.719601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  364.719617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.719633] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  364.719650] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  364.719666] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  364.719685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.719707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  364.723085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.723111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  364.723136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  364.723161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  364.723186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  364.723210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  364.723237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  364.723262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  364.723288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  364.723311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  364.723335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  364.723361] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  364.723383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  364.725437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.725459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.725478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.725498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.727064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  364.727087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  364.727111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.728659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.728682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  364.730536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.733031] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  364.733085] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  364.733117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  364.733159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  364.733239] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  364.733272] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  364.749891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  364.749942] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.750012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  364.850107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.866636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  364.866684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  364.866844] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  364.885463] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  364.885512] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  364.885552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  364.885597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.885637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  364.885681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  364.885721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  364.885841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  364.885891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  364.885951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  364.886004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  364.886056] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  364.886107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  364.886148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  364.886193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  364.886298] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.887121] [drm:drm_mode_addfb2] [FB:58]
>[  364.895434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  364.895449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  364.895516] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  364.895539] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.895563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  364.895588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  364.895607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  364.895629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.895654] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  364.895680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  364.895706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  364.896040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  364.896062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.896067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  364.896088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.896092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  364.896117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  364.896142] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  364.896168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.896193] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  364.896218] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  364.896243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.896268] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  364.896294] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  364.896319] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  364.896346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.896374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  364.899662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  364.899683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  364.899702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  364.899800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  364.899831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  364.899863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  364.899893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  364.899916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  364.899936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  364.899956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  364.899973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  364.899998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  364.900019] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  364.902069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.902090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.902108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.902127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.903700] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  364.903762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  364.903781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.905352] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.905373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  364.907264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.910576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  364.910632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  364.910672] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  364.910724] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  364.911010] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  364.911031] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  364.927429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  364.927479] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  364.927544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.027631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.044201] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  365.044249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.044323] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  365.061323] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  365.061367] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  365.061400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  365.061439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.061471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.061506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.061537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.061566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.061597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.061640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.061682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.061725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.061856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.061908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.061959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.062062] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  365.062830] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  365.092428] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  365.092466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.092505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  365.092545] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  365.092578] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  365.092615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.092655] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  365.092696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  365.092765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  365.092804] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.092843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.092851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.092889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.092895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.092935] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  365.092975] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  365.093014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.093061] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  365.093093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  365.093120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.093145] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  365.093170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  365.093193] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  365.093221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.093251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  365.093343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.093368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.093392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.093416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.093439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.093463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.093491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.093517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.093543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.093565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.093587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.093615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  365.093641] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  365.095751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.095770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.095787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.095805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.097387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  365.097404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  365.097421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.098988] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.099006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  365.100889] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.104214] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  365.104270] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  365.104318] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  365.104358] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.104426] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  365.104454] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  365.121059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.121107] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  365.121176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.121414] Console: switching to colour frame buffer device 240x75
>[  365.230148] Console: switching to colour dummy device 80x25
>[  365.230321] [IGT] kms_pipe_crc_basic: executing
>[  365.246367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  365.246419] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  365.248544] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  365.248583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  365.250690] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  365.250740] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  365.252826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  365.252861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  365.254975] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  365.254986] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  365.254994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  365.255023] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  365.255065] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  365.256170] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  365.257094] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  365.257116] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  365.257138] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  365.257161] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  365.258188] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  365.258208] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  365.259323] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  365.259327] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  365.259433] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  365.259436] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  365.259441] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  365.259444] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  365.259449] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  365.259452] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  365.259461] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  365.259464] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.259468] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.259471] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.259474] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  365.259477] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  365.259481] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  365.259484] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  365.259487] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.259490] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.259493] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  365.259497] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  365.259500] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  365.259503] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  365.259506] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  365.259509] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  365.259513] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  365.259516] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  365.259519] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  365.259522] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  365.259525] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  365.259529] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  365.259532] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  365.259535] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  365.259538] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  365.259541] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  365.259545] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  365.259548] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  365.259551] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  365.259554] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  365.259557] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  365.259598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  365.259622] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  365.260791] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  365.260813] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  365.262927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  365.262938] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  365.265038] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  365.265074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  365.267169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  365.267179] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  365.267186] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  365.280296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  365.280322] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  365.282442] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  365.282481] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  365.284598] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  365.284609] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  365.286728] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  365.286796] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  365.288913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  365.288924] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  365.288931] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  365.289446] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  365.289487] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  365.290575] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  365.291500] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  365.291522] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  365.291541] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  365.291558] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  365.292582] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  365.292602] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  365.293741] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  365.293745] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  365.293846] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  365.293848] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  365.293853] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  365.293856] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  365.293861] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  365.293863] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  365.293872] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  365.293875] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.293878] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.293881] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.293884] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  365.293887] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  365.293890] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  365.293893] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  365.293896] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.293899] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  365.293902] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  365.293905] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  365.293908] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  365.293911] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  365.293914] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  365.293917] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  365.293920] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  365.293923] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  365.293926] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  365.293929] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  365.293931] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  365.293934] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  365.293937] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  365.293940] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  365.293943] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  365.293946] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  365.293949] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  365.293952] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  365.293955] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  365.293958] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  365.293961] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  365.294244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  365.294266] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  365.295765] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  365.295793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  365.297796] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  365.297807] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  365.299796] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  365.299838] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  365.301796] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  365.301807] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  365.301814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  365.302385] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-B
>[  365.303116] [drm:drm_mode_addfb2] [FB:58]
>[  365.310510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  365.310568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.321217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  365.321266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.321340] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  365.338362] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  365.338406] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  365.338439] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  365.338477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.338510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.338545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.338575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.338604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.338636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.338670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.338701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.338817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.338869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.338913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.338959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.339055] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  365.339210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  365.339230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  365.339315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  365.339346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.339377] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  365.339414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  365.339441] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  365.339473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.339502] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.339533] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.339560] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  365.339589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.339614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.339621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.339648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.339654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.339683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  365.339736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  365.339763] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.339792] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.339822] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  365.339852] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.339878] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  365.339907] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  365.339934] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  365.339966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.340001] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  365.343393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.343414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.343433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.343451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.343468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.343487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.343507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.343526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.343544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.343561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.343577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.343598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  365.343617] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  365.345672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.345692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.345767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.345794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.347365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  365.347385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  365.347403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.348963] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.348983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  365.350847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.354187] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.354240] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  365.354283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  365.354310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.371059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.371109] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.371174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.387760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  365.454637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.454813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  365.454879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.454988] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  365.473558] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  365.473595] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  365.473636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.473669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.473704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.473826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.473872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.473924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.473983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.474035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.474085] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.474136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.474181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.474227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.474320] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.475145] [drm:drm_mode_addfb2] [FB:58]
>[  365.482295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  365.482310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  365.482371] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  365.482393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.482417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  365.482444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  365.482467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  365.482491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.482515] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.482538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.482561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  365.482584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.482607] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.482612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.482634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.482638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.482662] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  365.482688] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  365.482767] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.482799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.482832] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  365.482862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.482893] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  365.482921] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  365.482952] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  365.482984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.483020] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  365.486309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.486330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.486349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.486367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.486384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.486403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.486423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.486442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.486461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.486478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.486494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.486515] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  365.486534] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  365.488589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.488610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.488629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.488648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.490262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  365.490292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  365.490319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.491974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.492005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  365.493899] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.497220] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.497272] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  365.497304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  365.497345] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.514064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.514115] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.514180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.597600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.597687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  365.597827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.597931] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  365.616568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  365.616606] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  365.616645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.616679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.616798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.616846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.616895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.616940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.616996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.617047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.617096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.617145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.617185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.617229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.617331] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.618732] [drm:drm_mode_addfb2] [FB:58]
>[  365.627858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  365.627878] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  365.627968] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  365.627999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.628032] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  365.628066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  365.628094] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  365.628124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.628153] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.628182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.628210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  365.628237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.628262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.628268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.628294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.628300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.628327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  365.628353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  365.628379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.628404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.628433] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  365.628459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.628486] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  365.628511] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  365.628537] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  365.628566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.628598] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  365.632070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.632092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.632110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.632133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.632157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.632181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.632206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.632231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.632256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.632279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.632302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.632327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  365.632348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  365.634413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.634434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.634452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.634472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.636050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  365.636073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  365.636092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.637667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.637690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  365.639581] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.642876] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.642928] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  365.642960] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  365.643001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.659775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.659824] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.659890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.743262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.743347] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  365.743392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.743462] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  365.761475] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  365.761512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  365.761552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.761585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.761620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.761650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.761679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.761793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.761851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.761905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.761967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.762015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.762059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.762102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.762179] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.763274] [drm:drm_mode_addfb2] [FB:58]
>[  365.773202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  365.773223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  365.773321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  365.773354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  365.773389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  365.773426] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  365.773455] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  365.773488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  365.773520] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  365.773550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  365.773580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  365.773609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  365.773637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  365.773644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.773671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  365.773743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  365.773790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  365.773832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  365.773876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  365.773918] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  365.773966] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  365.774008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  365.774052] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  365.774094] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  365.774136] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  365.774184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.774235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  365.778115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.778142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.778165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.778186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.778207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.778230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.778254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.778276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.778298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.778318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.778350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.778377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  365.778402] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  365.780515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  365.780540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.780561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.780583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.782221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  365.782245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  365.782267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.783881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.783907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  365.785867] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.789158] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.789211] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  365.789243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  365.789286] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  365.806021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.806071] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  365.806135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.889558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.889643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  365.889687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  365.889875] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  365.908471] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  365.908508] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  365.908548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  365.908582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  365.908617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  365.908647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  365.908676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  365.908796] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  365.908854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  365.908890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  365.908922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  365.908954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  365.908981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  365.909009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  365.909075] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  369.750607] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  374.749982] [drm] GPU HANG: ecode 8:0:0xe75ffffe, in kms_pipe_crc_ba [8883], reason: Hang on render ring, action: reset
>[  374.750188] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  374.750370] drm/i915: Resetting chip after gpu hang
>[  374.752059] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8883]/0 marked guilty (score 10) banned? no
>[  374.752095] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x17a005
>[  374.752328] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  374.754906] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  374.754938] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x17a005, 0x0]
>[  374.754978] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  374.755015] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  374.755051] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  374.755085] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  374.755118] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  374.756175] [drm:drm_mode_addfb2] [FB:58]
>[  374.766838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  374.766851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  374.766912] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  374.766933] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.766955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  374.766978] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  374.766997] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  374.767017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.767037] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  374.767057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  374.767075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  374.767093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.767110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.767115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.767131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.767135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.767152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  374.767169] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  374.767185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.767201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.767223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  374.767247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.767270] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  374.767293] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  374.767367] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  374.767400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.767437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  374.770909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.770933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  374.770954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  374.770974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  374.770992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  374.771013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  374.771035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  374.771055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  374.771075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  374.771093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  374.771110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  374.771132] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  374.771153] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  374.773199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  374.773222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  374.773246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.773272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  374.774853] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  374.774877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  374.774900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.776464] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  374.776487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  374.778356] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  374.781630] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  374.781687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  374.781727] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  374.781779] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  374.798471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  374.798520] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  374.798585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  374.882205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.882561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  374.882696] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  374.882908] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  374.900546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  374.900584] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  374.900624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.900658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  374.900693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  374.900723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  374.900752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  374.900784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  374.900819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  374.900851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  374.900882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  374.900912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  374.900940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  374.900967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  374.901031] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  374.902557] [drm:drm_mode_addfb2] [FB:58]
>[  374.911118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  374.911133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  374.911203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  374.911227] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.911253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  374.911280] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  374.911301] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  374.911365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.911395] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  374.911424] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  374.911453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  374.911480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  374.911508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.911515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.911543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.911551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  374.911578] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  374.911605] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  374.911631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.911657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.911689] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  374.911716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.911742] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  374.911771] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  374.911797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  374.911826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.911860] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  374.915350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  374.915372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  374.915391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  374.915409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  374.915426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  374.915445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  374.915465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  374.915484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  374.915502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  374.915519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  374.915535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  374.915556] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  374.915575] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  374.917621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  374.917643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  374.917665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.917689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  374.919298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  374.919339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  374.919358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.920919] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  374.920940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  374.922830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  374.926120] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  374.926164] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  374.926187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  374.926218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  374.942991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  374.943041] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  374.943106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.026513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.026598] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  375.026643] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.026714] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  375.044849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  375.044887] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.044927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.044960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.044995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.045025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.045054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.045086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.045120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.045153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.045184] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.045225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.045264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.045302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.045430] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  375.045975] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  375.072099] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  375.072137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.072175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  375.072215] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  375.072247] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  375.072281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.072342] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  375.072382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  375.072422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  375.072461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.072500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.072508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.072546] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.072552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.072592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  375.072632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  375.072672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.072711] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  375.072752] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  375.072790] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.072837] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  375.072866] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  375.072893] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  375.072922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.072954] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  375.073060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.073086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.073110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.073134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.073157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.073182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.073212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.073246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.073280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.073337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.073365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.073400] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  375.073432] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  375.075491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.075512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.075529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.075548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.077121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  375.077139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  375.077156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.078716] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.078735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  375.080611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.083792] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  375.083843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  375.083880] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  375.083933] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.084018] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  375.084056] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  375.100630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.100678] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  375.100747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.100984] Console: switching to colour frame buffer device 240x75
>[  375.209948] Console: switching to colour dummy device 80x25
>[  375.210099] [IGT] kms_pipe_crc_basic: executing
>[  375.221873] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.221925] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.223391] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.223433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.225398] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.225409] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.227387] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.227426] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.229389] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.229400] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.229408] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.229439] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.229480] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.230609] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.231537] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.231559] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.231578] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.231596] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.232613] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.232636] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.233753] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.233757] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.233854] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.233857] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.233862] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.233864] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.233869] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.233871] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.233880] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.233884] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.233887] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.233890] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.233893] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.233896] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.233899] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.233902] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.233905] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.233908] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.233911] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.233914] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.233916] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.233919] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.233922] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.233925] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.233928] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.233931] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.233934] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.233937] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.233940] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.233943] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.233946] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.233949] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.233952] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.233955] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.233958] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.233960] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.233963] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.233966] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.233969] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.234008] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.234031] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.235349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.235374] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.237397] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.237412] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.239392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.239432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.241390] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.241400] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.241407] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.254534] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  375.254559] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  375.256660] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.256697] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.258789] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  375.258799] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  375.260919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.260958] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  375.263077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  375.263088] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.263095] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  375.263710] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  375.263751] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  375.264838] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  375.265804] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  375.265826] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  375.265845] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  375.265862] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  375.266909] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  375.266929] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  375.268050] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  375.268054] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  375.268154] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.268156] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.268161] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  375.268164] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  375.268169] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  375.268171] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  375.268180] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  375.268184] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.268187] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.268189] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.268192] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.268195] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  375.268198] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.268201] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  375.268204] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.268207] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  375.268210] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  375.268213] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.268216] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  375.268219] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  375.268222] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.268225] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  375.268228] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  375.268231] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.268234] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  375.268237] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  375.268240] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  375.268243] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.268246] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  375.268249] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  375.268252] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  375.268254] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.268257] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  375.268260] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  375.268263] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.268266] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  375.268269] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  375.268899] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  375.268935] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  375.270357] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.270383] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.272392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  375.272403] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  375.274384] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.274422] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  375.276387] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  375.276398] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  375.276405] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  375.276972] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-C
>[  375.277743] [drm:drm_mode_addfb2] [FB:58]
>[  375.285194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  375.285252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.300771] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  375.300817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.300887] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  375.317915] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  375.317959] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  375.317991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.318029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.318068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.318112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.318151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.318190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.318229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.318273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.318438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.318496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.318548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.318595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.318642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.318743] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  375.318929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  375.319114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  375.319131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  375.319184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  375.319204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.319226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  375.319249] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  375.319267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  375.319287] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.319364] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.319398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.319433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  375.319463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.319494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.319502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.319532] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.319540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.319571] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  375.319601] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  375.319632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.319662] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.319697] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  375.319728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.319759] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  375.319789] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  375.319819] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  375.319851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.319888] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  375.323247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.323269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.323287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.323352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.323383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.323417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.323452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.323486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.323520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.323549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.323578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.323612] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  375.323644] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  375.325710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.325731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.325749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.325768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.327335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  375.327358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  375.327381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.328932] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.328953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  375.330841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.334134] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  375.334176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  375.334203] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  375.334238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.350998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.351046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.351110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.434543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.434626] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  375.434674] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.434748] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  375.453380] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  375.453418] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.453462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.453503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.453547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.453587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.453626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.453665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.453709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.453756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.453789] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.453819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.453845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.453870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.453929] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.455501] [drm:drm_mode_addfb2] [FB:58]
>[  375.464975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  375.464995] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  375.465089] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  375.465120] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.465152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  375.465186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  375.465214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  375.465244] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.465274] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.465350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.465382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  375.465413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.465442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.465451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.465479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.465487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.465517] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  375.465546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  375.465575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.465799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.465832] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  375.465862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.465892] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  375.465921] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  375.465950] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  375.465982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.466016] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  375.469463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.469487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.469507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.469526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.469547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.469572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.469599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.469625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.469650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.469674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.469698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.469724] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  375.469746] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  375.471804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.471826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.471845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.471864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.473518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  375.473540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  375.473559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.475112] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.475138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  375.477002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.480336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  375.480369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  375.480389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  375.480415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.497165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.497215] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.497281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.580702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.580791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  375.580841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.580918] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  375.598221] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  375.598259] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.598385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.598427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.598464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.598495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.598525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.598556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.598593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.598626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.598659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.598691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.598720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.598748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.598815] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.599912] [drm:drm_mode_addfb2] [FB:58]
>[  375.608311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  375.608326] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  375.608399] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  375.608424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.608449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  375.608477] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  375.608498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  375.608523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.608550] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.608576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.608603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  375.608629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.608655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.608659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.608685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.608689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.608716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  375.608742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  375.608768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.608794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.608819] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  375.608845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.608871] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  375.608897] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  375.608923] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  375.608950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.608979] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  375.612483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.612507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.612527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.612546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.612565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.612585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.612607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.612627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.612647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.612665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.612682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.612705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  375.612729] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  375.614793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.614814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.614833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.614852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.616526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  375.616548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  375.616567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.618126] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.618147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  375.620015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.623354] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  375.623408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  375.623441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  375.623483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.640215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.640265] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.640426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.723753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.723839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  375.723883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.723955] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  375.742148] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  375.742190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.742234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.742275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.742404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.742446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.742479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.742512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.742549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.742583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.742614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.742645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.742674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.742702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.742767] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.743870] [drm:drm_mode_addfb2] [FB:58]
>[  375.753696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  375.753716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  375.753815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  375.753849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.753884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  375.753921] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  375.753951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  375.753983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.754014] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  375.754044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  375.754073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  375.754101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.754128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.754135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.754162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.754167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  375.754195] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  375.754222] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  375.754249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.754275] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.754357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  375.754394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.754432] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  375.754469] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  375.754506] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  375.754548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.754592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  375.758525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.758552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.758575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.758597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.758618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.758641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.758665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.758688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.758710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.758730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.758762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.758791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  375.758817] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  375.760945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.760971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.760993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.761017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.762649] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  375.762679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  375.762704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.764373] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.764403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  375.766334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.769671] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  375.769724] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  375.769756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  375.769806] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.786505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.786558] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  375.786629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.870056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  375.870142] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  375.870187] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  375.870278] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  375.887575] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  375.887613] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  375.887657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  375.887697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  375.887742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  375.887782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  375.887821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  375.887860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  375.887905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  375.887947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  375.887989] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  375.888031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  375.888074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  375.888097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  375.888144] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  379.734317] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes
>[  386.717672] [drm] GPU HANG: ecode 8:0:0xe757fffe, in kms_pipe_crc_ba [8887], reason: Hang on render ring, action: reset
>[  386.717943] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  386.718057] drm/i915: Resetting chip after gpu hang
>[  386.721020] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8887]/0 marked guilty (score 10) banned? no
>[  386.721052] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x17a026
>[  386.721225] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  386.723336] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  386.723372] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x17a026, 0x0]
>[  386.723417] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  386.723477] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  386.723538] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  386.723598] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  386.723655] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  386.724880] [drm:drm_mode_addfb2] [FB:58]
>[  386.735621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  386.735634] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  386.735694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  386.735716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.735738] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  386.735762] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  386.735780] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  386.735801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.735875] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  386.735907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  386.735939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  386.735968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  386.735995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.736004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  386.736032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.736040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  386.736070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  386.736098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  386.736125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.736156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.736187] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  386.736216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.736242] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  386.736271] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  386.736296] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  386.736327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.736362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  386.739733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.739757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  386.739780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  386.739816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  386.739909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  386.739943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  386.739980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  386.740014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  386.740046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  386.740066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  386.740084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  386.740108] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  386.740130] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  386.742183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  386.742206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  386.742228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  386.742253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  386.743819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  386.743866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  386.743889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  386.745460] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  386.745483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  386.747351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  386.750640] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  386.750688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  386.750716] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  386.750753] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  386.767519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  386.767569] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  386.767635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  386.851097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.851183] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  386.851229] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.851325] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  386.869658] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  386.869696] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  386.869736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.869770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  386.869805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  386.869922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  386.869971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  386.870022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  386.870079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  386.870129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  386.870163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  386.870195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  386.870225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  386.870253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  386.870320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  386.871159] [drm:drm_mode_addfb2] [FB:58]
>[  386.879527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  386.879542] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  386.879614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  386.879640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.879666] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  386.879693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  386.879715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  386.879738] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.879761] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  386.879783] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  386.879805] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  386.879878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  386.879908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.879917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  386.879947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.879955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  386.879986] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  386.880017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  386.880048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.880077] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.880107] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  386.880138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.880168] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  386.880197] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  386.880226] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  386.880260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.880294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  386.883620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  386.883642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  386.883661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  386.883679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  386.883696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  386.883715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  386.883735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  386.883754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  386.883772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  386.883788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  386.883822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  386.883903] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  386.883925] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  386.885972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  386.885993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  386.886011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  386.886030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  386.887595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  386.887615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  386.887633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  386.889185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  386.889205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  386.891064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  386.894410] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  386.894464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  386.894496] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  386.894538] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  386.911273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  386.911321] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  386.911385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  386.994800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  386.994942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  386.994983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.995052] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.013581] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  387.013619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  387.013659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.013693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  387.013727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  387.013757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  387.013786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  387.013901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  387.013968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  387.014020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  387.014069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  387.014118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.014161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  387.014204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  387.014279] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  387.015032] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  387.033608] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  387.033647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.033686] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  387.033726] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  387.033758] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  387.033793] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.033856] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  387.033889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  387.033921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  387.033951] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  387.033984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.033992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.034031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.034036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.034076] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  387.034116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  387.034156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.034195] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  387.034235] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  387.034274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.034313] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  387.034353] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  387.034397] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  387.034421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.034445] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  387.034517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.034537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  387.034555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  387.034572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  387.034589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  387.034608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  387.034629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  387.034648] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  387.034668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.034685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  387.034702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  387.034724] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  387.034743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  387.036858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.036880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.036902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.036926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.038507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  387.038528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  387.038550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.040118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.040138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  387.042017] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.045276] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  387.045329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  387.045360] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  387.045403] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  387.045503] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  387.045550] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  387.062144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  387.062192] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  387.062261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.062499] Console: switching to colour frame buffer device 240x75
>[  387.172771] Console: switching to colour dummy device 80x25
>[  387.173085] [IGT] kms_pipe_crc_basic: executing
>[  387.185468] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  387.185520] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  387.186913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.186955] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.188894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.188906] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  387.190894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.190933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.192896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.192907] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.192915] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  387.192944] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  387.192986] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  387.194089] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  387.195028] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  387.195050] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  387.195069] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  387.195087] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  387.196104] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  387.196124] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  387.197239] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  387.197243] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  387.197341] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.197343] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.197348] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  387.197350] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  387.197355] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.197358] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.197367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  387.197370] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.197373] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.197376] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.197379] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.197382] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.197385] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.197388] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  387.197391] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.197394] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.197397] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.197400] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.197403] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.197406] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  387.197408] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.197411] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.197414] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  387.197417] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.197420] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.197423] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  387.197426] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  387.197429] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  387.197432] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  387.197435] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  387.197438] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  387.197441] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.197444] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.197447] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  387.197449] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.197452] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.197455] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  387.197492] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  387.197515] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  387.198867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.198889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.200908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.200919] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  387.202874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.202911] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.204901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.204911] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.204919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  387.217644] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  387.217669] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  387.219770] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.219806] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.221967] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.221979] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  387.224098] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.224137] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.226253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.226264] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.226271] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  387.226778] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  387.226883] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  387.227958] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  387.228885] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  387.228920] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  387.228951] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  387.228973] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  387.229994] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  387.230014] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  387.231135] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  387.231138] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  387.231239] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.231241] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.231246] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  387.231249] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  387.231253] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.231256] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.231265] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  387.231268] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.231271] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.231274] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.231277] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.231280] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.231283] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.231286] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  387.231289] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.231292] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.231295] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.231298] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.231301] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.231304] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  387.231307] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.231310] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.231313] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  387.231316] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.231319] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.231322] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  387.231325] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  387.231328] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  387.231331] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  387.231333] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  387.231336] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  387.231339] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.231342] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.231345] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  387.231348] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.231351] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.231354] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  387.231635] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  387.231659] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  387.233765] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.233798] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.235907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.235918] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  387.238022] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.238059] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.240150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.240159] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.240167] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  387.240721] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A
>[  387.241402] [drm:drm_mode_addfb2] [FB:58]
>[  387.248770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  387.248830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  387.278934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.279124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  387.395946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.412393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  387.412442] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.412516] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  387.429540] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  387.429584] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  387.429624] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  387.429668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.429709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  387.429753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  387.429793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  387.429915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  387.429968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  387.430029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  387.430083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  387.430136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  387.430190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.430232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  387.430260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  387.430305] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  387.431077] [drm:drm_mode_addfb2] [FB:58]
>[  387.439418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  387.439432] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  387.439503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  387.439528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.439553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  387.439580] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  387.439601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  387.439624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.439647] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  387.439669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  387.439689] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  387.439709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  387.439729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.439733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.439752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.439756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.439776] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  387.440225] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  387.440247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.440266] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  387.440289] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  387.440308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.440327] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  387.440345] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  387.440363] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  387.440384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.440408] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  387.443854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.443876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  387.443894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  387.443912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  387.443929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  387.443948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  387.443969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  387.443988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  387.444007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.444024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  387.444040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  387.444061] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  387.444080] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  387.446143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.446165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.446184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.446203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.447783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  387.447841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  387.447872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.449440] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.449462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  387.451337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.454624] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  387.454676] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  387.454709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  387.454735] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  387.454809] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  387.454909] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  387.471511] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  387.471561] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  387.471625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.605130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.621621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  387.621669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.621759] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  387.638866] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  387.638915] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  387.638956] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  387.639000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.639041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  387.639084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  387.639124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  387.639164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  387.639208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  387.639243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  387.639273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  387.639302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  387.639337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.639372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  387.639406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  387.639474] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  387.640644] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  387.661554] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  387.661592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.661630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  387.661670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  387.661702] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  387.661742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.661783] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  387.661850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  387.661890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  387.661929] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  387.661968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.661975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.662014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.662020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.662060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  387.662099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  387.662139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.662178] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  387.662218] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  387.662257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.662296] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  387.662335] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  387.662375] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  387.662417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.662460] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  387.662599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  387.662635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  387.662656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  387.662675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  387.662693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  387.662712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  387.662734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  387.662754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  387.662773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.662803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  387.662820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  387.662842] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  387.662861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  387.664929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.664948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.664965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.664983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.666553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  387.666571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  387.666587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.668145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.668172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  387.670055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.673540] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  387.673592] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  387.673622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  387.673664] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  387.673744] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  387.673775] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  387.690426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  387.690475] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  387.690544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  387.690823] Console: switching to colour frame buffer device 240x75
>[  387.799258] Console: switching to colour dummy device 80x25
>[  387.799406] [IGT] kms_pipe_crc_basic: executing
>[  387.811632] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  387.811684] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  387.813843] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.813879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.815993] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.816005] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  387.818123] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.818162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.820107] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.820119] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.820127] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  387.820158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  387.820200] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  387.821307] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  387.822275] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  387.822298] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  387.822317] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  387.822335] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  387.823384] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  387.823404] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  387.824530] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  387.824534] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  387.824633] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.824635] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.824640] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  387.824643] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  387.824648] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.824650] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.824659] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  387.824662] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.824665] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.824668] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.824671] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.824674] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.824677] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.824680] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  387.824683] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.824686] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.824689] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.824692] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.824695] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.824698] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  387.824701] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.824704] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.824707] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  387.824710] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.824713] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.824716] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  387.824719] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  387.824722] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  387.824725] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  387.824728] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  387.824731] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  387.824734] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.824737] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.824739] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  387.824742] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.824745] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.824748] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  387.824857] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  387.824894] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  387.826999] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.827035] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.828876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.828887] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  387.831016] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.831055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.832864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.832875] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.832882] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  387.846220] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  387.846245] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  387.848366] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.848408] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.850533] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  387.850544] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  387.852664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.852702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  387.854821] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  387.854832] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.854839] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  387.855359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  387.855402] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  387.856509] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  387.857436] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  387.857458] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  387.857477] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  387.857494] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  387.858533] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  387.858557] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  387.859679] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  387.859683] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  387.859854] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.859859] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.859868] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  387.859873] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  387.859883] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  387.859888] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  387.859904] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  387.859910] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  387.859916] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.859922] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.859929] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.859934] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  387.859941] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.859946] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  387.859953] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.859958] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  387.859965] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  387.859971] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.859978] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  387.859983] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  387.859990] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.859995] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  387.860001] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  387.860008] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.860014] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  387.860021] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  387.860027] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  387.860033] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  387.860039] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  387.860045] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  387.860050] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  387.860056] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.860062] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  387.860068] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  387.860074] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.860080] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  387.860087] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  387.860640] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  387.860673] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  387.862799] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.862870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.864883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  387.864894] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  387.867014] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.867052] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  387.869165] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  387.869176] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  387.869183] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  387.869805] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[  387.870431] [drm:drm_mode_addfb2] [FB:58]
>[  387.877841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  387.877855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  387.907284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  387.907452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  388.024211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.040699] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  388.040747] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.040929] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  388.057958] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  388.058003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  388.058036] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  388.058075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.058108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.058144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.058174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.058213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.058253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.058298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.058341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.058386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.058417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.058443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.058469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.058529] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  388.060128] [drm:drm_mode_addfb2] [FB:58]
>[  388.068946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  388.068960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  388.069033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  388.069058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.069083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  388.069110] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  388.069132] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  388.069164] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.069186] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  388.069206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  388.069226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  388.069245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.069263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.069267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.069285] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.069289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.069307] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  388.069325] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  388.069342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.069360] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  388.069381] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  388.069399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.069416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  388.069434] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  388.069451] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  388.069471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.069495] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  388.072975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.072999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.073020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.073039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.073058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.073078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.073100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.073121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.073140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.073158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.073176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.073198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  388.073218] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  388.075267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.075288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.075306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.075325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.077025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  388.077047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  388.077065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.078627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.078649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  388.080521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.083831] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  388.083864] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  388.083883] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  388.083909] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.083972] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  388.083993] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  388.100688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.100737] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  388.100894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.234290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.250821] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  388.250869] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.250941] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  388.267946] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  388.267990] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  388.268022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  388.268060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.268093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.268128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.268159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.268188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.268220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.268255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.268287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.268318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.268349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.268377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.268404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.268445] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  388.269122] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  388.290518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  388.290557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.290595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  388.290636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  388.290668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  388.290703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.290737] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  388.290802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  388.290830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  388.290855] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.290880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.290886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.290910] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.290914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.290939] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  388.290963] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  388.290987] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.291010] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  388.291038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  388.291062] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.291085] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  388.291108] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  388.291131] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  388.291159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.291190] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  388.291285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.291312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.291338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.291362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.291387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.291413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.291442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.291470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.291496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.291520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.291544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.291574] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  388.291602] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  388.293714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.293736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.293796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.293816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.295399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  388.295417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  388.295433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.297003] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.297021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  388.298905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.302373] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  388.302416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  388.302446] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  388.302489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.302559] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  388.302589] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  388.319227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.319278] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  388.319355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.319645] Console: switching to colour frame buffer device 240x75
>[  388.428892] Console: switching to colour dummy device 80x25
>[  388.429066] [IGT] kms_pipe_crc_basic: executing
>[  388.455139] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  388.455191] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  388.456842] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  388.456881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  388.458850] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  388.458861] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  388.460839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  388.460878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  388.462857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  388.462868] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  388.462876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  388.462905] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  388.462944] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  388.464068] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  388.465010] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  388.465040] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  388.465065] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  388.465089] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  388.466112] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  388.466132] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  388.467243] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  388.467247] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  388.467345] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  388.467348] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  388.467353] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  388.467355] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  388.467360] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  388.467363] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  388.467372] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  388.467375] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.467378] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.467381] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.467384] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  388.467387] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  388.467390] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  388.467393] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  388.467396] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.467399] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.467402] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  388.467405] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  388.467408] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  388.467411] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  388.467414] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  388.467416] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  388.467419] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  388.467422] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  388.467425] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  388.467428] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  388.467431] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  388.467434] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  388.467437] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  388.467440] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  388.467443] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  388.467446] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  388.467449] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  388.467452] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  388.467455] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  388.467458] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  388.467461] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  388.467499] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  388.467521] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  388.468807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  388.468832] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  388.470858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  388.470869] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  388.472986] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  388.473024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  388.475138] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  388.475148] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  388.475155] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  388.488219] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  388.488244] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  388.490364] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  388.490404] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  388.492523] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  388.492534] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  388.494653] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  388.494691] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  388.496807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  388.496817] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  388.496824] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  388.497337] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  388.497378] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  388.498479] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  388.499403] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  388.499425] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  388.499444] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  388.499462] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  388.500487] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  388.500507] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  388.501616] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  388.501619] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  388.501719] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  388.501722] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  388.501727] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  388.501765] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  388.501775] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  388.501782] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  388.501797] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  388.501804] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.501810] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.501815] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.501821] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  388.501826] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  388.501832] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  388.501837] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  388.501845] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.501851] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  388.501859] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  388.501866] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  388.501872] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  388.501879] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  388.501886] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  388.501891] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  388.501897] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  388.501903] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  388.501908] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  388.501915] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  388.501921] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  388.501928] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  388.501935] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  388.501941] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  388.501947] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  388.501952] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  388.501958] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  388.501964] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  388.501971] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  388.501977] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  388.501984] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  388.502557] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  388.502591] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  388.503811] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  388.503837] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  388.505818] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  388.505828] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  388.507847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  388.507886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  388.509836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  388.509846] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  388.509853] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  388.510424] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B
>[  388.511197] [drm:drm_mode_addfb2] [FB:58]
>[  388.518620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  388.518679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.519349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  388.519378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.519434] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  388.537713] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  388.537757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  388.537870] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  388.537929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.537975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.538027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.538070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.538117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.538162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.538214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.538265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.538314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.538363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.538404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.538447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.538544] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  388.538809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.538830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  388.538921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  388.538955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.538989] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  388.539014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  388.539033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  388.539055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.539076] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  388.539104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  388.539122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  388.539139] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.539155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.539159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.539175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.539179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.539195] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  388.539211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  388.539227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.539243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.539262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  388.539278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.539294] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  388.539310] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  388.539326] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  388.539345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.539366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  388.542733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.542772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.542790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.542808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.542825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.542843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.542864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.542882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.542901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.542917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.542934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.542954] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  388.542973] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  388.545020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.545041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.545059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.545078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.546652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  388.546672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  388.546690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.548273] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.548294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  388.550174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.553401] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  388.553434] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  388.553458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  388.553489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.570210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.570256] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.570319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.586901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  388.687361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.687495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  388.687567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.687680] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  388.705720] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  388.705791] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  388.705836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.705877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.705921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.705961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.706001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.706040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.706085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.706127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.706169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.706211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.706250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.706288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.706364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.708053] [drm:drm_mode_addfb2] [FB:58]
>[  388.717424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  388.717444] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  388.717536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  388.717567] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.717600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  388.717634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  388.717662] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  388.717693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.717722] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  388.717799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  388.717832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  388.717862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.717891] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.717899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.717928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.717936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.717966] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  388.717995] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  388.718024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.718053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.718243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  388.718275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.718305] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  388.718334] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  388.718362] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  388.718395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.718429] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  388.721853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.721879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.721903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.721928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.721952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.721977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.722003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.722029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.722056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.722087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.722124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.722149] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  388.722170] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  388.724244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.724267] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.724290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.724314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.725880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  388.725902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  388.725920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.727471] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.727493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  388.729359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.732661] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  388.732710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  388.732741] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  388.732869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.749516] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.749564] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.749627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.866462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.866550] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  388.866595] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.866679] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  388.884688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  388.884726] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  388.884853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.884907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.884965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.885021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.885060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.885099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.885143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.885184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.885225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.885266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.885303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.885341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.885416] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  388.886156] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  388.907423] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  388.907463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.907504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  388.907547] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  388.907584] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  388.907623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.907662] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  388.907700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  388.907739] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  388.907803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  388.907840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.907848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.907885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.907891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  388.907930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  388.907968] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  388.908006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.908044] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  388.908082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  388.908120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.908157] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  388.908195] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  388.908232] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  388.908272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  388.908314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  388.908436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  388.908463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  388.908487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  388.908510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  388.908532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  388.908561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  388.908595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  388.908628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  388.908661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.908691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  388.908718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  388.908766] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  388.908796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  388.910881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  388.910903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  388.910925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.910949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  388.912532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  388.912551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  388.912569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  388.914138] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  388.914158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  388.916040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  388.919565] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  388.919598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  388.919617] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  388.919643] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  388.919706] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  388.919727] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  388.936413] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  388.936461] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  388.936532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  388.936852] Console: switching to colour frame buffer device 240x75
>[  389.044245] Console: switching to colour dummy device 80x25
>[  389.044419] [IGT] kms_pipe_crc_basic: executing
>[  389.060599] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  389.060652] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  389.062179] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.062218] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.063816] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.063827] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  389.065816] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.065857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.067818] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.067829] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.067837] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  389.067867] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  389.067908] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  389.069024] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  389.069963] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  389.069985] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  389.070004] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  389.070021] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  389.071042] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  389.071063] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  389.072180] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  389.072184] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  389.072282] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.072285] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.072290] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  389.072292] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  389.072297] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.072299] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.072308] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  389.072311] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.072314] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.072317] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.072320] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.072323] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.072326] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.072329] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  389.072332] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.072335] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.072338] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.072341] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.072344] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.072347] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  389.072350] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.072353] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.072356] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  389.072359] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.072362] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.072365] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  389.072367] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  389.072370] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  389.072373] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  389.072376] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  389.072379] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  389.072382] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.072385] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.072388] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  389.072391] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.072394] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.072397] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  389.072435] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  389.072458] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  389.073795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.073819] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.075932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.075942] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  389.078042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.078079] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.080171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.080180] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.080187] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  389.093226] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  389.093251] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  389.095372] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.095410] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.097527] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.097538] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  389.099657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.099696] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.101867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.101877] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.101885] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  389.102396] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  389.102437] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  389.103531] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  389.104454] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  389.104477] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  389.104500] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  389.104523] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  389.105555] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  389.105578] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  389.106698] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  389.106701] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  389.106917] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.106920] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.106925] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  389.106928] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  389.106932] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.106935] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.106944] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  389.106947] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.106950] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.106953] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.106956] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.106959] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.106962] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.106965] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  389.106968] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.106971] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.106974] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.106977] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.106980] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.106983] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  389.106986] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.106989] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.106992] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  389.106994] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.106997] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.107000] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  389.107003] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  389.107006] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  389.107009] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  389.107012] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  389.107015] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  389.107018] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.107021] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.107024] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  389.107027] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.107029] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.107032] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  389.107312] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  389.107336] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  389.108782] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.108809] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.110769] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.110779] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  389.112794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.112834] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.114794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.114804] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.114811] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  389.115377] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B-frame-sequence
>[  389.116157] [drm:drm_mode_addfb2] [FB:58]
>[  389.123675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  389.123786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.136555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  389.136604] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.136676] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  389.153691] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  389.153817] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  389.153856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  389.153895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.153928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.153965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.153995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.154026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.154058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.154094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.154129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.154159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.154191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.154218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.154248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.154312] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  389.154448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.154461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  389.154514] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  389.154534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.154559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  389.154588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.154614] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.154641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.154667] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  389.154693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  389.154719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.154772] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.154801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.154810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.154837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.154845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.154873] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  389.154900] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.154928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.154955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.154985] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  389.155012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.155039] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  389.155065] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  389.155091] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  389.155123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.155155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  389.158452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.158476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.158496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.158514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.158533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.158553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.158574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.158595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.158614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.158632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.158650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.158672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  389.158692] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  389.160796] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.160816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.160835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.160853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.162440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  389.162462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  389.162482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.164046] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.164067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  389.165941] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.169250] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  389.169301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  389.169333] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  389.169375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.186104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.186154] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.186219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.202783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  389.303316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.303481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  389.303568] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.303716] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  389.321799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  389.321837] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  389.321877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.321911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.321946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.321975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.322004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.322035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.322070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.322102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.322141] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.322170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.322196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.322221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.322285] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.323626] [drm:drm_mode_addfb2] [FB:58]
>[  389.332014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.332029] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  389.332099] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  389.332124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.332150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  389.332176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.332197] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.332220] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.332243] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  389.332265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  389.332286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.332306] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.332326] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.332330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.332349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.332353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.332373] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  389.332392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.332411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.332430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.332453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  389.332473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.332492] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  389.332511] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  389.332529] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  389.332551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.332576] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  389.336050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.336074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.336094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.336113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.336131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.336151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.336177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.336203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.336229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.336253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.336277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.336303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  389.336325] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  389.338671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.338693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.338770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.338805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.340360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  389.340381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  389.340398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.341966] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.341990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  389.343854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.347144] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  389.347192] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  389.347223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  389.347263] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.364017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.364066] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.364131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.480957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.481044] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  389.481090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.481174] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  389.499666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  389.499703] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  389.499828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.499875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.499930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.499973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.500019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.500064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.500123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.500166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.500209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.500250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.500284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.500320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.500406] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  389.501149] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  389.522486] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  389.522527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.522568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  389.522614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.522653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.522694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.522760] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  389.522800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  389.522840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.522879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.522918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.522925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.522964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.522970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.523010] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  389.523049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.523089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.523128] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  389.523168] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  389.523206] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.523246] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  389.523285] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  389.523324] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  389.523366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.523410] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  389.523531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.523577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.523609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.523641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.523672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.523704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.523755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.523789] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.523823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.523855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.523897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.523930] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  389.523962] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  389.526043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.526063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.526080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.526098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.527680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  389.527697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  389.527731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.529294] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.529316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  389.531227] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.534747] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  389.534780] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  389.534798] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  389.534825] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.534889] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  389.534909] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  389.551607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.551655] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  389.551763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.552007] Console: switching to colour frame buffer device 240x75
>[  389.660570] Console: switching to colour dummy device 80x25
>[  389.660946] [IGT] kms_pipe_crc_basic: executing
>[  389.677522] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  389.677567] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  389.679139] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.679181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.680787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.680798] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  389.682797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.682834] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.684794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.684805] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.684812] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  389.684843] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  389.684885] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  389.686012] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  389.686946] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  389.686975] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  389.687007] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  389.687025] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  389.688045] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  389.688065] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  389.689182] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  389.689186] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  389.689284] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.689286] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.689291] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  389.689294] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  389.689299] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.689301] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.689310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  389.689313] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.689316] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.689319] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.689322] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.689325] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.689328] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.689331] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  389.689334] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.689337] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.689340] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.689343] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.689346] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.689349] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  389.689352] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.689354] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.689357] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  389.689360] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.689363] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.689366] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  389.689369] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  389.689372] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  389.689375] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  389.689378] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  389.689381] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  389.689384] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.689387] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.689390] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  389.689393] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.689396] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.689398] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  389.689437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  389.689460] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  389.690753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.690777] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.692897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.692908] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  389.695006] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.695041] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.697155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.697165] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.697173] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  389.709946] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  389.709971] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  389.712092] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.712131] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.714247] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  389.714257] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  389.715458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.715497] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  389.716795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  389.716806] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.716813] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  389.717320] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  389.717362] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  389.718467] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  389.719408] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  389.719435] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  389.719458] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  389.719479] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  389.720501] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  389.720521] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  389.721628] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  389.721631] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  389.721811] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.721814] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.721820] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  389.721823] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  389.721828] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  389.721830] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  389.721840] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  389.721844] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.721847] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.721850] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.721854] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.721857] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  389.721860] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.721863] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  389.721867] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.721870] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  389.721873] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  389.721876] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.721879] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  389.721882] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  389.721886] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.721889] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  389.721892] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  389.721895] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.721898] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  389.721910] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  389.721913] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  389.721916] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  389.721919] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  389.721922] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  389.721925] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  389.721928] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.721931] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  389.721934] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  389.721937] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.721940] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  389.721943] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  389.722237] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  389.722260] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  389.723757] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.723799] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.725766] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  389.725776] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  389.727787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.727829] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  389.729944] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  389.729954] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  389.729962] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  389.730527] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[  389.731157] [drm:drm_mode_addfb2] [FB:58]
>[  389.738475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  389.738533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.751773] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  389.751822] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.751910] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  389.770405] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  389.770449] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  389.770482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  389.770520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.770552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.770587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.770618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.770647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.770678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.770794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.770855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.770898] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.770941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.770975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.771013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.771095] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  389.771261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  389.771479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  389.771495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  389.771565] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  389.771594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.771624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  389.771661] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.771693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.771771] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.771818] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  389.771856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.771901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.771928] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.771958] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.771966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.771995] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.772003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.772034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  389.772062] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.772090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.772116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.772148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  389.772174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.772202] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  389.772228] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  389.772255] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  389.772284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.772317] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  389.775623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.775644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.775662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.775679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.775744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.775779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.775813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.775847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.775879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.775906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.775933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.775967] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  389.775995] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  389.778062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.778083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.778101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.778120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.779689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  389.779725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  389.779744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.781316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.781338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  389.783241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.786551] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.786601] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  389.786639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  389.786687] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.803390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.803441] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  389.803507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.920352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.920437] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.920481] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.920562] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.938642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  389.938679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  389.938807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.938860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.938917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.938975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.939005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.939036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.939071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.939104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.939141] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.939183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.939220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.939258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.939329] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  389.940380] [drm:drm_mode_addfb2] [FB:58]
>[  389.948925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  389.948940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  389.949011] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  389.949036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.949062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  389.949089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.949114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.949142] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.949169] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  389.949195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.949222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.949248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  389.949274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.949278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.949304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.949308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  389.949335] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  389.949361] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.949387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.949413] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.949439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  389.949465] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.949491] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  389.949517] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  389.949543] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  389.949570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.949599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  389.953072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  389.953096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  389.953116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  389.953135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  389.953154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  389.953174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  389.953196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  389.953216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  389.953236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  389.953254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  389.953272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  389.953294] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  389.953325] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  389.956641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.956662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.956688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.956767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.958350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  389.958371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  389.958389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.959953] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.959974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  389.961836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.965185] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.965238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  389.965270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  389.965312] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  389.982050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  389.982103] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  389.982174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.098985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.099072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.099123] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.099211] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.116872] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  390.116910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  390.116950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.116983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.117018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.117047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.117076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.117107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.117142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.117175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.117206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.117238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.117265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.117293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.117358] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  390.118343] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  390.135462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  390.135500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.135538] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  390.135578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  390.135610] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  390.135644] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.135687] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  390.135759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  390.135788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  390.135816] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.135842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.135850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.135876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.135881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.135908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  390.135934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  390.135960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.135987] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  390.136005] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  390.136021] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.136037] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  390.136052] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  390.136067] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  390.136086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.136107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  390.136178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.136201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.136224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.136247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.136270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.136292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.136318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.136343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.136367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.136389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.136411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.136435] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  390.136458] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  390.138523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.138542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.138560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.138578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.140149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  390.140180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  390.140202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.141775] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.141796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  390.143683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.147192] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  390.147238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  390.147264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  390.147300] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  390.147370] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  390.147395] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  390.164067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.164116] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  390.164185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.164420] Console: switching to colour frame buffer device 240x75
>[  390.271793] Console: switching to colour dummy device 80x25
>[  390.271967] [IGT] kms_pipe_crc_basic: executing
>[  390.301027] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  390.301072] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  390.302777] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.302816] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.304762] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.304773] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  390.306761] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.306800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.308764] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.308775] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.308783] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  390.308813] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  390.308858] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  390.309976] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  390.310913] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  390.310939] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  390.310962] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  390.310983] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  390.312006] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  390.312029] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  390.313144] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  390.313148] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  390.313247] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.313249] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.313255] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  390.313257] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  390.313262] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.313264] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.313273] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  390.313277] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.313280] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.313282] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.313286] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.313289] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.313292] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.313295] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  390.313298] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.313300] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.313303] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.313306] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.313309] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.313312] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  390.313315] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.313318] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.313321] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  390.313324] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.313327] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.313330] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  390.313333] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  390.313336] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  390.313339] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  390.313342] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  390.313345] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  390.313347] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.313350] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.313353] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  390.313356] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.313359] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.313362] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  390.313400] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  390.313423] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  390.314720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.314743] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.316765] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.316776] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  390.318894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.318933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.321047] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.321058] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.321066] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  390.334111] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  390.334136] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  390.336254] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.336296] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.338412] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.338423] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  390.340543] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.340581] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.342724] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.342734] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.342742] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  390.343251] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  390.343292] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  390.344396] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  390.345320] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  390.345342] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  390.345365] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  390.345388] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  390.346420] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  390.346442] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  390.347566] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  390.347569] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  390.347728] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.347733] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.347742] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  390.347744] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  390.347750] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.347753] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.347763] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  390.347767] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.347770] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.347773] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.347777] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.347780] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.347784] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.347787] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  390.347790] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.347793] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.347798] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.347801] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.347804] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.347807] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  390.347810] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.347814] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.347817] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  390.347821] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.347824] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.347828] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  390.347831] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  390.347834] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  390.347837] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  390.347841] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  390.347845] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  390.347848] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.347851] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.347854] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  390.347858] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.347861] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.347864] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  390.348171] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  390.348197] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  390.349744] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.349776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.351761] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.351771] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  390.353741] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.353778] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.355742] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.355751] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.355759] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  390.356324] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C-frame-sequence
>[  390.357108] [drm:drm_mode_addfb2] [FB:58]
>[  390.364577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  390.364634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.380904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  390.380952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.381041] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  390.398061] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  390.398105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  390.398137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  390.398175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.398207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.398241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.398270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.398298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.398329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.398364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.398396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.398427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.398458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.398485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.398521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.398574] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  390.398794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  390.399024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  390.399041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  390.399112] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  390.399146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.399182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  390.399220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  390.399253] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  390.399289] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.399322] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  390.399352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.399387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  390.399421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.399454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.399461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.399493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.399500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.399540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  390.399563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  390.399586] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.399606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.399632] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  390.399652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.399706] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  390.399735] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  390.399766] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  390.399801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.399836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  390.403272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.403293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.403316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.403340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.403363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.403386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.403411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.403436] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.403461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.403484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.403505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.403530] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  390.403551] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  390.405620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.405640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.405659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.405735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.407308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  390.407328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  390.407346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.408923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.408946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  390.410819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.414137] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.414183] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  390.414213] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  390.414250] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  390.430984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.431034] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  390.431100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.547935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.548022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.548067] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.548139] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.566619] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  390.566657] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  390.566781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.566830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.566885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.566928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.566974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.567019] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.567072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.567122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.567172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.567221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.567261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.567306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.567407] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  390.568623] [drm:drm_mode_addfb2] [FB:58]
>[  390.575958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  390.575973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  390.576033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  390.576054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.576077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  390.576100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  390.576118] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  390.576138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.576158] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  390.576176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.576194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  390.576211] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.576228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.576232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.576249] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.576252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.576269] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  390.576285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  390.576301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.576317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.576337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  390.576359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.576393] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  390.576413] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  390.576432] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  390.576462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.576485] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  390.579935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.579961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.579992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.580011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.580029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.580049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.580071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.580091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.580111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.580129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.580153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.580179] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  390.580202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  390.582283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.582307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.582327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.582348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.583936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  390.583968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  390.583995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.585579] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.585610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  390.587539] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.590875] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.590929] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  390.590962] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  390.591005] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  390.607759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.607809] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  390.607875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.724755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.724838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.724881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.724970] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.743245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  390.743283] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  390.743323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.743363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.743407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.743447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.743487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.743527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.743571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.743613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.743655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.743762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.743810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.743854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.743957] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  390.744507] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  390.767379] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  390.767421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.767463] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  390.767509] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  390.767549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  390.767589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.767630] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  390.767670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  390.767740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  390.767780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.767819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.767827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.767865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.767871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.767911] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  390.767951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  390.767990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.768029] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  390.768070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  390.768109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.768148] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  390.768187] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  390.768226] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  390.768268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.768311] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  390.768432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  390.768473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  390.768516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  390.768538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  390.768558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  390.768578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  390.768601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  390.768621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  390.768651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.768680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  390.768699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  390.768730] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  390.768750] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  390.770811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.770830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.770848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.770868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.772443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  390.772461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  390.772477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.774039] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.774057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  390.775931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.779076] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  390.779121] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  390.779147] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  390.779184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  390.779253] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  390.779280] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  390.795920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  390.795961] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  390.796026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  390.796262] Console: switching to colour frame buffer device 240x75
>[  390.904161] Console: switching to colour dummy device 80x25
>[  390.904342] [IGT] kms_pipe_crc_basic: executing
>[  390.916490] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  390.916536] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  390.918109] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.918149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.919735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.919747] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  390.921735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.921774] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.923739] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.923750] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.923757] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  390.923789] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  390.923831] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  390.924942] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  390.925886] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  390.925913] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  390.925936] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  390.925957] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  390.926970] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  390.926992] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  390.928102] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  390.928106] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  390.928205] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.928207] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.928213] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  390.928215] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  390.928220] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.928222] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.928231] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  390.928235] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.928238] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.928241] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.928244] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.928247] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.928250] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.928253] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  390.928256] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.928259] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.928262] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.928265] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.928268] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.928270] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  390.928273] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.928276] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.928279] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  390.928282] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.928285] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.928288] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  390.928291] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  390.928294] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  390.928297] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  390.928300] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  390.928303] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  390.928306] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.928309] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.928312] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  390.928315] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.928317] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.928320] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  390.928359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  390.928382] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  390.929689] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.929713] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.931795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.931804] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  390.933899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.933932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.936025] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.936033] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.936040] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  390.949344] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  390.949369] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  390.951490] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.951529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.953648] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  390.953677] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  390.955796] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.955838] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  390.957955] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  390.957965] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.957972] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  390.958487] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  390.958530] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  390.959619] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  390.960582] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  390.960604] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  390.960622] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  390.960641] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  390.961715] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  390.961736] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  390.962892] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  390.962895] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  390.962995] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.962998] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.963003] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  390.963005] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  390.963010] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  390.963012] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  390.963022] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  390.963025] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  390.963028] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.963031] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.963034] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.963037] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  390.963040] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.963043] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  390.963046] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.963049] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  390.963052] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  390.963055] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.963058] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  390.963061] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  390.963063] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.963066] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  390.963069] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  390.963072] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.963075] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  390.963078] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  390.963081] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  390.963084] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  390.963087] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  390.963090] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  390.963093] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  390.963096] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.963099] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  390.963102] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  390.963105] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.963107] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  390.963110] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  390.963399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  390.963422] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  390.964697] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.964730] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.966716] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  390.966726] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  390.968716] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.968753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  390.970747] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  390.970757] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  390.970765] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  390.971331] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A
>[  390.972033] [drm:drm_mode_addfb2] [FB:58]
>[  390.979479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  390.979493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  391.012749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.012915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  391.096558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.112890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  391.112939] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.113012] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  391.130006] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  391.130054] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  391.130095] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  391.130140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.130180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.130224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.130264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.130304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.130343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.130388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.130431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.130473] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.130515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.130554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.130591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.130752] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.131703] [drm:drm_mode_addfb2] [FB:58]
>[  391.140059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  391.140074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  391.140145] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  391.140170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.140195] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  391.140223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  391.140245] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  391.140268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.140291] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  391.140312] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  391.140333] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  391.140353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.140372] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.140377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.140396] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.140400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.140420] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  391.140439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  391.140458] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.140481] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  391.140508] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  391.140534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.140560] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  391.140586] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  391.140609] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  391.140637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.140713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  391.144189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.144212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.144233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.144252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.144270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.144290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.144312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.144332] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.144352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.144370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.144397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.144421] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  391.144443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  391.146489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.146510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.146529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.146547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.148116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  391.148136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  391.148154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.149738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.149759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  391.151637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.154963] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  391.155014] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  391.155045] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  391.155086] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.155161] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  391.155192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  391.171800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.171845] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.171907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.272040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.288564] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  391.288613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.288793] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  391.305783] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  391.305827] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  391.305859] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  391.305897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.305929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.305965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.305995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.306024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.306055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.306090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.306122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.306154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.306185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.306213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.306240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.306308] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.307584] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  391.328390] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  391.328430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.328468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  391.328507] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  391.328540] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  391.328575] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.328609] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  391.328670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  391.328703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  391.328733] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.328762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.328769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.328798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.328804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.328834] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  391.328863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  391.328891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.328918] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  391.328952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  391.328979] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.329007] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  391.329035] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  391.329062] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  391.329098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.329142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  391.329281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.329322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.329362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.329402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.329442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.329481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.329531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.329564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.329598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.329629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.329677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.329711] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  391.329743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  391.331842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.331866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.331888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.331910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.333471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  391.333494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  391.333517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.335081] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.335101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  391.336985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.340515] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  391.340572] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  391.340610] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  391.340684] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.340784] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  391.340813] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  391.357358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.357408] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.357484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.357811] Console: switching to colour frame buffer device 240x75
>[  391.465497] Console: switching to colour dummy device 80x25
>[  391.465789] [IGT] kms_pipe_crc_basic: executing
>[  391.482473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  391.482525] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  391.484082] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  391.484121] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  391.485715] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  391.485726] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  391.487725] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  391.487763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  391.489718] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  391.489729] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  391.489736] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  391.489766] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  391.489807] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  391.490931] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  391.491864] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  391.491885] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  391.491903] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  391.491921] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  391.492946] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  391.492967] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  391.494083] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  391.494086] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  391.494184] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  391.494186] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  391.494191] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  391.494194] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  391.494198] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  391.494201] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  391.494210] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  391.494213] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.494216] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.494219] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.494222] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  391.494225] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  391.494228] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  391.494231] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  391.494234] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.494237] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.494240] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  391.494243] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  391.494246] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  391.494249] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  391.494252] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.494255] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.494258] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  391.494261] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.494264] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.494267] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  391.494270] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  391.494273] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  391.494276] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  391.494279] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  391.494282] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  391.494284] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.494287] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.494290] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  391.494293] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.494296] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.494299] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  391.494338] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  391.494361] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  391.495675] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  391.495701] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  391.497793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  391.497804] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  391.499921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  391.499960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  391.502073] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  391.502084] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  391.502091] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  391.515016] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  391.515040] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  391.517164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  391.517206] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  391.519323] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  391.519334] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  391.521452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  391.521494] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  391.522738] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  391.522750] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  391.522757] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  391.523266] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  391.523308] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  391.524428] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  391.525355] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  391.525376] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  391.525395] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  391.525412] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  391.526433] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  391.526453] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  391.527571] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  391.527575] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  391.527750] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  391.527762] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  391.527767] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  391.527769] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  391.527774] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  391.527776] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  391.527785] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  391.527789] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.527792] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.527795] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.527798] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  391.527801] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  391.527804] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  391.527807] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  391.527810] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.527813] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.527816] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  391.527819] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  391.527821] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  391.527825] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  391.527827] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.527830] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.527833] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  391.527836] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.527839] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.527842] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  391.527845] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  391.527848] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  391.527851] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  391.527854] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  391.527857] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  391.527860] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.527863] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.527866] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  391.527869] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.527872] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.527874] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  391.528155] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  391.528178] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  391.529673] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  391.529694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  391.531687] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  391.531695] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  391.533688] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  391.533721] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  391.535694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  391.535704] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  391.535712] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  391.536270] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A-frame-sequence
>[  391.536964] [drm:drm_mode_addfb2] [FB:58]
>[  391.544335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  391.544349] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  391.574157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  391.574345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  391.658029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.674360] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  391.674451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.674591] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  391.691777] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  391.691825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  391.691865] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  391.691910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.691950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.691994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.692033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.692073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.692113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.692157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.692200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.692242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.692284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.692323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.692344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.692387] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.693274] [drm:drm_mode_addfb2] [FB:58]
>[  391.701782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  391.701796] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  391.701861] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  391.701885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.701909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  391.701934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  391.701954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  391.701976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.701998] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  391.702018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  391.702038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  391.702056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.702074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.702079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.702097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.702101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.702119] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  391.702137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  391.702154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.702171] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  391.702192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  391.702210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.702228] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  391.702245] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  391.702262] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  391.702283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.702306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  391.705670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.705692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.705712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.705730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.705747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.705766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.705787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.705806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.705825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.705842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.705859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.705880] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  391.705899] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  391.707942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.707962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.707981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.707999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.709656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  391.709678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  391.709700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.711271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.711292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  391.713164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.716450] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  391.716502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  391.716541] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  391.716592] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.716770] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  391.716800] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  391.733332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.733380] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.733445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.833546] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.850031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  391.850079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.850150] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  391.868545] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  391.868590] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  391.868708] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  391.868756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.868791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.868828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.868859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.868889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.868923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.868959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.868993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.869026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.869058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.869088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.869116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.869183] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.869928] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  391.891472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  391.891510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.891548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  391.891588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  391.891648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  391.891683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.891718] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  391.891750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  391.891789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  391.891815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  391.891839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.891845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.891869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.891873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  391.891898] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  391.891922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  391.891946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.891969] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  391.891998] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  391.892022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.892046] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  391.892069] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  391.892101] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  391.892137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  391.892174] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  391.892297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  391.892331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  391.892365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  391.892399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  391.892433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  391.892466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  391.892503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  391.892539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  391.892575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.892608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  391.892659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  391.892695] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  391.892729] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  391.894821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.894841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.894858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.894876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.896445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  391.896464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  391.896482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.898041] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.898059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  391.899945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.903387] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  391.903435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  391.903468] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  391.903512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.903587] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  391.903639] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  391.920267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  391.920315] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  391.920384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  391.920654] Console: switching to colour frame buffer device 240x75
>[  392.030876] Console: switching to colour dummy device 80x25
>[  392.030982] [IGT] kms_pipe_crc_basic: executing
>[  392.043424] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  392.043476] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  392.045051] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.045093] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.046692] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.046703] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  392.048676] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.048712] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.050693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.050704] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.050711] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  392.050741] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  392.050783] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  392.051910] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  392.052850] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  392.052883] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  392.052914] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  392.052945] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  392.053969] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  392.053993] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.055111] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  392.055115] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  392.055213] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.055215] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.055220] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  392.055223] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  392.055228] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.055230] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.055239] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  392.055242] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.055245] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.055248] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.055251] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.055254] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.055257] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.055260] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  392.055263] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.055266] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.055269] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.055272] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.055275] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.055278] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  392.055281] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.055284] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.055287] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  392.055290] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.055293] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.055296] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  392.055299] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  392.055302] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.055305] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.055308] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.055310] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  392.055313] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.055316] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.055319] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  392.055322] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.055325] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.055328] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  392.055366] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  392.055390] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  392.056680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.056711] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.058702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.058713] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  392.060693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.060732] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.062693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.062703] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.062711] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  392.075694] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  392.075718] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  392.077835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.077873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.079989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.080000] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  392.082120] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.082158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.084275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.084286] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.084293] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  392.084962] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  392.085003] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  392.086095] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  392.087027] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  392.087049] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  392.087067] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  392.087084] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  392.088104] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  392.088124] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.089267] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  392.089270] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  392.089369] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.089372] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.089377] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  392.089379] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  392.089384] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.089386] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.089396] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  392.089399] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.089402] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.089405] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.089408] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.089411] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.089414] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.089417] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  392.089420] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.089423] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.089426] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.089429] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.089432] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.089435] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  392.089438] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.089440] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.089443] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  392.089446] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.089449] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.089452] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  392.089455] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  392.089458] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.089461] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.089464] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.089467] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  392.089470] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.089473] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.089476] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  392.089479] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.089482] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.089485] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  392.089986] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  392.090022] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  392.091656] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.091682] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.093704] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.093714] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  392.095834] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.095873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.097969] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.097979] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.097986] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  392.098540] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B
>[  392.099133] [drm:drm_mode_addfb2] [FB:58]
>[  392.106481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  392.106538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.120393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  392.120441] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.120514] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  392.138851] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  392.138896] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  392.138928] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  392.138966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.138999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.139034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.139064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.139093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.139124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.139158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.139189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.139220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.139249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.139286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.139325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.139399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  392.139557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.139576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  392.139779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  392.139823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.139858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  392.139894] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  392.139922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  392.139954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.139983] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  392.140013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  392.140040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  392.140068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.140094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.140102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.140129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.140135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.140163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  392.140189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  392.140217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.140242] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.140273] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  392.140299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.140326] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  392.140352] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  392.140380] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  392.140409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.140441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  392.143845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.143866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.143884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.143902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.143919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.143937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.143957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.143976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.143999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.144022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.144045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.144070] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  392.144094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  392.146189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.146210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.146228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.146247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.147833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  392.147856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  392.147879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.149446] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.149467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  392.151342] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.154687] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  392.154740] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  392.154773] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  392.154814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.171551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.171602] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.171768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.188204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  392.255092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.255176] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  392.255221] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.255291] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  392.273486] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  392.273524] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  392.273568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.273688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.273750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.273801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.273850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.273897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.273936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.273971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.274012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.274038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.274064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.274090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.274140] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.274994] [drm:drm_mode_addfb2] [FB:58]
>[  392.283389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.283404] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  392.283474] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  392.283499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.283525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  392.283552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  392.283573] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  392.283648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.283681] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  392.283713] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  392.283745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  392.283776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.283805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.283814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.283843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.283850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.283880] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  392.283908] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  392.283936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.283962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.283993] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  392.284023] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.284049] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  392.284078] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  392.284107] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  392.284139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.284174] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  392.287660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.287683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.287702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.287719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.287737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.287755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.287776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.287795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.287814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.287831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.287847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.287868] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  392.287891] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  392.289949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.289970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.289989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.290008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.291585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  392.291617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  392.291635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.293199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.293220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  392.295125] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.298438] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  392.298491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  392.298524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  392.298574] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.315288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.315338] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.315403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.398807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.398892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  392.398936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.399008] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  392.417360] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  392.417397] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  392.417437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.417470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.417506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.417536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.417565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.417688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.417755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.417803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.417848] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.417895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.417936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.417977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.418067] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.418866] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  392.437379] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  392.437418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.437456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  392.437502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  392.437541] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  392.437582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.437662] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  392.437702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  392.437742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  392.437781] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.437820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.437828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.437866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.437872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.437912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  392.437952] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  392.437991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.438030] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  392.438070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  392.438108] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.438146] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  392.438167] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  392.438189] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  392.438214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.438239] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  392.438317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.438341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.438365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.438388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.438412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.438435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.438462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.438487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.438512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.438535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.438556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.438592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  392.438646] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  392.440714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.440733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.440750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.440769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.442337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  392.442364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  392.442380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.443935] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.443962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  392.445848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.449362] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  392.449413] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  392.449433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  392.449461] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.449528] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  392.449559] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  392.466220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.466268] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  392.466336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.466607] Console: switching to colour frame buffer device 240x75
>[  392.574298] Console: switching to colour dummy device 80x25
>[  392.574449] [IGT] kms_pipe_crc_basic: executing
>[  392.586478] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  392.586529] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  392.588697] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.588735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.590851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.590863] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  392.592981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.593021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.595138] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.595149] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.595157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  392.595186] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  392.595229] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  392.596346] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  392.597274] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  392.597296] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  392.597315] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  392.597334] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  392.598354] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  392.598375] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.599487] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  392.599491] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  392.599648] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.599651] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.599658] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  392.599660] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  392.599666] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.599668] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.599678] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  392.599682] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.599686] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.599690] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.599693] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.599696] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.599699] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.599703] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  392.599706] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.599710] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.599713] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.599716] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.599720] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.599723] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  392.599727] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.599730] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.599734] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  392.599737] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.599740] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.599743] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  392.599748] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  392.599752] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.599755] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.599758] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.599761] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  392.599765] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.599769] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.599772] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  392.599775] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.599780] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.599783] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  392.599827] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  392.599853] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  392.601682] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.601720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.603670] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.603681] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  392.605676] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.605716] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.607680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.607690] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.607698] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  392.620734] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  392.620759] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  392.622860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.622896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.624995] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  392.625005] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  392.627124] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.627162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  392.629278] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  392.629289] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.629297] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  392.630006] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  392.630048] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  392.631106] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  392.632066] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  392.632088] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  392.632110] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  392.632133] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  392.633188] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  392.633209] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.634326] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  392.634329] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  392.634429] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.634431] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.634436] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  392.634439] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  392.634443] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.634446] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.634455] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  392.634458] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.634461] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.634464] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.634467] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.634470] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.634473] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.634476] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  392.634479] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.634482] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.634485] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.634488] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.634491] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.634494] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  392.634497] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.634500] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.634503] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  392.634506] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.634509] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.634512] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  392.634515] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  392.634518] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.634521] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.634524] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.634526] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  392.634529] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.634532] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.634535] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  392.634538] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.634541] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.634544] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  392.635166] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  392.635201] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  392.636680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.636719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.638671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.638682] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  392.640802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.640840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.642955] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.642965] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.642972] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  392.643550] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B-frame-sequence
>[  392.644306] [drm:drm_mode_addfb2] [FB:58]
>[  392.651835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  392.651893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.666378] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  392.666426] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.666499] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  392.683524] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  392.683568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  392.683689] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  392.683736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.683770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.683805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.683836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.683865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.683897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.683932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.683973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.684017] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.684060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.684100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.684140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.684217] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  392.684363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.684382] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  392.684454] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  392.684476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.684501] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  392.684526] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  392.684545] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  392.684569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.684627] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  392.684656] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  392.684686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  392.684712] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.684740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.684750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.684775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.684783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.684810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  392.684836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  392.684863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.684891] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.684921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  392.684948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.684974] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  392.685000] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  392.685026] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  392.685057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.685088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  392.688484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.688505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.688523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.688540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.688557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.688621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.688653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.688686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.688714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.688733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.688751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.688774] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  392.688795] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  392.690849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.690871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.690890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.690909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.692479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  392.692500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  392.692518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.694098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.694119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  392.696006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.699316] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  392.699371] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  392.699411] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  392.699462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.716152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.716201] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.716271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.732850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  392.799781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.799865] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  392.799914] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.800008] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  392.818352] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  392.818389] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  392.818430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.818463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.818498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.818537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.818577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.818695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.818753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.818807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.818859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.818913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.818940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.818968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.819033] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.819898] [drm:drm_mode_addfb2] [FB:58]
>[  392.828774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  392.828795] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  392.828900] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  392.828931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.828962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  392.828997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  392.829025] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  392.829055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.829084] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  392.829112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  392.829140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  392.829167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.829192] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.829199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.829224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.829231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.829258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  392.829283] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  392.829309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.829336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.829365] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  392.829390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.829416] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  392.829442] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  392.829467] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  392.829496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.829527] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  392.833535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.833559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.833633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.833667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.833696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.833726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.833760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.833792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.833824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.833850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.833877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.833911] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  392.833940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  392.836020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.836043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.836061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.836081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.837669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  392.837689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  392.837707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.839255] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.839276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  392.841145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.844441] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  392.844475] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  392.844499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  392.844531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.861310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.861362] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.861433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.944846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.944933] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  392.944983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  392.945076] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  392.963531] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  392.963574] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  392.963699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.963747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.963804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.963848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.963893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.963937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  392.963990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.964040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.964090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.964140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.964180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.964222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.964320] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  392.964969] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  392.986347] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  392.986385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.986424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  392.986464] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  392.986496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  392.986530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.986565] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  392.986625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  392.986658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  392.986688] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  392.986717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.986724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.986752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.986757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  392.986786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  392.986815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  392.986843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.986871] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  392.986904] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  392.986932] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.986969] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  392.986992] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  392.987015] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  392.987044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  392.987075] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  392.987185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  392.987212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  392.987238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  392.987262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  392.987286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  392.987311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  392.987340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  392.987367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  392.987394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  392.987418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  392.987442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  392.987471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  392.987499] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  392.989612] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  392.989633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.989651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.989670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.991253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  392.991271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  392.991288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.992859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.992877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  392.994765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.998260] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  392.998293] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  392.998315] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  392.998347] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  392.998411] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  392.998439] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  393.015137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.015185] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  393.015257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.015582] Console: switching to colour frame buffer device 240x75
>[  393.124283] Console: switching to colour dummy device 80x25
>[  393.124452] [IGT] kms_pipe_crc_basic: executing
>[  393.141439] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  393.141491] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  393.143028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.143067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.144644] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.144655] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  393.146642] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.146684] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.148647] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.148658] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.148665] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  393.148695] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  393.148737] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  393.149860] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  393.150801] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  393.150830] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  393.150855] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  393.150879] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  393.151899] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  393.151920] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.153041] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  393.153044] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  393.153142] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.153145] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.153150] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  393.153153] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  393.153157] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.153160] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.153169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  393.153172] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.153175] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.153178] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.153181] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.153184] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.153187] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.153190] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  393.153193] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.153196] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.153199] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.153202] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.153205] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.153208] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  393.153210] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.153213] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.153216] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  393.153219] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.153222] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.153225] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  393.153228] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  393.153231] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.153234] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  393.153237] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.153240] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  393.153243] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.153246] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.153249] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  393.153251] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.153254] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.153257] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  393.153296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  393.153318] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  393.154602] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.154626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.156740] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.156751] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  393.158853] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.158889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.161003] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.161014] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.161021] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  393.174074] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  393.174099] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  393.176219] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.176258] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.178374] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.178385] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  393.180507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.180545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.182721] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.182732] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.182739] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  393.183296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  393.183340] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  393.184449] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  393.185374] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  393.185397] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  393.185415] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  393.185433] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  393.186455] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  393.186476] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.187615] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  393.187619] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  393.187718] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.187721] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.187726] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  393.187728] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  393.187733] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.187735] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.187744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  393.187748] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.187751] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.187754] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.187757] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.187760] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.187763] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.187766] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  393.187769] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.187772] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.187775] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.187778] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.187781] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.187784] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  393.187786] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.187789] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.187792] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  393.187795] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.187798] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.187801] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  393.187804] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  393.187807] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.187810] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  393.187813] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.187816] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  393.187819] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.187822] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.187825] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  393.187828] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.187831] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.187834] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  393.188116] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  393.188139] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  393.189625] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.189656] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.191771] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.191782] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  393.193899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.193937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.196051] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.196062] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.196069] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  393.196766] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C
>[  393.197280] [drm:drm_mode_addfb2] [FB:58]
>[  393.204643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  393.204701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.215308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  393.215357] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.215431] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  393.232439] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  393.232488] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  393.232541] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  393.232671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.232724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.232780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.232828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.232875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.232925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.232981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.233031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.233063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.233095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.233125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.233153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.233218] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  393.233349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.233463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  393.233475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  393.233524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  393.233547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.233624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  393.233664] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  393.233698] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  393.233733] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.233767] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  393.233800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  393.233832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  393.233864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.233894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.233904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.233933] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.233940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.233971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  393.234001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  393.234031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.234058] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.234091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  393.234121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.234150] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  393.234177] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  393.234207] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  393.234240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.234275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  393.237679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.237700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.237718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.237735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.237751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.237769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.237789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.237807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.237825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.237841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.237857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.237877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  393.237896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  393.239948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.239968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.239986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.240005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.241593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  393.241613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  393.241631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.243196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.243220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  393.245098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.248360] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  393.248393] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  393.248416] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  393.248448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.265192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.265242] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  393.265313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.348736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.348822] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  393.348866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.348953] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  393.367407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  393.367446] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  393.367486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.367526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.367654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.367695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.367728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.367760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.367797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.367829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.367861] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.367892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.367920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.367948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.368014] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  393.369024] [drm:drm_mode_addfb2] [FB:58]
>[  393.378068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  393.378088] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  393.378179] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  393.378211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.378244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  393.378278] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  393.378305] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  393.378335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.378365] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  393.378393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  393.378422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  393.378449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.378475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.378481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.378507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.378513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.378540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  393.378613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  393.378644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.378674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.378708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  393.378738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.378768] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  393.378797] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  393.378825] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  393.378858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.378893] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  393.382252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.382275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.382295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.382314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.382332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.382352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.382374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.382394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.382414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.382432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.382449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.382471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  393.382492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  393.384590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.384612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.384630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.384650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.386224] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  393.386244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  393.386262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.387821] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.387841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  393.389708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.392989] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  393.393022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  393.393041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  393.393067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.409818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.409869] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  393.409935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.493341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.493428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  393.493472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.493560] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  393.510431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  393.510468] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  393.510509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.510542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.510660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.510706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.510754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.510799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.510857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.510911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.510944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.510976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.511002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.511029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.511094] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  393.511698] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  393.529329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  393.529364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.529401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  393.529444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  393.529481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  393.529522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.529592] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  393.529624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  393.529654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  393.529682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.529709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.529716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.529743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.529748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.529775] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  393.529802] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  393.529828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.529853] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  393.529886] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  393.529912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.529938] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  393.529963] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  393.529988] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  393.530019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.530054] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  393.530181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.530210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.530238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.530266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.530282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.530298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.530318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.530335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.530352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.530379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.530395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.530420] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  393.530445] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  393.532496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.532520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.532563] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.532587] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.534166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  393.534185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  393.534202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.535764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.535783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  393.537664] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.541130] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  393.541181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  393.541211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  393.541254] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.541354] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  393.541402] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  393.557953] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.557995] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  393.558061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.558298] Console: switching to colour frame buffer device 240x75
>[  393.665030] Console: switching to colour dummy device 80x25
>[  393.665203] [IGT] kms_pipe_crc_basic: executing
>[  393.676414] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  393.676466] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  393.678600] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.678636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.680749] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.680760] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  393.682879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.682918] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.685034] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.685045] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.685053] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  393.685084] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  393.685126] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  393.686240] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  393.687166] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  393.687188] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  393.687206] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  393.687224] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  393.688250] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  393.688270] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.689389] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  393.689392] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  393.689490] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.689493] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.689498] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  393.689500] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  393.689505] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.689507] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.689556] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  393.689563] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.689569] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.689575] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.689583] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.689589] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.689596] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.689602] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  393.689608] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.689613] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.689619] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.689624] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.689630] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.689636] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  393.689642] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.689649] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.689655] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  393.689662] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.689668] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.689675] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  393.689681] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  393.689688] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.689693] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  393.689699] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.689705] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  393.689712] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.689718] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.689724] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  393.689730] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.689736] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.689742] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  393.689796] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  393.689821] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  393.691941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.691980] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.694095] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.694106] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  393.696224] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.696263] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.698378] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.698389] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.698396] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  393.711331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  393.711356] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  393.713478] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.713520] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.715693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  393.715704] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  393.717824] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.717866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  393.719982] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  393.719992] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.720000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  393.720511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  393.720629] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  393.721730] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  393.722648] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  393.722680] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  393.722699] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  393.722717] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  393.723739] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  393.723760] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.724869] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  393.724872] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  393.724973] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.724975] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.724981] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  393.724983] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  393.724988] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.724990] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.724999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  393.725003] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.725006] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.725009] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.725012] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.725015] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.725018] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.725021] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  393.725024] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.725027] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.725030] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.725033] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.725036] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.725039] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  393.725042] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.725045] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.725048] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  393.725051] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.725054] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.725056] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  393.725059] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  393.725062] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.725065] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  393.725068] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.725071] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  393.725074] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.725077] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.725080] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  393.725083] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.725086] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.725089] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  393.725383] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  393.725406] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  393.727496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.727531] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.729608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.729617] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  393.730874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.730913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.733009] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.733018] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.733025] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  393.733762] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C-frame-sequence
>[  393.734346] [drm:drm_mode_addfb2] [FB:58]
>[  393.741663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  393.741719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.758143] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  393.758191] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.758265] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  393.775336] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  393.775380] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  393.775412] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  393.775451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.775483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.775518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.775699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.775749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.775800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.775853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.775887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.775919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.775951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.775979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.776007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.776072] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  393.776205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  393.776351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  393.776365] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  393.776431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  393.776457] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.776486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  393.776521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  393.776596] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  393.776635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.776672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  393.776708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  393.776743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  393.776777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.776810] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.776820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.776852] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.776862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.776896] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  393.776928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  393.776962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.776994] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.777031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  393.777064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.777101] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  393.777136] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  393.777170] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  393.777214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.777250] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  393.780557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.780577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.780595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.780613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.780630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.780648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.780667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.780686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.780704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.780721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.780737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.780757] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  393.780776] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  393.782815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.782836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.782854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.782873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.784433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  393.784453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  393.784471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.786053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.786074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  393.787967] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.791283] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  393.791333] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  393.791365] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  393.791413] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.808118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.808169] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  393.808239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.891718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.891801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  393.891843] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  393.891941] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  393.910185] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  393.910223] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  393.910266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.910307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.910351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.910391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.910431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.910470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.910518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.910654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.910710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.910766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.910813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.910862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.910966] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  393.911973] [drm:drm_mode_addfb2] [FB:58]
>[  393.919096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  393.919109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  393.919170] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  393.919192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.919214] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  393.919237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  393.919255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  393.919276] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.919296] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  393.919314] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  393.919332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  393.919349] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  393.919366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.919370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.919386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.919390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  393.919407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  393.919423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  393.919439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.919455] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.919474] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  393.919491] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.919510] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  393.919582] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  393.919611] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  393.919646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  393.919681] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  393.922970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  393.922992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  393.923010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  393.923028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  393.923045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  393.923064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  393.923084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  393.923103] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  393.923121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  393.923138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  393.923154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  393.923175] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  393.923194] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  393.925257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  393.925280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.925299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.925319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.926882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  393.926904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  393.926923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.928462] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.928486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  393.930331] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.933659] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  393.933713] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  393.933745] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  393.933788] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  393.950496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  393.950629] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  393.950733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.034031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.034118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  394.034162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  394.034249] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  394.052355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  394.052391] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  394.052432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.052465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  394.052499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  394.052618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  394.052667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  394.052718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  394.052775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  394.052823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  394.052858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  394.052889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.052919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  394.052952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  394.052998] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.053457] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  394.075222] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  394.075262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  394.075302] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  394.075346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  394.075383] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  394.075422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  394.075461] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  394.075499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  394.075563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  394.075601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  394.075638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.075646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.075683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.075689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.075727] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  394.075766] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  394.075804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.075841] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  394.075880] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  394.075917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.075955] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  394.075993] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  394.076030] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  394.076070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.076113] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  394.076229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.076268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  394.076314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  394.076343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  394.076375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  394.076407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  394.076443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  394.076477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  394.076511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.076573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  394.076600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  394.076631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  394.076656] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  394.078744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  394.078763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.078779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.078802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.080385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  394.080404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  394.080422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.081991] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.082010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  394.083917] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.087441] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  394.087494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  394.087524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  394.087589] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  394.087652] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  394.087680] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  394.104289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  394.104336] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  394.104405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.104675] Console: switching to colour frame buffer device 240x75
>[  394.211275] Console: switching to colour dummy device 80x25
>[  394.211444] [IGT] kms_pipe_crc_basic: executing
>[  394.223396] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  394.223441] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  394.224599] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  394.224634] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  394.226615] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  394.226626] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  394.228602] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  394.228640] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  394.230606] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  394.230617] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.230624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  394.230655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  394.230696] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  394.231802] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  394.232737] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  394.232759] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  394.232781] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  394.232804] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  394.233825] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  394.233846] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  394.234965] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  394.234969] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  394.235067] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.235070] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.235075] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  394.235077] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  394.235082] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.235084] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.235093] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  394.235096] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.235100] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.235103] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.235106] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.235109] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.235112] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  394.235115] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  394.235118] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.235120] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.235123] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  394.235126] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.235129] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.235132] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  394.235135] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.235138] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.235141] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  394.235144] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.235147] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.235150] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  394.235153] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  394.235156] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  394.235159] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  394.235161] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  394.235164] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  394.235167] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.235170] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.235173] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  394.235176] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.235179] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.235182] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  394.235221] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  394.235244] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  394.236566] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.236592] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.238690] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.238700] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  394.240800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.240836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.242950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.242960] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.242968] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  394.255621] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  394.255647] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  394.257765] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  394.257804] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  394.259921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  394.259931] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  394.262051] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  394.262090] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  394.264207] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  394.264217] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.264225] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  394.264888] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  394.264928] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  394.265993] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  394.266914] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  394.266936] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  394.266955] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  394.266975] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  394.267995] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  394.268016] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  394.269135] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  394.269138] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  394.269238] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.269240] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.269245] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  394.269248] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  394.269252] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.269255] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.269264] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  394.269267] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.269270] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.269273] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.269276] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.269279] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.269282] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  394.269285] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  394.269288] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.269291] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.269294] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  394.269297] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.269300] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.269303] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  394.269306] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.269309] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.269312] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  394.269315] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.269318] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.269321] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  394.269324] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  394.269326] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  394.269329] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  394.269332] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  394.269335] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  394.269338] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.269341] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.269344] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  394.269347] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.269350] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.269353] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  394.269826] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  394.269859] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  394.271613] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.271652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.273603] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.273613] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  394.275733] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.275773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.277870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.277880] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.277887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  394.278439] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
>[  394.317825] PM: Syncing filesystems ... done.
>[  394.318093] PM: Preparing system for sleep (mem)
>[  394.318745] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  394.320431] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  394.321941] PM: Suspending system (mem)
>[  394.322062] Suspending console(s) (use no_console_suspend to debug)
>[  394.324286] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  394.324382] sd 0:0:0:0: [sda] Stopping disk
>[  394.325467] e1000e: EEE TX LPI TIMER: 00000011
>[  394.338796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.354430] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  394.354467] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  394.373503] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  394.373585] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  394.373620] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  394.373664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.373704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  394.373747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  394.373786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  394.373826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  394.373865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  394.373909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  394.373950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  394.373991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  394.374032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.374070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  394.374108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  394.374178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  394.376262] PM: suspend of devices complete after 52.965 msecs
>[  394.377737] [drm:intel_power_well_disable [i915]] disabling display
>[  394.377766] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  394.377782] [drm:intel_power_well_disable [i915]] disabling always-on
>[  394.377807] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  394.389604] PM: late suspend of devices complete after 13.336 msecs
>[  394.391599] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  394.391890] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  394.403635] PM: noirq suspend of devices complete after 14.026 msecs
>[  394.404011] ACPI: Preparing to enter system sleep state S3
>[  394.429275] PM: Saving platform NVS memory
>[  394.453643] Disabling non-boot CPUs ...
>[  394.467020] smpboot: CPU 1 is now offline
>[  394.483652] Broke affinity for irq 23
>[  394.483660] Broke affinity for irq 42
>[  394.485002] smpboot: CPU 2 is now offline
>[  394.501669] Broke affinity for irq 8
>[  394.501673] Broke affinity for irq 9
>[  394.501680] Broke affinity for irq 23
>[  394.501685] Broke affinity for irq 42
>[  394.501689] Broke affinity for irq 44
>[  394.502751] smpboot: CPU 3 is now offline
>[  394.505179] ACPI: Low-level resume complete
>[  394.505326] PM: Restoring platform NVS memory
>[  394.507654] Suspended for 16.327 seconds
>[  394.507748] Enabling non-boot CPUs ...
>[  394.507881] x86: Booting SMP configuration:
>[  394.507886] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  394.509939]  cache: parent cpu1 should not be sleeping
>[  394.511662] CPU1 is up
>[  394.511775] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  394.513168]  cache: parent cpu2 should not be sleeping
>[  394.514029] CPU2 is up
>[  394.514093] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  394.515329]  cache: parent cpu3 should not be sleeping
>[  394.517205] CPU3 is up
>[  394.542906] ACPI: Waking up from system sleep state S3
>[  394.566927] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  394.566932] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  394.567106] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  394.567629] PM: noirq resume of devices complete after 12.438 msecs
>[  394.568228] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  394.568319] [drm:intel_power_well_enable [i915]] enabling always-on
>[  394.568351] [drm:intel_power_well_enable [i915]] enabling display
>[  394.570465] PM: early resume of devices complete after 2.789 msecs
>[  394.570722] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  394.570781] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  394.570805] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  394.573045] hpet1: lost 7453 rtc interrupts
>[  394.573542] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  394.575380] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  394.580549] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  394.580572] [drm:intel_opregion_setup [i915]] ASLE supported
>[  394.580591] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  394.580609] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  394.580780] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  394.580802] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  394.580827] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  394.580857] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  394.580887] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  394.580917] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  394.581340] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  394.581421] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  394.581446] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  394.581494] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  394.581520] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  394.581549] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  394.581574] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  394.581601] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  394.581628] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  394.581655] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  394.581680] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  394.581706] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  394.581731] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  394.581759] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  394.581786] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  394.581812] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  394.581837] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  394.581862] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  394.581892] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  394.581921] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  394.581951] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  394.581983] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  394.582008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  394.582032] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  394.582057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.582062] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  394.582087] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.582091] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  394.582116] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  394.582140] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  394.582165] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.582190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  394.582215] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  394.582239] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.582264] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  394.582289] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  394.582314] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  394.582341] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  394.582366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  394.582390] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  394.582415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.582419] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  394.582440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.582457] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  394.582482] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  394.582507] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  394.582532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.582557] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  394.582582] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  394.582606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.582631] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  394.582656] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  394.582681] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  394.582708] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  394.582732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  394.582757] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  394.582781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.582785] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  394.582810] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.582814] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  394.582836] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  394.582860] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  394.582885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.582910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  394.582934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  394.582959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.582983] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  394.583008] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  394.583033] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  394.583061] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  394.583086] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  394.583111] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  394.583168] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  394.583193] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  394.583219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  394.583247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  394.583271] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  394.583297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  394.583322] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  394.583346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  394.583371] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  394.583396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  394.583420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.583424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.583448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.583463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.583488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  394.583513] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  394.583537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.583562] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  394.583587] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  394.583611] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.583636] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  394.583661] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  394.583686] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  394.583712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.583739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  394.583831] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  394.583866] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  394.583892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.583921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  394.583954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  394.583986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  394.584016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  394.584047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  394.584083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  394.584085] sd 0:0:0:0: [sda] Starting disk
>[  394.584118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  394.584145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  394.584172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  394.584198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.584223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  394.584248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  394.584274] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  394.584299] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  394.586341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  394.586366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.586390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.586416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.587995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  394.588014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  394.588032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.589592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.589612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  394.591492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.594829] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  394.594912] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  394.594937] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  394.594972] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  394.595016] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  394.595041] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  394.611689] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  394.611737] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  394.611806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.611843] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  394.611884] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  394.612081] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  394.612380] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  394.614154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  394.614175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  394.615398] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  394.615406] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  394.617539] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  394.617577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  394.619678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  394.619689] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.619697] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  394.619736] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  394.620852] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  394.621774] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  394.621796] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  394.621815] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  394.621834] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  394.622849] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  394.622868] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  394.623813] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  394.623837] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  394.625955] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.625993] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.628100] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.628113] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  394.630254] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.630295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.632424] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.632467] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.632475] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  394.762068] PM: resume of devices complete after 191.606 msecs
>[  394.763342] PM: Finishing wakeup.
>[  394.763345] Restarting tasks ... 
>[  394.763833] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  394.763837] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  394.765808] done.
>[  394.774404] [drm:drm_mode_addfb2] [FB:58]
>[  394.787235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  394.787249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  394.811893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  394.812069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  394.895393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.895624] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  394.911898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  394.911943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  394.912014] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  394.921303] ata1.00: configured for UDMA/133
>[  394.929965] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  394.930007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  394.930039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  394.930077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.930108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  394.930143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  394.930172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  394.930200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  394.930230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  394.930264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  394.930296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  394.930327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  394.930359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.930387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  394.930415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  394.930540] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  394.932096] [drm:drm_mode_addfb2] [FB:58]
>[  394.939455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  394.939469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  394.939540] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  394.939561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  394.939584] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  394.939607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  394.939626] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  394.939646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  394.939666] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  394.939685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  394.939708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  394.939731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  394.939754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  394.939759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.939781] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  394.939786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  394.939809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  394.939833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  394.939856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  394.939879] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  394.939903] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  394.939925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  394.939948] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  394.939971] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  394.939995] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  394.940019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  394.940045] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  394.943577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  394.943612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  394.943640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  394.943660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  394.943679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  394.943699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  394.943722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  394.943742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  394.943762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  394.943781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  394.943798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  394.943821] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  394.943841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  394.945872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  394.945895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.945915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.945936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.947555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  394.947580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  394.947604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.949136] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.949159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  394.951004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.953695] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  394.953729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  394.953748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  394.953774] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  394.953837] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  394.953858] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  394.970562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  394.970611] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  394.970676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.070810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.087321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  395.087370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.087444] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  395.104541] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  395.104585] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  395.104617] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  395.104656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.104689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.104724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.104755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.104784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.104815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.104850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.104883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.104914] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.104945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.104973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.105001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.105066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  395.106173] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  395.107193] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  395.127212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  395.127251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.127289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  395.127330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  395.127361] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  395.127396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.127430] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  395.127510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  395.127543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  395.127573] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.127602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.127609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.127637] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.127642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.127672] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  395.127700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  395.127728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.127756] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  395.127789] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.127825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.127841] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  395.127864] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  395.127888] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  395.127913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.127939] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  395.128015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.128039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.128063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.128087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.128111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.128135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.128161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.128186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.128212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.128235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.128255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.128280] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  395.128304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  395.130376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.130397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.130418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.130470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.132047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  395.132064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  395.132081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.133648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.133666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  395.135555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.139070] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  395.139104] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  395.139122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  395.139148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.139211] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  395.139231] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  395.155933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.155981] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  395.156050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.156293] Console: switching to colour frame buffer device 240x75
>[  395.261616] Console: switching to colour dummy device 80x25
>[  395.261788] [IGT] kms_pipe_crc_basic: executing
>[  395.279041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  395.279093] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  395.280535] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  395.280574] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  395.282519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  395.282530] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  395.284539] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  395.284578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  395.286676] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  395.286686] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.286694] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  395.286723] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  395.286762] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  395.287868] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  395.288791] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  395.288813] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  395.288832] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  395.288850] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  395.289866] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  395.289886] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  395.291002] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  395.291005] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  395.291104] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.291106] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.291111] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  395.291114] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  395.291118] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.291121] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.291130] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  395.291134] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.291137] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.291140] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.291143] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.291146] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.291149] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  395.291152] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  395.291155] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.291157] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.291160] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  395.291163] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.291166] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.291169] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  395.291172] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.291175] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.291178] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  395.291181] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.291184] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.291187] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  395.291190] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  395.291193] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  395.291196] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  395.291199] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  395.291201] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  395.291204] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.291207] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.291210] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  395.291213] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.291216] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.291219] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  395.291256] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  395.291278] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  395.293355] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.293378] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.295497] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.295508] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  395.297625] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.297668] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.299763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.299774] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.299781] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  395.312883] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  395.312908] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  395.315028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  395.315068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  395.317183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  395.317194] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  395.319316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  395.319355] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  395.321475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  395.321486] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.321493] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  395.321994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  395.322036] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  395.323132] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  395.324056] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  395.324079] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  395.324097] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  395.324115] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  395.325144] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  395.325164] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  395.326277] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  395.326281] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  395.326381] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.326384] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.326389] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  395.326391] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  395.326396] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.326399] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.326463] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  395.326471] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.326477] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.326485] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.326491] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.326496] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.326502] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  395.326508] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  395.326513] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.326519] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.326525] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  395.326533] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.326540] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.326546] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  395.326554] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.326561] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.326568] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  395.326574] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.326580] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.326585] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  395.326592] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  395.326597] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  395.326604] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  395.326611] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  395.326618] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  395.326625] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.326632] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.326637] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  395.326643] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.326650] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.326658] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  395.327229] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  395.327263] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  395.328521] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.328557] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.330516] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.330527] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  395.332646] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.332685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.334781] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.334791] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.334798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  395.335361] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B
>[  395.371226] PM: Syncing filesystems ... done.
>[  395.371620] PM: Preparing system for sleep (mem)
>[  395.372129] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  395.373612] Freezing remaining freezable tasks ... (elapsed 0.000 seconds) done.
>[  395.374603] PM: Suspending system (mem)
>[  395.374713] Suspending console(s) (use no_console_suspend to debug)
>[  395.376704] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  395.376778] sd 0:0:0:0: [sda] Stopping disk
>[  395.377765] e1000e: EEE TX LPI TIMER: 00000011
>[  395.392580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.406030] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  395.406064] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  395.424372] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  395.424414] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  395.424477] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  395.424516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.424549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.424584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.424613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.424642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.424672] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.424707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.424739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.424770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.424800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.424827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.424863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.424932] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  395.426608] PM: suspend of devices complete after 50.671 msecs
>[  395.428296] [drm:intel_power_well_disable [i915]] disabling display
>[  395.428330] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  395.428347] [drm:intel_power_well_disable [i915]] disabling always-on
>[  395.428372] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  395.440521] PM: late suspend of devices complete after 13.907 msecs
>[  395.442593] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  395.442943] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  395.454555] PM: noirq suspend of devices complete after 14.028 msecs
>[  395.454931] ACPI: Preparing to enter system sleep state S3
>[  395.479325] PM: Saving platform NVS memory
>[  395.479490] Disabling non-boot CPUs ...
>[  395.492939] smpboot: CPU 1 is now offline
>[  395.505536] Broke affinity for irq 23
>[  395.505544] Broke affinity for irq 42
>[  395.506866] smpboot: CPU 2 is now offline
>[  395.516354] Broke affinity for irq 8
>[  395.516358] Broke affinity for irq 9
>[  395.516363] Broke affinity for irq 23
>[  395.516366] Broke affinity for irq 42
>[  395.516370] Broke affinity for irq 44
>[  395.517414] smpboot: CPU 3 is now offline
>[  395.519847] ACPI: Low-level resume complete
>[  395.519994] PM: Restoring platform NVS memory
>[  395.520536] Suspended for 15.989 seconds
>[  395.520709] Enabling non-boot CPUs ...
>[  395.520858] x86: Booting SMP configuration:
>[  395.520864] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  395.523052]  cache: parent cpu1 should not be sleeping
>[  395.524847] CPU1 is up
>[  395.524966] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  395.526416]  cache: parent cpu2 should not be sleeping
>[  395.527314] CPU2 is up
>[  395.527380] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  395.528694]  cache: parent cpu3 should not be sleeping
>[  395.530497] CPU3 is up
>[  395.539459] ACPI: Waking up from system sleep state S3
>[  395.563926] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  395.563937] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  395.564127] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  395.564458] PM: noirq resume of devices complete after 12.223 msecs
>[  395.565066] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  395.565149] [drm:intel_power_well_enable [i915]] enabling always-on
>[  395.565172] [drm:intel_power_well_enable [i915]] enabling display
>[  395.567085] PM: early resume of devices complete after 2.569 msecs
>[  395.567374] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  395.567422] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  395.567442] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  395.567717] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  395.571045] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  395.573572] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  395.573617] [drm:intel_opregion_setup [i915]] ASLE supported
>[  395.573645] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  395.573672] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  395.573908] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  395.573939] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  395.573977] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  395.574013] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  395.574049] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  395.574084] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  395.574386] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  395.574497] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  395.574528] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  395.574564] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  395.574611] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  395.574648] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  395.574677] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  395.574708] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  395.574739] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  395.574770] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  395.574798] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  395.574816] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  395.574833] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  395.574853] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  395.574872] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  395.574890] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  395.574906] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  395.574923] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  395.574944] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  395.574965] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  395.574985] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  395.575012] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  395.575031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  395.575049] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  395.575067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.575073] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  395.575090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.575094] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  395.575112] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  395.575129] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  395.575146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.575163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.575183] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.575201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.575218] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  395.575235] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  395.575252] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  395.575271] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  395.575288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  395.575304] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  395.575320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.575324] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  395.575340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.575343] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  395.575367] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  395.575392] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  395.575417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.575442] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.575467] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.575491] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.575516] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  395.575541] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  395.575566] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  395.575616] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  395.575641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  395.575665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  395.575689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.575694] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  395.575718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.575722] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  395.575747] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  395.575772] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  395.575797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.575821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.575846] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.575870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.575895] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  395.575920] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  395.575945] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  395.575973] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  395.575998] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  395.576023] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  395.576080] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  395.576106] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.576132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  395.576160] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  395.576184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  395.576210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.576235] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  395.576259] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  395.576285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  395.576309] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.576333] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.576338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.576362] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.576366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.576391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  395.576416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  395.576441] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.576465] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  395.576490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.576514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.576539] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  395.576564] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  395.576599] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  395.576626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.576653] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  395.576744] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  395.576780] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  395.576805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.576831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.576856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.576881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.576906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.576931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  395.576959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  395.576987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.577014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.577041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.577068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.577092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.577117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.577143] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  395.577168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  395.578018] sd 0:0:0:0: [sda] Starting disk
>[  395.579234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.579255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.579273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.579292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.580854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  395.580873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  395.580891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.582438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.582457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  395.584327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.587830] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  395.587915] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  395.587947] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  395.587991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.588052] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  395.588083] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  395.604704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.604752] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  395.604823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.604868] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  395.604917] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  395.605117] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  395.605186] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  395.607230] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  395.607280] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  395.608344] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  395.608350] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  395.609673] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  395.609704] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  395.611794] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  395.611803] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.611810] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  395.611843] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  395.612952] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  395.613917] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  395.613937] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  395.613954] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  395.613971] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  395.614996] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  395.615016] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  395.615963] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  395.615988] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  395.618105] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.618146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.620261] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.620272] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  395.622521] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.622558] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.624720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.624730] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.624737] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  395.760702] PM: resume of devices complete after 193.619 msecs
>[  395.761763] PM: Finishing wakeup.
>[  395.761767] Restarting tasks ... 
>[  395.762235] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  395.762239] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  395.764222] done.
>[  395.775354] [drm:drm_mode_addfb2] [FB:58]
>[  395.789379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  395.789469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.804862] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  395.804909] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.804979] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  395.822146] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  395.822194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  395.822234] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  395.822280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.822320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.822363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.822403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.822442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.822481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.822525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.822570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.822719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.822751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.822784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.822813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.822880] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  395.823051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  395.823070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  395.823171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  395.823201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.823243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  395.823276] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  395.823302] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  395.823331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.823358] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  395.823386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  395.823413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  395.823439] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.823462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.823469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.823493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.823499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.823525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  395.823549] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  395.823585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.823640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.823671] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.823700] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.823727] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  395.823757] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  395.823782] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  395.823815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.823850] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  395.827326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.827352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.827376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.827400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.827423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.827446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.827471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.827496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.827521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.827544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.827566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.827652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  395.827683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  395.829755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.829776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.829795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.829814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.831378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  395.831399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  395.831417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.832970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.832993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  395.834870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.838121] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  395.838186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  395.838205] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  395.838231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  395.854979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.855029] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  395.855094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.871647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  395.889353] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  395.931954] ata1.00: configured for UDMA/133
>[  395.938493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.938577] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  395.938687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  395.938793] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  395.957358] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  395.957396] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  395.957437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.957470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.957505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.957535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.957564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.957677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  395.957742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.957790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.957837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.957881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.957923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.957966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.958059] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  395.959104] [drm:drm_mode_addfb2] [FB:58]
>[  395.968342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  395.968361] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  395.968458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  395.968493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.968529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  395.968568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  395.968862] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  395.968898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.968932] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  395.968964] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  395.968996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  395.969026] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  395.969055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.969062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.969091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.969098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  395.969127] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  395.969155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  395.969184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.969212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.969244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  395.969272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.969300] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  395.969328] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  395.969356] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  395.969388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.969422] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  395.973653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  395.973690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  395.973722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  395.973752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  395.973782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  395.973814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  395.973849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  395.973882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  395.973915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  395.973945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  395.973973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  395.974008] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  395.974040] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  395.976578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.976669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.976701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.976734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.978324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  395.978358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  395.978390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.979935] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.979959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  395.983545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.986943] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  395.986997] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  395.987035] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  395.987087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.003750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.003796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  396.003860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.087313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.087401] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  396.087446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.087517] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  396.105685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  396.105723] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  396.105762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.105796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.105831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.105862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.105900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.105941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.105985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.106028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.106070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.106112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.106151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.106190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.106266] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  396.107354] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  396.108364] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  396.128316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  396.128355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.128393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  396.128433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  396.128465] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  396.128500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.128534] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  396.128567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  396.128626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  396.128657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.128686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.128693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.128721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.128726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.128756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  396.128784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  396.128812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.128839] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  396.128872] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.128906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.128922] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  396.128939] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  396.128955] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  396.128975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.128997] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  396.129066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.129085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.129102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.129119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.129136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.129154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.129174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.129193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.129212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.129228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.129245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.129266] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  396.129285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  396.131371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.131394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.131416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.131440] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.133028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  396.133048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.133065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.134654] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.134673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  396.136543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.140060] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  396.140111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  396.140139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  396.140166] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.140229] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  396.140249] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  396.156927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.156975] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  396.157045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.157280] Console: switching to colour frame buffer device 240x75
>[  396.264437] Console: switching to colour dummy device 80x25
>[  396.264758] [IGT] kms_pipe_crc_basic: executing
>[  396.277140] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  396.277193] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  396.278651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.278690] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.280635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.280646] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  396.282647] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.282685] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.284651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.284662] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.284670] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  396.284700] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  396.284742] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  396.285864] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  396.286823] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  396.286852] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  396.286878] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  396.286902] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  396.287931] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  396.287952] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  396.289070] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  396.289073] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  396.289174] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.289177] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.289182] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  396.289184] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  396.289189] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.289191] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.289201] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  396.289204] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.289208] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.289210] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.289213] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.289216] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.289219] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.289222] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  396.289225] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.289228] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.289231] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.289234] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.289237] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.289240] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  396.289243] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.289246] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.289249] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  396.289252] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.289255] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.289258] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  396.289261] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  396.289264] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  396.289267] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  396.289269] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  396.289272] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  396.289275] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.289278] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.289281] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  396.289284] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.289287] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.289290] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  396.289329] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  396.289351] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  396.290604] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.290629] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.292648] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.292658] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  396.294640] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.294682] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.296631] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.296641] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.296649] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  396.309345] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  396.309370] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  396.311488] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.311527] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.313699] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.313710] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  396.315829] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.315867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.317984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.317995] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.318002] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  396.318509] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  396.318551] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  396.319684] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  396.320606] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  396.320642] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  396.320674] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  396.320702] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  396.321726] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  396.321746] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  396.322861] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  396.322865] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  396.322963] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.322966] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.322971] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  396.322974] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  396.322979] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  396.322981] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  396.322990] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  396.322993] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.322997] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.323000] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.323003] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.323006] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  396.323009] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.323012] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  396.323015] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.323018] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  396.323020] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  396.323023] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.323026] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  396.323029] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  396.323032] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.323035] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  396.323038] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  396.323041] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.323044] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  396.323047] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  396.323050] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  396.323053] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  396.323056] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  396.323059] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  396.323062] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  396.323065] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.323068] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  396.323070] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  396.323073] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.323076] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  396.323079] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  396.323354] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  396.323376] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  396.324608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.324633] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.326645] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.326656] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  396.328655] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.328694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.330626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.330636] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.330644] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  396.331205] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-C
>[  396.367989] PM: Syncing filesystems ... done.
>[  396.368303] PM: Preparing system for sleep (mem)
>[  396.368965] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  396.370656] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  396.371743] PM: Suspending system (mem)
>[  396.371855] Suspending console(s) (use no_console_suspend to debug)
>[  396.373776] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  396.374058] sd 0:0:0:0: [sda] Stopping disk
>[  396.374888] e1000e: EEE TX LPI TIMER: 00000011
>[  396.383818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.390458] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  396.390514] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.408222] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.408258] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  396.408285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  396.408318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.408345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.408374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.408399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.408424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.408450] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.408480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.408508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.408545] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.408610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.408634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.408658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.408711] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  396.414842] PM: suspend of devices complete after 41.764 msecs
>[  396.416307] [drm:intel_power_well_disable [i915]] disabling display
>[  396.416339] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  396.416354] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.416379] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  396.427659] PM: late suspend of devices complete after 12.809 msecs
>[  396.429735] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  396.429945] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  396.441699] PM: noirq suspend of devices complete after 14.033 msecs
>[  396.442076] ACPI: Preparing to enter system sleep state S3
>[  396.466405] PM: Saving platform NVS memory
>[  396.466575] Disabling non-boot CPUs ...
>[  396.480507] smpboot: CPU 1 is now offline
>[  396.492779] Broke affinity for irq 23
>[  396.492786] Broke affinity for irq 42
>[  396.494109] smpboot: CPU 2 is now offline
>[  396.499663] Broke affinity for irq 8
>[  396.499668] Broke affinity for irq 9
>[  396.499675] Broke affinity for irq 23
>[  396.499679] Broke affinity for irq 42
>[  396.499684] Broke affinity for irq 44
>[  396.500737] smpboot: CPU 3 is now offline
>[  396.503227] ACPI: Low-level resume complete
>[  396.503371] PM: Restoring platform NVS memory
>[  396.503910] Suspended for 16.018 seconds
>[  396.504014] Enabling non-boot CPUs ...
>[  396.504160] x86: Booting SMP configuration:
>[  396.504167] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  396.506283]  cache: parent cpu1 should not be sleeping
>[  396.508096] CPU1 is up
>[  396.508218] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  396.509696]  cache: parent cpu2 should not be sleeping
>[  396.510588] CPU2 is up
>[  396.510697] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  396.512033]  cache: parent cpu3 should not be sleeping
>[  396.514025] CPU3 is up
>[  396.522906] ACPI: Waking up from system sleep state S3
>[  396.547029] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  396.547040] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  396.547202] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  396.547597] PM: noirq resume of devices complete after 12.260 msecs
>[  396.547985] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  396.548112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.548145] [drm:intel_power_well_enable [i915]] enabling display
>[  396.550282] PM: early resume of devices complete after 2.506 msecs
>[  396.550898] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  396.551104] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  396.551168] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  396.551196] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  396.554264] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  396.556762] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  396.556788] [drm:intel_opregion_setup [i915]] ASLE supported
>[  396.556812] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  396.556837] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  396.557008] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  396.557033] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  396.557064] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  396.557094] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  396.557125] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  396.557154] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  396.557419] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  396.557500] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  396.557526] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  396.557555] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  396.557581] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  396.557610] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  396.557635] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  396.557663] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  396.557704] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  396.557731] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  396.557756] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  396.557781] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  396.557806] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  396.557834] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  396.557861] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  396.557887] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  396.557912] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  396.557937] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  396.557967] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  396.557997] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  396.558026] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  396.558059] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  396.558084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  396.558108] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  396.558133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.558138] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  396.558162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.558166] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  396.558191] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  396.558216] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  396.558241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.558265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.558290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.558315] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.558340] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  396.558365] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  396.558390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  396.558416] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  396.558441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  396.558466] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  396.558490] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.558494] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  396.558518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.558522] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  396.558547] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  396.558572] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  396.558596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.558620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.558645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.558669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.558708] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  396.558733] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  396.558758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  396.558784] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  396.558809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  396.558833] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  396.558858] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.558862] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  396.558886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.558890] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  396.558912] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  396.558937] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  396.558961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.558985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.559010] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.559034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.559059] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  396.559084] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  396.559109] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  396.559137] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  396.559161] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  396.559186] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  396.559244] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  396.559269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.559294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  396.559323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  396.559347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  396.559373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.559398] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  396.559422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  396.559447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  396.559472] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.559496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.559500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.559525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.559529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.559554] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  396.559578] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  396.559603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.559627] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  396.559652] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.559688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.559713] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  396.559738] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  396.559762] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  396.559789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.559816] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  396.559907] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  396.559943] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  396.559969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.559994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.560019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.560044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.560069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.560093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  396.560122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  396.560150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.560177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.560203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.560229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.560254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.560278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.560305] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  396.560330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  396.561331] sd 0:0:0:0: [sda] Starting disk
>[  396.562400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.562421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.562442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.562466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.564041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  396.564062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.564081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.565643] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.565663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  396.567547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.571018] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  396.571079] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  396.571110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  396.571151] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.571209] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  396.571242] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  396.587848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.587890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  396.587954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.587988] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  396.588025] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  396.588212] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  396.588271] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  396.590302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.590337] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.592406] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  396.592415] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  396.594550] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.594587] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  396.596719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  396.596730] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.596738] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  396.596780] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  396.597897] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  396.598829] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  396.598849] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  396.598867] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  396.598889] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  396.599924] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  396.599943] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  396.600897] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  396.600931] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  396.603055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.603102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.604774] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  396.604787] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  396.606882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.606913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  396.608973] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  396.608980] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  396.608987] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  396.867606] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  396.898571] ata1.00: configured for UDMA/133
>[  396.918305] PM: resume of devices complete after 368.033 msecs
>[  396.919291] PM: Finishing wakeup.
>[  396.919293] Restarting tasks ... 
>[  396.919764] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  396.919768] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  396.928703] done.
>[  396.934721] [drm:drm_mode_addfb2] [FB:58]
>[  396.950174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  396.950239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.954775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  396.954820] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  396.954890] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.973390] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.973435] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  396.973474] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  396.973519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.973559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.973603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.973643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.973752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.973804] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  396.973866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.973920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.973970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.974022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.974067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.974112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.974213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  396.974467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  396.974597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  396.974609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  396.974724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  396.974757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.974793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  396.974830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  396.974860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  396.974895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.974928] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  396.974959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  396.974991] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  396.975020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.975049] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.975057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.975085] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.975092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  396.975121] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  396.975150] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  396.975178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.975206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.975237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  396.975265] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.975295] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  396.975321] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  396.975349] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  396.975382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.975417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  396.978789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  396.978812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  396.978833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  396.978852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  396.978870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  396.978890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  396.978912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  396.978932] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  396.978952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  396.978970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  396.978987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  396.979009] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  396.979030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  396.981086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.981107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.981125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.981144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.982715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  396.982735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.982753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.984314] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.984336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  396.986212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.989529] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  396.989595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  396.989627] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  396.989763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  397.006337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  397.006385] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.006453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  397.089922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.090012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  397.090064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  397.090142] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  397.108610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  397.108648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  397.108780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.108818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  397.108863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  397.108903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  397.108945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  397.108985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  397.109032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  397.109075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  397.109118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  397.109162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  397.109202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  397.109242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  397.109318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.110233] [drm:drm_mode_addfb2] [FB:58]
>[  397.118617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  397.118630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  397.118766] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  397.118800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  397.118835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  397.118870] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  397.118897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  397.118930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  397.118960] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  397.118989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  397.119020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  397.119046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  397.119074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  397.119081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  397.119109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  397.119115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  397.119144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  397.119170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  397.119197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.119222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  397.119254] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  397.119279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  397.119307] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  397.119332] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  397.119359] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  397.119388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.119422] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  397.122956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.122981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  397.123001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  397.123020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  397.123039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  397.123058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  397.123080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  397.123105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  397.123131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  397.123155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  397.123179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  397.123205] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  397.123227] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  397.125297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  397.125319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  397.125338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.125357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  397.126937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  397.126959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  397.126978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.128538] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  397.128559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  397.130424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  397.133190] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  397.133225] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  397.133249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  397.133281] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  397.150041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  397.150092] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.150158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  397.233564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.233649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  397.233793] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  397.233884] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  397.252513] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  397.252550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  397.252590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.252624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  397.252748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  397.252786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  397.252816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  397.252848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  397.252886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  397.252920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  397.252951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  397.252984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  397.253020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  397.253039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  397.253083] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  397.253581] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  397.254501] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  397.275338] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  397.275376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  397.275414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  397.275454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  397.275486] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  397.275520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  397.275555] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  397.275586] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  397.275617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  397.275646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  397.275699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  397.275706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  397.275733] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  397.275738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  397.275766] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  397.275793] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  397.275819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.275845] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  397.275877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  397.275904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  397.275931] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  397.275958] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  397.275983] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  397.276015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.276050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  397.276175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  397.276204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  397.276231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  397.276257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  397.276283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  397.276312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  397.276344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  397.276374] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  397.276403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  397.276429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  397.276455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  397.276488] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  397.276526] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  397.278601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  397.278619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  397.278636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.278666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  397.280241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  397.280259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  397.280277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  397.281832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  397.281851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  397.283719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  397.286957] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  397.286989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  397.287007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  397.287033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  397.287097] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  397.287116] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  397.303833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  397.303878] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  397.303945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  397.304200] Console: switching to colour frame buffer device 240x75
>[  397.409378] Console: switching to colour dummy device 80x25
>[  397.409488] [IGT] kms_setmode: executing
>[  397.423347] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
>[  397.423580] [IGT] kms_setmode: exiting, ret=0
>[  397.470851] Console: switching to colour frame buffer device 240x75
>[  397.585390] Console: switching to colour dummy device 80x25
>[  397.585564] [IGT] kms_sink_crc_basic: executing
>[  397.628930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  397.628959] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  397.631083] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  397.631122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  397.633239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  397.633250] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  397.635370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  397.635409] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  397.637526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  397.637537] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  397.637544] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  397.638252] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  397.638294] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  397.639403] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  397.640330] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  397.640352] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  397.640370] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  397.640388] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  397.641411] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  397.641431] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  397.642564] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  397.642568] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  397.642759] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  397.642773] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  397.642782] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  397.642786] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  397.642794] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  397.642798] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  397.642813] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  397.642818] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  397.642821] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  397.642824] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  397.642827] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  397.642830] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  397.642833] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  397.642836] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  397.642839] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  397.642842] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  397.642845] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  397.642847] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  397.642850] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  397.642853] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  397.642856] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  397.642859] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  397.642862] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  397.642865] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  397.642868] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  397.642871] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  397.642874] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  397.642877] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  397.642880] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  397.642883] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  397.642886] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  397.642889] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  397.642891] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  397.642894] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  397.642897] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  397.642900] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  397.642903] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  397.643182] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  397.643206] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  397.644671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  397.644697] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  397.646719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  397.646730] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  397.648719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  397.648757] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  397.650719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  397.650730] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  397.650737] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  397.651289] [IGT] kms_sink_crc_basic: exiting, ret=77
>[  397.670931] Console: switching to colour frame buffer device 240x75
>[  397.776230] Console: switching to colour dummy device 80x25
>[  397.776384] [IGT] pm_backlight: executing
>[  397.776694] [IGT] pm_backlight: exiting, ret=77
>[  397.787771] Console: switching to colour frame buffer device 240x75
>[  397.897104] Console: switching to colour dummy device 80x25
>[  397.897215] [IGT] pm_rpm: executing
>[  397.924454] [drm:drm_mode_addfb2] [FB:76]
>[  398.976550] [IGT] pm_rpm: starting subtest basic-pci-d3-state
>[  398.976658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  398.976730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  398.988491] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  398.988544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  398.988697] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  399.007174] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  399.007219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  399.007251] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  399.007291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.007323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  399.007359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  399.007390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  399.007420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  399.007451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  399.007486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  399.007518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  399.007559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  399.007672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  399.007722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  399.007769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  399.007892] [drm:intel_power_well_disable [i915]] disabling display
>[  399.008037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  399.008080] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  399.008116] [drm:intel_power_well_disable [i915]] disabling always-on
>[  399.008447] [drm:intel_runtime_suspend [i915]] Suspending device
>[  399.008514] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  399.010195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  399.010288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  399.010734] [drm:intel_runtime_suspend [i915]] Device suspended
>[  399.112012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  399.112026] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  399.112095] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  399.112119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  399.112144] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  399.112170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  399.112190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  399.112212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  399.112234] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  399.112254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  399.112274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  399.112292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  399.112311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  399.112315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  399.112333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  399.112337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  399.112362] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  399.112387] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  399.112413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  399.112438] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  399.112464] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  399.112488] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  399.112513] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  399.112539] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  399.112569] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  399.112696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.112733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  399.124731] [drm:intel_runtime_resume [i915]] Resuming device
>[  399.126827] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  399.127311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  399.127553] [drm:intel_runtime_resume [i915]] Device resumed
>[  399.131148] [drm:intel_power_well_enable [i915]] enabling always-on
>[  399.131177] [drm:intel_power_well_enable [i915]] enabling display
>[  399.131197] [drm:hsw_set_power_well [i915]] Enabling power well
>[  399.131277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.131301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  399.131323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  399.131350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  399.131381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  399.131413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  399.131447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  399.131481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  399.131514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  399.131544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  399.131572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  399.131642] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  399.131672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  399.133775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  399.133812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  399.133844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.133878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  399.135458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  399.135492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  399.135524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.137129] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  399.137154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  399.139094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  399.141578] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  399.141657] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  399.141679] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  399.141707] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  399.141772] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  399.141804] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  399.158414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  399.158449] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  399.158493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  399.158616] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  399.160741] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  399.160812] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  399.161163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.162637] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  399.162647] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  399.164653] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  399.164700] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  399.166782] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  399.166796] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  399.166805] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  399.166847] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  399.167967] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  399.168898] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  399.168920] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  399.168939] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  399.168956] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  399.169987] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  399.170008] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  399.175112] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  399.175192] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  399.175780] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  399.192529] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  399.192669] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  399.192713] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  399.192759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.192792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  399.192827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  399.192856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  399.192884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  399.192916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  399.192950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  399.192982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  399.193013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  399.193044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  399.193071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  399.193098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  399.193192] [drm:intel_power_well_disable [i915]] disabling display
>[  399.193317] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  399.193386] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  399.193862] [IGT] pm_rpm: exiting, ret=0
>[  399.194736] [drm:intel_power_well_disable [i915]] disabling always-on
>[  399.194773] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  399.194808] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  399.194838] [drm:intel_power_well_enable [i915]] enabling always-on
>[  399.196922] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  399.196945] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  399.199058] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  399.199071] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  399.201190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  399.201229] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  399.203295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  399.203305] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  399.203334] [drm:intel_power_well_disable [i915]] disabling always-on
>[  399.203341] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  399.212027] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  399.212070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  399.212114] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  399.212161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  399.212202] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  399.212244] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  399.212286] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  399.212327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  399.212368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  399.212410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  399.212445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  399.212453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  399.212494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  399.212501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  399.212543] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  399.212648] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  399.212700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  399.212754] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  399.212808] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  399.212860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  399.212910] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  399.212960] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  399.213011] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  399.213047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  399.213084] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  399.213204] [drm:intel_power_well_enable [i915]] enabling always-on
>[  399.213268] [drm:intel_power_well_enable [i915]] enabling display
>[  399.213311] [drm:hsw_set_power_well [i915]] Enabling power well
>[  399.213423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  399.213456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  399.213487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  399.213518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  399.213548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  399.213615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  399.213653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  399.213686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  399.213719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  399.213748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  399.213777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  399.213812] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  399.213844] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  399.215912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  399.215933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  399.215951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.215971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  399.217550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  399.217581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  399.217599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.219289] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  399.219310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  399.221177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  399.223890] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  399.223953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  399.223985] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  399.224028] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  399.224126] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  399.224184] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  399.240729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  399.240776] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  399.240845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  399.257630] Console: switching to colour frame buffer device 240x75
>[  399.369048] Console: switching to colour dummy device 80x25
>[  399.369159] [IGT] pm_rpm: executing
>[  399.380931] [drm:drm_mode_addfb2] [FB:76]
>[  399.772787] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  400.428483] [IGT] pm_rpm: starting subtest basic-rte
>[  400.428602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  400.428690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.441643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  400.441693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  400.441768] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  400.458811] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  400.458855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  400.458888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  400.458927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.458959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  400.458994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  400.459024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  400.459053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  400.459091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  400.459135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  400.459177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  400.459219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  400.459261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  400.459299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  400.459338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  400.459395] [drm:intel_power_well_disable [i915]] disabling display
>[  400.459441] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  400.459491] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  400.459616] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.459688] [drm:intel_runtime_suspend [i915]] Suspending device
>[  400.459782] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  400.460285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  400.460437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  400.461902] [drm:intel_runtime_suspend [i915]] Device suspended
>[  400.560797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  400.560817] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  400.560916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  400.560958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  400.561001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  400.561048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  400.561088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  400.561130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  400.561170] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  400.561211] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  400.561252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  400.561292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  400.561332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  400.561340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  400.561380] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  400.561387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  400.561428] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  400.561469] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  400.561509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  400.561628] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  400.561681] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  400.561734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  400.561780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  400.561829] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  400.561873] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  400.561925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.561980] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  400.573673] [drm:intel_runtime_resume [i915]] Resuming device
>[  400.577808] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  400.577906] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  400.578175] [drm:intel_runtime_resume [i915]] Device resumed
>[  400.581940] [drm:intel_runtime_suspend [i915]] Suspending device
>[  400.582008] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  400.584121] [drm:intel_runtime_suspend [i915]] Device suspended
>[  400.607670] [drm:intel_runtime_resume [i915]] Resuming device
>[  400.609747] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  400.612466] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  400.612910] [drm:intel_runtime_resume [i915]] Device resumed
>[  400.612944] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.612974] [drm:intel_power_well_enable [i915]] enabling display
>[  400.613001] [drm:hsw_set_power_well [i915]] Enabling power well
>[  400.613057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.613091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  400.613123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  400.613154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  400.613183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  400.613214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  400.613247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  400.613285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  400.613304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  400.613326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  400.613349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  400.613375] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  400.613396] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  400.615478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  400.615501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  400.615581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.615617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  400.617211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  400.617233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  400.617252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.618819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  400.618840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  400.620701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  400.624045] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  400.624136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  400.624174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  400.624226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  400.624310] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  400.624346] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  400.640920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  400.640970] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  400.641034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  400.641181] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  400.642109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.643314] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  400.643354] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  400.645256] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  400.645268] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  400.647387] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  400.647427] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  400.649568] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  400.649580] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  400.649588] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  400.649627] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  400.650843] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  400.651775] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  400.651797] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  400.651816] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  400.651834] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  400.652864] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  400.652885] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  400.657589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  400.657637] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  400.657709] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  400.676350] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  400.676394] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  400.676433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  400.676479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.676519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  400.676634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  400.676688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  400.676738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  400.676790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  400.676849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  400.676904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  400.676943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  400.676977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  400.677005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  400.677034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  400.677088] [drm:intel_power_well_disable [i915]] disabling display
>[  400.677129] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  400.677172] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  400.677432] [IGT] pm_rpm: exiting, ret=0
>[  400.678313] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.678325] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  400.678374] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  400.678415] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.680510] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  400.680557] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  400.682658] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  400.682671] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  400.684772] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  400.684811] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  400.686926] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  400.686938] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  400.686971] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.686979] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  400.687031] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  400.687062] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.689175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  400.689229] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  400.691301] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  400.691310] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  400.693417] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  400.693452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  400.695572] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  400.695584] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  400.695615] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.695623] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  400.695660] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  400.695689] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.696920] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  400.697852] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  400.697874] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  400.697893] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  400.697911] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  400.698933] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  400.698955] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  400.699914] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.699928] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  400.699950] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  400.699967] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.702065] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  400.702104] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  400.704218] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  400.704229] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  400.706349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  400.706389] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  400.708509] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  400.708555] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  400.708587] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.708595] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  400.714812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  400.714856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  400.714899] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  400.714946] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  400.714986] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  400.715029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  400.715070] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  400.715112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  400.715154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  400.715194] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  400.715230] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  400.715238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  400.715278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  400.715285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  400.715327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  400.715369] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  400.715410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  400.715451] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  400.715492] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  400.715624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  400.715672] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  400.715719] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  400.715765] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  400.715818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  400.715870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  400.716016] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.716069] [drm:intel_power_well_enable [i915]] enabling display
>[  400.716118] [drm:hsw_set_power_well [i915]] Enabling power well
>[  400.716203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  400.716257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  400.716308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  400.716353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  400.716374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  400.716394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  400.716418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  400.716438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  400.716459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  400.716477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  400.716497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  400.716557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  400.716586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  400.718657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  400.718678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  400.718697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.718715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  400.720291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  400.720310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  400.720328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.721876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  400.721899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  400.723763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  400.726747] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  400.726827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  400.726847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  400.726873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  400.726938] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  400.726959] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  400.743636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  400.743686] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  400.743752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  400.760533] Console: switching to colour frame buffer device 240x75
>[  400.875735] Console: switching to colour dummy device 80x25
>[  400.875919] [IGT] pm_rps: executing
>[  400.890565] [IGT] pm_rps: starting subtest basic-api
>[  400.892790] [IGT] pm_rps: exiting, ret=0
>[  400.943957] Console: switching to colour frame buffer device 240x75
>[  401.054840] Console: switching to colour dummy device 80x25
>[  401.055015] [IGT] prime_busy: executing
>[  401.156784] [IGT] prime_busy: starting subtest basic-after-default
>[  402.379654] [IGT] prime_busy: exiting, ret=0
>[  402.411789] Console: switching to colour frame buffer device 240x75
>[  402.523791] Console: switching to colour dummy device 80x25
>[  402.523905] [IGT] prime_busy: executing
>[  402.559742] [IGT] prime_busy: starting subtest basic-before-default
>[  403.822794] [IGT] prime_busy: exiting, ret=0
>[  403.862945] Console: switching to colour frame buffer device 240x75
>[  403.998789] Console: switching to colour dummy device 80x25
>[  403.998942] [IGT] prime_busy: executing
>[  404.133571] [IGT] prime_busy: starting subtest basic-wait-after-default
>[  405.369469] [IGT] prime_busy: exiting, ret=0
>[  405.414166] Console: switching to colour frame buffer device 240x75
>[  405.524740] Console: switching to colour dummy device 80x25
>[  405.524917] [IGT] prime_busy: executing
>[  405.587516] [IGT] prime_busy: starting subtest basic-wait-before-default
>[  406.859441] [IGT] prime_busy: exiting, ret=0
>[  406.898683] Console: switching to colour frame buffer device 240x75
>[  407.011451] Console: switching to colour dummy device 80x25
>[  407.011630] [IGT] prime_self_import: executing
>[  407.011821] [IGT] prime_self_import: starting subtest basic-llseek-bad
>[  407.027920] [IGT] prime_self_import: exiting, ret=0
>[  407.065477] Console: switching to colour frame buffer device 240x75
>[  407.175486] Console: switching to colour dummy device 80x25
>[  407.175658] [IGT] prime_self_import: executing
>[  407.175846] [IGT] prime_self_import: starting subtest basic-llseek-size
>[  407.190907] [IGT] prime_self_import: exiting, ret=0
>[  407.232307] Console: switching to colour frame buffer device 240x75
>[  407.342098] Console: switching to colour dummy device 80x25
>[  407.342343] [IGT] prime_self_import: executing
>[  407.342545] [IGT] prime_self_import: starting subtest basic-with_fd_dup
>[  407.364121] [IGT] prime_self_import: exiting, ret=0
>[  407.415768] Console: switching to colour frame buffer device 240x75
>[  407.525362] Console: switching to colour dummy device 80x25
>[  407.525526] [IGT] prime_self_import: executing
>[  407.525699] [IGT] prime_self_import: starting subtest basic-with_one_bo
>[  407.563951] [IGT] prime_self_import: exiting, ret=0
>[  407.582549] Console: switching to colour frame buffer device 240x75
>[  407.704119] Console: switching to colour dummy device 80x25
>[  407.704410] [IGT] prime_self_import: executing
>[  407.704650] [IGT] prime_self_import: starting subtest basic-with_one_bo_two_files
>[  407.719394] [IGT] prime_self_import: exiting, ret=0
>[  407.766030] Console: switching to colour frame buffer device 240x75
>[  407.875427] Console: switching to colour dummy device 80x25
>[  407.875556] [IGT] prime_self_import: executing
>[  407.875717] [IGT] prime_self_import: starting subtest basic-with_two_bos
>[  407.911312] [IGT] prime_self_import: exiting, ret=0
>[  407.949514] Console: switching to colour frame buffer device 240x75
>[  408.060843] Console: switching to colour dummy device 80x25
>[  408.060990] [IGT] prime_vgem: executing
>[  408.107548] [IGT] prime_vgem: starting subtest basic-busy-default
>[  408.119332] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  408.120678] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  408.120778] [IGT] prime_vgem: exiting, ret=0
>[  408.166367] Console: switching to colour frame buffer device 240x75
>[  408.277448] Console: switching to colour dummy device 80x25
>[  408.277605] [IGT] prime_vgem: executing
>[  408.326564] [IGT] prime_vgem: starting subtest basic-fence-flip
>[  408.326625] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  408.331164] [drm:drm_mode_addfb2] [FB:58]
>[  408.331239] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  408.334901] [drm:drm_mode_addfb2] [FB:79]
>[  408.334944] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  408.334971] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  408.337094] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.337133] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.339252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.339263] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  408.341384] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.341423] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.343541] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.343552] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  408.343560] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  408.343574] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  408.343616] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  408.344731] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  408.345699] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  408.345721] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  408.345740] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  408.345758] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  408.346815] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  408.346838] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  408.347973] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  408.347977] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  408.348080] [drm:drm_mode_debug_printmodeline] Modeline 115:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  408.348083] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  408.348088] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  408.348090] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  408.348095] [drm:drm_mode_debug_printmodeline] Modeline 135:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  408.348097] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  408.348107] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  408.348111] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.348114] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.348117] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.348120] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  408.348123] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  408.348126] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  408.348129] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  408.348132] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.348135] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  408.348138] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  408.348141] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  408.348144] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  408.348146] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  408.348149] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  408.348152] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  408.348155] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  408.348158] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  408.348161] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  408.348164] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  408.348167] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  408.348227] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  408.348233] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  408.348239] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  408.348245] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  408.348251] [drm:drm_mode_debug_printmodeline] Modeline 94:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  408.348258] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  408.348265] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  408.348271] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  408.348277] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  408.348284] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  408.348353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  408.348371] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  408.348456] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  408.348491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.348518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 78750KHz
>[  408.348544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  408.348564] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000
>[  408.348587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.348609] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  408.348630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.348651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3058346, gmch_n: 4194304, link_m: 127431, link_n: 262144, tu: 64
>[  408.348670] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  408.348688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.348693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  408.348711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.348715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  408.348733] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  408.348752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750
>[  408.348770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.348787] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  408.348809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  408.348827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.348847] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  408.348872] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  408.348898] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  408.348925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.348954] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  408.366321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.366370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.366444] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.383470] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.383518] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  408.383559] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  408.383604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.383644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.383684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.383724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.383763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.383802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.383845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.383886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.383927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.383966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.384005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.384046] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  408.384085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  408.386141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  408.386164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  408.386242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.386277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  408.387831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  408.387851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  408.387869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.389412] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  408.389434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  408.391280] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  408.394527] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.394561] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  408.394585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  408.394617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  408.394679] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.394700] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.408042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.408100] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.408163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.728121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.741260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.741308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.741382] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.755924] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.755968] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  408.756000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  408.756039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.756072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.756108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.756138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.756167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.756282] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.756344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.756388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.756434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.756481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.756522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.756562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.756665] [drm:intel_power_well_disable [i915]] disabling display
>[  408.756784] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  408.756826] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.756857] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.757004] [drm:intel_runtime_suspend [i915]] Suspending device
>[  408.757119] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  408.757443] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  408.757616] [IGT] prime_vgem: exiting, ret=0
>[  408.759300] [drm:intel_runtime_suspend [i915]] Device suspended
>[  408.783379] [drm:intel_runtime_resume [i915]] Resuming device
>[  408.787553] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  408.788126] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  408.788562] [drm:intel_runtime_resume [i915]] Device resumed
>[  408.788854] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  408.788886] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.790222] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.790253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.792276] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  408.792287] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  408.794204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.794234] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  408.796240] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  408.796250] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  408.796281] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.796289] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  408.796325] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  408.796354] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.797503] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  408.798428] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  408.798450] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  408.798473] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  408.798497] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  408.799523] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  408.799544] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  408.800515] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.800520] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  408.800543] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  408.800560] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.802248] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  408.802282] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  408.804239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  408.804248] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  408.806236] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  408.806274] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  408.808286] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  408.808301] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  408.808345] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.808356] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  408.808546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  408.808581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.808618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  408.808663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  408.808702] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  408.808742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.808782] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  408.808821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.808862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  408.808900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  408.808939] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.808947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.808985] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.808993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  408.809033] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  408.809073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  408.809112] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.809152] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  408.809257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  408.809308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.809354] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  408.809399] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  408.809442] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  408.809491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.809542] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  408.809880] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.809900] [drm:intel_power_well_enable [i915]] enabling display
>[  408.809919] [drm:hsw_set_power_well [i915]] Enabling power well
>[  408.809957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  408.809980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  408.810001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  408.810021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  408.810041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  408.810061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  408.810085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  408.810105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  408.810127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.810145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  408.810195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  408.810228] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  408.810258] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  408.812450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  408.812471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  408.812490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.812510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  408.814069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  408.814090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  408.814109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.815659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  408.815680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  408.817570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  408.820536] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.820602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  408.820642] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  408.820695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  408.820779] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.820826] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.837385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  408.837435] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  408.837501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  408.854271] Console: switching to colour frame buffer device 240x75
>[  408.966553] Console: switching to colour dummy device 80x25
>[  408.966724] [IGT] prime_vgem: executing
>[  409.012514] [IGT] prime_vgem: starting subtest basic-fence-mmap
>[  409.012622] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  409.023414] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  409.023539] [IGT] prime_vgem: exiting, ret=0
>[  409.071075] Console: switching to colour frame buffer device 240x75
>[  409.180191] Console: switching to colour dummy device 80x25
>[  409.180365] [IGT] prime_vgem: executing
>[  409.203523] [IGT] prime_vgem: starting subtest basic-fence-read
>[  409.203630] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  409.220402] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  409.220506] [IGT] prime_vgem: exiting, ret=0
>[  409.271262] Console: switching to colour frame buffer device 240x75
>[  409.381888] Console: switching to colour dummy device 80x25
>[  409.382024] [IGT] prime_vgem: executing
>[  409.427501] [IGT] prime_vgem: starting subtest basic-fence-wait-default
>[  409.439302] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  410.441503] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  410.441782] [IGT] prime_vgem: exiting, ret=0
>[  410.488858] Console: switching to colour frame buffer device 240x75
>[  410.599571] Console: switching to colour dummy device 80x25
>[  410.599735] [IGT] prime_vgem: executing
>[  410.632956] [IGT] prime_vgem: starting subtest basic-gtt
>[  410.633017] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  410.644597] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  410.644695] [IGT] prime_vgem: exiting, ret=0
>[  410.689026] Console: switching to colour frame buffer device 240x75
>[  410.799949] Console: switching to colour dummy device 80x25
>[  410.800202] [IGT] prime_vgem: executing
>[  410.845479] [IGT] prime_vgem: starting subtest basic-read
>[  410.845538] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  410.856818] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  410.856923] [IGT] prime_vgem: exiting, ret=0
>[  410.889238] Console: switching to colour frame buffer device 240x75
>[  410.999159] Console: switching to colour dummy device 80x25
>[  410.999331] [IGT] prime_vgem: executing
>[  411.032368] [IGT] prime_vgem: starting subtest basic-sync-default
>[  411.041235] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  411.042241] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  411.042431] [IGT] prime_vgem: exiting, ret=0
>[  411.089349] Console: switching to colour frame buffer device 240x75
>[  411.201519] Console: switching to colour dummy device 80x25
>[  411.201694] [IGT] prime_vgem: executing
>[  411.245478] [IGT] prime_vgem: starting subtest basic-wait-default
>[  411.254260] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  411.255278] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  411.255411] [IGT] prime_vgem: exiting, ret=0
>[  411.306233] Console: switching to colour frame buffer device 240x75
>[  411.416368] Console: switching to colour dummy device 80x25
>[  411.416521] [IGT] prime_vgem: executing
>[  411.450489] [IGT] prime_vgem: starting subtest basic-write
>[  411.450549] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  411.462612] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  411.462721] [IGT] prime_vgem: exiting, ret=0
>[  411.506335] Console: switching to colour frame buffer device 240x75
>[  411.617446] Console: switching to colour dummy device 80x25
>[  411.617620] [IGT] vgem_basic: executing
>[  411.639807] [IGT] vgem_basic: starting subtest create
>[  411.639877] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  411.639941] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1048576
>[  411.639993] [drm:vgem_gem_dumb_create [vgem]] Created object of size 2147483648
>[  411.640239] [IGT] vgem_basic: exiting, ret=0
>[  411.656472] Console: switching to colour frame buffer device 240x75
>[  411.766744] Console: switching to colour dummy device 80x25
>[  411.766882] [IGT] vgem_basic: executing
>[  411.773169] [IGT] vgem_basic: starting subtest debugfs
>[  411.773470] [IGT] vgem_basic: exiting, ret=0
>[  411.789900] Console: switching to colour frame buffer device 240x75
>[  411.898992] Console: switching to colour dummy device 80x25
>[  411.899227] [IGT] vgem_basic: executing
>[  411.906691] [IGT] vgem_basic: starting subtest dmabuf-export
>[  411.925274] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  411.925512] [IGT] vgem_basic: exiting, ret=0
>[  411.973380] Console: switching to colour frame buffer device 240x75
>[  412.083952] Console: switching to colour dummy device 80x25
>[  412.084261] [IGT] vgem_basic: executing
>[  412.106871] [IGT] vgem_basic: starting subtest dmabuf-fence
>[  412.106936] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  412.107370] [IGT] vgem_basic: exiting, ret=0
>[  412.123506] Console: switching to colour frame buffer device 240x75
>[  412.234249] Console: switching to colour dummy device 80x25
>[  412.234427] [IGT] vgem_basic: executing
>[  412.256969] [IGT] vgem_basic: starting subtest dmabuf-fence-before
>[  412.257102] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  412.257319] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  412.257518] [IGT] vgem_basic: exiting, ret=0
>[  412.273613] Console: switching to colour frame buffer device 240x75
>[  412.386665] Console: switching to colour dummy device 80x25
>[  412.386839] [IGT] vgem_basic: executing
>[  412.407121] [IGT] vgem_basic: starting subtest dmabuf-mmap
>[  412.407188] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  412.407558] [IGT] vgem_basic: exiting, ret=0
>[  412.423746] Console: switching to colour frame buffer device 240x75
>[  412.542434] Console: switching to colour dummy device 80x25
>[  412.542611] [IGT] vgem_basic: executing
>[  412.557306] [IGT] vgem_basic: starting subtest mmap
>[  412.557373] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  412.557625] [IGT] vgem_basic: exiting, ret=0
>[  412.573853] Console: switching to colour frame buffer device 240x75
>[  412.683240] Console: switching to colour dummy device 80x25
>[  412.683402] [IGT] vgem_basic: executing
>[  412.690630] [IGT] vgem_basic: starting subtest second-client
>[  412.724042] [IGT] vgem_basic: exiting, ret=0
>[  412.740665] Console: switching to colour frame buffer device 240x75
>[  412.850711] Console: switching to colour dummy device 80x25
>[  412.850880] [IGT] vgem_basic: executing
>[  412.857451] [IGT] vgem_basic: starting subtest sysfs
>[  412.858240] [IGT] vgem_basic: exiting, ret=0
>[  412.874118] Console: switching to colour frame buffer device 240x75
>[  413.002210] Console: switching to colour dummy device 80x25
>[  413.002380] [IGT] vgem_basic: executing
>[  413.002560] [IGT] vgem_basic: starting subtest unload
>[  413.024576] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  413.046831] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  413.070479] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  413.074297] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  413.103525] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  413.107555] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  413.129553] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  413.141247] [IGT] vgem_basic: exiting, ret=0
>[  413.157649] Console: switching to colour frame buffer device 240x75
>[  413.271444] Console: switching to colour dummy device 80x25
>[  413.271619] [IGT] drv_module_reload: executing
>[  413.272449] [IGT] drv_module_reload: starting subtest basic-reload
>[  413.298487] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  413.298508] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  413.325117] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  413.325127] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  413.373621] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  413.373676] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  413.373711] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  413.373752] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.373786] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.373819] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  413.373851] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  413.373883] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  413.456215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.457717] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  413.457844] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  413.475413] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  413.475511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  413.475568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  413.475618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.475654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.475693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.475729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.475764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.475799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.475838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.475876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.475913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.475950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.475984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.476066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.476193] [drm:intel_power_well_disable [i915]] disabling display
>[  413.476380] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  413.476430] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.476471] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.489118] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.489153] [drm:intel_power_well_enable [i915]] enabling display
>[  413.489188] [drm:hsw_set_power_well [i915]] Enabling power well
>[  413.707561] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  413.707598] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  413.708967] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x1626 rev=0x09
>[  413.709009] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  413.709036] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  413.709062] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  413.709086] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  413.709115] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  413.709152] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  413.709187] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  413.709220] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  413.709255] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  413.709288] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  413.709322] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  413.709356] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  413.709389] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  413.709423] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  413.709456] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  413.709490] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  413.709524] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  413.709558] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  413.709592] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  413.709625] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  413.709659] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  413.709692] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  413.709725] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  413.709759] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  413.709792] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  413.709827] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  413.709862] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  413.709896] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  413.709929] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  413.709963] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  413.711014] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  413.711054] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  413.711093] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  413.711130] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  413.712338] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  413.712379] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  413.712414] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  413.712450] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  413.712483] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  413.712517] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  413.712548] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  413.712581] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  413.712612] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  413.712644] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  413.712679] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  413.712716] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  413.712768] [drm] Memory usable by graphics device = 4096M
>[  413.712809] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  413.712846] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  413.712860] [drm] Replacing VGA console driver
>[  413.712971] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  413.713191] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  413.713254] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  413.713289] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  413.719031] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  413.719068] [drm:intel_opregion_setup [i915]] ASLE supported
>[  413.719103] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  413.719138] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  413.719355] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  413.719363] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  413.719365] [drm] Driver supports precise vblank timestamp query.
>[  413.719401] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  413.719436] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  413.719471] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  413.719505] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  413.723077] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  413.723133] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  413.723178] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  413.723239] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  413.723248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  413.723301] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  413.723356] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  413.723415] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  413.723422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  413.723474] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  413.723533] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  413.723588] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  413.723641] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  413.723692] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  413.723744] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  413.723796] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  413.723842] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  413.724829] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  413.724870] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  413.724979] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.725096] [drm:intel_power_well_enable [i915]] enabling display
>[  413.726797] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  413.726845] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  413.726886] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  413.726925] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  413.726963] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  413.727248] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  413.727287] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  413.727325] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  413.727362] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  413.727398] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  413.727433] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  413.727468] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  413.727504] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  413.727538] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  413.727574] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  413.727608] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  413.727658] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  413.728524] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  413.728945] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  413.729160] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  413.729545] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  413.729601] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  413.729741] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  413.729792] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  413.729894] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  413.729939] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  413.730446] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  413.730496] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  413.730548] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  413.730591] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  413.730642] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  413.730686] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  413.730731] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  413.730773] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  413.730815] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  413.730852] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  413.730890] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  413.730927] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  413.730967] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  413.731087] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  413.731125] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  413.731162] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  413.731198] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  413.731259] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  413.731301] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  413.731341] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  413.731393] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  413.731430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  413.731467] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  413.731502] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.731511] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  413.731545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.731552] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  413.731588] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  413.731619] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  413.731652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.731684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.731724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.731757] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.731791] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  413.731824] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  413.731858] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  413.731895] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  413.731926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  413.731961] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  413.732162] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.732169] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  413.732205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.732211] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  413.732246] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  413.732279] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  413.732313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.732343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.732384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.732416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.732451] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  413.732483] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  413.732516] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  413.732552] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  413.732584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  413.732617] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  413.732648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.732656] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  413.732687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.732694] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  413.732728] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  413.732759] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  413.732792] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.732823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.732863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.732896] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.732929] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  413.732960] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  413.733124] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  413.733168] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  413.733205] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  413.733241] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  413.733309] [drm:intel_power_well_disable [i915]] disabling display
>[  413.733407] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  413.733444] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.733903] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  413.734037] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  413.734320] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  413.737738] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  413.737773] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  413.737812] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  413.737851] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  413.737889] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  413.737926] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  413.738478] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  413.738522] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  413.738565] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  413.738601] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  413.740422] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  413.741182] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  413.742151] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  413.754598] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  413.755536] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input11
>[  413.756476] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  413.756480] [drm] DRM_I915_DEBUG enabled
>[  413.756483] [drm] DRM_I915_DEBUG_GEM enabled
>[  413.756488] [drm:drm_setup_crtcs] 
>[  413.756497] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  413.756553] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  413.756618] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.758053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.758116] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.760034] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  413.760047] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  413.762034] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.762081] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  413.764062] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  413.764072] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.764105] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.764111] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  413.764124] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  413.764129] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  413.764164] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  413.764195] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.765414] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  413.766380] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  413.766427] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  413.766468] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  413.766507] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  413.767714] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  413.767750] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  413.782406] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  413.783336] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.783344] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  413.783544] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  413.783547] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  413.783605] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.783608] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.783615] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  413.783618] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  413.783624] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  413.783627] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  413.783636] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  413.783640] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.783643] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.783647] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.783651] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.783655] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  413.783658] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.783662] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  413.783666] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.783669] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  413.783673] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  413.783677] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.783680] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  413.783684] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  413.783688] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.783691] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  413.783695] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  413.783699] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.783702] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  413.783706] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  413.783710] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  413.783714] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  413.783717] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  413.783721] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  413.783725] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.783728] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.783732] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  413.783736] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  413.783740] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.783743] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  413.783747] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  413.783751] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  413.783788] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  413.783821] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.785042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.785088] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.787023] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  413.787034] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  413.789076] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.789127] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  413.791146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  413.791159] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  413.791210] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.791220] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  413.791225] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  413.791249] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  413.791254] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  413.791258] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  413.791319] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  413.791330] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  413.791335] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  413.791339] [drm:drm_setup_crtcs] found mode 1920x1200
>[  413.791344] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  413.791358] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  413.791432] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  413.792554] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  413.793187] fbcon: inteldrmfb (fb0) is primary device
>[  413.793713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  413.793746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.793781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  413.793820] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  413.793853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  413.793889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.793924] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  413.793959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  413.794025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  413.794066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  413.794103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.794110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.794145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.794151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  413.794187] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  413.794221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  413.794256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.794289] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  413.794330] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  413.794365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.794398] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  413.794432] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  413.794466] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  413.794506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  413.794550] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  413.794825] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.794877] [drm:intel_power_well_enable [i915]] enabling display
>[  413.794925] [drm:hsw_set_power_well [i915]] Enabling power well
>[  413.795076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  413.795121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  413.795163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  413.795202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  413.795238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  413.795278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  413.795327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  413.795369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  413.795409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.795445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  413.795479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  413.795582] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  413.795630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  413.797873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  413.797919] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  413.797958] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.798044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  413.800739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  413.800773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  413.800806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  413.803544] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  413.803590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  413.806616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  413.810226] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  413.810341] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  413.810399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  413.810505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  413.810587] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  413.810626] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  413.827248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  413.827314] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  413.827408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  413.827732] Console: switching to colour frame buffer device 240x75
>[  413.848931] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  413.863265] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  413.873974] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  413.874047] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  413.874070] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  413.874105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.874125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.874145] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  413.874164] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  413.874183] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  413.879019] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  413.879036] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  413.879041] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  413.879045] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  413.879049] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  413.879054] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  413.879689] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  413.894103] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input12
>[  413.895994] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input13
>[  413.896862] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input14
>[  413.897933] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input15
>[  413.898681] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input16
>[  413.933015] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input17
>[  413.935324] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input18
>[  414.160812] [IGT] drv_module_reload: exiting, ret=0
>[  414.251306] Console: switching to colour dummy device 80x25
>[  414.251463] [IGT] drv_module_reload: executing
>[  414.252077] [IGT] drv_module_reload: starting subtest basic-no-display
>[  414.276077] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  414.276087] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  414.302061] azx_init_pci: snd_hda_intel 0000:00:03.0: Clearing TCSEL
>[  414.302072] azx_init_pci: snd_hda_intel 0000:00:03.0: SCH snoop: Enabled
>[  414.350194] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  414.350259] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  414.350295] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  414.350337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.350370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.350403] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  414.350435] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  414.350467] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  414.397127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.410877] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  414.411051] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  414.430052] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  414.430209] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  414.430255] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  414.430306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.430347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.430392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.430428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.430460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.430500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.430543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.430585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.430627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.430669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.430709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.430748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.430815] [drm:intel_power_well_disable [i915]] disabling display
>[  414.430883] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  414.430914] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  414.430989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.443018] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.443052] [drm:intel_power_well_enable [i915]] enabling display
>[  414.443087] [drm:hsw_set_power_well [i915]] Enabling power well
>[  414.563861] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  414.563898] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  414.564807] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x1626 rev=0x09
>[  414.564838] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  414.564869] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  414.564898] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  414.564931] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  414.565002] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  414.565036] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  414.565074] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  414.565112] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  414.565148] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  414.565183] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  414.565211] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  414.565241] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  414.565272] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  414.565303] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  414.565334] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  414.565365] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  414.565395] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  414.565426] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  414.565456] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  414.565487] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  414.565518] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  414.565549] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  414.565579] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  414.565610] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  414.565641] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  414.565672] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  414.565702] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  414.565733] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  414.565763] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  414.565794] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  414.565824] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  414.565856] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  414.565886] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  414.565919] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  414.568405] [drm] Display disabled (module parameter)
>[  414.568463] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  414.568505] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  414.568543] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  414.568579] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  414.568616] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  414.568652] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  414.568688] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  414.568724] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  414.568759] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  414.568793] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  414.568832] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  414.568871] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  414.569459] [drm] Memory usable by graphics device = 4096M
>[  414.569506] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  414.569549] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  414.569564] [drm] Replacing VGA console driver
>[  414.569681] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  414.569854] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  414.569907] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  414.569943] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  414.576020] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  414.576054] [drm:intel_opregion_setup [i915]] ASLE supported
>[  414.576080] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  414.576111] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  414.576312] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  414.576345] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  414.576378] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  414.576411] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  414.576443] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  414.580586] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  414.580647] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  414.580704] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  414.580773] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  414.580782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  414.580838] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  414.580896] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  414.580958] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  414.581021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  414.581089] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  414.581161] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  414.581226] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  414.581280] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  414.581335] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  414.581393] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  414.581448] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  414.581503] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  414.582146] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  414.582199] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  414.582296] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.582336] [drm:intel_power_well_enable [i915]] enabling display
>[  414.584542] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  414.584591] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  414.584631] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  414.584670] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  414.584706] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  414.584741] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  414.584777] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  414.584812] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  414.584847] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  414.584881] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  414.584915] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  414.585089] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  414.585126] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  414.585162] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  414.585198] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  414.585234] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  414.585336] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  414.585433] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  414.585792] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  414.589878] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  414.589917] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  414.590112] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  414.590166] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  414.590217] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  414.590263] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  414.593562] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  414.595034] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  414.595038] [drm] DRM_I915_DEBUG enabled
>[  414.595041] [drm] DRM_I915_DEBUG_GEM enabled
>[  414.604586] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  414.604599] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  414.604987] [IGT] drv_module_reload: exiting, ret=0
>[  414.619176] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  414.619189] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  414.619193] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  414.619198] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  414.619202] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  414.619207] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  414.681170] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input19
>[  414.683460] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input20
>[  414.717644] [IGT] drv_module_reload: executing
>[  414.718550] [IGT] drv_module_reload: starting subtest basic-reload-inject
>[  414.839913] Setting dangerous option inject_load_failure - tainting kernel
>[  414.853814] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  414.853850] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  414.854751] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x1626 rev=0x09
>[  414.854783] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  414.854814] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  414.854844] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  414.854874] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  414.854906] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  414.854985] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  414.855027] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  414.855066] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  414.855105] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  414.855142] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  414.855179] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  414.855214] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  414.855249] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  414.855283] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  414.855319] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  414.855353] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  414.855388] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  414.855423] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  414.855458] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  414.855492] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  414.855526] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  414.855560] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  414.855594] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  414.855628] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  414.855662] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  414.855696] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  414.855729] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  414.855763] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  414.855797] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  414.855830] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  414.855864] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  414.855897] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  414.855954] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  414.855990] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  414.858495] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  414.858539] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  414.858577] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  414.858614] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  414.858650] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  414.858685] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  414.858721] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  414.858757] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  414.858792] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  414.858827] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  414.858867] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  414.858905] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  414.859411] [drm] Memory usable by graphics device = 4096M
>[  414.859457] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  414.859498] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  414.859512] [drm] Replacing VGA console driver
>[  414.859623] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  414.859806] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  414.859884] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  414.859925] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  414.868008] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  414.868040] [drm:intel_opregion_setup [i915]] ASLE supported
>[  414.868102] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  414.868156] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  414.868465] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  414.868477] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  414.868480] [drm] Driver supports precise vblank timestamp query.
>[  414.868534] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  414.868588] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  414.868642] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  414.868695] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  414.872018] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  414.872074] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  414.872120] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  414.872200] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  414.872209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  414.872265] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  414.872323] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  414.872384] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  414.872392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  414.872447] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  414.872508] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  414.872566] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  414.872621] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  414.872673] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  414.872728] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  414.872784] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  414.872832] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  414.873410] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  414.873464] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  414.873580] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.873632] [drm:intel_power_well_enable [i915]] enabling display
>[  414.875327] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  414.875362] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  414.875393] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  414.875423] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  414.875453] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  414.875480] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  414.875511] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  414.875541] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  414.875571] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  414.875601] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  414.875630] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  414.875661] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  414.875691] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  414.875721] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  414.875751] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  414.875781] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  414.875818] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  414.876226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  414.876639] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  414.876681] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  414.877074] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  414.877132] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  414.877275] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  414.877325] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  414.877430] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  414.877477] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  414.877686] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  414.877734] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  414.877785] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  414.877829] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  414.877879] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  414.877921] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  414.878012] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  414.878056] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  414.878099] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  414.878137] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  414.878174] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  414.878211] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  414.878252] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  414.878291] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  414.878326] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  414.878362] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  414.878397] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  414.878457] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  414.878500] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  414.878542] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  414.878594] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  414.878633] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  414.878670] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  414.878706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.878715] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  414.878749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.878757] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  414.878793] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  414.878829] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  414.878864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.878898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.879108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.879149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.879189] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  414.879226] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  414.879263] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  414.879302] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  414.879337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  414.879372] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  414.879407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.879415] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  414.879448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.879455] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  414.879490] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  414.879525] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  414.879561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.879595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.879637] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.879672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.879708] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  414.879743] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  414.879778] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  414.879815] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  414.879850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  414.879883] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  414.879917] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.880071] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  414.880106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.880113] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  414.880149] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  414.880184] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  414.880219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.880254] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.880296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.880332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.880368] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  414.880403] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  414.880439] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  414.880483] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  414.880521] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  414.880559] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  414.880624] [drm:intel_power_well_disable [i915]] disabling display
>[  414.880725] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  414.880764] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.881355] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  414.881464] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  414.881749] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  414.883816] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  414.883856] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  414.883897] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  414.884006] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  414.884058] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  414.884107] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  414.884618] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  414.884654] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  414.884699] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  414.884740] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  414.887018] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  414.888043] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  414.889597] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  414.902050] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  414.902865] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input21
>[  414.903753] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  414.903758] [drm] DRM_I915_DEBUG enabled
>[  414.903763] [drm:drm_setup_crtcs] 
>[  414.903766] [drm] DRM_I915_DEBUG_GEM enabled
>[  414.903769] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  414.903824] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  414.903895] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.906039] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.906103] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.907989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  414.908002] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  414.910026] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.910074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  414.911967] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  414.911977] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  414.912010] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.912016] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  414.912029] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  414.912034] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  414.912069] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  414.912100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.913307] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  414.914274] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  414.914324] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  414.914366] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  414.914406] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  414.915456] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  414.915502] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  414.930498] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  414.931510] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.931517] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  414.931699] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  414.931703] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  414.931753] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.931756] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.931762] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  414.931764] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  414.931770] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  414.931772] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  414.931780] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  414.931783] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.931787] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.931790] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.931793] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.931796] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  414.931799] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.931802] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  414.931806] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.931809] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  414.931812] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  414.931815] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.931818] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  414.931821] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  414.931824] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.931828] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  414.931831] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  414.931834] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.931837] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  414.931840] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  414.931843] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  414.931846] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  414.931850] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  414.931853] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  414.931856] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  414.931859] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.931862] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  414.931865] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  414.931868] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.931872] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  414.931875] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  414.931879] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  414.931932] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  414.932299] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.934168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.934198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  414.936012] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  414.936025] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  414.938025] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  414.938081] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  414.940010] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  414.940022] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  414.940077] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.940085] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  414.940091] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  414.940118] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  414.940123] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  414.940127] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  414.940190] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  414.940202] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  414.940207] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  414.940211] [drm:drm_setup_crtcs] found mode 1920x1200
>[  414.940215] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  414.940231] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  414.940308] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  414.941623] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  414.942062] fbcon: inteldrmfb (fb0) is primary device
>[  414.942469] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  414.942502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.942537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  414.942576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  414.942609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  414.942645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.942679] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  414.942725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  414.942767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  414.942805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  414.942840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.942847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.942880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.942886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  414.942921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  414.942993] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  414.943027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.943060] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  414.943101] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  414.943135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.943170] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  414.943204] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  414.943238] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  414.943279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  414.943323] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  414.943619] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.943667] [drm:intel_power_well_enable [i915]] enabling display
>[  414.943713] [drm:hsw_set_power_well [i915]] Enabling power well
>[  414.943820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  414.943862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  414.943913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  414.943989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  414.944025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  414.944062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  414.944110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  414.944148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  414.944185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.944218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  414.944250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  414.944341] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  414.944387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  414.946623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  414.946659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.946692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.946727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.950489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  414.950522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  414.950553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.953292] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.953333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  414.956310] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.959405] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  414.959487] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  414.959515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  414.959617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  414.959681] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  414.959721] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  414.976445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  414.976512] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  414.976601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  414.976879] Console: switching to colour frame buffer device 240x75
>[  414.998188] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  415.008559] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  415.012183] Console: switching to colour dummy device 80x25
>[  415.020494] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  415.020549] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  415.020584] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  415.020641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.020675] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.020708] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  415.020740] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  415.020773] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  415.025035] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  415.025053] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.025058] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.025062] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  415.025066] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  415.025071] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  415.041892] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input22
>[  415.046820] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input23
>[  415.048033] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input24
>[  415.048740] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input25
>[  415.049682] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input26
>[  415.078464] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input27
>[  415.083727] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input28
>[  415.089462] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  415.089514] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  415.089547] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  415.089585] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.089615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.089645] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  415.089674] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  415.089704] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  415.172189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  415.176411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  415.176501] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  415.195229] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  415.195390] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  415.195435] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  415.195490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  415.195511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  415.195537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  415.195559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  415.195579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  415.195602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  415.195628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  415.195653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  415.195678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  415.195703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  415.195726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  415.195750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  415.195791] [drm:intel_power_well_disable [i915]] disabling display
>[  415.195860] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  415.195892] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  415.195977] [drm:intel_power_well_disable [i915]] disabling always-on
>[  415.204585] [drm:intel_power_well_enable [i915]] enabling always-on
>[  415.204617] [drm:intel_power_well_enable [i915]] enabling display
>[  415.204647] [drm:hsw_set_power_well [i915]] Enabling power well
>[  415.317424] Setting dangerous option inject_load_failure - tainting kernel
>[  415.332187] [drm] Injecting failure at checkpoint 1 [i915_driver_init_early:809]
>[  415.332224] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  415.340495] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  415.340509] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  415.355256] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  415.355265] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.355267] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.355270] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  415.355272] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  415.355275] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  415.403826] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input29
>[  415.410367] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input30
>[  415.526152] Setting dangerous option inject_load_failure - tainting kernel
>[  415.539868] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  415.539919] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  415.540757] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x1626 rev=0x09
>[  415.540789] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  415.540822] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  415.540853] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  415.540885] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  415.540963] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  415.541002] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  415.541037] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  415.541072] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  415.541108] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  415.541144] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  415.541178] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  415.541209] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  415.541244] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  415.541279] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  415.541313] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  415.541347] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  415.541381] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  415.541414] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  415.541447] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  415.541482] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  415.541514] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  415.541548] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  415.541581] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  415.541614] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  415.541647] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  415.541681] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  415.541715] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  415.541749] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  415.541782] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  415.541816] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  415.541850] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  415.541883] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  415.541943] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  415.541974] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  415.541981] [drm] Injecting failure at checkpoint 2 [i915_driver_init_mmio:941]
>[  415.560251] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  415.573495] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  415.573506] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  415.580766] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  415.580779] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.580784] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.580788] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  415.580792] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  415.580797] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  415.632662] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input31
>[  415.635486] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input32
>[  415.763041] Setting dangerous option inject_load_failure - tainting kernel
>[  415.777114] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  415.777147] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  415.778122] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x1626 rev=0x09
>[  415.778150] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  415.778176] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  415.778200] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  415.778223] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  415.778251] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  415.778282] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  415.778313] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  415.778343] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  415.778373] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  415.778403] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  415.778433] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  415.778463] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  415.778493] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  415.778523] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  415.778553] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  415.778583] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  415.778613] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  415.778643] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  415.778673] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  415.778703] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  415.778733] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  415.778762] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  415.778792] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  415.778818] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  415.778843] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  415.778867] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  415.779562] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  415.779598] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  415.779634] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  415.779670] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  415.779705] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  415.779739] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  415.779773] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  415.779808] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  415.780656] [drm] Injecting failure at checkpoint 3 [i915_driver_init_hw:1007]
>[  415.807166] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  415.814927] [IGT] drv_module_reload: exiting, ret=0
>[  415.820934] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
>[  415.820953] snd_hda_intel 0000:00:03.0: HSW/BDW HD-audio HDMI/DP requires binding with gfx driver
>[  415.828861] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  415.828898] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.828902] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  415.828904] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  415.828906] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  415.828909] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  415.878111] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input33
>[  415.886444] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input34
>[  415.931710] [IGT] drv_module_reload: executing
>[  415.932549] [IGT] drv_module_reload: starting subtest basic-reload-final
>[  416.032285] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  416.032320] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  416.033243] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x1626 rev=0x09
>[  416.033275] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  416.033306] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  416.033336] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  416.033366] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  416.033396] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  416.033426] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  416.033456] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  416.033485] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  416.033515] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  416.033545] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  416.033574] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  416.033604] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  416.033634] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  416.033664] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  416.033694] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  416.033724] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  416.033753] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  416.033783] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  416.033813] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  416.033843] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  416.033876] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  416.033948] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  416.033985] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  416.034022] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  416.034059] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  416.034095] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  416.034131] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  416.034167] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  416.034202] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  416.034236] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  416.034272] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  416.034306] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  416.034341] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  416.034375] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  416.035086] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  416.035131] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  416.035175] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  416.035218] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  416.035261] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  416.035305] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  416.035347] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  416.035391] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  416.035434] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  416.035476] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  416.035519] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  416.035561] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  416.035610] [drm] Memory usable by graphics device = 4096M
>[  416.035656] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  416.035702] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  416.035717] [drm] Replacing VGA console driver
>[  416.035830] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  416.036032] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  416.036114] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  416.036163] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  416.041938] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  416.041986] [drm:intel_opregion_setup [i915]] ASLE supported
>[  416.042026] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  416.042064] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  416.042379] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  416.042393] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  416.042396] [drm] Driver supports precise vblank timestamp query.
>[  416.042443] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  416.042486] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  416.042526] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  416.042563] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  416.046092] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  416.046151] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  416.046206] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  416.046269] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  416.046278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  416.046332] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  416.046385] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  416.046444] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  416.046451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  416.046503] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  416.046562] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  416.046614] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  416.046667] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  416.046720] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  416.046772] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  416.046824] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  416.046883] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  416.047737] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  416.047807] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  416.047994] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.048061] [drm:intel_power_well_enable [i915]] enabling display
>[  416.049636] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  416.049671] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  416.049702] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  416.049733] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  416.049763] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  416.049794] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  416.049824] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  416.049856] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  416.049926] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  416.049963] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  416.049999] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  416.050032] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  416.050065] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  416.050098] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  416.050134] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  416.050167] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  416.050213] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  416.050653] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  416.051164] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  416.051209] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  416.051594] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  416.051651] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  416.051789] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  416.051840] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  416.052055] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  416.052105] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  416.052336] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  416.052384] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  416.052435] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  416.052480] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  416.052528] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  416.052570] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  416.052614] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  416.052656] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  416.052696] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  416.052733] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  416.052770] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  416.052806] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  416.052846] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  416.053017] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  416.053056] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  416.053092] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  416.053128] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  416.053185] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  416.053229] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  416.053272] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  416.053324] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  416.053363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  416.053401] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  416.053437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.053446] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  416.053481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.053489] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  416.053527] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  416.053562] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  416.053598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.053634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  416.053677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  416.053712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.053749] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  416.053785] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  416.053820] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  416.053857] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  416.054026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  416.054062] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  416.054098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.054105] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  416.054140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.054147] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  416.054181] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  416.054215] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  416.054250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.054284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  416.054325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  416.054361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.054397] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  416.054430] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  416.054465] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  416.054502] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  416.054536] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  416.054571] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  416.054603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.054611] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  416.054644] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.054651] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  416.054686] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  416.054721] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  416.054755] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.054788] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  416.054828] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  416.054864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.055043] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  416.055079] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  416.055116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  416.055159] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  416.055198] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  416.055236] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  416.055303] [drm:intel_power_well_disable [i915]] disabling display
>[  416.055401] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  416.055441] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.055981] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  416.056090] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  416.056379] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  416.058493] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  416.058530] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  416.058578] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  416.058617] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  416.058657] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  416.058701] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  416.059294] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  416.059339] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  416.059379] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  416.059416] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  416.059955] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  416.060030] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.061634] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  416.061964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  416.062026] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  416.062574] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  416.063815] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  416.064053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  416.064065] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  416.066013] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  416.066060] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  416.067960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  416.067972] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  416.068016] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.068024] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  416.068070] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  416.068112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.069388] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  416.070366] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  416.070403] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  416.070439] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  416.070474] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  416.071531] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  416.071565] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  416.084874] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  416.085486] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  416.086341] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input35
>[  416.086457] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.086466] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  416.086518] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  416.086563] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.087364] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  416.087368] [drm] DRM_I915_DEBUG enabled
>[  416.087371] [drm] DRM_I915_DEBUG_GEM enabled
>[  416.088002] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  416.088048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  416.092413] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  416.092424] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  416.093949] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  416.093996] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  416.095930] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  416.095943] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  416.095990] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.095998] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  416.096290] [drm:drm_setup_crtcs] 
>[  416.096298] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  416.096350] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  416.096424] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.097956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  416.098016] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  416.100087] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  416.100096] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  416.101955] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  416.101993] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  416.104064] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  416.104074] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  416.104108] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.104118] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  416.104122] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  416.104159] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  416.104192] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.105360] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  416.106311] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  416.106360] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  416.106405] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  416.106446] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  416.107666] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  416.107714] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  416.108837] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.109208] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  416.109215] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  416.109295] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  416.109299] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  416.109310] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  416.109314] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  416.109324] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  416.109328] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  416.109341] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  416.109347] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  416.109352] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  416.109358] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  416.109363] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  416.109368] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  416.109374] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  416.109379] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  416.109385] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  416.109390] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  416.109396] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  416.109401] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  416.109407] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  416.109412] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  416.109418] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  416.109423] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  416.109429] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  416.109435] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  416.109440] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  416.109446] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  416.109451] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  416.109457] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  416.109463] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  416.109468] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  416.109474] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  416.109480] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  416.109485] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  416.109491] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  416.109497] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  416.109502] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  416.109508] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  416.109513] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  416.109560] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  416.109603] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.110932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  416.110979] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  416.112985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  416.112997] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  416.114954] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  416.115005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  416.117024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  416.117036] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  416.117087] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.117095] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  416.117118] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  416.117123] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  416.117127] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  416.117184] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  416.117195] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  416.117199] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  416.117204] [drm:drm_setup_crtcs] found mode 1920x1200
>[  416.117208] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  416.117222] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  416.117289] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  416.118397] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  416.118728] fbcon: inteldrmfb (fb0) is primary device
>[  416.119214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  416.119247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  416.119282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  416.119321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  416.119354] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  416.119390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  416.119425] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  416.119459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  416.119493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  416.119526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  416.119560] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.119565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  416.119598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.119602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  416.119636] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  416.119669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  416.119703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.119736] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  416.119771] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  416.119804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.119838] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  416.119877] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  416.119941] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  416.119983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  416.120029] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  416.120316] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.120374] [drm:intel_power_well_enable [i915]] enabling display
>[  416.120430] [drm:hsw_set_power_well [i915]] Enabling power well
>[  416.120555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  416.120604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  416.120655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  416.120704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  416.120751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  416.120800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  416.120861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  416.120945] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  416.120996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.121043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  416.121090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  416.121203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  416.121256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  416.123526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  416.123569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  416.123622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  416.123664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  416.127509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  416.127556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  416.127603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  416.130344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  416.130394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  416.133481] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  416.137102] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  416.137211] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  416.137265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  416.137406] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  416.137465] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  416.137505] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  416.154093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  416.154156] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  416.154247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  416.154538] Console: switching to colour frame buffer device 240x75
>[  416.176300] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  416.186481] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  416.197181] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  416.197238] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  416.197272] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  416.197329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  416.197361] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  416.197391] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  416.197422] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  416.197452] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  416.204199] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  416.204216] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  416.204221] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  416.204225] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  416.204229] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  416.204234] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  416.212974] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  416.223784] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input36
>[  416.225350] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input37
>[  416.226020] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input38
>[  416.226629] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input39
>[  416.234187] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input40
>[  416.471201] [IGT] drv_module_reload: exiting, ret=0
>[  416.563804] Console: switching to colour dummy device 80x25
>[  416.564129] [IGT] gvt_basic: executing
>[  416.659043] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  416.659098] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  416.659132] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  416.659172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  416.659204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  416.659238] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  416.659270] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  416.659301] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  417.256483] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input41
>[  417.257123] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input42
>[  417.341998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.354924] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  417.355022] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  417.374232] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  417.374387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  417.374433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  417.374480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.374513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  417.374548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  417.374578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  417.374607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  417.374639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  417.374673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  417.374706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  417.374737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  417.374768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.374801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  417.374874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  417.374939] [drm:intel_power_well_disable [i915]] disabling display
>[  417.375031] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  417.375077] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  417.375113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.387553] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.387585] [drm:intel_power_well_enable [i915]] enabling display
>[  417.387615] [drm:hsw_set_power_well [i915]] Enabling power well
>[  417.505757] [drm:i915_driver_load [i915]] Found LynxPoint LP PCH
>[  417.505794] [drm:intel_power_domains_init [i915]] Allowed DC state mask 00
>[  417.507083] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROADWELL gen=8 pciid=0x1626 rev=0x09
>[  417.507121] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  417.507156] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  417.507191] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  417.507224] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  417.507257] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  417.507289] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: no
>[  417.507321] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  417.507353] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  417.507384] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  417.507432] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  417.507466] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  417.507501] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  417.507534] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  417.507568] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  417.507603] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  417.507636] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: no
>[  417.507670] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  417.507705] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  417.507737] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  417.507770] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  417.507804] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  417.508505] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  417.508542] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  417.508578] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  417.508613] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  417.508648] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  417.508682] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  417.508716] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  417.508751] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  417.508786] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  417.509201] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  417.509240] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  417.509276] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  417.509311] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  417.510191] [drm:intel_device_info_runtime_init [i915]] slice mask: 0003
>[  417.510233] [drm:intel_device_info_runtime_init [i915]] slice total: 2
>[  417.510272] [drm:intel_device_info_runtime_init [i915]] subslice total: 6
>[  417.510309] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  417.510345] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  417.510381] [drm:intel_device_info_runtime_init [i915]] EU total: 48
>[  417.510415] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  417.510449] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  417.510483] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  417.510516] [drm:intel_device_info_runtime_init [i915]] has EU power gating: n
>[  417.510554] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  417.510591] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[  417.510636] [drm] Memory usable by graphics device = 4096M
>[  417.510682] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  417.510728] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  417.510743] [drm] Replacing VGA console driver
>[  417.511712] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  417.512611] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  417.512692] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  417.512733] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  417.517914] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  417.517956] [drm:intel_opregion_setup [i915]] ASLE supported
>[  417.517991] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  417.518025] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  417.518271] [drm:intel_gvt_init [i915]] Not in host or MPT modules not found
>[  417.518282] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  417.518284] [drm] Driver supports precise vblank timestamp query.
>[  417.518327] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  417.518372] [drm:intel_bios_init [i915]] VBT signature "$VBT HASWELL        ", BDB version 189
>[  417.518415] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[  417.518458] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  417.522610] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  417.522658] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  417.522697] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  417.522752] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  417.522759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  417.522807] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  417.522946] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  417.523019] [drm:intel_bios_init [i915]] Found SDVO panel mode in BIOS VBT tables:
>[  417.523031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[  417.523086] [drm:intel_bios_init [i915]] No SDVO device info is found in VBT
>[  417.523153] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  417.523214] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  417.523272] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  417.523330] [drm:intel_bios_init [i915]] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[  417.523380] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 6
>[  417.523418] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  417.523453] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 6
>[  417.524124] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  417.524178] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  417.524293] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.524344] [drm:intel_power_well_enable [i915]] enabling display
>[  417.526338] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  417.526386] [drm:intel_print_wm_latency [i915]] Primary WM0 latency 20 (2.0 usec)
>[  417.526427] [drm:intel_print_wm_latency [i915]] Primary WM1 latency 50 (25.0 usec)
>[  417.526466] [drm:intel_print_wm_latency [i915]] Primary WM2 latency 90 (45.0 usec)
>[  417.526504] [drm:intel_print_wm_latency [i915]] Primary WM3 latency 130 (65.0 usec)
>[  417.526540] [drm:intel_print_wm_latency [i915]] Primary WM4 latency 160 (80.0 usec)
>[  417.526576] [drm:intel_print_wm_latency [i915]] Sprite WM0 latency 20 (2.0 usec)
>[  417.526612] [drm:intel_print_wm_latency [i915]] Sprite WM1 latency 50 (25.0 usec)
>[  417.526647] [drm:intel_print_wm_latency [i915]] Sprite WM2 latency 90 (45.0 usec)
>[  417.526682] [drm:intel_print_wm_latency [i915]] Sprite WM3 latency 130 (65.0 usec)
>[  417.526717] [drm:intel_print_wm_latency [i915]] Sprite WM4 latency 160 (80.0 usec)
>[  417.526752] [drm:intel_print_wm_latency [i915]] Cursor WM0 latency 20 (2.0 usec)
>[  417.526787] [drm:intel_print_wm_latency [i915]] Cursor WM1 latency 50 (25.0 usec)
>[  417.527118] [drm:intel_print_wm_latency [i915]] Cursor WM2 latency 90 (45.0 usec)
>[  417.527156] [drm:intel_print_wm_latency [i915]] Cursor WM3 latency 130 (65.0 usec)
>[  417.527193] [drm:intel_print_wm_latency [i915]] Cursor WM4 latency 160 (80.0 usec)
>[  417.527242] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  417.527686] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  417.528327] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 540000 kHz
>[  417.528374] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 540000 kHz
>[  417.528743] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[  417.528787] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT)
>[  417.528970] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  417.529008] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  417.529075] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  417.529108] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  417.529277] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  417.529310] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  417.529344] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  417.529379] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  417.529419] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  417.529454] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  417.529487] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  417.529524] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  417.529561] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  417.529595] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  417.529630] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  417.529664] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  417.529700] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  417.529737] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  417.529775] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  417.529820] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  417.529909] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  417.529973] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  417.530020] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  417.530066] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  417.530122] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  417.530163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  417.530201] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.530239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.530247] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.530284] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.530293] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.530330] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  417.530367] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  417.530403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.530438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.530481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.530517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.530555] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  417.530592] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  417.530629] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  417.530669] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  417.530704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  417.530740] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.530773] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.530781] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.530815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.530845] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.530880] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  417.530915] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  417.530949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.530984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.531027] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.531063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.531099] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  417.531136] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  417.531170] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  417.531209] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  417.531245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  417.531278] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.531312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.531320] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.531353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.531360] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  417.531394] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  417.531429] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  417.531463] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.531498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.531540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.531576] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.531612] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  417.531648] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  417.531685] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  417.531729] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  417.531769] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  417.531808] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  417.531896] [drm:intel_power_well_disable [i915]] disabling display
>[  417.531996] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  417.532038] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.532492] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  417.532598] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  417.532907] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  417.534956] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  417.535004] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  417.535054] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  417.535102] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  417.535148] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  417.535192] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  417.535754] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  417.535813] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  417.535894] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  417.535936] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  417.536454] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  417.536534] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.538691] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>[  417.538919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.538980] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.540029] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  417.540902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.540915] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  417.541635] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  417.542881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.542930] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.544874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.544884] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.544918] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.544924] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from unknown to disconnected
>[  417.544961] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  417.544993] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.546225] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  417.547170] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  417.547206] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  417.547241] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  417.547276] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  417.548322] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  417.548359] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  417.560367] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  417.561688] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input43
>[  417.562321] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  417.562460] [drm] Initialized i915 1.6.0 20170306 for 0000:00:02.0 on minor 0
>[  417.562464] [drm] DRM_I915_DEBUG enabled
>[  417.562467] [drm] DRM_I915_DEBUG_GEM enabled
>[  417.563327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.563337] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from unknown to connected
>[  417.563386] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  417.563428] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.564876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.564923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.566910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.566924] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  417.568871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.568906] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.570882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.570892] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.570925] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.570931] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[  417.571211] [drm:drm_setup_crtcs] 
>[  417.571220] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  417.571274] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  417.571429] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.572892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.572952] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.575016] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  417.575028] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  417.577120] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.577169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  417.578871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  417.578882] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.578916] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.578926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  417.578931] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  417.578967] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  417.579001] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.580153] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  417.581129] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  417.581174] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  417.581214] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  417.581252] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  417.582334] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  417.582379] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  417.583559] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.583925] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  417.583932] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  417.584022] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  417.584027] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  417.584037] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  417.584041] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  417.584051] [drm:drm_mode_debug_printmodeline] Modeline 100:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  417.584055] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  417.584068] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  417.584074] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.584079] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.584085] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.584091] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  417.584096] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  417.584102] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  417.584107] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  417.584113] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.584119] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  417.584124] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  417.584130] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  417.584136] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  417.584141] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  417.584147] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  417.584153] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  417.584158] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  417.584164] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  417.584170] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  417.584175] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  417.584181] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  417.584187] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  417.584192] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  417.584198] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  417.584203] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  417.584209] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  417.584215] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  417.584220] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  417.584226] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  417.584232] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  417.584237] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  417.584243] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  417.584291] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  417.584334] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.585878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.585928] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.588026] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  417.588036] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  417.590126] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.590176] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  417.591910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  417.591925] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  417.591992] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.592001] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  417.592022] [drm:drm_setup_crtcs] connector 48 enabled? no
>[  417.592026] [drm:drm_setup_crtcs] connector 53 enabled? yes
>[  417.592031] [drm:drm_setup_crtcs] connector 57 enabled? no
>[  417.592087] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  417.592098] [drm:drm_setup_crtcs] looking for cmdline mode on connector 53
>[  417.592103] [drm:drm_setup_crtcs] looking for preferred mode on connector 53 0
>[  417.592107] [drm:drm_setup_crtcs] found mode 1920x1200
>[  417.592111] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  417.592126] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 32 (0,0)
>[  417.592192] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  417.593506] [drm:intelfb_create [i915]] allocated 1920x1200 fb: 0x00015000
>[  417.593905] fbcon: inteldrmfb (fb0) is primary device
>[  417.594317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  417.594349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  417.594386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  417.594424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  417.594458] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  417.594494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.594529] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  417.594563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  417.594598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  417.594631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  417.594664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.594669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.594702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.594706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  417.594740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  417.594774] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  417.594814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.594862] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  417.594897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  417.594930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.594964] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  417.594997] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  417.595031] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  417.595066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.595104] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  417.595321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.595361] [drm:intel_power_well_enable [i915]] enabling display
>[  417.595399] [drm:hsw_set_power_well [i915]] Enabling power well
>[  417.595490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  417.595525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  417.595559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  417.595593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  417.595627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  417.595661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  417.595705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  417.595741] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  417.595778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.595820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  417.595878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  417.595973] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  417.596016] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  417.598175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  417.598210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.598244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.598280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.602147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  417.602195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  417.602240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.604949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.604995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  417.608026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.611624] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  417.611730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  417.611774] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  417.611979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  417.612049] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  417.612081] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  417.628684] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  417.628753] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  417.628885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  417.629207] Console: switching to colour frame buffer device 240x75
>[  417.650827] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  417.661868] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  417.673711] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  417.673769] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  417.673804] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  417.674077] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
>[  417.674094] snd_hda_codec_realtek hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  417.674099] snd_hda_codec_realtek hdaudioC1D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  417.674103] snd_hda_codec_realtek hdaudioC1D0:    mono: mono_out=0x0
>[  417.674107] snd_hda_codec_realtek hdaudioC1D0:    inputs:
>[  417.674111] snd_hda_codec_realtek hdaudioC1D0:      Mic=0x19
>[  417.677929] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  417.677968] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  417.678002] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  417.678034] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  417.678066] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  417.678676] [IGT] gvt_basic: exiting, ret=77
>[  417.688462] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input44
>[  417.691658] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input45
>[  417.692683] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input46
>[  417.693648] input: HDA Intel HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/sound/card0/input47
>[  417.694618] input: HDA Intel HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:03.0/sound/card0/input48
>[  417.725119] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input49
>[  417.727473] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input50
>[  417.810118] Console: switching to colour dummy device 80x25
>[  417.810296] [IGT] core_auth: executing
>[  417.811653] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  417.822316] [IGT] core_auth: starting subtest many-magics
>[  425.094162] [IGT] core_auth: exiting, ret=0
>[  425.117947] Console: switching to colour frame buffer device 240x75
>[  425.225703] Console: switching to colour dummy device 80x25
>[  425.225885] [IGT] core_getclient: executing
>[  425.240340] [IGT] core_getclient: exiting, ret=0
>[  425.284734] Console: switching to colour frame buffer device 240x75
>[  425.396224] Console: switching to colour dummy device 80x25
>[  425.396375] [IGT] core_get_client_auth: executing
>[  425.396642] [IGT] core_get_client_auth: starting subtest master-drop
>[  425.408487] [IGT] core_get_client_auth: exiting, ret=0
>[  425.451559] Console: switching to colour frame buffer device 240x75
>[  425.563584] Console: switching to colour dummy device 80x25
>[  425.563692] [IGT] core_get_client_auth: executing
>[  425.563832] [IGT] core_get_client_auth: starting subtest simple
>[  425.575363] [IGT] core_get_client_auth: exiting, ret=0
>[  425.618333] Console: switching to colour frame buffer device 240x75
>[  425.728861] Console: switching to colour dummy device 80x25
>[  425.729004] [IGT] core_getstats: executing
>[  425.743293] [IGT] core_getstats: exiting, ret=0
>[  425.785136] Console: switching to colour frame buffer device 240x75
>[  425.895344] Console: switching to colour dummy device 80x25
>[  425.895540] [IGT] core_getversion: executing
>[  425.909279] [IGT] core_getversion: exiting, ret=0
>[  425.951931] Console: switching to colour frame buffer device 240x75
>[  426.062857] Console: switching to colour dummy device 80x25
>[  426.062992] [IGT] core_prop_blob: executing
>[  426.076297] [IGT] core_prop_blob: starting subtest invalid-get-prop
>[  426.076492] [IGT] core_prop_blob: exiting, ret=0
>[  426.118724] Console: switching to colour frame buffer device 240x75
>[  426.229398] Console: switching to colour dummy device 80x25
>[  426.229711] [IGT] core_prop_blob: executing
>[  426.241264] [IGT] core_prop_blob: starting subtest blob-prop-lifetime
>[  426.241761] [IGT] core_prop_blob: exiting, ret=0
>[  426.285541] Console: switching to colour frame buffer device 240x75
>[  426.395867] Console: switching to colour dummy device 80x25
>[  426.396003] [IGT] core_prop_blob: executing
>[  426.407250] [IGT] core_prop_blob: starting subtest invalid-set-prop-any
>[  426.407404] [IGT] core_prop_blob: exiting, ret=0
>[  426.452326] Console: switching to colour frame buffer device 240x75
>[  426.561696] Console: switching to colour dummy device 80x25
>[  426.561827] [IGT] core_prop_blob: executing
>[  426.578253] [IGT] core_prop_blob: starting subtest invalid-set-prop
>[  426.578503] [IGT] core_prop_blob: exiting, ret=0
>[  426.635824] Console: switching to colour frame buffer device 240x75
>[  426.745180] Console: switching to colour dummy device 80x25
>[  426.745288] [IGT] core_prop_blob: executing
>[  426.757230] [IGT] core_prop_blob: starting subtest blob-prop-validate
>[  426.757532] [IGT] core_prop_blob: exiting, ret=0
>[  426.802629] Console: switching to colour frame buffer device 240x75
>[  426.911880] Console: switching to colour dummy device 80x25
>[  426.912057] [IGT] core_prop_blob: executing
>[  426.924219] [IGT] core_prop_blob: starting subtest blob-multiple
>[  426.925071] [IGT] core_prop_blob: exiting, ret=0
>[  426.969442] Console: switching to colour frame buffer device 240x75
>[  427.079271] Console: switching to colour dummy device 80x25
>[  427.079554] [IGT] core_prop_blob: executing
>[  427.093256] [IGT] core_prop_blob: starting subtest blob-prop-core
>[  427.093502] [IGT] core_prop_blob: exiting, ret=0
>[  427.136135] Console: switching to colour frame buffer device 240x75
>[  427.249750] Console: switching to colour dummy device 80x25
>[  427.249886] [IGT] core_prop_blob: executing
>[  427.262218] [IGT] core_prop_blob: starting subtest invalid-get-prop-any
>[  427.262371] [IGT] core_prop_blob: exiting, ret=0
>[  427.303004] Console: switching to colour frame buffer device 240x75
>[  427.413409] Console: switching to colour dummy device 80x25
>[  427.413595] [IGT] core_setmaster_vs_auth: executing
>[  427.439030] [IGT] core_setmaster_vs_auth: exiting, ret=0
>[  427.469816] Console: switching to colour frame buffer device 240x75
>[  427.582024] Console: switching to colour dummy device 80x25
>[  427.582194] [IGT] drm_read: executing
>[  427.594291] [IGT] drm_read: starting subtest empty-nonblock
>[  427.594502] [IGT] drm_read: exiting, ret=0
>[  427.619916] Console: switching to colour frame buffer device 240x75
>[  427.723634] Console: switching to colour dummy device 80x25
>[  427.723743] [IGT] drm_read: executing
>[  427.736170] [IGT] drm_read: starting subtest short-buffer-block
>[  427.736337] [IGT] drm_read: exiting, ret=0
>[  427.770045] Console: switching to colour frame buffer device 240x75
>[  427.873738] Console: switching to colour dummy device 80x25
>[  427.873856] [IGT] drm_read: executing
>[  427.883213] [IGT] drm_read: starting subtest empty-block
>[  428.883434] [IGT] drm_read: exiting, ret=0
>[  428.904273] Console: switching to colour frame buffer device 240x75
>[  429.009828] Console: switching to colour dummy device 80x25
>[  429.009960] [IGT] drm_read: executing
>[  429.025165] [IGT] drm_read: starting subtest invalid-buffer
>[  429.025278] [IGT] drm_read: exiting, ret=0
>[  429.054442] Console: switching to colour frame buffer device 240x75
>[  429.159537] Console: switching to colour dummy device 80x25
>[  429.159710] [IGT] drm_read: executing
>[  429.174167] [IGT] drm_read: starting subtest short-buffer-nonblock
>[  429.174414] [IGT] drm_read: exiting, ret=0
>[  429.204580] Console: switching to colour frame buffer device 240x75
>[  429.308136] Console: switching to colour dummy device 80x25
>[  429.308285] [IGT] drm_read: executing
>[  429.320128] [IGT] drm_read: starting subtest fault-buffer
>[  429.320772] [IGT] drm_read: exiting, ret=0
>[  429.354630] Console: switching to colour frame buffer device 240x75
>[  429.462470] Console: switching to colour dummy device 80x25
>[  429.462645] [IGT] kms_render: executing
>[  429.478182] [IGT] kms_render: starting subtest direct-render
>[  429.478766] [drm:drm_mode_addfb2] [FB:78]
>[  429.478813] [drm:drm_mode_addfb2] [FB:79]
>[  429.478834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  429.478852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  436.750747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  436.760314] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  436.760388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  436.760502] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  436.779156] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  436.779312] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  436.779357] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  436.779404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  436.779437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  436.779473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  436.779504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  436.779533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  436.779564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  436.779600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  436.779632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  436.779664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  436.779695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  436.779723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  436.779750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  436.779823] [drm:intel_power_well_disable [i915]] disabling display
>[  436.779908] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  436.779955] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  436.780003] [drm:intel_power_well_disable [i915]] disabling always-on
>[  436.780311] [drm:drm_mode_addfb2] [FB:77]
>[  436.780366] [drm:drm_mode_addfb2] [FB:78]
>[  436.780402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  436.780416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  436.780476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  436.780502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  436.780529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  436.780558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  436.780583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  436.780610] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  436.780636] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  436.780663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  436.780688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  436.780714] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  436.780739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  436.780745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  436.780769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  436.780774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  436.780800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  436.780826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  436.780853] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  436.780878] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  436.780905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  436.780930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  436.780957] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  436.780983] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  436.781015] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  436.781095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  436.781131] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  436.790524] [drm:intel_power_well_enable [i915]] enabling always-on
>[  436.790566] [drm:intel_power_well_enable [i915]] enabling display
>[  436.790588] [drm:hsw_set_power_well [i915]] Enabling power well
>[  436.790646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  436.790669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  436.790690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  436.790709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  436.790728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  436.790749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  436.790776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  436.790802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  436.790828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  436.790853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  436.790877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  436.790914] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  436.790950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  436.793103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  436.793126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  436.793146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  436.793167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  436.796981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  436.797027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  436.797148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  436.799819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  436.799855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  436.802813] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  436.806185] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  436.806249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  436.806282] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  436.806349] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  436.806510] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  436.806567] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  436.823078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  436.823128] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  436.823194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  443.868694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  443.878646] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  443.878695] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  443.878856] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  443.897751] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  443.897827] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  443.897867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  443.897912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  443.897953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  443.897997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  443.898037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  443.898077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  443.898114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  443.898158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  443.898201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  443.898243] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  443.898285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  443.898323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  443.898362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  443.898420] [drm:intel_power_well_disable [i915]] disabling display
>[  443.898467] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  443.898514] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  443.898535] [drm:intel_power_well_disable [i915]] disabling always-on
>[  443.898696] [drm:drm_mode_addfb2] [FB:77]
>[  443.898795] [drm:drm_mode_addfb2] [FB:78]
>[  443.898834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  443.898855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  443.898950] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  443.898985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  443.899020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  443.899058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  443.899088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  443.899121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  443.899152] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  443.899182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  443.899210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  443.899241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  443.899267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  443.899275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  443.899302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  443.899308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  443.899337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  443.899364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  443.899391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  443.899417] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  443.899448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  443.899473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  443.899501] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  443.899527] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  443.899555] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  443.899584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  443.899617] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  443.909236] [drm:intel_power_well_enable [i915]] enabling always-on
>[  443.909260] [drm:intel_power_well_enable [i915]] enabling display
>[  443.909280] [drm:hsw_set_power_well [i915]] Enabling power well
>[  443.909320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  443.909347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  443.909374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  443.909401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  443.909428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  443.909454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  443.909483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  443.909512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  443.909539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  443.909565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  443.909591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  443.909620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  443.909646] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  443.911683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  443.911706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  443.911771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  443.911801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  443.913348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  443.913369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  443.913389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  443.914933] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  443.914954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  443.916816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  443.920503] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  443.920550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  443.920584] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  443.920628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  443.920700] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  443.920786] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  443.937338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  443.937388] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  443.937453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  451.426917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.443273] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  451.443322] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  451.443398] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  451.460407] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  451.460483] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  451.460517] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  451.460556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  451.460589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  451.460624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  451.460653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  451.460682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  451.460714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  451.460749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  451.460782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  451.460822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  451.460864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  451.460903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  451.460942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  451.461002] [drm:intel_power_well_disable [i915]] disabling display
>[  451.461049] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  451.461100] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  451.461139] [drm:intel_power_well_disable [i915]] disabling always-on
>[  451.461379] [drm:drm_mode_addfb2] [FB:77]
>[  451.461496] [drm:drm_mode_addfb2] [FB:78]
>[  451.461551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  451.461569] [drm:drm_mode_setcrtc] Invalid pixel format AR24 little-endian (0x34325241)
>[  451.461853] [drm:drm_mode_addfb2] [FB:77]
>[  451.461918] [drm:drm_mode_addfb2] [FB:79]
>[  451.461968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  451.461991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  451.462112] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  451.462153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  451.462198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  451.462247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  451.462293] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  451.462329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  451.462362] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  451.462395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  451.462455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  451.462488] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  451.462518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  451.462528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  451.462558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  451.462567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  451.462600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  451.462629] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  451.462661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  451.462691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  451.462725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  451.462754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  451.462786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  451.462814] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  451.462846] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  451.462878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.462915] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  451.467813] [drm:intel_power_well_enable [i915]] enabling always-on
>[  451.467835] [drm:intel_power_well_enable [i915]] enabling display
>[  451.467855] [drm:hsw_set_power_well [i915]] Enabling power well
>[  451.467901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  451.467923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  451.467944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  451.467963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  451.467982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  451.468003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  451.468029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  451.468055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  451.468081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  451.468105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  451.468129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  451.468155] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  451.468180] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  451.470272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  451.470297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  451.470318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  451.470341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  451.474097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  451.474121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  451.474150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  451.476808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  451.476840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  451.479846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  451.483219] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  451.483283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  451.483315] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  451.483357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  451.500062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  451.500113] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  451.500179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  458.733231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.733322] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  458.733368] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  458.733461] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  458.739830] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  458.739905] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  458.739985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  458.740053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  458.740143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  458.740358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  458.740446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  458.740541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  458.740650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  458.740698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  458.740751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  458.740804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  458.740851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  458.740898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  458.740967] [drm:intel_power_well_disable [i915]] disabling display
>[  458.741008] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  458.741050] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  458.741082] [drm:intel_power_well_disable [i915]] disabling always-on
>[  458.741400] [drm:drm_mode_addfb2] [FB:77]
>[  458.741459] [drm:drm_mode_addfb2] [FB:79]
>[  458.741481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  458.741500] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  458.741588] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  458.741622] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  458.741658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  458.741704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  458.741722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  458.741742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  458.741761] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  458.741781] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  458.741799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  458.741816] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  458.741832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  458.741837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  458.741853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  458.741856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  458.741873] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  458.741889] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  458.741905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.741921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  458.741940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  458.741956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  458.741972] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  458.741988] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  458.742004] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  458.742024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.742045] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  458.752253] [drm:intel_power_well_enable [i915]] enabling always-on
>[  458.752276] [drm:intel_power_well_enable [i915]] enabling display
>[  458.752303] [drm:hsw_set_power_well [i915]] Enabling power well
>[  458.752342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  458.752364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  458.752385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  458.752404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  458.752423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  458.752443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  458.752465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  458.752485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  458.752505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  458.752522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  458.752540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  458.752565] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  458.752590] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  458.754682] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  458.754704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  458.754724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  458.754744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  458.758590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  458.758628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  458.758661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  458.761419] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  458.761452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  458.764407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  458.767720] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  458.767791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  458.767823] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  458.767865] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  458.784574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  458.784624] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  458.784690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  465.837443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.837534] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  465.837580] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  465.837657] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  465.841382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  465.841420] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  465.841460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  465.841494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  465.841528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  465.841557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  465.841585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  465.841616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  465.841651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  465.841683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  465.841715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  465.841755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  465.841781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  465.841817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  465.841948] [drm:intel_power_well_disable [i915]] disabling display
>[  465.842014] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  465.842077] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  465.842128] [drm:intel_power_well_disable [i915]] disabling always-on
>[  465.842333] [drm:drm_mode_addfb2] [FB:77]
>[  465.842379] [drm:drm_mode_addfb2] [FB:79]
>[  465.842412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  465.842429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  465.842510] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  465.842543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  465.842577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  465.842619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  465.842656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  465.842696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.842734] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  465.842782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  465.842819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  465.842898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  465.842935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.842944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  465.842977] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.842986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  465.843020] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  465.843056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  465.843092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.843126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.843165] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  465.843201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.843237] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  465.843272] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  465.843307] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  465.843338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.843368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  465.855749] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.855771] [drm:intel_power_well_enable [i915]] enabling display
>[  465.855790] [drm:hsw_set_power_well [i915]] Enabling power well
>[  465.855896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  465.855927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  465.855958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  465.855986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  465.856015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  465.856044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  465.856076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  465.856108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  465.856140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  465.856166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  465.856194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  465.856228] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  465.856256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  465.858324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  465.858346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  465.858365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.858384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  465.859977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  465.859998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  465.860020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.861571] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  465.861592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  465.863456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  465.866184] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  465.866279] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  465.866308] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  465.866349] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  465.883068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  465.883119] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  465.883185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  473.368755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.368928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  473.369014] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  473.369156] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  473.373266] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  473.373342] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  473.373422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.373489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  473.373725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  473.373824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  473.373923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  473.374024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  473.374128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  473.374199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  473.374265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  473.374331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  473.374387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  473.374446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  473.374668] [drm:intel_power_well_disable [i915]] disabling display
>[  473.374807] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  473.374940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  473.375045] [drm:intel_power_well_disable [i915]] disabling always-on
>[  473.375613] [drm:drm_mode_addfb2] [FB:77]
>[  473.375767] [drm:drm_mode_addfb2] [FB:79]
>[  473.375835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  473.375861] [drm:drm_mode_setcrtc] Invalid pixel format AR24 little-endian (0x34325241)
>[  473.376220] [drm:drm_mode_addfb2] [FB:77]
>[  473.376302] [drm:drm_mode_addfb2] [FB:80]
>[  473.376362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  473.376392] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  473.376712] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  473.376811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  473.376918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  473.377036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  473.377125] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  473.377233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  473.377334] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  473.377401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  473.377463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  473.377546] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  473.377695] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  473.377720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  473.377803] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  473.377824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  473.377916] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  473.378002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  473.378091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  473.378151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  473.378217] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  473.378273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  473.378328] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  473.378395] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  473.378450] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  473.378535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.378788] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  473.384883] [drm:intel_power_well_enable [i915]] enabling always-on
>[  473.384901] [drm:intel_power_well_enable [i915]] enabling display
>[  473.384918] [drm:hsw_set_power_well [i915]] Enabling power well
>[  473.384953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  473.384974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  473.384997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  473.385021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  473.385044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  473.385067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  473.385093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  473.385118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  473.385143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  473.385166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  473.385189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  473.385214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  473.385237] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  473.387299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  473.387330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  473.387358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.387388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  473.388985] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  473.389015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  473.389043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.390708] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  473.390733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  473.392594] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  473.395775] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  473.395808] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  473.395827] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  473.395853] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  473.412614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  473.412667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  473.412739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  480.691608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  480.691788] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  480.691891] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  480.692048] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  480.703778] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  480.703815] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  480.703855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  480.703889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  480.703924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  480.703954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  480.703984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  480.704015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  480.704051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  480.704083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  480.704114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  480.704145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  480.704173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  480.704260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  480.704354] [drm:intel_power_well_disable [i915]] disabling display
>[  480.704425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  480.704492] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  480.704545] [drm:intel_power_well_disable [i915]] disabling always-on
>[  480.704762] [drm:drm_mode_addfb2] [FB:77]
>[  480.704792] [drm:drm_mode_addfb2] [FB:80]
>[  480.704816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  480.704827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  480.704883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  480.704905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  480.704929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  480.704954] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  480.704974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  480.704996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  480.705018] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  480.705039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  480.705059] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  480.705078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  480.705096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  480.705101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  480.705119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  480.705124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  480.705142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  480.705159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  480.705177] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  480.705227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  480.705257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  480.705284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  480.705311] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  480.705338] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  480.705364] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  480.705396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  480.705428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  480.715506] [drm:intel_power_well_enable [i915]] enabling always-on
>[  480.715528] [drm:intel_power_well_enable [i915]] enabling display
>[  480.715546] [drm:hsw_set_power_well [i915]] Enabling power well
>[  480.715584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  480.715607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  480.715627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  480.715647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  480.715665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  480.715685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  480.715706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  480.715727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  480.715747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  480.715765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  480.715782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  480.715805] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  480.715825] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  480.717932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  480.717957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  480.717979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  480.718014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  480.719598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  480.719619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  480.719637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  480.721181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  480.721227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  480.723073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  480.726331] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  480.726392] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  480.726417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  480.726451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  480.743190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  480.743277] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  480.743346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  487.796341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  487.796519] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  487.796609] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  487.796756] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  487.800641] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  487.800716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  487.800795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  487.800861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  487.800931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  487.801126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  487.801225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  487.801332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  487.801448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  487.801553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  487.801659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  487.801760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  487.801849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  487.801942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  487.802183] [drm:intel_power_well_disable [i915]] disabling display
>[  487.802315] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  487.802441] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  487.802541] [drm:intel_power_well_disable [i915]] disabling always-on
>[  487.803125] [drm:drm_mode_addfb2] [FB:77]
>[  487.803230] [drm:drm_mode_addfb2] [FB:80]
>[  487.803307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  487.803341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  487.803531] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  487.803603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  487.803682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  487.803772] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  487.803849] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  487.803930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  487.804170] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  487.804265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  487.804359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  487.804446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  487.804541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  487.804565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  487.804647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  487.804670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  487.804756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  487.804846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  487.804937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  487.805120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  487.805221] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  487.805312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  487.805403] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  487.805486] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  487.805574] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  487.805679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  487.805788] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  487.816594] [drm:intel_power_well_enable [i915]] enabling always-on
>[  487.816624] [drm:intel_power_well_enable [i915]] enabling display
>[  487.816652] [drm:hsw_set_power_well [i915]] Enabling power well
>[  487.816693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  487.816714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  487.816732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  487.816750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  487.816767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  487.816786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  487.816806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  487.816825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  487.816843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  487.816866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  487.816899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  487.816964] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  487.816999] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  487.819084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  487.819115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  487.819143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  487.819171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  487.820761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  487.820785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  487.820806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  487.822347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  487.822370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  487.824224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  487.827569] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  487.827659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  487.827691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  487.827741] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  487.844438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  487.844489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  487.844556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  495.333274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  495.333430] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  495.333512] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  495.333843] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  495.352241] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  495.352279] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  495.352320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  495.352353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  495.352388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  495.352418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  495.352447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  495.352479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  495.352514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  495.352555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  495.352597] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  495.352705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  495.352752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  495.352801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  495.352885] [drm:intel_power_well_disable [i915]] disabling display
>[  495.352950] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  495.353014] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  495.353063] [drm:intel_power_well_disable [i915]] disabling always-on
>[  495.353360] [drm:drm_mode_addfb2] [FB:77]
>[  495.353438] [drm:drm_mode_addfb2] [FB:80]
>[  495.353480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  495.353492] [drm:drm_mode_setcrtc] Invalid pixel format AR24 little-endian (0x34325241)
>[  495.353886] [IGT] kms_render: exiting, ret=0
>[  495.364087] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  495.364132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  495.364176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  495.364224] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  495.364265] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  495.364307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  495.364349] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  495.364390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  495.364432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  495.364473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  495.364513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  495.364521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  495.364562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  495.364569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  495.364683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  495.364732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  495.364778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  495.364822] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  495.364871] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  495.364915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  495.364960] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  495.365005] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  495.365049] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  495.365098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  495.365155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  495.365333] [drm:intel_power_well_enable [i915]] enabling always-on
>[  495.365379] [drm:intel_power_well_enable [i915]] enabling display
>[  495.365414] [drm:hsw_set_power_well [i915]] Enabling power well
>[  495.365515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  495.365548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  495.365589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  495.365694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  495.365739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  495.365769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  495.365804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  495.365833] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  495.365853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  495.365872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  495.365890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  495.365922] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  495.365951] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  495.368283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  495.368306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  495.368327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  495.368347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  495.369889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  495.369911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  495.369931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  495.371462] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  495.371485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  495.373347] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  495.375954] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  495.376017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  495.376045] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  495.376101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  495.376251] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  495.376305] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  495.392832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  495.392886] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  495.392959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  495.409707] Console: switching to colour frame buffer device 240x75
>[  495.521970] Console: switching to colour dummy device 80x25
>[  495.522080] [IGT] kms_setmode: executing
>[  495.533461] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
>[  495.533798] [IGT] kms_setmode: exiting, ret=0
>[  495.576454] Console: switching to colour frame buffer device 240x75
>[  495.711339] [drm:drm_mode_addfb2] [FB:77]
>[  495.791329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  495.791345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  500.809925] [drm:drm_mode_addfb2] [FB:78]
>[  500.862203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  500.862217] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  500.862287] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  500.862308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  500.862331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  500.862352] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  500.862427] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  500.862463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  500.862499] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  500.862531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  500.862564] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  500.862596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  500.862626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  500.862634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  500.862664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  500.862672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  500.862702] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  500.862733] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  500.862762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  500.862791] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  500.862821] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  500.862850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  500.862881] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  500.862910] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  500.862936] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  500.862968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  500.863004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  500.880489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  500.880554] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  500.880686] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  500.897721] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  500.897780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  500.897820] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  500.897865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  500.897906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  500.897946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  500.897985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  500.898025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  500.898064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  500.898107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  500.898148] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  500.898190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  500.898229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  500.898268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  500.898309] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  500.898348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  500.900517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  500.900538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  500.900557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  500.900577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  500.902149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  500.902169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  500.902187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  500.903752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  500.903773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  500.905647] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  500.908897] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  500.908930] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  500.908950] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  500.908975] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  500.909036] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  500.909075] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  500.925763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  500.925825] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  500.925889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  505.926095] [drm:drm_mode_addfb2] [FB:77]
>[  505.979164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  505.979180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  505.979249] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  505.979273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  505.979297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148352KHz
>[  505.979318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  505.979337] [drm:intel_dp_compute_config [i915]] DP link bw required 445056 available 648000
>[  505.979357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.979378] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  505.979398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  505.979417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5761420, gmch_n: 8388608, link_m: 240059, link_n: 262144, tu: 64
>[  505.979434] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  505.979451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  505.979456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  505.979473] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  505.979477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  505.979494] [drm:intel_dump_pipe_config [i915]] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  505.979511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148352
>[  505.979527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.979543] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  505.979563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  505.979580] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  505.979598] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  505.979614] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  505.979630] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  505.979650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  505.979672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  505.992216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  505.992269] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  505.992360] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  506.009360] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  506.009404] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  506.009437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  506.009476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  506.009509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  506.009541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  506.009571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  506.009600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  506.009631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  506.009673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  506.009715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  506.009756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  506.009796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  506.009835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  506.009876] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  506.009915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  506.012014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  506.012036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  506.012058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  506.012083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  506.013686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  506.013707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  506.013725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  506.015284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  506.015305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  506.017194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  506.020531] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  506.020576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  506.020596] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  506.020622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  506.020681] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  506.020702] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  506.037415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  506.037473] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  506.037537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  511.037626] [drm:drm_mode_addfb2] [FB:78]
>[  511.089376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  511.089392] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  511.089462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  511.089488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  511.089513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  511.089538] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  511.089561] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  511.089585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.089609] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  511.089632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  511.089656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  511.089679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  511.089702] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  511.089707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  511.089730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  511.089734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  511.089758] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  511.089781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  511.089804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.089827] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  511.089851] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  511.089874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  511.089899] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  511.089922] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  511.090004] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  511.090042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  511.090081] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  511.108923] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  511.109005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  511.109077] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  511.126072] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  511.126116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  511.126148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  511.126188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  511.126222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  511.126253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  511.126284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  511.126313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  511.126345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  511.126379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  511.126411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  511.126442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  511.126470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  511.126498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  511.126532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  511.126563] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  511.128654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  511.128675] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  511.128693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  511.128712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  511.130268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  511.130288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  511.130306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  511.131837] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  511.131857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  511.133712] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  511.137011] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  511.137042] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  511.137061] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  511.137087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  511.137148] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  511.137174] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  511.153887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  511.153946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  511.154104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  516.154304] [drm:drm_mode_addfb2] [FB:77]
>[  516.213460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  516.213474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  516.213544] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  516.213566] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  516.213589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  516.213610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  516.213628] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  516.213648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  516.213668] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  516.213687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  516.213705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  516.213722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  516.213796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  516.213806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  516.213833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  516.213841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  516.213868] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  516.213895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  516.213922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  516.213949] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  516.213980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  516.214007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  516.214036] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  516.214065] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  516.214093] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  516.214125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  516.214160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  516.220357] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  516.220406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  516.220496] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  516.237547] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  516.237591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  516.237624] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  516.237663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  516.237696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  516.237726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  516.237848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  516.237893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  516.237940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  516.237995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  516.238031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  516.238064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  516.238092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  516.238122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  516.238156] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  516.238189] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  516.240312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  516.240332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  516.240351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  516.240370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  516.241923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  516.241942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  516.241965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  516.243512] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  516.243533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  516.245394] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  516.248680] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  516.248730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  516.248839] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  516.248904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  516.248982] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  516.249015] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  516.265591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  516.265655] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  516.265726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  521.266054] [drm:drm_mode_addfb2] [FB:78]
>[  521.319336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  521.319351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  521.319420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  521.319443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  521.319466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  521.319489] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  521.319507] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  521.319583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  521.319614] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  521.319644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  521.319673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  521.319700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  521.319728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  521.319736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  521.319765] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  521.319774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  521.319801] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  521.319827] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  521.319854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  521.319880] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  521.319914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  521.319944] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  521.319974] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  521.320004] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  521.320032] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  521.320065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  521.320101] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  521.337121] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  521.337171] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  521.337246] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  521.354270] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  521.354314] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  521.354347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  521.354386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  521.354426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  521.354466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  521.354506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  521.354637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  521.354691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  521.354748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  521.354801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  521.354853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  521.354900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  521.354946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  521.355000] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  521.355049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  521.357148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  521.357171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  521.357189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  521.357208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  521.358778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  521.358798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  521.358816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  521.360378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  521.360399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  521.362265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  521.365575] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  521.365619] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  521.365646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  521.365682] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  521.365746] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  521.365774] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  521.385757] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  521.385819] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  521.385884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  526.386086] [drm:drm_mode_addfb2] [FB:77]
>[  526.445379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  526.445394] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  526.445465] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  526.445488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  526.445511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  526.445533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  526.445552] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  526.445572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  526.445593] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  526.445612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  526.445631] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  526.445649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  526.445665] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  526.445670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  526.445687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  526.445691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  526.445708] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  526.445725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  526.445741] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  526.445757] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  526.445778] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  526.445794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  526.445812] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  526.445828] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  526.445851] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  526.445877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  526.445903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  526.465545] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  526.465593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  526.465665] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  526.486849] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  526.486894] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  526.486926] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  526.486965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  526.486998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  526.487029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  526.487059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  526.487088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  526.487120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  526.487168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  526.487200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  526.487232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  526.487260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  526.487288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  526.487397] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  526.487443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  526.489534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  526.489555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  526.489574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  526.489597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  526.491139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  526.491159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  526.491176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  526.492711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  526.492731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  526.494574] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  526.497902] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  526.497955] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  526.497987] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  526.498029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  526.498106] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  526.498133] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  526.518079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  526.518138] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  526.518201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  531.518476] [drm:drm_mode_addfb2] [FB:78]
>[  531.577474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  531.577489] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  531.577557] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  531.577580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  531.577603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  531.577626] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  531.577644] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  531.577665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  531.577685] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  531.577704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  531.577722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  531.577739] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  531.577756] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  531.577762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  531.577779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  531.577783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  531.577799] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  531.577816] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  531.577838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  531.577862] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  531.577886] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  531.577909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  531.577933] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  531.577957] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  531.577980] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  531.578005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  531.578031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  531.597881] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  531.597930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  531.598002] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  531.619179] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  531.619223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  531.619255] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  531.619300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  531.619341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  531.619381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  531.619421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  531.619460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  531.619500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  531.619542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  531.619584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  531.619626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  531.619664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  531.619703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  531.619744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  531.619783] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  531.621885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  531.621907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  531.621926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  531.621945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  531.623494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  531.623515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  531.623533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  531.625091] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  531.625129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  531.626973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  531.630313] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  531.630366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  531.630399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  531.630441] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  531.630523] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  531.630544] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  531.663842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  531.663902] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  531.663968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  536.664167] [drm:drm_mode_addfb2] [FB:77]
>[  536.723463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  536.723478] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  536.723547] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  536.723569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  536.723591] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  536.723614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  536.723636] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  536.723661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  536.723685] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  536.723708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  536.723732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  536.723755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  536.723777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  536.723782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  536.723805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  536.723808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  536.723832] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  536.723856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  536.723879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  536.723954] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  536.723989] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  536.724019] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  536.724048] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  536.724077] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  536.724106] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  536.724138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  536.724172] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  536.730320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  536.730369] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  536.730459] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  536.766076] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  536.766120] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  536.766152] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  536.766190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  536.766223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  536.766254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  536.766283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  536.766311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  536.766343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  536.766376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  536.766408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  536.766439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  536.766467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  536.766494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  536.766528] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  536.766559] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  536.768619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  536.768640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  536.768658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  536.768677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  536.770229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  536.770252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  536.770275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  536.771813] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  536.771835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  536.773687] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  536.777013] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  536.777045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  536.777065] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  536.777091] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  536.777151] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  536.777182] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  536.810553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  536.810614] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  536.810679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  541.810881] [drm:drm_mode_addfb2] [FB:78]
>[  541.871231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  541.871246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  541.871314] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  541.871340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  541.871365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  541.871391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  541.871414] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  541.871438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  541.871463] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  541.871486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  541.871510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  541.871534] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  541.871557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  541.871562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  541.871585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  541.871589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  541.871613] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  541.871636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  541.871660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  541.871735] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  541.871769] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  541.871801] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  541.871832] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  541.871860] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  541.871888] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  541.871921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  541.871955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  541.882069] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  541.882114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  541.882184] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  541.917753] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  541.917797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  541.917829] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  541.917869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  541.917901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  541.917933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  541.917963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  541.917992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  541.918023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  541.918057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  541.918089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  541.918120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  541.918148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  541.918175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  541.918209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  541.918240] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  541.920320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  541.920345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  541.920368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  541.920392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  541.921957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  541.921978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  541.922000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  541.923535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  541.923557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  541.925406] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  541.928754] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  541.928810] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  541.928850] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  541.928895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  541.928956] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  541.928986] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  541.968955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  541.969016] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  541.969082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  546.969168] [drm:drm_mode_addfb2] [FB:77]
>[  547.028012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  547.028028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  547.028095] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  547.028118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  547.028142] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  547.028165] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  547.028184] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  547.028205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  547.028226] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  547.028246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  547.028264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  547.028282] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  547.028298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  547.028303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  547.028320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  547.028323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  547.028340] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  547.028357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  547.028373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  547.028389] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  547.028409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  547.028426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  547.028444] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  547.028515] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  547.028542] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  547.028574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  547.028607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  547.048742] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  547.048791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  547.048862] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  547.090629] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  547.090672] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  547.090705] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  547.090744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  547.090777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  547.090808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  547.090839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  547.090868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  547.090899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  547.090934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  547.090965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  547.090997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  547.091035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  547.091073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  547.091115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  547.091154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  547.093238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  547.093262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  547.093285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  547.093309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  547.094871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  547.094893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  547.094911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  547.096451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  547.096492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  547.098337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  547.101678] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  547.101726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  547.101746] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  547.101772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  547.101831] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  547.101852] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  547.143540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  547.143600] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  547.143666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  552.143867] [drm:drm_mode_addfb2] [FB:78]
>[  552.202960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  552.202975] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  552.203048] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  552.203072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  552.203097] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  552.203123] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  552.203145] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  552.203170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  552.203194] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  552.203218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  552.203241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  552.203316] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  552.203348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  552.203356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  552.203386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  552.203393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  552.203423] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  552.203456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  552.203485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  552.203516] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  552.203546] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  552.203573] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  552.203605] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  552.203632] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  552.203659] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  552.203689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  552.203725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  552.226675] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  552.226729] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  552.226804] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  552.270656] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  552.270701] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  552.270734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  552.270773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  552.270806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  552.270837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  552.270867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  552.270896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  552.270927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  552.270960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  552.270992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  552.271023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  552.271051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  552.271078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  552.271118] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  552.271158] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  552.273244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  552.273285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  552.273307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  552.273332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  552.274893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  552.274914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  552.274933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  552.276480] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  552.276501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  552.278348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  552.281690] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  552.281743] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  552.281775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  552.281818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  552.281893] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  552.281926] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  552.323600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  552.323661] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  552.323733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  557.323936] [drm:drm_mode_addfb2] [FB:77]
>[  557.376095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  557.376110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  557.376180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  557.376202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  557.376227] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 162000KHz
>[  557.376254] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  557.376277] [drm:intel_dp_compute_config [i915]] DP link bw required 486000 available 648000
>[  557.376302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  557.376325] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  557.376349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  557.376372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6291456, gmch_n: 8388608, link_m: 262144, link_n: 262144, tu: 64
>[  557.376396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  557.376418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  557.376423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  557.376446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  557.376450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  557.376473] [drm:intel_dump_pipe_config [i915]] crtc timings: 162000 1600 1664 1856 2160 1200 1201 1204 1250, type: 0x40 flags: 0x5
>[  557.376496] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1600x1200, pixel rate 162000
>[  557.376519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  557.376542] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  557.376566] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  557.376589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  557.376614] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  557.376637] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  557.376660] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  557.376685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  557.376712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  557.411836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  557.411896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  557.411983] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  557.455203] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  557.455247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  557.455280] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  557.455320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  557.455353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  557.455385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  557.455416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  557.455445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  557.455477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  557.455511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  557.455543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  557.455575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  557.455604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  557.455633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  557.455666] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  557.455705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  557.457770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  557.457797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  557.457823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  557.457855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  557.459442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  557.459464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  557.459483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  557.461034] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  557.461083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  557.462955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  557.466260] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  557.466305] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  557.466338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  557.466381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  557.466450] [drm:intel_fbc_enable [i915]] reserved 15360000 bytes of contiguous stolen space for FBC, threshold: 1
>[  557.466483] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  557.483108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  557.483170] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  557.483242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  562.483442] [drm:drm_mode_addfb2] [FB:78]
>[  562.538817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  562.538833] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  562.538902] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  562.538924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  562.538946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 135000KHz
>[  562.538970] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  562.538988] [drm:intel_dp_compute_config [i915]] DP link bw required 405000 available 648000
>[  562.539009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  562.539029] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  562.539048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  562.539066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5242880, gmch_n: 8388608, link_m: 218453, link_n: 262144, tu: 64
>[  562.539084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  562.539100] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  562.539105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  562.539121] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  562.539125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  562.539141] [drm:intel_dump_pipe_config [i915]] crtc timings: 135000 1280 1296 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  562.539158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 135000
>[  562.539174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  562.539190] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  562.539210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  562.539232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  562.539256] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1600x1200 format = XR24 little-endian (0x34325258)
>[  562.539280] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  562.539303] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  562.539328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  562.539354] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  562.549557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  562.549604] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  562.549676] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  562.566699] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  562.566743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  562.566776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  562.566814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  562.566945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  562.566998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  562.567049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  562.567098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  562.567149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  562.567203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  562.567254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  562.567304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  562.567349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  562.567402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  562.567434] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  562.567465] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  562.569532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  562.569553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  562.569571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  562.569590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  562.571155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  562.571176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  562.571194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  562.572753] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  562.572774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  562.574685] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  562.578021] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  562.578074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  562.578107] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  562.578149] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  562.578224] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1
>[  562.578257] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  562.591556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  562.591616] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  562.591681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  567.591769] [drm:drm_mode_addfb2] [FB:77]
>[  567.647484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  567.647500] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  567.647569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  567.647591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  567.647675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz
>[  567.647712] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  567.647742] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000
>[  567.647772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  567.647805] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  567.647833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  567.647854] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  567.647872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  567.647891] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  567.647896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  567.647914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  567.647918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  567.647937] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  567.647956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 108000
>[  567.647973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  567.647992] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  567.648014] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  567.648033] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  567.648052] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1280x1024 format = XR24 little-endian (0x34325258)
>[  567.648072] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  567.648089] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  567.648112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  567.648136] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  567.656340] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  567.656391] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  567.656497] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  567.671443] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  567.671488] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  567.671520] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  567.671564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  567.671604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  567.671726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  567.671779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  567.671830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  567.671882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  567.671930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  567.671965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  567.671998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  567.672027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  567.672055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  567.672092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  567.672124] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  567.674250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  567.674272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  567.674290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  567.674310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  567.675864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  567.675885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  567.675902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  567.677439] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  567.677460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  567.679314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  567.682665] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  567.682718] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  567.682751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  567.682792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  567.682873] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1
>[  567.682908] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  567.699526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  567.699586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  567.699755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  572.699884] [drm:drm_mode_addfb2] [FB:78]
>[  572.753514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  572.753529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  572.753599] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  572.753624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  572.753649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz
>[  572.753673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  572.753696] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000
>[  572.753720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  572.753744] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  572.753768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  572.753791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  572.753815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  572.753837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  572.753842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  572.753865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  572.753869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  572.753893] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1152 1216 1344 1600 864 865 868 900, type: 0x40 flags: 0x5
>[  572.753916] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1152x864, pixel rate 108000
>[  572.753939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  572.753962] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  572.753986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  572.754009] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  572.754033] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1280x1024 format = XR24 little-endian (0x34325258)
>[  572.754057] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  572.754080] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  572.754105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  572.754131] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  572.764316] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  572.764366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  572.764765] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  572.783344] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  572.783387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  572.783509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  572.783569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  572.783620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  572.783670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  572.783704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  572.783734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  572.783766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  572.783802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  572.783834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  572.783867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  572.783897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  572.783916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  572.783938] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  572.783960] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  572.786007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  572.786030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  572.786049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  572.786068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  572.787635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  572.787655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  572.787673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  572.789220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  572.789240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  572.791091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  572.794385] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  572.794458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  572.794487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  572.794525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  572.794593] [drm:intel_fbc_enable [i915]] reserved 7962624 bytes of contiguous stolen space for FBC, threshold: 1
>[  572.794623] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  572.807923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  572.807986] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  572.808057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  577.808147] [drm:drm_mode_addfb2] [FB:77]
>[  577.861808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  577.861824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  577.861893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  577.861919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  577.861946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  577.861971] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  577.861994] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  577.862018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  577.862043] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  577.862067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  577.862091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  577.862115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  577.862138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  577.862143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  577.862166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  577.862218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  577.862252] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  577.862284] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250
>[  577.862312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  577.862340] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  577.862373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  577.862401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  577.862431] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1152x864 format = XR24 little-endian (0x34325258)
>[  577.862458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  577.862484] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  577.862516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  577.862551] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  577.874381] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  577.874431] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  577.874504] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  577.889473] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  577.889518] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  577.889551] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  577.889590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  577.889623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  577.889655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  577.889684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  577.889712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  577.889743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  577.889777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  577.889809] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  577.889849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  577.889889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  577.889928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  577.889969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  577.890008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  577.892069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  577.892090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  577.892109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  577.892128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  577.893700] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  577.893720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  577.893738] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  577.895326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  577.895349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  577.897229] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  577.900526] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  577.900559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  577.900578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  577.900604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  577.900661] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  577.900690] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  577.917396] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  577.917457] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  577.917523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  582.917721] [drm:drm_mode_addfb2] [FB:78]
>[  582.971352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  582.971366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  582.971434] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  582.971456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  582.971478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  582.971502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  582.971525] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  582.971550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  582.971573] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  582.971597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  582.971621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  582.971644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  582.971667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  582.971671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  582.971694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  582.971698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  582.971722] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  582.971746] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74176
>[  582.971769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  582.971792] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  582.971816] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  582.971839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  582.971863] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  582.971886] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  582.971909] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  582.971934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  582.971960] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  582.983848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  582.983898] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  582.983969] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  583.001045] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  583.001089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  583.001121] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  583.001160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  583.001193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  583.001224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  583.001253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  583.001282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  583.001313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  583.001355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  583.001397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  583.001439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  583.001478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  583.001524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  583.001558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  583.001591] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  583.003668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  583.003693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  583.003716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  583.003740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  583.005306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  583.005327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  583.005345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  583.006889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  583.006910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  583.008770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  583.012099] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  583.012149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  583.012180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  583.012221] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  583.012293] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  583.012324] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  583.028953] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  583.029048] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  583.029114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  588.029314] [drm:drm_mode_addfb2] [FB:77]
>[  588.075893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  588.075908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  588.075975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  588.075998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  588.076020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  588.076046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  588.076069] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  588.076095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  588.076119] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  588.076143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  588.076166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  588.076189] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  588.076213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  588.076218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  588.076241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  588.076245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  588.076269] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1720 1760 1980 720 725 730 750, type: 0x40 flags: 0x5
>[  588.076292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250
>[  588.076315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  588.076338] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  588.076362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  588.076385] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  588.076409] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  588.076433] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  588.076456] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  588.076480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  588.076506] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  588.083810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  588.083859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  588.083947] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  588.100952] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  588.100996] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  588.101028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  588.101067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  588.101100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  588.101139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  588.101179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  588.101218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  588.101257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  588.101300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  588.101342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  588.101384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  588.101423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  588.101461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  588.101503] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  588.101542] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  588.103656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  588.103678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  588.103697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  588.103716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  588.105321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  588.105342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  588.105360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  588.106963] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  588.106984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  588.108836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  588.112177] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  588.112230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  588.112263] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  588.112308] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  588.112366] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  588.112395] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  588.132380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  588.132439] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  588.132505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  593.132631] [drm:drm_mode_addfb2] [FB:78]
>[  593.177918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  593.177934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  593.178003] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  593.178027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  593.178052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 78750KHz
>[  593.178076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  593.178099] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000
>[  593.178124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  593.178146] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  593.178170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  593.178193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3058346, gmch_n: 4194304, link_m: 127431, link_n: 262144, tu: 64
>[  593.178216] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  593.178239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  593.178244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  593.178267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  593.178271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  593.178294] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  593.178317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750
>[  593.178341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  593.178364] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  593.178387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  593.178410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  593.178434] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  593.178458] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  593.178481] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  593.178505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  593.178531] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  593.192172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  593.192223] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  593.192311] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  593.213472] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  593.213517] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  593.213549] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  593.213674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  593.213726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  593.213777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  593.213825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  593.213866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  593.213899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  593.213934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  593.213975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  593.214019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  593.214059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  593.214099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  593.214142] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  593.214182] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  593.216234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  593.216255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  593.216273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  593.216292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  593.217850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  593.217870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  593.217888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  593.219432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  593.219456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  593.221305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  593.224541] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  593.224591] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  593.224610] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  593.224636] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  593.224694] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  593.224723] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  593.238068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  593.238127] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  593.238193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  598.238452] [drm:drm_mode_addfb2] [FB:77]
>[  598.285406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  598.285422] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  598.285489] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  598.285511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  598.285533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 65000KHz
>[  598.285556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  598.285579] [drm:intel_dp_compute_config [i915]] DP link bw required 195000 available 324000
>[  598.285603] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  598.285627] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  598.285651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  598.285674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2524349, gmch_n: 4194304, link_m: 105181, link_n: 262144, tu: 64
>[  598.285697] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  598.285720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  598.285725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  598.285748] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  598.285752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  598.285775] [drm:intel_dump_pipe_config [i915]] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  598.285798] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 65000
>[  598.285821] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  598.285844] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  598.285868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  598.285891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  598.285916] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 1024x768 format = XR24 little-endian (0x34325258)
>[  598.285939] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  598.285962] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  598.285987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  598.286013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  598.289266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  598.289316] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  598.289494] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  598.304244] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  598.304287] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  598.304320] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  598.304445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  598.304497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  598.304547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  598.304595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  598.304643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  598.304685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  598.304721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  598.304755] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  598.304787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  598.304817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  598.304845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  598.304880] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  598.304912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  598.306968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  598.306989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  598.307007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  598.307026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  598.308595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  598.308617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  598.308636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  598.310172] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  598.310193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  598.312051] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  598.315243] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  598.315288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  598.315316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  598.315424] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  598.315664] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  598.315685] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  598.332115] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  598.332179] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  598.332250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  603.332554] [drm:drm_mode_addfb2] [FB:78]
>[  603.377952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  603.377967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  603.378036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  603.378060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  603.378084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 49500KHz
>[  603.378108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  603.378182] [drm:intel_dp_compute_config [i915]] DP link bw required 148500 available 162000
>[  603.378216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  603.378248] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  603.378278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  603.378310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1922389, gmch_n: 2097152, link_m: 80099, link_n: 262144, tu: 64
>[  603.378339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  603.378367] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  603.378375] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  603.378402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  603.378410] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  603.378441] [drm:intel_dump_pipe_config [i915]] crtc timings: 49500 800 816 896 1056 600 601 604 625, type: 0x40 flags: 0x5
>[  603.378471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 49500
>[  603.378500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  603.378529] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  603.378562] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  603.378592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  603.378624] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 1024x768 format = XR24 little-endian (0x34325258)
>[  603.378646] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  603.378664] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  603.378687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  603.378715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  603.381572] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  603.381621] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  603.381692] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  603.398708] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  603.398756] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  603.398797] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  603.398842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  603.398882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  603.398922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  603.398961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  603.399000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  603.399039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  603.399081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  603.399123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  603.399257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  603.399312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  603.399364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  603.399423] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  603.399478] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  603.401544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  603.401565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  603.401583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  603.401603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  603.403163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  603.403183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  603.403202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  603.404751] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  603.404774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  603.406657] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  603.409954] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  603.410001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  603.410030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  603.410067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  603.410187] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  603.410232] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  603.423477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  603.423535] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  603.423599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  608.423689] [drm:drm_mode_addfb2] [FB:77]
>[  608.473443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  608.473457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  608.473524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  608.473547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  608.473571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 40000KHz
>[  608.473596] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  608.473614] [drm:intel_dp_compute_config [i915]] DP link bw required 120000 available 162000
>[  608.473634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  608.473655] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  608.473674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  608.473693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1553445, gmch_n: 2097152, link_m: 64726, link_n: 262144, tu: 64
>[  608.473710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  608.473728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  608.473733] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  608.473750] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  608.473754] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  608.473772] [drm:intel_dump_pipe_config [i915]] crtc timings: 40000 800 840 968 1056 600 601 605 628, type: 0x40 flags: 0x5
>[  608.473788] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 40000
>[  608.473805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  608.473821] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  608.473841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  608.473863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  608.473888] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  608.473911] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  608.473987] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  608.474021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  608.474055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  608.476632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  608.476681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  608.476752] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  608.491709] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  608.491753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  608.491785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  608.491824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  608.491857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  608.491888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  608.491918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  608.492026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  608.492073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  608.492129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  608.492177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  608.492230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  608.492277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  608.492323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  608.492377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  608.492429] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  608.494517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  608.494538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  608.494556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  608.494575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  608.496148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  608.496178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  608.496206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  608.497766] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  608.497788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  608.499633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  608.502968] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  608.503016] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  608.503046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  608.503084] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  608.503153] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  608.503186] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  608.519756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  608.519816] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  608.519883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  613.520191] [drm:drm_mode_addfb2] [FB:78]
>[  613.564225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  613.564240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  613.564311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  613.564332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  613.564355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 27000KHz
>[  613.564377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  613.564395] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000
>[  613.564415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  613.564435] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  613.564454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  613.564473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  613.564490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  613.564506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  613.564511] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  613.564527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  613.564531] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  613.564548] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 732 796 864 576 581 586 625, type: 0x40 flags: 0xa
>[  613.564565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x576, pixel rate 27000
>[  613.564581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  613.564597] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  613.564617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  613.564633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  613.564651] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  613.564667] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  613.564683] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  613.564754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  613.564790] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  613.576263] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  613.576317] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  613.576393] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  613.593387] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  613.593432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  613.593464] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  613.593504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  613.593537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  613.593576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  613.593617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  613.593656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  613.593695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  613.593813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  613.593869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  613.593920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  613.593964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  613.594011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  613.594054] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  613.594086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  613.596193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  613.596214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  613.596233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  613.596252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  613.597820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  613.597840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  613.597858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  613.599381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  613.599404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  613.601234] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  613.604552] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  613.604605] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  613.604637] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  613.604679] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  613.605014] [drm:intel_fbc_enable [i915]] reserved 3317760 bytes of contiguous stolen space for FBC, threshold: 1
>[  613.605036] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  613.624757] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  613.624816] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  613.624885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  618.624974] [drm:drm_mode_addfb2] [FB:77]
>[  618.658976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  618.658990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  618.659057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  618.659082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  618.659106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 27027KHz
>[  618.659130] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  618.659153] [drm:intel_dp_compute_config [i915]] DP link bw required 81081 available 162000
>[  618.659177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  618.659201] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  618.659224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  618.659248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1049624, gmch_n: 2097152, link_m: 43734, link_n: 262144, tu: 64
>[  618.659271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  618.659294] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  618.659298] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  618.659321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  618.659325] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  618.659349] [drm:intel_dump_pipe_config [i915]] crtc timings: 27027 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  618.659372] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27027
>[  618.659395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  618.659418] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  618.659442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  618.659465] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  618.659489] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 720x576 format = XR24 little-endian (0x34325258)
>[  618.659566] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  618.659600] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  618.659638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  618.659678] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  618.664584] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  618.664636] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  618.664713] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  618.685868] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  618.685912] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  618.685944] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  618.685983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  618.686015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  618.686046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  618.686076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  618.686115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  618.686154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  618.686203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  618.686236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  618.686267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  618.686294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  618.686320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  618.686353] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  618.686383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  618.688476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  618.688515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  618.688539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  618.688563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  618.690124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  618.690146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  618.690165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  618.691712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  618.691734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  618.693586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  618.696930] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  618.696983] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  618.697016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  618.697058] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  618.697152] [drm:intel_fbc_enable [i915]] reserved 2764800 bytes of contiguous stolen space for FBC, threshold: 1
>[  618.697202] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  618.713801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  618.713866] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  618.713924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  623.714094] [drm:drm_mode_addfb2] [FB:78]
>[  623.754478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  623.754493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  623.754559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  623.754581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  623.754603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 27000KHz
>[  623.754624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  623.754642] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000
>[  623.754662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  623.754686] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  623.754710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  623.754733] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  623.754757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  623.754780] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  623.754784] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  623.754807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  623.754811] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  623.754835] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  623.754859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27000
>[  623.754882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  623.754905] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  623.754929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  623.754952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  623.754976] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 720x480 format = XR24 little-endian (0x34325258)
>[  623.755000] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  623.755023] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  623.755048] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  623.755074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  623.763618] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  623.763668] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  623.763739] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  623.780753] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  623.780797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  623.780829] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  623.780869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  623.780902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  623.780933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  623.780963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  623.780992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  623.781024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  623.781059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  623.781091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  623.781122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  623.781150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  623.781177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  623.781211] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  623.781242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  623.783379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  623.783400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  623.783419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  623.783438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  623.784979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  623.784999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  623.785018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  623.786556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  623.786577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  623.788414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  623.791681] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  623.791713] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  623.791733] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  623.791758] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  623.791816] [drm:intel_fbc_enable [i915]] reserved 2764800 bytes of contiguous stolen space for FBC, threshold: 1
>[  623.791838] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  623.808534] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  623.808596] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  623.808667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  628.808754] [drm:drm_mode_addfb2] [FB:77]
>[  628.840903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  628.840918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  628.840984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  628.841006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  628.841028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 31500KHz
>[  628.841051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  628.841070] [drm:intel_dp_compute_config [i915]] DP link bw required 94500 available 162000
>[  628.841145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  628.841176] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  628.841206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  628.841235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1223338, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64
>[  628.841263] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  628.841291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  628.841298] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  628.841328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  628.841337] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  628.841365] [drm:intel_dump_pipe_config [i915]] crtc timings: 31500 640 656 720 840 480 481 484 500, type: 0x40 flags: 0xa
>[  628.841395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 31500
>[  628.841421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  628.841452] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  628.841484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  628.841513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  628.841544] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 720x480 format = XR24 little-endian (0x34325258)
>[  628.841574] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  628.841602] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  628.841637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  628.841672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  628.846763] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  628.846813] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  628.846887] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  628.863888] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  628.863932] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  628.863965] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  628.864004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  628.864044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  628.864084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  628.864198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  628.864250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  628.864296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  628.864354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  628.864406] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  628.864457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  628.864504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  628.864550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  628.864599] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  628.864632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  628.866714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  628.866736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  628.866755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  628.866774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  628.868329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  628.868349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  628.868367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  628.869901] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  628.869923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  628.871774] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  628.875127] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  628.875169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  628.875196] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  628.875231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  628.875291] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  628.875317] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  628.888649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  628.888708] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  628.888773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  633.888887] [drm:drm_mode_addfb2] [FB:78]
>[  633.928110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  633.928124] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  633.928192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  633.928214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  633.928237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 25200KHz
>[  633.928257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  633.928280] [drm:intel_dp_compute_config [i915]] DP link bw required 75600 available 162000
>[  633.928304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  633.928328] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  633.928351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  633.928375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 978670, gmch_n: 2097152, link_m: 40777, link_n: 262144, tu: 64
>[  633.928398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  633.928421] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  633.928426] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  633.928448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  633.928452] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  633.928476] [drm:intel_dump_pipe_config [i915]] crtc timings: 25200 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  633.928499] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25200
>[  633.928523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  633.928546] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  633.928570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  633.928593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  633.928617] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  633.928640] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  633.928664] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  633.928689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  633.928715] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  633.941807] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  633.941859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  633.942027] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  633.956679] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  633.956724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  633.956756] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  633.956795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  633.956828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  633.956859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  633.956975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  633.957020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  633.957054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  633.957089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  633.957123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  633.957155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  633.957185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  633.957213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  633.957248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  633.957280] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  633.959375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  633.959399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  633.959422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  633.959446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  633.960996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  633.961017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  633.961035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  633.962574] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  633.962596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  633.964447] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  633.967762] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  633.967815] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  633.967847] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  633.967987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  633.968094] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  633.968125] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  633.984603] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  633.984662] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  633.984728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  638.984811] [drm:drm_mode_addfb2] [FB:77]
>[  639.017097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  639.017112] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  639.017177] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  639.017202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  639.017227] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 25175KHz
>[  639.017251] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  639.017274] [drm:intel_dp_compute_config [i915]] DP link bw required 75525 available 162000
>[  639.017298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  639.017321] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  639.017345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  639.017368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 977700, gmch_n: 2097152, link_m: 40737, link_n: 262144, tu: 64
>[  639.017391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  639.017414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  639.017419] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  639.017442] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  639.017446] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  639.017469] [drm:intel_dump_pipe_config [i915]] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  639.017492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25175
>[  639.017515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  639.017538] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  639.017563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  639.017586] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  639.017610] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:78, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  639.017633] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  639.017711] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  639.017747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  639.017787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  639.034507] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  639.034561] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  639.034636] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  639.051743] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  639.051791] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  639.051832] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  639.051877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  639.051917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  639.051957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  639.051997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  639.052037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  639.052076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  639.052119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  639.052160] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  639.052202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  639.052240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  639.052279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  639.052320] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  639.052359] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  639.054423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  639.054446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  639.054469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  639.054494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  639.056046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  639.056067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  639.056085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  639.057646] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  639.057682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  639.059527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  639.062860] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  639.062912] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  639.062942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  639.062968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  639.063028] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  639.063049] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  639.079746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  639.079806] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  639.079871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  644.079957] [drm:drm_mode_addfb2] [FB:78]
>[  644.108111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  644.108125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  644.108191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  644.108213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  644.108237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 28320KHz
>[  644.108260] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  644.108277] [drm:intel_dp_compute_config [i915]] DP link bw required 84960 available 162000
>[  644.108298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  644.108318] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  644.108337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  644.108355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1099839, gmch_n: 2097152, link_m: 45826, link_n: 262144, tu: 64
>[  644.108372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  644.108389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  644.108393] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  644.108410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  644.108414] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  644.108431] [drm:intel_dump_pipe_config [i915]] crtc timings: 28320 720 738 846 900 400 412 414 449, type: 0x40 flags: 0x6
>[  644.108504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x400, pixel rate 28320
>[  644.108535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  644.108567] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  644.108601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  644.108632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  644.108665] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:77, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  644.108696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  644.108726] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  644.108762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  644.108798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  644.117929] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  644.117978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  644.118050] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  644.135080] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  644.135124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  644.135157] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  644.135196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  644.135229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  644.135259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  644.135289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  644.135317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  644.135349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  644.135383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  644.135415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  644.135446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  644.135549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  644.135592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  644.135641] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  644.135687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  644.137806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  644.137827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  644.137845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  644.137864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  644.139439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  644.139475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  644.139493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  644.141043] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  644.141064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  644.142903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  644.146258] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  644.146310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  644.146343] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  644.146385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  644.146511] [drm:intel_fbc_enable [i915]] reserved 2304000 bytes of contiguous stolen space for FBC, threshold: 1
>[  644.146541] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  644.160701] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  644.160759] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  644.160822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  649.160965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  649.169012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  649.169061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  649.169133] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  649.184108] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  649.184152] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  649.184184] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  649.184223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  649.184347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  649.184395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  649.184427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  649.184457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  649.184489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  649.184525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  649.184559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  649.184591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  649.184624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  649.184653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  649.184682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  649.184736] [drm:intel_power_well_disable [i915]] disabling display
>[  649.184764] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  649.184798] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  649.184824] [drm:intel_power_well_disable [i915]] disabling always-on
>[  649.185247] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  649.185344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  649.185378] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  649.185414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  649.185442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  649.185471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  649.185503] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  649.185540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  649.185568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  649.185594] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  649.185620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  649.185626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  649.185651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  649.185656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  649.185682] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  649.185707] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  649.185730] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  649.185755] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  649.185783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  649.185806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  649.185831] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  649.185854] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  649.185879] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  649.185905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  649.185936] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  649.186112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  649.186145] [drm:intel_power_well_enable [i915]] enabling display
>[  649.186177] [drm:hsw_set_power_well [i915]] Enabling power well
>[  649.186293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  649.186321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  649.186347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  649.186374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  649.186401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  649.186428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  649.186464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  649.186493] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  649.186521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  649.186547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  649.186571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  649.186611] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  649.186644] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  649.188761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  649.188780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  649.188798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  649.188816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  649.190395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  649.190416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  649.190434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  649.191999] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  649.192020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  649.193884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  649.197144] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  649.197199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  649.197229] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  649.197301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  649.197547] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  649.197579] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  649.214015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  649.214063] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  649.214128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  649.354675] Console: switching to colour dummy device 80x25
>[  649.354788] [IGT] kms_flip: executing
>[  649.370078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  649.370126] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  649.371318] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  649.371368] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  649.373318] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  649.373331] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  649.375318] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  649.375357] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  649.377320] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  649.377331] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  649.377339] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  649.377371] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  649.377413] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  649.378613] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  649.379542] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  649.379564] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  649.379583] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  649.379601] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  649.380621] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  649.380642] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  649.381806] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  649.381809] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  649.381909] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  649.381912] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  649.381917] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  649.381919] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  649.381924] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  649.381926] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  649.381936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  649.381939] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  649.381942] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  649.381945] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  649.381948] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  649.381951] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  649.381954] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  649.381957] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  649.381960] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  649.381963] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  649.381966] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  649.381969] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  649.381972] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  649.381975] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  649.381978] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  649.381981] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  649.381984] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  649.381987] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  649.381990] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  649.381992] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  649.381995] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  649.381998] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  649.382001] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  649.382004] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  649.382007] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  649.382010] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  649.382013] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  649.382016] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  649.382019] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  649.382022] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  649.382025] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  649.382067] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  649.382091] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  649.383282] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  649.383306] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  649.385318] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  649.385330] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  649.387309] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  649.387349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  649.389305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  649.389316] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  649.389324] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  649.391410] [IGT] kms_flip: starting subtest wf_vblank-interruptible
>[  649.392028] [drm:drm_mode_addfb2] [FB:58]
>[  649.392057] [drm:drm_mode_addfb2] [FB:79]
>[  649.445775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  649.445852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  649.447515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  649.447564] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  649.447654] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  649.465905] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  649.465948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  649.465981] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  649.466020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  649.466052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  649.466087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  649.466117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  649.466146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  649.466178] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  649.466212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  649.466325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  649.466378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  649.466431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  649.466476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  649.466522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  649.466616] [drm:intel_power_well_disable [i915]] disabling display
>[  649.466677] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  649.466718] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  649.466753] [drm:intel_power_well_disable [i915]] disabling always-on
>[  649.466863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  649.467053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  649.467185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  649.467197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  649.467316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  649.467349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  649.467384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  649.467420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  649.467448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  649.467480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  649.467509] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  649.467540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  649.467568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  649.467596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  649.467622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  649.467629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  649.467656] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  649.467662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  649.467691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  649.467717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  649.467744] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  649.467769] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  649.467800] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  649.467825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  649.467853] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  649.467878] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  649.467905] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  649.467938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  649.467971] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  649.471314] [drm:intel_power_well_enable [i915]] enabling always-on
>[  649.471336] [drm:intel_power_well_enable [i915]] enabling display
>[  649.471354] [drm:hsw_set_power_well [i915]] Enabling power well
>[  649.471391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  649.471413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  649.471434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  649.471454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  649.471473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  649.471493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  649.471515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  649.471535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  649.471555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  649.471578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  649.471602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  649.471628] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  649.471653] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  649.473737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  649.473758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  649.473776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  649.473796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  649.475483] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  649.475505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  649.475524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  649.477087] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  649.477108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  649.478983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  649.482299] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  649.482364] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  649.482397] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  649.482439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  649.482534] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  649.482584] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  649.499146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  649.499196] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  649.499355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  659.523901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  659.540425] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  659.540475] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  659.540564] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  659.557574] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  659.557618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  659.557652] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  659.557691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  659.557724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  659.557760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  659.557790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  659.557904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  659.557950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  659.558009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  659.558063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  659.558114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  659.558172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  659.558203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  659.558232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  659.558287] [drm:intel_power_well_disable [i915]] disabling display
>[  659.558317] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  659.558346] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  659.558368] [drm:intel_power_well_disable [i915]] disabling always-on
>[  659.558583] [drm:drm_mode_addfb2] [FB:58]
>[  659.558614] [drm:drm_mode_addfb2] [FB:78]
>[  659.591270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  659.591367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  659.591431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  659.591491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  659.591503] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  659.591561] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  659.591583] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  659.591605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  659.591629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  659.591648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  659.591668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  659.591688] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  659.591711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  659.591735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  659.591758] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  659.591781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  659.591828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  659.591859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  659.591869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  659.591901] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  659.591929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  659.591958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  659.591989] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  659.592021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  659.592049] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  659.592079] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  659.592106] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  659.592135] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  659.592166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  659.592200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  659.595590] [drm:intel_power_well_enable [i915]] enabling always-on
>[  659.595609] [drm:intel_power_well_enable [i915]] enabling display
>[  659.595626] [drm:hsw_set_power_well [i915]] Enabling power well
>[  659.595661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  659.595681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  659.595699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  659.595717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  659.595734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  659.595753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  659.595774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  659.595793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  659.595877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  659.595904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  659.595935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  659.595972] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  659.596001] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  659.598076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  659.598097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  659.598119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  659.598143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  659.599715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  659.599735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  659.599753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  659.601339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  659.601360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  659.603256] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  659.606583] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  659.606638] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  659.606670] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  659.606712] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  659.623414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  659.623462] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  659.623525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  669.648121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  669.648214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  669.648260] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  669.648335] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  669.665356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  669.665394] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  669.665519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  669.665573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  669.665633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  669.665682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  669.665717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  669.665749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  669.665787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  669.665821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  669.665853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  669.665894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  669.665912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  669.665931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  669.665966] [drm:intel_power_well_disable [i915]] disabling display
>[  669.665994] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  669.666026] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  669.666050] [drm:intel_power_well_disable [i915]] disabling always-on
>[  669.666284] [drm:drm_mode_addfb2] [FB:58]
>[  669.666313] [drm:drm_mode_addfb2] [FB:78]
>[  669.695861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  669.695963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  669.696034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  669.696101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  669.696113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  669.696171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  669.696193] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  669.696215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  669.696238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  669.696256] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  669.696288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  669.696310] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  669.696331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  669.696358] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  669.696375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  669.696448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  669.696457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  669.696486] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  669.696495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  669.696526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  669.696557] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  669.696587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  669.696617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  669.696651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  669.696682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  669.696713] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  669.696744] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  669.696775] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  669.696810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  669.696845] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  669.700141] [drm:intel_power_well_enable [i915]] enabling always-on
>[  669.700161] [drm:intel_power_well_enable [i915]] enabling display
>[  669.700177] [drm:hsw_set_power_well [i915]] Enabling power well
>[  669.700213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  669.700233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  669.700252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  669.700270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  669.700288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  669.700307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  669.700327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  669.700347] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  669.700365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  669.700447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  669.700475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  669.700510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  669.700540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  669.702619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  669.702643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  669.702663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  669.702684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  669.704235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  669.704256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  669.704275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  669.705840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  669.705861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  669.707730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  669.710986] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  669.711056] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  669.711083] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  669.711112] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  669.727844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  669.727897] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  669.727975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  679.752567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  679.752658] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  679.752703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  679.752775] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  679.769800] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  679.769838] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  679.769878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  679.769912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  679.769947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  679.770056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  679.770100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  679.770150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  679.770205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  679.770259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  679.770311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  679.770362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  679.770410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  679.770451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  679.770508] [drm:intel_power_well_disable [i915]] disabling display
>[  679.770554] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  679.770613] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  679.770647] [drm:intel_power_well_disable [i915]] disabling always-on
>[  679.772185] [IGT] kms_flip: exiting, ret=0
>[  679.792817] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  679.792857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  679.792898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  679.792942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  679.792979] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  679.793041] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  679.793075] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  679.793095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  679.793113] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  679.793130] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  679.793146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  679.793150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  679.793172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  679.793176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  679.793199] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  679.793222] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  679.793244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  679.793267] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  679.793290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  679.793312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  679.793335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  679.793358] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  679.793377] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  679.793402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  679.793428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  679.793513] [drm:intel_power_well_enable [i915]] enabling always-on
>[  679.793540] [drm:intel_power_well_enable [i915]] enabling display
>[  679.793565] [drm:hsw_set_power_well [i915]] Enabling power well
>[  679.793638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  679.793661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  679.793684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  679.793707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  679.793729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  679.793752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  679.793778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  679.793801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  679.793825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  679.793846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  679.793868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  679.793905] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  679.793932] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  679.796304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  679.796325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  679.796343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  679.796361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  679.797948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  679.797987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  679.798005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  679.799570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  679.799589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  679.801497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  679.804986] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  679.805084] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  679.805122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  679.805205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  679.805381] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  679.805412] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  679.821882] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  679.821930] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  679.822037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  679.822291] Console: switching to colour frame buffer device 240x75
>[  679.928573] Console: switching to colour dummy device 80x25
>[  679.928685] [IGT] kms_flip: executing
>[  679.939861] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  679.939906] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  679.942043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  679.942080] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  679.944053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  679.944065] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  679.946076] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  679.946113] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  679.948056] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  679.948067] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  679.948075] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  679.948105] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  679.948148] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  679.949267] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  679.950200] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  679.950223] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  679.950242] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  679.950260] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  679.951284] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  679.951304] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  679.952427] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  679.952431] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  679.952534] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  679.952536] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  679.952541] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  679.952544] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  679.952548] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  679.952551] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  679.952560] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  679.952563] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  679.952566] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  679.952569] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  679.952572] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  679.952575] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  679.952578] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  679.952581] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  679.952584] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  679.952587] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  679.952590] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  679.952593] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  679.952596] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  679.952599] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  679.952601] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  679.952604] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  679.952607] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  679.952610] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  679.952613] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  679.952616] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  679.952619] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  679.952622] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  679.952625] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  679.952628] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  679.952631] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  679.952634] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  679.952637] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  679.952640] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  679.952643] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  679.952645] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  679.952648] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  679.952687] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  679.952709] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  679.953990] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  679.954012] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  679.956031] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  679.956039] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  679.958066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  679.958104] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  679.960057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  679.960068] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  679.960075] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  679.960484] [IGT] kms_flip: starting subtest flip-vs-dpms-off-vs-modeset
>[  679.961424] [drm:drm_mode_addfb2] [FB:77]
>[  679.961469] [drm:drm_mode_addfb2] [FB:79]
>[  680.014925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.015066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.022043] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.022093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.022168] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.039167] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.039211] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.039243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.039282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.039315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.039358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.039398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.039438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.039476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.039521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.039563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.039605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.039646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.039685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.039724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.039782] [drm:intel_power_well_disable [i915]] disabling display
>[  680.039828] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.039877] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.039913] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.040311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.040507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  680.040616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.040630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.040687] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.040710] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.040735] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.040760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.040781] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.040804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.040825] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.040847] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.040867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.040887] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.040911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.040917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.040942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.040972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.041003] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.041031] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.041060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.041086] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.041117] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.041144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.041171] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  680.041198] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.041225] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.041256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.041288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.044675] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.044695] [drm:intel_power_well_enable [i915]] enabling display
>[  680.044712] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.044746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.044766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.044785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.044802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.044819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.044837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.044857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.044876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.044894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.044910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.044926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.044947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  680.045030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.047102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.047122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.047141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.047160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.048729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.048749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.048767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.050331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.050352] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.052213] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.055528] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  680.055594] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.055627] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  680.055669] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.055741] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  680.055762] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  680.072380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.072432] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.072503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.089210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.089250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.089289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.089331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.089364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.089400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.089436] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.089476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.089518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.089559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.089599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.089607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.089647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.089654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.089696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.089737] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.089778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.089818] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.089859] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.089899] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.089941] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  680.090059] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.090107] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.090159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.090211] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.105725] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.105774] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.105846] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.122878] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.122922] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.122954] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.123087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.123140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.123190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.123238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.123291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.123333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.123378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.123421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.123464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.123502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.123540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.123612] [drm:intel_power_well_disable [i915]] disabling display
>[  680.123667] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.123708] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.123752] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.123799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.123839] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.124003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.124020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.124094] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.124127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.124162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.124199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.124232] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.124266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.124303] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.124323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.124342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.124362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.124385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.124390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.124412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.124417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.124440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.124464] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.124487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.124510] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.124533] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.124556] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.124580] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  680.124603] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.124626] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.124651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.124676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.124735] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.124755] [drm:intel_power_well_enable [i915]] enabling display
>[  680.124775] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.124810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.124834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.124857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.124880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.124904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.124927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.124952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.125026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.125065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.125098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.125129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.125166] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  680.125199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.127270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.127291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.127310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.127328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.128899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.128923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.128945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.130533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.130554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.132432] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.135670] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  680.135748] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.135767] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  680.135793] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.135853] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  680.135874] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  680.152547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.152605] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.152670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.152901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.153084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.185891] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.185938] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.186106] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.203102] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.203145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.203177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.203215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.203254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.203298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.203338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.203377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.203415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.203459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.203501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.203543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.203584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.203623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.203662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.203719] [drm:intel_power_well_disable [i915]] disabling display
>[  680.203764] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.203814] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.203852] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.204132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.204151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.204239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.204273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.204308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.204346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.204377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.204411] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.204444] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.204475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.204507] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.204538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.204567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.204575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.204603] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.204611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.204640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.204670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.204699] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.204729] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.204761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.204791] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.204821] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  680.204850] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.204876] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.204909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.204944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.205059] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.205093] [drm:intel_power_well_enable [i915]] enabling display
>[  680.205124] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.205175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.205208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.205239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.205271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.205302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.205333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.205364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.205397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.205429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.205458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.205487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.205521] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  680.205553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.207632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.207654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.207673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.207692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.209265] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.209286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.209306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.210860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.210882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.212750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.216100] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  680.216185] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.216218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  680.216259] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.216346] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  680.216373] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  680.233006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.233056] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.233121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.233321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.233398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.266326] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.266373] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.266445] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.283497] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.283541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.283573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.283610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.283643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.283678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.283709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.283738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.283769] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.283803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.283844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.283886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.283928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.284019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.284048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.284102] [drm:intel_power_well_disable [i915]] disabling display
>[  680.284146] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.284178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.284200] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.284329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.284341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.284394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.284416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.284438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.284463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.284484] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.284505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.284526] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.284546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.284565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.284584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.284602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.284607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.284624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.284628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.284647] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.284664] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.284682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.284699] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.284720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.284738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.284756] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  680.284773] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.284791] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.284812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.284835] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.284893] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.284913] [drm:intel_power_well_enable [i915]] enabling display
>[  680.284930] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.285000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.285029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.285057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.285084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.285111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.285139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.285171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.285200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.285229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.285256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.285281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.285313] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  680.285342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.287450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.287472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.287491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.287510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.289138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.289161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.289180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.290752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.290775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.292653] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.295996] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  680.296087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.296120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  680.296167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.296232] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  680.296260] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  680.312871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.312923] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.313193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.313423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.313513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.346214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.346262] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.346333] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.363542] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.363585] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.363617] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.363654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.363688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.363722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.363753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.363781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.363813] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.363848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.363881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.363920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.364022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.364063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.364103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.364181] [drm:intel_power_well_disable [i915]] disabling display
>[  680.364233] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.364273] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.364306] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.364502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.364519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.364597] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.364635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.364686] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.364731] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.364761] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.364793] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.364825] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.364854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.364883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.364920] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.364939] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.364974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.365001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.365010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.365037] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.365064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.365091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.365118] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.365149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.365175] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.365202] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  680.365229] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.365255] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.365286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.365317] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.365406] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.365439] [drm:intel_power_well_enable [i915]] enabling display
>[  680.365470] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.365521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.365554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.365585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.365617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.365647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.365678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.365702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.365722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.365743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.365762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.365786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.365815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  680.365841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.367893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.367914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.367933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.368009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.369577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.369598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.369616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.371181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.371202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.373064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.376331] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  680.376379] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.376399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  680.376424] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.376485] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  680.376506] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  680.393179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.393228] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.393293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.393495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.393595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.426523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.426572] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.426642] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.443672] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.443715] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.443748] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.443786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.443818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.443853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.443884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.443913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.443944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.444063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.444117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.444164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.444216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.444249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.444277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.444331] [drm:intel_power_well_disable [i915]] disabling display
>[  680.444372] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.444415] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.444449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.444609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.444627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.444709] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.444742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.444778] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.444823] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.444862] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.444896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.444917] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.444939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.444994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.445022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.445048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.445057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.445082] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.445090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.445119] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.445145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.445171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.445197] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.445227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.445252] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.445279] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  680.445306] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.445332] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.445364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.445399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.445475] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.445495] [drm:intel_power_well_enable [i915]] enabling display
>[  680.445513] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.445546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.445567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.445587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.445612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.445639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.445664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.445693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.445721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.445749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.445774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.445801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.445828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  680.445854] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.447904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.447927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.447995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.448030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.449662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.449683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.449701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.451265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.451286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.453156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.456462] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  680.456539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.456571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  680.456621] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.456703] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  680.456740] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  680.473320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.473370] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.473435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.473659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.473751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.506667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.506714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.506784] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.523800] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.523843] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.523876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.523915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.524022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.524080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.524129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.524177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.524226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.524283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.524322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.524356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.524386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.524416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.524443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.524498] [drm:intel_power_well_disable [i915]] disabling display
>[  680.524539] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.524582] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.524616] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.524777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.524790] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.524844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.524865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.524888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.524913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.524932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.524991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.525022] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  680.525051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  680.525080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.525108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.525134] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.525143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.525169] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.525176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.525203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.525230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.525256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.525282] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  680.525312] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.525338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.525365] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  680.525391] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  680.525418] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  680.525449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.525481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  680.525570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.525603] [drm:intel_power_well_enable [i915]] enabling display
>[  680.525633] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.525685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.525717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.525748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.525778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.525808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.525838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.525862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.525882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.525903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.525921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.525972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.526003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  680.526032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.528098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.528119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.528138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.528157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.529730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.529750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.529768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.531320] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.531341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.533215] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.536543] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  680.536596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.536629] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  680.536670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.536746] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  680.536779] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  680.553380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.553430] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.553494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.553723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.553814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.586725] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  680.586772] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.586842] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  680.603871] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  680.603915] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  680.604035] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.604080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.604114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.604150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.604180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.604209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.604240] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.604275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.604308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.604340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.604371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.604399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.604427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.604479] [drm:intel_power_well_disable [i915]] disabling display
>[  680.604520] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.604563] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  680.604601] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.604798] [drm:drm_mode_addfb2] [FB:77]
>[  680.604827] [drm:drm_mode_addfb2] [FB:78]
>[  680.633901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  680.634126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.634210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  680.634273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.634285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.634343] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.634365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.634388] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.634415] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.634438] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.634463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.634486] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  680.634510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  680.634534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.634557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.634580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.634584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.634607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.634612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.634635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.634658] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.634682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.634704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  680.634728] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.634751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.634774] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  680.634796] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  680.634819] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  680.634844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.634870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  680.638170] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.638191] [drm:intel_power_well_enable [i915]] enabling display
>[  680.638209] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.638247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.638272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.638297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.638321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.638346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.638370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.638397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.638422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.638448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.638472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.638496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.638522] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  680.638547] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.640828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.640850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.640868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.640888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.642469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.642489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.642508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.644161] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.644184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.646057] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.649400] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  680.649485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.649513] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  680.649549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.666279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.666330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.666401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.683147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.683185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.683222] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.683261] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.683290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.683324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.683357] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  680.683396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  680.683436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.683475] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.683514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.683522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.683561] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.683568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.683608] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.683647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.683686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.683732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  680.683772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.683810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.683851] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  680.683890] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  680.683930] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  680.684031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.684087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  680.684234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  680.684268] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.684325] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  680.701357] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  680.701395] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.701434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.701468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.701498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.701528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.701565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.701605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.701648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.701690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.701731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.701770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.701809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.701866] [drm:intel_power_well_disable [i915]] disabling display
>[  680.701911] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.702039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.702099] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.702156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.702206] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.702344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.702373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.702509] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.702555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.702589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.702625] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.702656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.702688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.702721] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  680.702752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  680.702783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.702813] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.702841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.702849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.702877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.702884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.702914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.702967] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.702996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.703026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  680.703061] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.703090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.703123] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  680.703152] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  680.703183] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  680.703218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.703253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  680.703341] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.703372] [drm:intel_power_well_enable [i915]] enabling display
>[  680.703403] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.703455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.703487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.703518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.703548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.703578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.703608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.703641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.703674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.703706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.703735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.703764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.703797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  680.703828] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.705891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.705912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.705988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.706025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.707593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.707616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.707638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.709194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.709216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.711069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.714398] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  680.714452] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.714485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  680.714527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.731233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.731293] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.731358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.731582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.731674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.747931] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  680.748015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.748103] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  680.765105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  680.765143] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.765182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.765216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.765251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.765281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.765311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.765342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.765384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.765427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.765469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.765511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.765561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.765602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.765655] [drm:intel_power_well_disable [i915]] disabling display
>[  680.765695] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.765738] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.765768] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.766013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.766032] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.766103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.766126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.766150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.766175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.766195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.766218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.766240] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  680.766261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  680.766281] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.766301] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.766318] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.766325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.766342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.766346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.766366] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.766383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.766402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.766420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  680.766441] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.766459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.766477] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  680.766494] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  680.766512] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  680.766533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.766556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  680.766615] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.766634] [drm:intel_power_well_enable [i915]] enabling display
>[  680.766652] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.766686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.766706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.766726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.766744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.766762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.766782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.766804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.766824] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.766843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.766862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.766879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.766901] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  680.766926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.769017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.769038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.769056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.769076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.770645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.770665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.770683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.772247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.772268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.774139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.777434] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  680.777524] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.777561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  680.777610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.794301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.794351] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.794416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.794646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.794738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.811004] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  680.811059] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.811148] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  680.828151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  680.828188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.828228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.828262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.828304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.828344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.828384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.828422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.828466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.828508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.828549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.828591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.828630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.828668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.828724] [drm:intel_power_well_disable [i915]] disabling display
>[  680.828770] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.828820] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.828855] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.829119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.829138] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.829227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.829271] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.829295] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.829320] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.829345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.829372] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.829398] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  680.829424] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  680.829450] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.829476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.829501] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.829506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.829530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.829536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.829559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.829585] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.829611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.829635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  680.829661] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.829687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.829713] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  680.829738] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  680.829764] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  680.829792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.829819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  680.829881] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.829903] [drm:intel_power_well_enable [i915]] enabling display
>[  680.829950] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.830006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.830037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.830066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.830094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.830122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.830151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.830183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.830215] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.830245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.830274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.830300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.830335] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  680.830367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.832424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.832445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.832463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.832482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.834064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.834085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.834103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.835662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.835682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.837559] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.840818] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  680.840887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.840915] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  680.841026] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.857671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.857722] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.857788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.858090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.858195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.874369] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  680.874415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.874501] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  680.891501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  680.891538] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.891582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.891622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.891666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.891706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.891745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.891782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.891825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.891868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.891909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.892028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.892074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.892119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.892202] [drm:intel_power_well_disable [i915]] disabling display
>[  680.892271] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.892339] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.892391] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.892591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.892610] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.892704] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.892726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.892749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.892777] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.892803] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.892830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.892856] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  680.892882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  680.892908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.892962] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.892992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.893000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.893028] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.893035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.893064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.893091] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.893118] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.893145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  680.893176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.893203] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.893230] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  680.893257] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  680.893283] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  680.893317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.893351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  680.893441] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.893472] [drm:intel_power_well_enable [i915]] enabling display
>[  680.893502] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.893556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.893589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.893613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.893633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.893652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.893672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.893694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.893714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.893733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.893751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.893768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.893791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  680.893816] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.895872] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.895893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.895912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.895990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.897554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.897574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.897592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.899154] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.899175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.901048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.904353] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  680.904432] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.904464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  680.904505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.921212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.921262] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.921327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.921554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.921645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.937908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  680.937984] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  680.938071] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  680.955075] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  680.955112] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  680.955152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.955187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.955222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.955252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.955281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.955313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.955348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.955388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.955430] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.955472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.955511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.955550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.955607] [drm:intel_power_well_disable [i915]] disabling display
>[  680.955653] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  680.955703] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.955739] [drm:intel_power_well_disable [i915]] disabling always-on
>[  680.956062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.956092] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  680.956192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  680.956215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  680.956239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  680.956264] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  680.956284] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  680.956306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  680.956328] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  680.956348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  680.956368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  680.956386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  680.956406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  680.956411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.956429] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  680.956433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  680.956452] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  680.956470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  680.956489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  680.956506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  680.956529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  680.956547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  680.956565] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  680.956583] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  680.956601] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  680.956622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  680.956646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  680.956704] [drm:intel_power_well_enable [i915]] enabling always-on
>[  680.956722] [drm:intel_power_well_enable [i915]] enabling display
>[  680.956740] [drm:hsw_set_power_well [i915]] Enabling power well
>[  680.956773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  680.956793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  680.956812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  680.956830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  680.956848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  680.956868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  680.956890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  680.956910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  680.956969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.956997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  680.957024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  680.957056] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  680.957085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  680.959153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  680.959176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  680.959199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.959223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  680.960795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  680.960816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  680.960834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  680.962397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  680.962417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  680.964317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  680.967575] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  680.967646] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  680.967675] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  680.967713] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  680.984427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  680.984478] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  680.984544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  680.984745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  680.984845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.001126] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  681.001172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.001258] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  681.018264] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  681.018302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.018341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.018374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.018409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.018439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.018468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.018499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.018533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.018565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.018605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.018647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.018686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.018725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.018781] [drm:intel_power_well_disable [i915]] disabling display
>[  681.018826] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.018876] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.018911] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.019257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.019286] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.019422] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.019452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.019486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.019522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.019550] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.019582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.019612] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  681.019642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  681.019670] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.019699] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.019724] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.019732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.019759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.019766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.019795] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.019821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.019848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.019874] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.019905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.019957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.019988] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  681.020014] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  681.020044] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  681.020080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.020115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  681.020202] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.020232] [drm:intel_power_well_enable [i915]] enabling display
>[  681.020262] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.020312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.020340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.020370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.020397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.020425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.020453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.020485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.020517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.020548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.020574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.020602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.020632] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  681.020663] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.022755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.022779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.022802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.022826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.024405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.024427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.024445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.026035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.026056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.027923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.031270] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  681.031369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.031402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  681.031444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.048147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.048197] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.048261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.048483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.048574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.064845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  681.064890] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.065227] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  681.083878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  681.083915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.084043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.084085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.084132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.084172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.084213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.084253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.084299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.084343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.084386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.084430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.084470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.084511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.084567] [drm:intel_power_well_disable [i915]] disabling display
>[  681.084613] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.084664] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.084700] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.084890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.084934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.085022] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.085045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.085068] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.085093] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.085112] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.085134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.085163] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  681.085182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  681.085200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.085217] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.085233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.085238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.085254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.085258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.085275] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.085292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.085308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.085323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.085343] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.085359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.085375] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  681.085391] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  681.085407] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  681.085426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.085447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  681.085502] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.085519] [drm:intel_power_well_enable [i915]] enabling display
>[  681.085535] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.085570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.085594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.085617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.085641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.085665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.085687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.085713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.085738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.085762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.085786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.085808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.085833] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  681.085856] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.087957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.087979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.087998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.088017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.089591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.089615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.089638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.091211] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.091235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.093108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.096408] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  681.096488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.096517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  681.096554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.113273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.113323] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.113389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.113620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.113711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.130007] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  681.130054] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.130123] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  681.147124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  681.147167] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.147211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.147251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.147295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.147334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.147374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.147411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.147454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.147496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.147537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.147579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.147618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.147656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.147712] [drm:intel_power_well_disable [i915]] disabling display
>[  681.147758] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.147807] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.147842] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.148144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.148164] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.148255] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.148278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.148302] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.148327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.148348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.148370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.148395] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  681.148421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  681.148447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.148473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.148499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.148504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.148529] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.148534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.148560] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.148585] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.148611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.148637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.148663] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.148688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.148714] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  681.148739] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  681.148764] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  681.148791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.148819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  681.148879] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.148901] [drm:intel_power_well_enable [i915]] enabling display
>[  681.148961] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.149016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.149047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.149077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.149104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.149132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.149161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.149194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.149225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.149256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.149283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.149310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.149341] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  681.149374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.151439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.151460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.151478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.151497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.153082] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.153103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.153121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.154668] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.154689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.156553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.159823] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  681.159884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.159921] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  681.160045] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.176664] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.176716] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.176788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.177079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.177176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.193362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  681.193408] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.193477] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  681.211865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  681.211902] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.212024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.212084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.212141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.212191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.212227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.212259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.212297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.212329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.212361] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.212392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.212421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.212449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.212502] [drm:intel_power_well_disable [i915]] disabling display
>[  681.212542] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.212593] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  681.212614] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.212809] [drm:drm_mode_addfb2] [FB:77]
>[  681.212837] [drm:drm_mode_addfb2] [FB:78]
>[  681.242038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  681.242145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  681.242218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.242286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.242297] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.242359] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.242383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.242407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.242433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.242453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.242475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.242497] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.242518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.242538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.242557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.242574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.242579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.242596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.242600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.242618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.242636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.242654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.242671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.242692] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.242710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.242728] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.242745] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.242762] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.242782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.242805] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.246088] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.246109] [drm:intel_power_well_enable [i915]] enabling display
>[  681.246129] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.246167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.246191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.246215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.246238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.246262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.246285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.246310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.246335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.246360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.246383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.246406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.246431] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.246455] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.248525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.248547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.248566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.248585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.250157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.250177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.250195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.251748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.251768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.253638] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.256995] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.257076] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.257115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.257167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.273860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.273911] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.274090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.290680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.290721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.290761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.290802] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.290835] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.290871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.290907] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.291029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.291075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.291124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.291166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.291179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.291223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.291234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.291280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.291322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.291369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.291410] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.291460] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.291500] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.291546] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  681.291586] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.291629] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.291674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.291728] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.291882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.291983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.292274] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.308821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.308858] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.308898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.309021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.309068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.309119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.309166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.309216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.309268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.309320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.309370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.309417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.309464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.309545] [drm:intel_power_well_disable [i915]] disabling display
>[  681.309596] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.309637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.309678] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.309720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.309758] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.309873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.309946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.310059] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.310101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.310146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.310194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.310246] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.310289] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.310323] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.310349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.310374] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.310397] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.310419] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.310425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.310447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.310452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.310475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.310497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.310525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.310543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.310565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.310584] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.310608] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  681.310638] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.310668] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.310697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.310724] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.310791] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.310814] [drm:intel_power_well_enable [i915]] enabling display
>[  681.310836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.310876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.310905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.310967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.310999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.311028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.311059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.311091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.311123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.311155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.311182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.311211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.311244] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.311273] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.313351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.313373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.313392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.313411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.315030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.315051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.315069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.316629] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.316650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.318526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.321840] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.321892] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.321974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.322018] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.338689] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.338750] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.338822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.339132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.339252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.355363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.355411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.355480] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.372508] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.372546] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.372585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.372619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.372653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.372683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.372711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.372743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.372777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.372810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.372841] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.372872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.372899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.373011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.373063] [drm:intel_power_well_disable [i915]] disabling display
>[  681.373106] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.373145] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.373177] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.373347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.373366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.373451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.373480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.373513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.373549] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.373577] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.373609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.373638] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.373668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.373695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.373724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.373749] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.373756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.373783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.373790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.373820] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.373845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.373873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.373900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.373956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.373984] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.374014] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.374040] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.374071] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.374105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.374140] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.374229] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.374259] [drm:intel_power_well_enable [i915]] enabling display
>[  681.374288] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.374338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.374366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.374395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.374422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.374450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.374477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.374509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.374541] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.374572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.374598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.374625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.374655] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.374685] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.376751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.376772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.376791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.376810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.378383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.378403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.378421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.380012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.380032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.381899] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.385261] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.385340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.385366] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.385400] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.402127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.402180] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.402253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.402452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.402533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.418801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.418849] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.418993] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.435984] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.436021] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.436061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.436093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.436127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.436157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.436186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.436217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.436251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.436283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.436313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.436344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.436372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.436399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.436455] [drm:intel_power_well_disable [i915]] disabling display
>[  681.436493] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.436535] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.436565] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.436741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.436757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.436832] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.436866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.436900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.437011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.437051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.437096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.437137] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.437175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.437213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.437250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.437285] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.437296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.437330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.437339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.437375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.437413] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.437456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.437484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.437515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.437542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.437569] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.437594] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.437623] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.437650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.437674] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.437733] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.437751] [drm:intel_power_well_enable [i915]] enabling display
>[  681.437770] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.437803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.437824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.437843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.437861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.437879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.437927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.437958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.437988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.438018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.438045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.438071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.438106] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.438135] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.440177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.440197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.440216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.440235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.441794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.441813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.441831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.443394] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.443414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.445316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.448615] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.448684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.448708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.448739] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.465476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.465530] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.465601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.465802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.465883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.482153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.482204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.482278] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.499301] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.499338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.499382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.499422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.499466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.499505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.499555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.499608] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.499655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.499689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.499727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.499752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.499775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.499806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.499855] [drm:intel_power_well_disable [i915]] disabling display
>[  681.499893] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.500004] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.500043] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.500256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.500272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.500346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.500374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.500406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.500438] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.500470] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.500506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.500539] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.500574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.500608] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.500642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.500675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.500683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.500715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.500731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.500758] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.500781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.500803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.500823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.500847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.500873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.500903] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.500959] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.500990] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.501025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.501061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.501157] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.501186] [drm:intel_power_well_enable [i915]] enabling display
>[  681.501220] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.501261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.501283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.501304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.501331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.501359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.501386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.501417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.501446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.501476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.501503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.501531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.501560] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.501588] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.503639] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.503661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.503680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.503699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.505264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.505285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.505303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.506897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.506934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.508807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.512105] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.512185] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.512218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.512261] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.528971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.529022] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.529088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.529269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.529346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.545646] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.545692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.545762] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.562789] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.562827] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.562866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.562899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.563024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.563065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.563095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.563135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.563170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.563201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.563232] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.563261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.563288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.563314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.563364] [drm:intel_power_well_disable [i915]] disabling display
>[  681.563407] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.563455] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.563489] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.563672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.563691] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.563776] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.563815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.563855] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.563899] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.563981] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.564031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.564078] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.564120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.564163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.564206] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.564238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.564248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.564279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.564288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.564321] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.564353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.564385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.564416] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.564452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.564483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.564514] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.564545] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.564577] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.564614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.564653] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.564752] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.564774] [drm:intel_power_well_enable [i915]] enabling display
>[  681.564800] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.564846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.564877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.564940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.564975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.565009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.565044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.565086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.565121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.565146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.565168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.565197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.565223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.565248] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.567287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.567307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.567331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.567359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.568946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.568966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.568984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.570553] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.570576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.572442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.575710] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.575768] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.575797] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.575834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.592554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.592607] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.592679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.592950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.593061] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.609228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.609276] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.609347] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.626376] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.626413] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.626452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.626486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.626522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.626552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.626582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.626613] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.626648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.626689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.626719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.626757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.626794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.626831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.626885] [drm:intel_power_well_disable [i915]] disabling display
>[  681.627000] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.627065] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.627110] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.627394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.627413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.627496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.627529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.627563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.627600] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.627628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.627662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.627704] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.627725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.627745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.627764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.627788] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.627793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.627818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.627823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.627849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.627875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.627928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.627957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.627988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.628016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.628045] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.628072] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.628098] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.628129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.628162] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.628252] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.628284] [drm:intel_power_well_enable [i915]] enabling display
>[  681.628314] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.628368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.628401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.628431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.628460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.628486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.628513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.628542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.628569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.628596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.628622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.628647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.628676] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.628701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.630748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.630770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.630788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.630808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.632383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.632403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.632421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.634009] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.634031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.635896] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.639231] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.639293] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.639328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.639374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.656072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.656124] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.656190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.656386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.656462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.672748] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.672795] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.672864] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.690021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.690059] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.690098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.690131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.690166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.690196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.690224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.690255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.690297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.690340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.690382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.690424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.690462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.690501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.690556] [drm:intel_power_well_disable [i915]] disabling display
>[  681.690602] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.690652] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.690687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.690858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.690936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.691084] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.691114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.691138] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.691167] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.691192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.691218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.691243] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.691269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.691295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.691321] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.691347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.691353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.691378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.691383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.691408] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.691434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.691460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.691485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.691511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.691537] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.691562] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.691589] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.691614] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.691641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.691670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.691729] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.691751] [drm:intel_power_well_enable [i915]] enabling display
>[  681.691773] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.691812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.691838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.691864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.691893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.691948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.691979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.692013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.692044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.692076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.692102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.692129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.692161] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.692191] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.694251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.694271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.694290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.694308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.695882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.695917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.695936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.697501] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.697522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.699417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.702698] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.702749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.702782] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.702823] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.719530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.719581] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.719647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.719841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.720013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.736205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.736252] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.736322] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.753355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.753397] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.753441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.753482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.753525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.753564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.753603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.753641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.753685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.753727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.753768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.753810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.753848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.753887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.754014] [drm:intel_power_well_disable [i915]] disabling display
>[  681.754082] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.754152] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.754204] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.754462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.754476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  681.754533] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.754559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.754586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.754616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.754638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.754665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.754692] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  681.754718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  681.754744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.754770] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.754794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.754799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.754824] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.754829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.754856] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.754881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.754936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.754966] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  681.754999] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.755028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.755057] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  681.755085] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  681.755112] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  681.755144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.755176] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  681.755265] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.755297] [drm:intel_power_well_enable [i915]] enabling display
>[  681.755327] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.755381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.755413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.755445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.755476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.755497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.755517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.755540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.755560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.755587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.755613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.755639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.755668] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  681.755693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.757739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.757760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.757779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.757798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.759370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.759390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.759408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.760986] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.761007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.762885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.766244] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  681.766335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.766368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  681.766410] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.783111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.783163] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.783229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.783424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  681.783500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.799788] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  681.799839] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  681.799984] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  681.816976] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  681.817014] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  681.817054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.817087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.817122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.817151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.817180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.817212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.817246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.817279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.817310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.817340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.817368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.817395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.817449] [drm:intel_power_well_disable [i915]] disabling display
>[  681.817493] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  681.817544] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  681.817579] [drm:intel_power_well_disable [i915]] disabling always-on
>[  681.820520] [IGT] kms_flip: exiting, ret=0
>[  681.839795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  681.839833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  681.839874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  681.839968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  681.840008] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  681.840049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  681.840089] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  681.840129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  681.840170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  681.840209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  681.840248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  681.840255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.840294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  681.840300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  681.840334] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  681.840355] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  681.840374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  681.840392] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  681.840413] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  681.840431] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  681.840451] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  681.840474] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  681.840497] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  681.840523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  681.840549] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  681.840615] [drm:intel_power_well_enable [i915]] enabling always-on
>[  681.840636] [drm:intel_power_well_enable [i915]] enabling display
>[  681.840656] [drm:hsw_set_power_well [i915]] Enabling power well
>[  681.840695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  681.840719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  681.840743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  681.840767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  681.840790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  681.840814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  681.840840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  681.840865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  681.840915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.840945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  681.840964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  681.840986] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  681.841006] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  681.843072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  681.843091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  681.843108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.843127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  681.844707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  681.844725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  681.844744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  681.846312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  681.846331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  681.848222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  681.851711] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  681.851800] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  681.851825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  681.851861] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  681.851961] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  681.851999] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  681.868599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  681.868648] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  681.868716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  681.868993] Console: switching to colour frame buffer device 240x75
>[  681.975704] Console: switching to colour dummy device 80x25
>[  681.975819] [IGT] kms_flip: executing
>[  681.986785] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  681.986830] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  681.988999] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  681.989035] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  681.991151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  681.991163] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  681.993280] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  681.993319] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  681.995433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  681.995444] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  681.995452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  681.995484] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  681.995529] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  681.996628] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  681.997559] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  681.997580] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  681.997599] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  681.997616] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  681.998623] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  681.998647] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  681.999772] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  681.999776] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  681.999943] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  681.999949] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  681.999959] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  681.999964] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  681.999973] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  681.999978] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  681.999994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  682.000000] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.000006] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  682.000012] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  682.000018] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  682.000024] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  682.000030] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  682.000036] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  682.000042] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  682.000048] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  682.000053] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  682.000059] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  682.000065] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  682.000070] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  682.000077] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  682.000083] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  682.000090] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  682.000095] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  682.000102] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  682.000108] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  682.000114] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  682.000120] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  682.000126] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  682.000132] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  682.000137] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  682.000143] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  682.000149] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  682.000154] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  682.000161] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  682.000167] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  682.000173] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  682.000243] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  682.000276] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  682.001928] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  682.001951] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  682.003933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  682.003940] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  682.005933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  682.005960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  682.007970] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  682.007981] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  682.007989] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  682.010137] [IGT] kms_flip: starting subtest single-buffer-flip-vs-dpms-off-vs-modeset-interruptible
>[  682.010746] [drm:drm_mode_addfb2] [FB:58]
>[  682.010775] [drm:drm_mode_addfb2] [FB:79]
>[  682.064707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.064767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.068738] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.068798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.068882] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.085886] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.085964] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.085997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.086036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.086069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.086104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.086134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.086163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.086195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.086230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.086270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.086298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.086324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.086349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.086373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.086422] [drm:intel_power_well_disable [i915]] disabling display
>[  682.086458] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.086495] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.086525] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.086610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.086726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  682.086820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.086836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.086981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.087024] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.087071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.087119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.087159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.087202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.087243] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.087291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.087328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.087361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.087392] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.087401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.087433] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.087441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.087465] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.087486] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.087506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.087527] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.087550] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.087571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.087590] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  682.087610] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.087629] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.087658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.087697] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.091150] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.091171] [drm:intel_power_well_enable [i915]] enabling display
>[  682.091190] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.091226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.091248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.091272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.091297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.091319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.091343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.091370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.091396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.091422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.091446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.091470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.091495] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  682.091519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.093582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.093604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.093623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.093642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.095210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.095230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.095248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.096801] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.096823] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.098687] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.102029] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  682.102122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.102155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  682.102197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.102278] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  682.102311] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  682.118938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.118988] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.119060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.135728] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.135769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.135809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.135851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.135944] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.135995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.136050] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.136096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.136146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.136189] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.136232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.136245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.136289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.136300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.136347] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.136388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.136430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.136470] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.136517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.136557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.136602] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  682.136642] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.136685] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.136735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.136787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.152264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.152313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.152387] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.170821] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.170865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.170982] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.171039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.171085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.171131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.171173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.171217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.171261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.171312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.171362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.171411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.171452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.171496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.171578] [drm:intel_power_well_disable [i915]] disabling display
>[  682.171640] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.171690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.171740] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.171793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.171839] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.172026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.172046] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.172119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.172141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.172172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.172194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.172213] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.172232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.172252] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.172271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.172289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.172306] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.172322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.172327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.172344] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.172348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.172365] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.172381] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.172398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.172414] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.172434] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.172450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.172468] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  682.172484] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.172500] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.172520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.172541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.172587] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.172605] [drm:intel_power_well_enable [i915]] enabling display
>[  682.172624] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.172660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.172684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.172708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.172731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.172755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.172778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.172803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.172827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.172852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.172919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.172954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.172987] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  682.173019] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.175083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.175105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.175127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.175151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.176724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.176744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.176763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.178317] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.178339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.180201] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.183505] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  682.183584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.183615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  682.183654] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.183727] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  682.183758] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  682.183828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.183876] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.184032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.200524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.200609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.233751] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.233803] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.233880] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.250968] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.251016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.251056] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.251101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.251141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.251185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.251224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.251264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.251301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.251345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.251387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.251429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.251470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.251509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.251547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.251602] [drm:intel_power_well_disable [i915]] disabling display
>[  682.251627] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.251656] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.251677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.251817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.251828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.251959] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.251995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.252032] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.252070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.252101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.252137] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.252170] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.252201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.252233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.252263] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.252293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.252301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.252329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.252336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.252365] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.252396] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.252425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.252454] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.252486] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.252515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.252544] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  682.252573] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.252602] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.252634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.252669] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.252762] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.252794] [drm:intel_power_well_enable [i915]] enabling display
>[  682.252824] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.252899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.252933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.252964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.252995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.253025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.253057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.253093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.253127] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.253160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.253190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.253216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.253253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  682.253284] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.255372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.255393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.255411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.255430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.257016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.257038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.257057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.258609] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.258630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.260506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.263814] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  682.263942] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.263971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  682.264006] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.264084] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  682.264126] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  682.280670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.280720] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.280786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.281075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.281181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.314014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.314062] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.314149] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.331166] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.331210] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.331242] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.331285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.331326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.331369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.331409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.331448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.331486] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.331530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.331571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.331613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.331655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.331693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.331732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.331788] [drm:intel_power_well_disable [i915]] disabling display
>[  682.331834] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.331960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.332014] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.332296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.332317] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.332406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.332429] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.332453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.332479] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.332500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.332522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.332543] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.332563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.332583] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.332601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.332620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.332624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.332642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.332646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.332665] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.332683] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.332702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.332719] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.332741] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.332759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.332779] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  682.332796] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.332815] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.332837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.332861] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.332972] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.333004] [drm:intel_power_well_enable [i915]] enabling display
>[  682.333033] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.333086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.333118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.333149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.333179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.333209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.333240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.333274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.333296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.333316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.333336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.333354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.333377] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  682.333397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.335465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.335486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.335504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.335523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.337106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.337126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.337144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.338703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.338724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.340599] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.343918] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  682.343983] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.344015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  682.344066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.344161] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  682.344212] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  682.360766] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.360815] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.360959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.361264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.361356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.394110] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.394158] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.394243] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.411260] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.411307] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.411347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.411391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.411431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.411475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.411514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.411554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.411593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.411637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.411679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.411720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.411762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.411801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.411839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.411980] [drm:intel_power_well_disable [i915]] disabling display
>[  682.412039] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.412099] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.412146] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.412361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.412377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.412452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.412490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.412535] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.412571] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.412597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.412626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.412654] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.412708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.412749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.412776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.412800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.412806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.412830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.412837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.412861] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.412930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.412958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.412985] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.413014] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.413041] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.413067] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  682.413094] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.413120] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.413151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.413183] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.413274] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.413306] [drm:intel_power_well_enable [i915]] enabling display
>[  682.413336] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.413388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.413420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.413452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.413482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.413504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.413524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.413546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.413566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.413586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.413604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.413622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.413645] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  682.413670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.415716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.415737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.415760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.415784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.417386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.417407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.417425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.419000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.419024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.420907] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.424198] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  682.424288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.424321] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  682.424365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.424448] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  682.424491] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  682.441073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.441122] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.441187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.441436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.441526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.474416] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.474467] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.474557] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.491564] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.491607] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.491640] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.491678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.491711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.491745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.491776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.491805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.491837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.491952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.492006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.492058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.492110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.492153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.492196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.492279] [drm:intel_power_well_disable [i915]] disabling display
>[  682.492342] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.492403] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.492455] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.492707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.492725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.492817] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.492844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.492913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.492953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.492983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.493017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.493047] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.493080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.493109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.493138] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.493164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.493173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.493200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.493208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.493238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.493264] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.493292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.493317] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.493348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.493373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.493400] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  682.493426] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.493453] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.493483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.493515] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.493602] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.493632] [drm:intel_power_well_enable [i915]] enabling display
>[  682.493662] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.493710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.493740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.493767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.493795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.493820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.493850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.493906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.493939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.493972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.493999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.494028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.494063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  682.494092] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.496157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.496178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.496196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.496215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.497776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.497796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.497818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.499431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.499452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.501328] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.504650] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  682.504719] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.504746] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  682.504782] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.504862] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  682.504954] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  682.521495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.521545] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.521610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.521835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.522024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.554835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.554917] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.555006] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.573156] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.573199] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.573232] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.573271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.573303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.573337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.573367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.573396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.573428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.573463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.573496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.573527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.573558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.573586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.573613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.573665] [drm:intel_power_well_disable [i915]] disabling display
>[  682.573705] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.573746] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.573780] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.574447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.574459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.574513] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.574534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.574555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.574579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.574597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.574617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.574637] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  682.574656] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  682.574674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.574696] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.574719] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.574724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.574747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.574751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.574774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.574798] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.574821] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.574844] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  682.574913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.574950] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.574993] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  682.575022] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  682.575053] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  682.575088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.575123] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  682.575478] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.575509] [drm:intel_power_well_enable [i915]] enabling display
>[  682.575540] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.575591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.575622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.575649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.575678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.575705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.575735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.575768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.575799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.575831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.575881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.575911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.575943] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  682.575974] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.578218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.578239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.578257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.578276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.579846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.579883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.579901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.581457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.581479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.583382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.586654] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  682.586705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.586730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  682.586763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.586838] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  682.586926] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  682.603479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.603527] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.603589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.603834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.604171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.636840] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  682.636921] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.637010] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  682.654008] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  682.654051] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  682.654083] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.654121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.654154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.654197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.654237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.654277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.654314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.654358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.654400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.654441] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.654483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.654522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.654561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.654617] [drm:intel_power_well_disable [i915]] disabling display
>[  682.654662] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.654712] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  682.654751] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.655371] [drm:drm_mode_addfb2] [FB:58]
>[  682.655398] [drm:drm_mode_addfb2] [FB:78]
>[  682.688112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  682.688223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.688303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  682.688376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.688388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.688448] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.688470] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.688493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.688520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.688543] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.688568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.688591] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  682.688615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  682.688639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.688662] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.688685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.688690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.688713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.688717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.688741] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.688764] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.688788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.688811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  682.688835] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.688912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.688947] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  682.688977] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  682.689005] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  682.689041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.689077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  682.692497] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.692517] [drm:intel_power_well_enable [i915]] enabling display
>[  682.692534] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.692570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.692590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.692609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.692627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.692644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.692663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.692683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.692702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.692720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.692737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.692754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.692775] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  682.692794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.694898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.694918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.694936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.694955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.696541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.696565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.696589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.698162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.698184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.700055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.703406] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  682.703490] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.703524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  682.703566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.720265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.720315] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.720381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.737060] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.737100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.737140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.737181] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.737214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.737250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.737285] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  682.737319] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  682.737351] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.737382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.737411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.737419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.737448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.737455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.737486] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.737515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.737544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.737573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  682.737608] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.737638] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.737669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  682.737698] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  682.737737] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  682.737788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.737829] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  682.738046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  682.738110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.738212] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  682.754738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  682.754776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.754816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.754849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.754958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.755007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.755055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.755105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.755159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.755195] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.755228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.755256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.755285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.755339] [drm:intel_power_well_disable [i915]] disabling display
>[  682.755380] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.755412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.755446] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.755477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.755508] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.755609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.755628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.755724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.755765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.755807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.755854] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.755942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.755976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.756008] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  682.756037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  682.756066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.756094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.756120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.756128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.756153] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.756161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.756188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.756215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.756241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.756266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  682.756297] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.756324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.756351] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  682.756377] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  682.756404] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  682.756438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.756472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  682.756566] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.756597] [drm:intel_power_well_enable [i915]] enabling display
>[  682.756628] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.756682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.756714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.756745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.756776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.756806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.756838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.756896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.756927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.756958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.756984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.757011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.757043] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  682.757072] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.759141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.759162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.759180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.759199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.760761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.760781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.760799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.762371] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.762392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.764262] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.767602] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  682.767696] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.767729] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  682.767772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.767955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.768031] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.768141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.784619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.784702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.801159] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  682.801204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.801274] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  682.818298] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  682.818334] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.818374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.818408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.818443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.818481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.818521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.818559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.818603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.818645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.818687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.818729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.818767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.818806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.818952] [drm:intel_power_well_disable [i915]] disabling display
>[  682.819019] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.819089] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.819139] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.819424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.819442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.819537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.819567] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.819599] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.819633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.819662] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.819692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.819723] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  682.819753] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  682.819782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.819810] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.819836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.819884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.819914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.819924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.819956] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.819987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.820017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.820047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  682.820078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.820119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.820149] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  682.820180] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  682.820210] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  682.820241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.820277] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  682.820351] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.820382] [drm:intel_power_well_enable [i915]] enabling display
>[  682.820413] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.820464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.820496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.820527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.820557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.820587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.820618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.820652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.820684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.820717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.820746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.820775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.820809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  682.820841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.822929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.822952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.822971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.822991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.824544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.824567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.824590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.826151] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.826173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.828048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.831367] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  682.831432] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.831465] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  682.831504] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.848219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.848269] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.848334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.848552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.848630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.864903] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  682.864955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.865032] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  682.882086] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  682.882124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.882163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.882196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.882230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.882259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.882287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.882318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.882352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.882393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.882435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.882477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.882516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.882555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.882621] [drm:intel_power_well_disable [i915]] disabling display
>[  682.882655] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.882693] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.882718] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.883224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.883247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.883362] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.883404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.883447] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.883493] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.883532] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.883573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.883613] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  682.883655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  682.883685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.883712] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.883740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.883747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.883774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.883781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.883808] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.883835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.883903] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.883935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  682.883966] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.883997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.884028] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  682.884059] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  682.884090] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  682.884125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.884160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  682.884484] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.884515] [drm:intel_power_well_enable [i915]] enabling display
>[  682.884545] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.884596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.884629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.884660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.884691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.884721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.884752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.884786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.884818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.884875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.884905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.884935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.884970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  682.885002] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.887214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.887235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.887253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.887272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.888864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.888904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.888923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.890483] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.890514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.892393] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.895685] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  682.895776] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.895815] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  682.895921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.912553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.912604] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.912669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.912956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.913035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.929254] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  682.929301] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.929387] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  682.946412] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  682.946449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  682.946489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.946522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.946557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.946588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.946617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.946648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.946690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.946733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.946775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.946817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.946931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.946961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.947015] [drm:intel_power_well_disable [i915]] disabling display
>[  682.947060] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  682.947103] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.947136] [drm:intel_power_well_disable [i915]] disabling always-on
>[  682.947287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.947299] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  682.947356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  682.947378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  682.947401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  682.947425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  682.947448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  682.947480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  682.947511] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  682.947532] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  682.947552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  682.947571] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  682.947589] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  682.947594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.947611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  682.947617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  682.947635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  682.947653] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  682.947672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  682.947689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  682.947711] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  682.947728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  682.947747] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  682.947764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  682.947782] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  682.947803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.947826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  682.947935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  682.947962] [drm:intel_power_well_enable [i915]] enabling display
>[  682.947990] [drm:hsw_set_power_well [i915]] Enabling power well
>[  682.948042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  682.948074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  682.948103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  682.948134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  682.948164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  682.948196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  682.948231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  682.948264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  682.948297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.948326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  682.948356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  682.948390] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  682.948423] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  682.950471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  682.950494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  682.950517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.950541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  682.952118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  682.952139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  682.952161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  682.953725] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  682.953748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  682.955624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  682.958927] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  682.959008] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  682.959041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  682.959083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  682.975787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  682.975837] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  682.976100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  682.976341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  682.976430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  682.992485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  682.992531] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  682.992618] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  683.009639] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  683.009676] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.009716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.009749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.009784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.009814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.009922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.009974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.010230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.010257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.010285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.010313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.010338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.010364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.010401] [drm:intel_power_well_disable [i915]] disabling display
>[  683.010431] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.010464] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.010488] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.010657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.010674] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.010728] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.010749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.010771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.010794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.010812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.010832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.010901] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  683.010931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  683.010960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.010988] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.011015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.011024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.011051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.011059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.011086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.011113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.011141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.011167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.011198] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.011224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.011254] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  683.011466] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  683.011485] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  683.011509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.011532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  683.011591] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.011610] [drm:intel_power_well_enable [i915]] enabling display
>[  683.011628] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.011663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.011683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.011702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.011721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.011739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.011759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.011781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.011801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.011821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.011869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.011896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.011928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  683.011957] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.014154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.014175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.014193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.014215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.015834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.015872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.015895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.017463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.017484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.019369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.022436] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  683.022498] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.022536] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  683.022571] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.039278] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.039328] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.039394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.039641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.039731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.055975] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  683.056021] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.056107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  683.073106] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  683.073143] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.073183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.073223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.073266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.073306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.073345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.073382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.073426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.073468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.073509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.073551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.073590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.073629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.073685] [drm:intel_power_well_disable [i915]] disabling display
>[  683.073723] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.073752] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.073771] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.074133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.074145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.074206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.074229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.074253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.074279] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.074298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.074321] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.074342] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  683.074364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  683.074383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.074402] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.074420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.074426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.074443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.074447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.074467] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.074485] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.074503] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.074520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.074543] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.074561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.074580] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  683.074597] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  683.074615] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  683.074636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.074660] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  683.074718] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.074736] [drm:intel_power_well_enable [i915]] enabling display
>[  683.074758] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.074798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.074824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.074885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.074916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.074944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.074973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.075006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.075037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.075067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.075093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.075119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.075151] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  683.075181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.077498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.077519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.077541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.077565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.079141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.079162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.079180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.080742] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.080763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.082637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.085949] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  683.086004] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.086023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  683.086049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.102800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.102921] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.103030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.103298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.103397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.119499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  683.119544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.119631] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  683.136642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  683.136679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.136719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.136752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.136787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.136817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.136924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.136974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.137213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.137252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.137295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.137326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.137359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.137396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.137447] [drm:intel_power_well_disable [i915]] disabling display
>[  683.137489] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.137534] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.137567] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.137769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.137785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.137938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.138107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.138130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.138153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.138171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.138192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.138214] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  683.138238] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  683.138262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.138285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.138307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.138312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.138335] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.138339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.138362] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.138386] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.138409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.138432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.138455] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.138478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.138501] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  683.138524] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  683.138547] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  683.138571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.138596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  683.138652] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.138672] [drm:intel_power_well_enable [i915]] enabling display
>[  683.138692] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.138728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.138751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.138775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.138798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.138822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.138892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.138930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.138962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.138994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.139022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.139048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.139080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  683.139110] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.141438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.141461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.141480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.141499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.143074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.143094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.143112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.144671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.144692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.146566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.149893] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  683.149948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.149980] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  683.150021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.166717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.166765] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.166827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.167266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.167355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.183427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  683.183473] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.183560] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  683.200610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  683.200648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.200687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.200720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.200755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.200785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.200813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.200921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.200979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.201151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.201186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.201217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.201247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.201284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.201318] [drm:intel_power_well_disable [i915]] disabling display
>[  683.201345] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.201372] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.201392] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.201537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.201549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.201603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.201624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.201648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.201672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.201692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.201718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.201744] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  683.201770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  683.201796] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.201821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.201875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.201884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.201913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.201921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.201950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.201978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.202006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.202033] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.202064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.202091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.202118] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  683.202145] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  683.202172] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  683.202203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.202235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  683.202496] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.202515] [drm:intel_power_well_enable [i915]] enabling display
>[  683.202534] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.202570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.202593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.202618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.202648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.202672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.202697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.202726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.202754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.202781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.202807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.202859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.202893] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  683.202922] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.205113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.205134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.205152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.205172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.206740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.206760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.206789] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.208383] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.208404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.210287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.213617] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  683.213654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.213674] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  683.213700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.230449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.230499] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.230566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.230792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.231125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.247145] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  683.247191] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.247277] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  683.264278] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  683.264316] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.264356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.264390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.264424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.264454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.264483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.264515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.264550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.264582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.264621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.264650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.264676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.264701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.264751] [drm:intel_power_well_disable [i915]] disabling display
>[  683.264789] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.264834] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  683.264938] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.265386] [drm:drm_mode_addfb2] [FB:58]
>[  683.265456] [drm:drm_mode_addfb2] [FB:78]
>[  683.298542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  683.298646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  683.298723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.298794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.298846] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.298943] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.298977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.299014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.299051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.299080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.299113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.299143] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.299173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.299201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.299230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.299256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.299263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.299290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.299297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.299325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.299353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.299382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.299408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.299439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.299466] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.299494] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.299519] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.299547] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.299576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.299609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.303060] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.303090] [drm:intel_power_well_enable [i915]] enabling display
>[  683.303107] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.303142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.303166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.303190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.303214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.303237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.303261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.303286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.303311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.303336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.303359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.303382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.303407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.303431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.305719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.305745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.305770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.305803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.307397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.307419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.307442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.309022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.309045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.310924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.314263] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.314374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.314407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.314450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.331153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.331205] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.331271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.348017] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.348066] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.348121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.348163] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.348194] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.348234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.348275] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.348314] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.348355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.348394] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.348432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.348440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.348479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.348485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.348525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.348565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.348604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.348642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.348682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.348720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.348761] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  683.348800] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.348903] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.348958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.349011] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.349149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.349203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.349280] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.366363] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.366401] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.366441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.366474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.366506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.366536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.366565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.366597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.366640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.366670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.366700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.366727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.366753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.366803] [drm:intel_power_well_disable [i915]] disabling display
>[  683.366919] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.366963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.367015] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.367312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.367341] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.367437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.367454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.367537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.367569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.367603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.367650] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.367670] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.367691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.367712] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.367733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.367752] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.367771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.367789] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.367794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.367813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.367848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.367877] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.367904] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.367931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.367957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.367988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.368014] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.368043] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  683.368070] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.368097] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.368128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.368160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.368255] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.368287] [drm:intel_power_well_enable [i915]] enabling display
>[  683.368317] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.368371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.368404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.368435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.368465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.368485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.368506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.368528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.368548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.368568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.368588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.368605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.368629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.368649] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.370698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.370719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.370737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.370756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.372344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.372364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.372382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.373973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.373996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.375866] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.379176] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.379247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.379276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.379313] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.379412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.379461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.379518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.396203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.396304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.412728] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.412773] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.413047] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.430076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.430114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.430153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.430187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.430222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.430253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.430283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.430314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.430349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.430382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.430413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.430453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.430492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.430531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.430587] [drm:intel_power_well_disable [i915]] disabling display
>[  683.430632] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.430683] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.430718] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.431019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.431038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.431131] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.431166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.431201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.431238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.431269] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.431303] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.431335] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.431367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.431400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.431430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.431459] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.431466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.431494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.431501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.431530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.431560] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.431589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.431618] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.431651] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.431680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.431710] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.431740] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.431769] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.431802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.431863] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.431951] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.431982] [drm:intel_power_well_enable [i915]] enabling display
>[  683.432013] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.432064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.432096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.432128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.432159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.432188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.432219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.432253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.432286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.432318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.432348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.432377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.432411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.432442] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.434513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.434537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.434561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.434586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.436166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.436188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.436210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.437829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.437869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.439743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.443080] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.443168] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.443188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.443213] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.459954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.460005] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.460071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.460292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.460393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.476657] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.476704] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.476771] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.493785] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.493822] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.493955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.494007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.494063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.494111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.494159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.494209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.494264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.494316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.494372] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.494412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.494448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.494484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.494552] [drm:intel_power_well_disable [i915]] disabling display
>[  683.494603] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.494654] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.494693] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.494938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.494960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.495074] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.495116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.495160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.495203] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.495228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.495256] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.495283] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.495307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.495331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.495354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.495381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.495386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.495402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.495406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.495423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.495439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.495455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.495471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.495491] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.495508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.495535] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.495559] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.495591] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.495611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.495633] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.495679] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.495699] [drm:intel_power_well_enable [i915]] enabling display
>[  683.495718] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.495754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.495778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.495802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.495874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.495906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.495941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.495977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.496012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.496046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.496076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.496108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.496145] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.496177] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.498249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.498270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.498289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.498307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.499915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.499938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.499961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.501512] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.501534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.503399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.506681] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.506722] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.506748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.506782] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.523510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.523561] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.523627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.523939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.524055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.540199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.540246] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.540315] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.558773] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.558811] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.558929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.558977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.559031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.559074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.559118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.559163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.559216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.559267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.559316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.559365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.559405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.559448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.559528] [drm:intel_power_well_disable [i915]] disabling display
>[  683.559591] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.559651] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.559697] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.559940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.559958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.560053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.560085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.560118] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.560145] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.560163] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.560183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.560203] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.560222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.560240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.560257] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.560273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.560278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.560294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.560297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.560315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.560331] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.560347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.560363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.560382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.560399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.560415] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.560431] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.560447] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.560466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.560487] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.560542] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.560559] [drm:intel_power_well_enable [i915]] enabling display
>[  683.560576] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.560607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.560625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.560642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.560659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.560675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.560693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.560717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.560742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.560775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.560794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.560855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.560887] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.560918] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.562983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.563004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.563023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.563046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.564608] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.564629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.564647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.566209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.566230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.568106] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.571407] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.571490] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.571522] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.571564] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.588257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.588308] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.588375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.588623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.588715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.604969] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.605015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.605085] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.622097] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.622139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.622184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.622225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.622268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.622308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.622347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.622387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.622430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.622472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.622514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.622555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.622594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.622633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.622690] [drm:intel_power_well_disable [i915]] disabling display
>[  683.622735] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.622785] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.622897] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.623139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.623157] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.623247] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.623278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.623312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.623348] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.623377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.623408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.623438] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.623468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.623496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.623527] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.623555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.623562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.623589] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.623595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.623624] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.623649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.623677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.623702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.623733] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.623758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.623786] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.623814] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.623867] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.623898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.623933] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.624022] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.624054] [drm:intel_power_well_enable [i915]] enabling display
>[  683.624084] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.624134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.624164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.624191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.624219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.624245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.624274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.624306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.624338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.624368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.624394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.624421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.624451] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.624481] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.626554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.626576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.626596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.626615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.628200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.628221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.628239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.629818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.629860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.631723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.635088] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.635156] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.635189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.635232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.651934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.651985] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.652051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.652293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.652387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.668632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.668679] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.668745] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.685762] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.685799] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.685923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.685962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.686000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.686030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.686060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.686091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.686135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.686179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.686223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.686267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.686307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.686347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.686406] [drm:intel_power_well_disable [i915]] disabling display
>[  683.686434] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.686465] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.686486] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.686627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.686638] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.686695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.686716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.686741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.686766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.686786] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.686838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.686868] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.686898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.686928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.686955] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.686982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.686990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.687016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.687024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.687051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.687078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.687105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.687131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.687161] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.687187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.687214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.687240] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.687267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.687297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.687329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.687418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.687442] [drm:intel_power_well_enable [i915]] enabling display
>[  683.687460] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.687493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.687513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.687532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.687550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.687569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.687588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.687609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.687629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.687648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.687665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.687683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.687709] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.687736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.689779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.689801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.689865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.689899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.691520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.691549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.691567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.693129] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.693152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.695026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.698328] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.698410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.698442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.698483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.715195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.715246] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.715312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.715561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.715657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.731895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.731943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.732019] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.749061] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.749099] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.749138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.749171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.749205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.749234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.749263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.749294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.749329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.749361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.749392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.749422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.749450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.749477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.749529] [drm:intel_power_well_disable [i915]] disabling display
>[  683.749570] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.749611] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.749642] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.749949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.749968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.750039] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.750062] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.750085] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.750110] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.750130] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.750152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.750173] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.750194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.750213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.750232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.750250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.750256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.750274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.750278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.750297] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.750314] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.750332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.750350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.750371] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.750389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.750407] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.750432] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.750457] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.750485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.750513] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.750581] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.750612] [drm:intel_power_well_enable [i915]] enabling display
>[  683.750633] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.750670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.750691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.750712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.750731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.750751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.750770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.750793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.750846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.750878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.750905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.750932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.750965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.750993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.753059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.753080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.753098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.753117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.754686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.754709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.754738] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.756295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.756316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.758221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.761594] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.761654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.761687] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.761729] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.778431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.778483] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.778549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.778752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.778921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.795107] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.795155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.795241] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.812238] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.812275] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.812314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.812347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.812381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.812411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.812439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.812470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.812504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.812536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.812567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.812598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.812625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.812652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.812707] [drm:intel_power_well_disable [i915]] disabling display
>[  683.812753] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.812803] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.812920] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.813177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.813196] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  683.813284] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.813315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.813348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.813383] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.813411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.813442] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.813471] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  683.813501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  683.813529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.813557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.813583] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.813590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.813616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.813623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.813651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.813677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.813706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.813732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  683.813763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.813788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.813843] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  683.813869] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  683.813899] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  683.813929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.813964] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  683.814052] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.814082] [drm:intel_power_well_enable [i915]] enabling display
>[  683.814111] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.814161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.814191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.814218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.814246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.814272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.814302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.814334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.814365] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.814396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.814422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.814450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.814480] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  683.814511] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.816582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.816605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.816623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.816642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.818220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.818240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.818259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.819881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.819902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.821885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.825211] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  683.825268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.825308] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  683.825334] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.842053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.842103] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.842170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.842394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  683.842474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.858748] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  683.858796] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  683.859126] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  683.876173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  683.876211] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  683.876251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.876284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.876319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.876349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.876378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.876410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.876444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.876476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.876506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.876537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.876574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.876613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.876669] [drm:intel_power_well_disable [i915]] disabling display
>[  683.876715] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  683.876765] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  683.876800] [drm:intel_power_well_disable [i915]] disabling always-on
>[  683.878699] [IGT] kms_flip: exiting, ret=0
>[  683.899724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  683.899763] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  683.899802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  683.899890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  683.899923] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  683.899959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  683.899994] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  683.900026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  683.900058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  683.900088] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  683.900116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  683.900123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.900152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  683.900157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  683.900186] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  683.900215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  683.900243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.900271] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  683.900311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  683.900350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  683.900390] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  683.900430] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  683.900465] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  683.900508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  683.900552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  683.900658] [drm:intel_power_well_enable [i915]] enabling always-on
>[  683.900694] [drm:intel_power_well_enable [i915]] enabling display
>[  683.900727] [drm:hsw_set_power_well [i915]] Enabling power well
>[  683.900790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  683.900857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  683.900889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  683.900909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  683.900928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  683.900947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  683.900969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  683.900989] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  683.901008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.901025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  683.901042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  683.901064] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  683.901084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  683.903145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  683.903164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  683.903182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.903200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  683.904779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  683.904810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  683.904827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  683.906386] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  683.906405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  683.908283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  683.911542] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  683.911611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  683.911639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  683.911684] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  683.911765] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  683.911801] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  683.928411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  683.928459] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  683.928528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  683.928770] Console: switching to colour frame buffer device 240x75
>[  684.034359] Console: switching to colour dummy device 80x25
>[  684.034476] [IGT] kms_flip: executing
>[  684.046663] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  684.046716] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  684.047884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  684.047920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  684.049886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  684.049898] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  684.051886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  684.051928] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  684.053890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  684.053901] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  684.053909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  684.053940] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  684.053982] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  684.055062] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  684.055980] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  684.056001] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  684.056020] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  684.056037] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  684.057053] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  684.057073] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  684.058196] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  684.058200] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  684.058304] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  684.058307] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  684.058313] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  684.058315] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  684.058320] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  684.058322] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  684.058331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  684.058334] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  684.058338] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.058341] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.058344] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  684.058347] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  684.058350] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  684.058352] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  684.058355] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.058358] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.058361] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  684.058364] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  684.058367] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  684.058370] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  684.058373] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  684.058376] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  684.058379] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  684.058382] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  684.058385] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  684.058388] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  684.058391] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  684.058394] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  684.058397] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  684.058400] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  684.058403] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  684.058406] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  684.058409] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  684.058411] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  684.058414] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  684.058417] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  684.058420] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  684.058459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  684.058482] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  684.059847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  684.059870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  684.061901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  684.061911] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  684.063886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  684.063925] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  684.065886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  684.065896] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  684.065904] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  684.066302] [IGT] kms_flip: starting subtest 2x-wf_vblank-ts-check
>[  684.069650] [IGT] kms_flip: exiting, ret=77
>[  684.095336] Console: switching to colour frame buffer device 240x75
>[  684.201070] Console: switching to colour dummy device 80x25
>[  684.201185] [IGT] kms_flip: executing
>[  684.212661] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  684.212714] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  684.214858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  684.214894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  684.217008] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  684.217020] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  684.219139] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  684.219181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  684.221296] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  684.221308] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  684.221316] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  684.221349] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  684.221393] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  684.222495] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  684.223416] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  684.223438] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  684.223457] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  684.223475] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  684.224525] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  684.224548] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  684.225673] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  684.225676] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  684.225837] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  684.225842] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  684.225852] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  684.225856] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  684.225866] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  684.225870] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  684.225887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  684.225893] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  684.225899] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.225905] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.225910] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  684.225916] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  684.225922] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  684.225928] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  684.225933] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.225939] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  684.225945] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  684.225950] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  684.225956] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  684.225962] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  684.225967] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  684.225973] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  684.225979] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  684.225984] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  684.225990] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  684.225996] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  684.226001] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  684.226007] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  684.226013] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  684.226018] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  684.226024] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  684.226030] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  684.226035] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  684.226041] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  684.226047] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  684.226052] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  684.226057] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  684.226126] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  684.226160] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  684.227864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  684.227900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  684.229875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  684.229886] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  684.231870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  684.231907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  684.233875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  684.233885] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  684.233893] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  684.234276] [IGT] kms_flip: starting subtest absolute-wf_vblank
>[  684.235227] [drm:drm_mode_addfb2] [FB:58]
>[  684.235272] [drm:drm_mode_addfb2] [FB:79]
>[  684.288262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  684.288325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  684.295349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  684.295396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  684.295487] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  684.312489] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  684.312533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  684.312566] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  684.312605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  684.312644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  684.312688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  684.312728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  684.312768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  684.312880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  684.312941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  684.312998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  684.313051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  684.313100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  684.313143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  684.313188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  684.313272] [drm:intel_power_well_disable [i915]] disabling display
>[  684.313335] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  684.313399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  684.313451] [drm:intel_power_well_disable [i915]] disabling always-on
>[  684.313588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  684.313723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  684.313854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  684.313874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  684.313971] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  684.314003] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  684.314029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  684.314053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  684.314071] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  684.314091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  684.314114] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  684.314138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  684.314162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  684.314185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  684.314208] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  684.314213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  684.314236] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  684.314240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  684.314263] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  684.314287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  684.314310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  684.314333] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  684.314357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  684.314380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  684.314403] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  684.314427] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  684.314450] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  684.314475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  684.314499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  684.317893] [drm:intel_power_well_enable [i915]] enabling always-on
>[  684.317914] [drm:intel_power_well_enable [i915]] enabling display
>[  684.317933] [drm:hsw_set_power_well [i915]] Enabling power well
>[  684.317971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  684.317996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  684.318021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  684.318045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  684.318070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  684.318094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  684.318121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  684.318146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  684.318172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  684.318196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  684.318220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  684.318246] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  684.318270] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  684.320377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  684.320398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  684.320421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  684.320445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  684.322030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  684.322051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  684.322069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  684.323623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  684.323643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  684.325519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  684.328851] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  684.328885] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  684.328909] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  684.328940] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  684.329005] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  684.329030] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  684.345692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  684.345742] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  684.345894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  694.370436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  694.386961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  694.387010] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  694.387086] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  694.404107] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  694.404150] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  694.404183] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  694.404222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  694.404255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  694.404291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  694.404321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  694.404351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  694.404465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  694.404524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  694.404573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  694.404625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  694.404659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  694.404687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  694.404716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  694.404770] [drm:intel_power_well_disable [i915]] disabling display
>[  694.404811] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  694.404855] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  694.404889] [drm:intel_power_well_disable [i915]] disabling always-on
>[  694.405190] [drm:drm_mode_addfb2] [FB:58]
>[  694.405230] [drm:drm_mode_addfb2] [FB:78]
>[  694.434295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  694.434475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  694.434566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  694.434635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  694.434646] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  694.434704] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  694.434725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  694.434747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  694.434771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  694.434789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  694.434810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  694.434830] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  694.434849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  694.434867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  694.434885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  694.434901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  694.434905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  694.434922] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  694.434925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  694.434942] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  694.434964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  694.434988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  694.435011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  694.435035] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  694.435058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  694.435082] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  694.435105] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  694.435128] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  694.435153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  694.435179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  694.438490] [drm:intel_power_well_enable [i915]] enabling always-on
>[  694.438509] [drm:intel_power_well_enable [i915]] enabling display
>[  694.438526] [drm:hsw_set_power_well [i915]] Enabling power well
>[  694.438562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  694.438582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  694.438600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  694.438623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  694.438646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  694.438670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  694.438695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  694.438720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  694.438745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  694.438768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  694.438791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  694.438816] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  694.438839] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  694.440897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  694.440918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  694.440936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  694.440955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  694.442541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  694.442560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  694.442578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  694.444134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  694.444156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  694.446034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  694.449427] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  694.449519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  694.449550] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  694.449590] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  694.466300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  694.466350] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  694.466515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.491053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.491146] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  704.491197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  704.491275] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  704.509379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  704.509433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  704.509491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.509541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.509594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.509640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.509684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.509731] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.509786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.509836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.509884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.509933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.510050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.510095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.510181] [drm:intel_power_well_disable [i915]] disabling display
>[  704.510248] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  704.510312] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  704.510345] [drm:intel_power_well_disable [i915]] disabling always-on
>[  704.510664] [drm:drm_mode_addfb2] [FB:58]
>[  704.510710] [drm:drm_mode_addfb2] [FB:78]
>[  704.542866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  704.543052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  704.543140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  704.543214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  704.543226] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  704.543285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  704.543307] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  704.543330] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  704.543353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  704.543371] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  704.543391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  704.543414] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  704.543438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  704.543462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  704.543485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  704.543508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  704.543513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.543536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  704.543540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  704.543564] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  704.543587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  704.543610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  704.543633] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  704.543657] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  704.543680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  704.543703] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  704.543726] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  704.543749] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  704.543774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  704.543800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  704.547088] [drm:intel_power_well_enable [i915]] enabling always-on
>[  704.547107] [drm:intel_power_well_enable [i915]] enabling display
>[  704.547124] [drm:hsw_set_power_well [i915]] Enabling power well
>[  704.547160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  704.547180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  704.547199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  704.547217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  704.547239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  704.547263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  704.547290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  704.547314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  704.547339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  704.547362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  704.547385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  704.547410] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  704.547434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  704.549539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  704.549561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  704.549579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.549598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  704.551175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  704.551195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  704.551213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  704.552771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  704.552791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  704.554665] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  704.557956] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  704.558048] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  704.558081] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  704.558122] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  704.574829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  704.574880] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  704.574946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  714.599817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  714.599993] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  714.600081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  714.600222] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  714.617323] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  714.617361] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  714.617401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  714.617435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  714.617469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  714.617499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  714.617528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  714.617649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  714.617712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  714.617766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  714.617817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  714.617870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  714.617915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  714.617960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  714.618041] [drm:intel_power_well_disable [i915]] disabling display
>[  714.618107] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  714.618170] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  714.618220] [drm:intel_power_well_disable [i915]] disabling always-on
>[  714.621238] [IGT] kms_flip: exiting, ret=0
>[  714.640493] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  714.640532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  714.640595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  714.640636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  714.640668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  714.640703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  714.640739] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  714.640779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  714.640820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  714.640859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  714.640898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  714.640906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  714.640945] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  714.640951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  714.640992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  714.641032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  714.641072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  714.641119] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  714.641151] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  714.641179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  714.641211] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  714.641242] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  714.641270] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  714.641304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  714.641339] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  714.641425] [drm:intel_power_well_enable [i915]] enabling always-on
>[  714.641454] [drm:intel_power_well_enable [i915]] enabling display
>[  714.641481] [drm:hsw_set_power_well [i915]] Enabling power well
>[  714.641531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  714.641590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  714.641623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  714.641654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  714.641686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  714.641718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  714.641753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  714.641787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  714.641821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  714.641852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  714.641883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  714.641917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  714.641949] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  714.644056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  714.644077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  714.644095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  714.644114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  714.645698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  714.645715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  714.645737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  714.647310] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  714.647329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  714.649211] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  714.652645] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  714.652678] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  714.652697] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  714.652724] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  714.652789] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  714.652810] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  714.669483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  714.669531] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  714.669637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  714.669880] Console: switching to colour frame buffer device 240x75
>[  714.806292] Console: switching to colour dummy device 80x25
>[  714.806406] [IGT] kms_flip: executing
>[  714.818407] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  714.818460] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  714.819611] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  714.819646] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  714.821592] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  714.821602] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  714.823614] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  714.823653] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  714.825617] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  714.825628] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  714.825636] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  714.825666] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  714.825709] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  714.826816] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  714.827740] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  714.827762] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  714.827780] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  714.827798] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  714.828814] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  714.828837] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  714.829958] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  714.829962] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  714.830064] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  714.830067] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  714.830072] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  714.830074] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  714.830079] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  714.830082] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  714.830091] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  714.830094] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  714.830097] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  714.830100] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  714.830103] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  714.830106] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  714.830109] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  714.830112] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  714.830115] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  714.830118] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  714.830121] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  714.830124] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  714.830127] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  714.830130] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  714.830133] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  714.830135] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  714.830139] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  714.830142] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  714.830145] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  714.830147] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  714.830150] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  714.830153] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  714.830156] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  714.830159] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  714.830162] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  714.830165] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  714.830168] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  714.830171] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  714.830174] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  714.830177] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  714.830179] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  714.830217] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  714.830239] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  714.831579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  714.831602] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  714.833626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  714.833637] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  714.835613] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  714.835651] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  714.837614] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  714.837625] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  714.837632] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  714.839794] [IGT] kms_flip: starting subtest nonexisting-fb-interruptible
>[  714.840424] [drm:drm_mode_addfb2] [FB:77]
>[  714.840451] [drm:drm_mode_addfb2] [FB:79]
>[  714.894235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.894300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  714.902985] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  714.903034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  714.903113] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  714.921444] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  714.921489] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  714.921523] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  714.921644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  714.921697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  714.921754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  714.921802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  714.921840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  714.921873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  714.921910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  714.921952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  714.921996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  714.922045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  714.922065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  714.922084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  714.922135] [drm:intel_power_well_disable [i915]] disabling display
>[  714.922163] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  714.922193] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  714.922215] [drm:intel_power_well_disable [i915]] disabling always-on
>[  714.922286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  714.922375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  714.922457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.922469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  714.922568] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  714.922600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  714.922633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  714.922668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  714.922696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  714.922727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  714.922757] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  714.922787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  714.922818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  714.922845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  714.922873] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  714.922881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  714.922907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  714.922915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  714.922942] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  714.922971] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  714.922999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  714.923027] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  714.923057] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  714.923083] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  714.923112] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  714.923142] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  714.923171] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  714.923203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  714.923237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  714.926608] [drm:intel_power_well_enable [i915]] enabling always-on
>[  714.926628] [drm:intel_power_well_enable [i915]] enabling display
>[  714.926645] [drm:hsw_set_power_well [i915]] Enabling power well
>[  714.926679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  714.926703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  714.926727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  714.926750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  714.926774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  714.926797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  714.926822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  714.926847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  714.926872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  714.926895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  714.926917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  714.926942] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  714.926966] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  714.929015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  714.929036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  714.929055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  714.929074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  714.930642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  714.930662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  714.930680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  714.932225] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  714.932246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  714.934107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  714.937369] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  714.937425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  714.937449] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  714.937480] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  714.937585] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  714.937621] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  714.954217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  714.954264] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  714.954328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  714.970887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.970894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.970926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.970931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.970973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.970978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.971982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.971987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.972982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.972986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.973982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.973988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.974986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.974991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.975985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.975990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.976949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.976955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.977964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.977969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.978982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.978988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.979977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.979982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.980981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.980986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.981985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.981990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.982994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.982999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.983972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.983977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.984987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.984992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.985981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.985984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.986976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.986982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.987988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.987994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.988975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.988980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.989994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.989997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.990970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.990976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.991990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.991995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.992979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.992984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.993978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.993983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.994990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.994994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.995983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.995988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.996962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.996967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.997963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.997968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.998964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.998971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  714.999951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  714.999957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.000970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.000999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.001990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.001995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.002994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.002998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.003960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.003966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.004969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.004974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.005965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.005971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.006965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.006996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.007986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.007991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.008993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.008996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.009971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.009976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.010983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.010986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.011976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.011982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.012979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.012984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.013980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.013985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.014966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.014999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.015943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.015995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.016974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.016979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.017949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.017997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.018970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.018976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.019986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.019989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.020978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.020983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.021994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.021997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.022987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.022993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.023979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.023982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.024991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.024996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.025992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.025995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.026980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.026985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.027994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.027997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.028990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.028996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.029979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.029998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.030983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.030988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.031954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.031959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.032969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.032975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.033970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.033975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.034993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.034998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.035978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.035982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.036994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.036997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.037993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.037996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.038973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.038978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.039980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.039983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.040978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.040983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.041989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.041992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.042980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.042985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.043974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.043979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.044963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.044969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.045963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.045969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.046979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.046982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.047966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.047971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.048970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.048997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.049989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.049994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.050978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.050981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.051975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.051980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.052954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.052960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.053975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.053980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.054988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.054994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.055985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.055992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.056991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.056994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.057970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.057976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.058971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.058976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.059984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.059988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.060996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.060999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.061979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.061984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.062985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.062989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.063963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.063968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.064986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.064989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.065957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.065962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.066987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.066990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.067984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.067989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.068982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.068985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.069981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.069987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.070955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.070961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.071962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.071967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.072972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.072977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.073994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.073997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.074980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.074985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.075989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.075992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.076978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.076984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.077964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.077969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.078949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.078998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.079989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.079993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.080943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.080948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.081983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.081986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.082987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.082992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.083994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.083997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.084985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.084990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.085993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.085996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.086973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.086977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.087978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.087982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.088979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.088985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.089965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.089970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.090958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.090964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.091995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.091998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.092990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.092995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.093971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.093998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.094990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.094995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.095963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.095996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.096994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.096997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.097963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.097969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.098991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.098994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.099952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.099958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.100968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.100999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.101969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.101974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.102975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.102979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.103963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.103968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.104982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.104985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.105966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.105971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.106986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.106990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.107991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.107996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.108988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.108991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.109987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.109992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.110984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.110987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.111994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.111997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.112994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.112997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.113969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.113974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.114972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.114977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.115968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.115973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.116972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.116977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.117988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.117993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.118963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.118997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.119981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.119987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.120964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.120997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.121991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.121996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.122961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.122967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.123991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.123994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.124983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.124989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.125993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.125996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.126964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.126969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.127969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.127998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.128975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.128980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.129983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.129986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.130972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.130978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.131986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.131989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.132960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.132965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.133991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.133995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.134962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.134998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.135989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.135994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.136952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.136999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.137984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.137987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.138967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.138972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.139984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.139987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.140954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.140960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.141984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.141988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.142949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.142997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.143993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.143996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.144951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.144956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.145949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.145997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.146990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.146994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.147952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.147957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.148975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.148979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.149984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.149989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.150975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.150978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.151955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.151960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.152987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.152992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.153989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.153995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.154996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.154999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.155974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.155979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.156996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.156999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.157957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.157963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.158973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.158979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.159962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.159995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.160972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.160976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.161979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.161985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.162978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.162981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.163973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.163978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.164950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.164999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.165966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.165971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.166970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.166997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.167987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.167993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.168971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.168997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.169990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.169994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.170965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.170970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.171987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.171990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.172975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.172980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.173991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.173994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.174983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.174989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.175988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.175991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.176948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.176953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.177978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.177981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.178989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.178994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.179973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.179976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.180953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.180958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.181991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.181994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.182977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.182983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.183984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.183987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.184986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.184991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.185981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.185984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.186991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.186995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.187974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.187977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.188949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.188955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.189973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.189976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.190947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.190996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.191988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.191991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.192986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.192991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.193972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.193977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.194972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.194977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.195969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.195974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.196962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.196967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.197976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.197982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.198994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.198998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.199945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.199996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.200981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.200984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.201969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.201975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.202991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.202994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.203963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.203968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.204971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.204976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.205950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.205955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.206975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.206978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.207954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.207998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.208963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.208998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.209960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.209965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.210984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.210988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.211979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.211984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.212963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.212995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.213972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.213977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.214972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.214976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.215985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.215990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.216947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.216952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.217991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.217994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.218950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.218956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.219996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.219998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.220986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.220990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.221947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.221997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.222978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.222983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.223990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.223993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.224993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.224998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.225981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.225984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.226965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.226996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.227971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.227997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.228975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.228980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.229976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.229979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.230993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.230998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.231986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.231989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.232991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.232997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.233956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.233962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.234963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.234968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.235994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.235997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.236977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.236982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.237994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.237998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.238989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.238995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.239975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.239978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.240985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.240988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.241971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.241998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.242965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.242970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.243980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.243983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.244979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.244986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.245989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.245992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.246973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.246978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.247967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.247999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.248976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.248981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.249948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.249999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.250974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.250977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.251987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.251993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.252964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.252969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.253990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.253996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.254969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.254974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.255983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.255989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.256979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.256997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.257948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.257953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.258977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.258980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.259956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.259961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.260976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.260981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.261985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.261988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.262987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.262993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.263979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.263998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.264949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.264954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.265971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.265976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.266992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.266995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.267953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.267958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.268991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.268994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.269946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.269951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.270980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.270985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.271963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.271998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.272951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.272956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.273950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.273956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.274992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.274997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.275972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.275975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.276975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.276980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.277992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.277995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.278960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.278965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.279995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.279998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.280950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.280996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.281995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.281998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.282980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.282985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.283979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.283985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.284939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.284997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.285992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.285995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.286974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.286979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.287976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.287979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.288976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.288982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.289986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.289989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.290947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.290952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.291988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.291991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.292996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.292999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.293985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.293990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.294972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.294977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.295980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.295986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.296979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.296982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.297983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.297986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.298981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.298986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.299948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.299954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.300985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.300988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.301984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.301989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.302993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.302996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.303981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.303986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.304967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.304972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.305991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.305997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.306987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.306990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.307978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.307984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.308970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.308975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.309977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.309981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.310968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.310998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.311947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.311952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.312988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.312990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.313993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.313996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.314983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.314988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.315994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.315997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.316963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.316996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.317961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.317966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.318965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.318970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.319988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.319994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.320969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.320972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.321951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.321996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.322978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.322981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.323966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.323971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.324951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.324957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.325959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.325999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.326951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.326997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.327995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.327998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.328950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.328997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.329973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.329976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.330958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.330963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.331984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.331988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.332966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.332998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.333973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.333977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.334993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.334998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.335981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.335984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.336988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.336993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.337984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.337987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.338982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.338985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.339980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.339984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.340968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.340974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.341956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.341961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.342962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.342998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.343969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.343975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.344992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.344995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.345954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.345959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.346978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.346997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.347957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.347962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.348983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.348987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.349984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.349989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.350957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.350962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.351978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.351984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.352963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.352968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.353971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.353976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.354993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.354996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.355962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.355994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.356991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.356993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.357974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.357979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.358990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.358993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.359962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.359967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.360984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.360989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.361980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.361986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.362988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.362993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.363988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.363993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.364956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.364961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.365971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.365976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.366973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.366979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.367996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.367999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.368994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.368998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.369962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.369967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.370991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.370994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.371950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.371999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.372991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.372994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.373950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.373956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.374973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.374978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.375974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.375979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.376944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.376994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.377979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.377982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.378945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.378995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.379987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.379990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.380988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.380994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.381988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.381991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.382975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.382980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.383986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.383990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.384983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.384988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.385984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.385987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.386967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.386972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.387965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.387970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.388992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.388997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.389972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.389999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.390972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.390977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.391988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.391992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.392950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.392955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.393980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.393984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.394969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.394974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.395972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.395975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.396991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.396995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.397950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.397956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.398996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.398999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.399953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.399959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.400986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.400990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.401975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.401980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.402965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.402998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.403993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.403998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.404959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.404964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.405979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.405984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.406965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.406970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.407970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.407976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.408951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.408956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.409945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.409995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.410976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.410981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411931] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.411936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.411998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.412988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.412991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.413948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.413997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.414979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.414983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.415955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.415960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.416980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.416983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.417959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.417999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.418972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.418999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.419991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.419996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.420995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.420998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.421968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.421973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.422988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.422992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.423946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.423951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.424990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.424993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.425949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.425955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.426965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.426970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.427990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.427994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.428990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.428995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.429988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.429991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.430972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.430977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.431971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.431998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.432980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.432985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.433991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.433994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.434965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.434970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.435993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.435996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.436968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.436974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.437980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.437983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.438953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.438958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.439965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.439970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.440995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.440999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.441963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.441969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442935] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.442971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.442976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.443972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.443976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.444963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.444968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.445977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.445980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.446984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.446989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.447984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.447988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.448995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.448999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.449965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.449997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.450967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.450972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.451979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.451984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.452981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.452984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.453949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.453954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.454975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.454980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.455961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.455966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.456972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.456977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.457962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.457967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.458985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.458989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.459987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.459993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.460985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.460990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.461948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.461954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.462974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.462978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.463956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.463961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.464995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.464998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.465990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.465997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.466968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.466973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.467993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.467998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.468977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.468980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.469989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.469994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.470854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.470859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.471018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  715.471228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  715.471258] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  715.471319] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  715.490167] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  715.490195] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  715.490216] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  715.490242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  715.490264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  715.490288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  715.490308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  715.490327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  715.490347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  715.490370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  715.490397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  715.490425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  715.490453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  715.490478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  715.490534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  715.490592] [drm:intel_power_well_disable [i915]] disabling display
>[  715.490638] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  715.490682] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  715.490719] [drm:intel_power_well_disable [i915]] disabling always-on
>[  715.490955] [drm:drm_mode_addfb2] [FB:77]
>[  715.490987] [drm:drm_mode_addfb2] [FB:78]
>[  715.526346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  715.526450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.526576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  715.526770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.526783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  715.526847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  715.526870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  715.526895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  715.526921] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  715.526941] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  715.526967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  715.526993] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  715.527018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  715.527044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  715.527069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  715.527094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  715.527099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  715.527124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  715.527128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  715.527154] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  715.527180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  715.527205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  715.527230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  715.527255] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  715.527280] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  715.527306] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  715.527331] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  715.527357] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  715.527384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  715.527411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  715.530822] [drm:intel_power_well_enable [i915]] enabling always-on
>[  715.530843] [drm:intel_power_well_enable [i915]] enabling display
>[  715.530862] [drm:hsw_set_power_well [i915]] Enabling power well
>[  715.530900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  715.530923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  715.530944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  715.530964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  715.530983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  715.531003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  715.531025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  715.531046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  715.531066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  715.531084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  715.531101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  715.531124] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  715.531149] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  715.533179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  715.533205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  715.533231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  715.533257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  715.534813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  715.534835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  715.534856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  715.536383] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  715.536406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  715.538254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  715.541270] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  715.541320] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  715.541341] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  715.541369] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  715.558069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  715.558104] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  715.558151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  715.574774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.574809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.574840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.574871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.574902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.574923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.574945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.574975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.574978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.575965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.575970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.576985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.576988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.577994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.577997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.578945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.578951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.579966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.579999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.580982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.580985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.581972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.581977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.582985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.582989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.583985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.583989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.584972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.584978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.585989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.585992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.586981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.586987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.587984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.587987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.588949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.588996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.589985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.589988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.590970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.590975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.591989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.591993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.592982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.592986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.593988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.593991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.594978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.594983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.595973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.595976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.596990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.596995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.597973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.597977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.598970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.598998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.599948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.599953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.600971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.600975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.601965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.601998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.602971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.602996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.603991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.603994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.604995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.604998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.605982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.605985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.606971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.606976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.607992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.607996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.608974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.608977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.609993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.609996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.610971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.610974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.611956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.611961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.612979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.612998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.613982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.613986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.614980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.614986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.615971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.615974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.616960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.616966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.617978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.617983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.618957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.618962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.619975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.619979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.620966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.620999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.621967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.621972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.622962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.622969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.623993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.623996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.624934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.624940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.625970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.625998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.626980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.626986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.627991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.627994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.628960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.628965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.629987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.629990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.630988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.630994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.631994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.631997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.632972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.632975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.633987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.633991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.634963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.634969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.635988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.635991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.636947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.636953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.637980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.637983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.638994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.638997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.639948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.639954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.640969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.640972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.641985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.641991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.642991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.642994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.643948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.643999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.644994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.644997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.645946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.645951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.646991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.646994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.647992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.647997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.648975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.648978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.649947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.649953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.650992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.650995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.651983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.651988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.652992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.652995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.653989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.653994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.654993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.654996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.655975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.655978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.656989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.656991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.657954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.657999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.658957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.658997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.659986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.659992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.660993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.660995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.661990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.661995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.662978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.662981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.663948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.663954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.664991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.664994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.665968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.665974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.666970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.666975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.667993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.667996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.668979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.668985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.669984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.669988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.670957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.670962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.671980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.671983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.672982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.672987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.673990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.673993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.674946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.674952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.675981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.675983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.676968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.676975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.677991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.677994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.678986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.678989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.679970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.679976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.680979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.680983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.681995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.681998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.682995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.682998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.683997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.683999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.684984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.684987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.685971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.685999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.686970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.686975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.687995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.687998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.688987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.688993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.689970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.689975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.690988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.690991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.691970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.691975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.692972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.692975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.693973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.693978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.694971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.694974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.695969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.695974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.696994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.696997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.697948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.697953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.698980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.698983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.699979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.699985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.700978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.700981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.701964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.701970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.702966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.702997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.703954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.703996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.704983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.704986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.705951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.705997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.706978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.706982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.707983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.707985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.708991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.708994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.709986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.709992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.710985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.710988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.711979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.711984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.712987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.712990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.713991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.713994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.714970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.714999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.715974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.715980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.716951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.716999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.717997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.717999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.718972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.718977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.719970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.719997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.720962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.720994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.721971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.721974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.722962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.722967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.723996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.723999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.724954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.724959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.725991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.725994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.726976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.726981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.727987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.727991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.728963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.728968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.729985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.729988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.730981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.730985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.731989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.731992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.732970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.732973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.733992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.733996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.734971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.734999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.735992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.735995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.736972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.736999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.737957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.737997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.738987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.738990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.739958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.739999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.740991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.740995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.741995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.741999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.742971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.742997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.743961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.743967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.744988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.744991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.745991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.745997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.746980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.746999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.747992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.747995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.748989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.748992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.749970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.749975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.750981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.750984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.751992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.751997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.752992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.752996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.753939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.753945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.754993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.754997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.755976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.755980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.756968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.756973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.757978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.757981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.758993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.758995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.759979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.759997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.760991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.760995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.761980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.761984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.762987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.762990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.763971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.763998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.764987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.764990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.765990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.765993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.766977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.766981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.767968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.767973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.768962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.768967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.769984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.769987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.770966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.770971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.771988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.771991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.772945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.772951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.773979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.773983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.774983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.774987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.775987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.775990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.776987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.776992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.777952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.777999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.778988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.778993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.779984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.779989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.780983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.780988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.781976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.781979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.782962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.782968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.783986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.783989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.784993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.784996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.785987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.785990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.786987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.786989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.787991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.787994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.788981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.788986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.789986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.789989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.790982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.790988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.791992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.791995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.792975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.792978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.793979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.793984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.794971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.794974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.795966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.795971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.796971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.796998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.797960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.797966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.798980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.798983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.799979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.799999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.800951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.800997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.801963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.801968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.802991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.802994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.803945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.803951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.804980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.804983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.805956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.805961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.806980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.806983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.807991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.807994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.808976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.808979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.809989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.809992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.810985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.810988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.811985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.811989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.812982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.812985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.813958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.813963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.814981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.814984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.815982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.815985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.816993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.816996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.817981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.817986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.818959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.818998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.819952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.819958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.820964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.820997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.821983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.821986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.822944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.822995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.823984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.823987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.824986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.824991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.825981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.825986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.826975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.826981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.827975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.827980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.828966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.828972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.829976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.829979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.830969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.830975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.831996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.831999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.832986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.832989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.833990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.833993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.834986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.834989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.835969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.835974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.836973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.836979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.837980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.837984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.838979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.838982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.839956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.839961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.840955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.840961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.841992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.841995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.842980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.842985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.843966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.843972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.844982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.844985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.845945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.845996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.846981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.846984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.847980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.847986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.848968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.848973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.849965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.849970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.850991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.850994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.851993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.851997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.852971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.852998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.853965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.853970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.854993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.854997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.855940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.855999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.856961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.856966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.857993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.857996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.858972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.858975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.859964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.859996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.860973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.860998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.861986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.861989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.862992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.862996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.863989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.863992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.864972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.864975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.865983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.865988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.866972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.866975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.867982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.867985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.868995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.868998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.869982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.869985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.870956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.870961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.871971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.871998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.872963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.872968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.873973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.873999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.874966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.874971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.875984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.875987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.876992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.876997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.877990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.877994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.878989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.878994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.879988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.879993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.880988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.880991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.881990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.881993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.882992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.882997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.883987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.883990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.884972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.884975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.885991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.885994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.886992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.886995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.887988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.887991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.888990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.888993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.889971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.889997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.890979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.890982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.891960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.891998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.892977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.892979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.893989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.893992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.894970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.894974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.895970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.895975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.896993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.896996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.897952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.897957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.898956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.898973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.899993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.899996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.900979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.900982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.901950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.901955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.902949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.902955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.903977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.903983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.904988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.904991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.905995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.905998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.906990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.906993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.907993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.907998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.908969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.908974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.909980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.909983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.910987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.910990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.911989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.911992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.912978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.912981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.913976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.913981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.914982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.914985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.915970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.915975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.916981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.916984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.917987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.917990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.918995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.918998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.919967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.919973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.920992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.920996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.921988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.921991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.922976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.922981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.923988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.923991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.924970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.924976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.925977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.925980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.926964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.926969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.927971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.927997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.928958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.928964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.929971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.929997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.930957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.930962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.931992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.931996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.932940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.932945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.933977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.933980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.934977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.934980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.935986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.935989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.936970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.936975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.937972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.937975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.938964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.938970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.939973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.939998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.940988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.940991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.941980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.941983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.942981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.942984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.943970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.943974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.944976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.944979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.945987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.945990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.946991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.946997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.947985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.947988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.948971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.948999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.949987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.949992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.950987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.950990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.951944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.951949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.952978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.952982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.953975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.953980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.954993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.954997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.955959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.955965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.956992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.956995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.957970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.957975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.958974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.958977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.959986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.959991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.960990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.960993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.961987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.961990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.962973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.962999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.963996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.963999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.964980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.964983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.965993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.965996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.966979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.966982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.967980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.967983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.968989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.968992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.969990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.969996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.970982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.970985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.971977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.971983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.972980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.972985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.973988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.973991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.974945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.974950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.975977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.975980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.976979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.976985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.977994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.977997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.978955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.978997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.979986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.979989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.980977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.980982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.981981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.981984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.982993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.982998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.983977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.983980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.984967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.984973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.985990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.985993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.986982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.986985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.987995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.987998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.988976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.988981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.989983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.989986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.990979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.990998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.991975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.991979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.992965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.992970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.993976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.993979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.994980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.994983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.995990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.995993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.996995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.996998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.997986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.997991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.998995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.998999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  715.999961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  715.999966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.000971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.000999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.001988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.001993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.002972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.002975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.003964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.003969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.004971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.004998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.005969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.005974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.006989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.006992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.007946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.007952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.008993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.008996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.009987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.009990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.010989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.010992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.011958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.011961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.012980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.012985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.013985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.013988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.014962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.014968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.015994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.015997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.016979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.016982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.017989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.017993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.018974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.018977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.019972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.019976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.020994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.020997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.021982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.021999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.022994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.022999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.023975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.023977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.024996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.024999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.025990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.025993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.026968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.026998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.027987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.027990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.028962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.028997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.029995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.029998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.030958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.030963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.031979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.031983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.032954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.032959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.033993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.033996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.034980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.034985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.035971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.035974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.036962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.036968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.037985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.037989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.038989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.038992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.039986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.039989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.040978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.040981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.041987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.041990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.042957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.042962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.043977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.043980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.044996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.044999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.045971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.045974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.046994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.046997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.047983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.047986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.048974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.048980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.049964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.049998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.050975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.050978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.051984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.051989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.052988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.052991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.053946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.053951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.054987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.054990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.055981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.055987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.056975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.056979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.057950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.057955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.058977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.058980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.059970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.059975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.060995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.060998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.061951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.061957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.062968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.062973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.063979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.063981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.064980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.064983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.065972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.065975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.066996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.066999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.067972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.067999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.068975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.068978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.069988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.069991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.070995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.070998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.071979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.071982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.072995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.072998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.073979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.073982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.074696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.074852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  716.074940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  716.074976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  716.075039] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  716.075596] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  716.075631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  716.075669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  716.075703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  716.075732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  716.075752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  716.075771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  716.075792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  716.075815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  716.075837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  716.075858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  716.075885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.075911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  716.075936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  716.075974] [drm:intel_power_well_disable [i915]] disabling display
>[  716.076005] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  716.076038] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  716.076062] [drm:intel_power_well_disable [i915]] disabling always-on
>[  716.076258] [drm:drm_mode_addfb2] [FB:77]
>[  716.076288] [drm:drm_mode_addfb2] [FB:78]
>[  716.112428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  716.112667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  716.112759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.112833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.112847] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  716.112911] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  716.112935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  716.112960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  716.112985] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  716.113005] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  716.113027] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  716.113050] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  716.113071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  716.113091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  716.113110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  716.113128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  716.113133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  716.113152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  716.113157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  716.113175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  716.113195] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  716.113212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  716.113230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  716.113252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  716.113270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  716.113288] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  716.113306] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  716.113323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  716.113344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  716.113368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  716.116776] [drm:intel_power_well_enable [i915]] enabling always-on
>[  716.116798] [drm:intel_power_well_enable [i915]] enabling display
>[  716.116816] [drm:hsw_set_power_well [i915]] Enabling power well
>[  716.116857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  716.116883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  716.116910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  716.116936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  716.116962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  716.116988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  716.117016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  716.117044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  716.117072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.117098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  716.117123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  716.117151] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  716.117177] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  716.119204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  716.119227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  716.119248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  716.119269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  716.120811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  716.120832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  716.120853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  716.122380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  716.122403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  716.124244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  716.127259] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  716.127310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  716.127335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  716.127370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  716.144060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  716.144095] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  716.144143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.160774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.160814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.160835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.160856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.160885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.160914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.160943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.160973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.160975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.161991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.161996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.162995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.162998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.163992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.163995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.164996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.164999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.165995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.165998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.166951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.166956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.167983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.167986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.168950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.168955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.169987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.169990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.170958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.170964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.171986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.171989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.172961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.172966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.173975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.173978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.174984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.174987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.175991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.175994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.176985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.176988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.177971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.177974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.178984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.178987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.179988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.179991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.180969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.180975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.181985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.181988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.182976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.182979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.183982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.183988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.184975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.184978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.185970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.185973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.186981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.186999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.187981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.187984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.188978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.188981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.189995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.189998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.190985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.190988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.191991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.191994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.192989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.192992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.193982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.193985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.194974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.194999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.195971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.195974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.196977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.196982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.197971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.197997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.198959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.198964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.199987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.199990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.200986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.200991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.201985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.201988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.202968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.202973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.203995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.203998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.204995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.204998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.205979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.205982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.206980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.206983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.207962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.207999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.208959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.208965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.209989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.209992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.210973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.210976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.211979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.211982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.212988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.212991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.213986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.213989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.214987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.214990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.215976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.215979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.216970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.216976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.217995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.217998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.218993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.218996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.219971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.219999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.220995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.220998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.221976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.221982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.222996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.222999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.223965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.223971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.224988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.224992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.225977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.225982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.226994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.226997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.227989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.227993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.228984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.228986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.229949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.229955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.230973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.230999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.231968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.231973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.232991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.232994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.233952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.233996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.234958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.234963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.235995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.235999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.236970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.236973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.237974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.237977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.238988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.238991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.239997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.239999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.240992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.240997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.241986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.241989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.242979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.242982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.243992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.243995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.244996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.244999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.245976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.245981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.246971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.246974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.247985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.247988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.248966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.248972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.249969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.249973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.250991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.250994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.251972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.251998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.252975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.252978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.253978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.253981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.254977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.254980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.255984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.255987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.256975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.256979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.257970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.257973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.258989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.258993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.259984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.259987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.260994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.260997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.261971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.261974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.262994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.262997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.263986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.263989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.264972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.264975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.265983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.265986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.266953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.266997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.267988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.267991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.268981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.268999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.269975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.269978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.270991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.270994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.271968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.271974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.272968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.272973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.273993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.273996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.274971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.274974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.275973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.275978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.276974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.276978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.277981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.277986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.278994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.278997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.279993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.279998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.280980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.280985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.281978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.281998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.282973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.282976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.283960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.283965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.284986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.284989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.285987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.285990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.286994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.286997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.287993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.287996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.288972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.288975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.289990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.289993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.290990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.290993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.291989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.291992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.292990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.292993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.293996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.293999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.294972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.294975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.295983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.295985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.296973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.296978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.297977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.297980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.298991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.298996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.299990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.299993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.300955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.300960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.301994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.301997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.302985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.302990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.303980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.303983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.304982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.304985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.305994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.305997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.306967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.306972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.307976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.307980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.308767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.308772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.309996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.309999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.310986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.310989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.311990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.311993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.312963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.312968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.313991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.313994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.314988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.314992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.315973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.315976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.316986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.316989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.317993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.317996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.318970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.318998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.319991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.319994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.320984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.320987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.321973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.321976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.322984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.322987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.323987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.323989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.324993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.324996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.325963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.325997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.326980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.326983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.327959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.327964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.328992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.328995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.329983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.329988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.330979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.330982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.331989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.331993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.332985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.332988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.333945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.333950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.334973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.334976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.335967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.335972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.336994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.336997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.337992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.337995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.338969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.338972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.339985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.339988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.340973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.340999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.341986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.341989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.342980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.342983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.343971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.343999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.344979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.344982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.345983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.345986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.346978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.346981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.347976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.347979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.348978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.348981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.349994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.349997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.350971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.350999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.351995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.351998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.352989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.352992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.353991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.353994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.354983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.354988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.355977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.355981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.356981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.356984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.357970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.357998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.358969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.358972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.359979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.359982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.360992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.360997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.361995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.361998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.362984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.362987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.363971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.363999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.364971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.364997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.365979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.365982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.366990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.366993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.367970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.367997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.368959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.368964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.369994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.369997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.370975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.370978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.371977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.371982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.372994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.372997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.373989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.373995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.374993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.374996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.375996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.375999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.376992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.376995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.377957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.377963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.378984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.378987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.379970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.379976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.380950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.380956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.381984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.381987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.382992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.382995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.383968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.383998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.384980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.384984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.385985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.385989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.386995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.386998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.387972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.387976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.388987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.388990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.389983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.389986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.390975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.390978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.391980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.391999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.392980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.392983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.393982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.393985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.394975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.394978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.395971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.395998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.396981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.396984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.397979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.397982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.398991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.398994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.399994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.399997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.400986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.400989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.401971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.401974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.402994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.402997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.403971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.403998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.404966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.404999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.405985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.405988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.406945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.406950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.407973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.407998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.408971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.408977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.409972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.409974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.410972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.410977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.411985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.411988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.412954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.412960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.413981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.413983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.414981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.414984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.415993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.415996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.416993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.416996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.417994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.417997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.418971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.418974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.419982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.419986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.420983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.420987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.421971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.421974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.422976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.422979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.423995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.423998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.424988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.424991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.425990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.425994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.426990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.426994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.427991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.427996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.428970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.428998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.429989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.429992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.430992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.430995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.431996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.431999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.432977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.432980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.433992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.433997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.434979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.434982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.435986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.435989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.436994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.436997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.437938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.437996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.438982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.438985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.439994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.439998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.440972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.440975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.441984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.441987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.442980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.442983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.443979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.443982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.444972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.444997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.445993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.445996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.446980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.446983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.447976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.447980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.448971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.448999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.449973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.449977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.450995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.450999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.451979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.451998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.452963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.452998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.453977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.453979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.454961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.454966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.455982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.455985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.456993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.456999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.457995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.457998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.458967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.458973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.459988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.459991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.460989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.460993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.461980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.461983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.462972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.462998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.463997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.463999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.464978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.464982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.465985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.465988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.466980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.466998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.467973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.467976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.468983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.468986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.469973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.469975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.470990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.470993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.471976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.471999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.472987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.472990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.473988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.473991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.474981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.474984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.475968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.475973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.476985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.476988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.477950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.477997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.478993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.478996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.479985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.479988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.480979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.480984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.481978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.481984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.482977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.482980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.483944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.483995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.484984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.484987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.485982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.485985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.486987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.486990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.487954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.487999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.488978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.488984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.489963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.489968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.490992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.490995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.491993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.491996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.492979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.492982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.493994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.493997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.494980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.494983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.495980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.495983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.496974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.496977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.497968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.497973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.498971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.498974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.499914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.499919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.500984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.500987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.501986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.501989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.502984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.502987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.503982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.503985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.504945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.504950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.505992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.505996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.506964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.506970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.507984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.507987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.508766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.508771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.509989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.509992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.510955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.510960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.511976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.511979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512872] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.512958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.512964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.513973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.513999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.514972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.514977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.515988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.515991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.516993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.516996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.517977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.517981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.518981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.518984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.519989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.519993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.520971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.520975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.521984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.521988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.522994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.522997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.523971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.523998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.524980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.524998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.525993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.525996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.526954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.526960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.527985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.527989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.528978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.528981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.529981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.529986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.530977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.530980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.531943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.531994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.532981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.532984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.533947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.533998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.534994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.534997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.535967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.535973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.536995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.536998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.537987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.537990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.538977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.538980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.539965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.539970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.540980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.540983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.541979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.541982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.542972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.542975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.543986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.543989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.544989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.544992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.545996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.545999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.546984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.546987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.547971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.547974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.548975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.548979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.549988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.549991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.550988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.550991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.551987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.551990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.552994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.552997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.553991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.553994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.554981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.554987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.555992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.555995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.556988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.556991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.557987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.557991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.558963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.558996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.559972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.559998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.560974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.560979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.561974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.561978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.562978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.562981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.563990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.563993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.564944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.564949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.565971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.565974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.566968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.566971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.567975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.567978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.568973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.568999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.569990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.569993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.570986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.570990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.571974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.571977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.572983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.572986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.573976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.573979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.574971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.574999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.575993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.575996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.576989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.576992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.577983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.577986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.578982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.578985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.579994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.579997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.580980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.580984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.581954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.581999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.582981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.582984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.583967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.583972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.584981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.584984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.585986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.585992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.586987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.586990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.587957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.587962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.588974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.588977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.589980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.589983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.590990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.590993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.591990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.591994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.592993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.592996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.593994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.593997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.594971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.594998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.595972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.595999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.596990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.596993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.597994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.597997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.598976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.598979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.599991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.599994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.600995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.600998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.601995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.601998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.602984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.602987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.603991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.603995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.604993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.604996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.605987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.605990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.606992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.606995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.607983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.607985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608885] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.608974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.608979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.609995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.609998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.610993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.610996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.611994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.611997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.612977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.612983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.613976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.613979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.614989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.614994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.615990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.615993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.616993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.616996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.617996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.617999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.618982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.618985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.619983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.619986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.620993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.620996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.621971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.621997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.622994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.622997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.623985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.623988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.624996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.624999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.625978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.625981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.626976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.626979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.627980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.627983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.628992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.628995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.629974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.629978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.630983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.630986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.631981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.631984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.632971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.632975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.633974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.633977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.634991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.634994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.635986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.635989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.636980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.636983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.637970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.637973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.638976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.638979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.639987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.639992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.640987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.640991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.641966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.641972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.642977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.642980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.643959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.643962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.644986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.644989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.645971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.645974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.646992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.646995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.647988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.647991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.648991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.648994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.649988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.649992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.650974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.650978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.651979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.651982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.652989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.652992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.653971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.653998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.654993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.654997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.655978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.655982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.656983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.656986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.657988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.657990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.658964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.658998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.659985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.659988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  716.660718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  716.660860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  716.660949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  716.660994] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  716.661059] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  716.679879] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  716.679903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  716.679931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  716.679953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  716.679976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  716.680002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  716.680028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  716.680054] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  716.680083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  716.680112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  716.680140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  716.680168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.680193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  716.680219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  716.680258] [drm:intel_power_well_disable [i915]] disabling display
>[  716.680289] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  716.680323] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  716.680347] [drm:intel_power_well_disable [i915]] disabling always-on
>[  716.682048] [IGT] kms_flip: exiting, ret=0
>[  716.694944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  716.694967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  716.694991] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  716.695015] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  716.695034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  716.695055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  716.695076] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  716.695095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  716.695114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  716.695132] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  716.695149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  716.695154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  716.695171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  716.695174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  716.695191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  716.695208] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  716.695225] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  716.695241] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  716.695261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  716.695278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  716.695295] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  716.695312] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  716.695328] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  716.695348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  716.695371] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  716.695463] [drm:intel_power_well_enable [i915]] enabling always-on
>[  716.695482] [drm:intel_power_well_enable [i915]] enabling display
>[  716.695500] [drm:hsw_set_power_well [i915]] Enabling power well
>[  716.695535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  716.695554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  716.695572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  716.695590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  716.695614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  716.695638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  716.695666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  716.695692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  716.695718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.695743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  716.695768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  716.695794] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  716.695819] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  716.697848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  716.697869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  716.697888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  716.697908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  716.699470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  716.699494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  716.699519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  716.701050] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  716.701072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  716.702927] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  716.705564] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  716.705639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  716.705659] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  716.705688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  716.705755] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  716.705785] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  716.722389] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  716.722419] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  716.722486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  716.722658] Console: switching to colour frame buffer device 240x75
>[  716.856371] Console: switching to colour dummy device 80x25
>[  716.856569] [IGT] kms_flip: executing
>[  716.868031] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  716.868063] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  716.869760] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  716.869784] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  716.871500] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  716.871508] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  716.873496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  716.873520] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  716.875489] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  716.875496] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  716.875501] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  716.875523] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  716.875549] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  716.876685] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  716.877598] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  716.877621] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  716.877643] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  716.877662] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  716.878669] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  716.878694] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  716.879807] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  716.879811] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  716.879918] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  716.879921] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  716.879926] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  716.879929] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  716.879935] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  716.879938] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  716.879947] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  716.879951] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  716.879954] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  716.879958] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  716.879962] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  716.879965] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  716.879969] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  716.879972] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  716.879975] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  716.879979] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  716.879983] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  716.879986] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  716.879989] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  716.879993] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  716.879996] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  716.880000] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  716.880003] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  716.880007] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  716.880010] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  716.880013] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  716.880017] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  716.880021] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  716.880024] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  716.880028] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  716.880031] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  716.880034] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  716.880037] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  716.880040] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  716.880044] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  716.880047] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  716.880051] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  716.880097] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  716.880122] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  716.881489] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  716.881515] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  716.883480] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  716.883487] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  716.885500] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  716.885524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  716.887592] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  716.887599] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  716.887604] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  716.889175] [IGT] kms_flip: starting subtest 2x-flip-vs-rmfb-interruptible
>[  716.891063] [IGT] kms_flip: exiting, ret=77
>[  716.922654] Console: switching to colour frame buffer device 240x75
>[  717.050503] Console: switching to colour dummy device 80x25
>[  717.050621] [IGT] kms_flip: executing
>[  717.062322] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  717.062375] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  717.064327] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  717.064370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  717.066477] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  717.066489] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  717.068521] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  717.068557] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  717.070522] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  717.070533] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  717.070541] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  717.070571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  717.070613] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  717.071722] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  717.072665] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  717.072696] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  717.072724] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  717.072749] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  717.073769] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  717.073790] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  717.074903] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  717.074907] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  717.075014] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  717.075017] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  717.075022] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  717.075024] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  717.075029] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  717.075032] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  717.075041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  717.075044] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.075048] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.075050] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.075054] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  717.075057] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  717.075060] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  717.075063] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  717.075066] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.075069] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.075072] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  717.075075] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  717.075078] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  717.075080] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  717.075083] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  717.075086] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  717.075089] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  717.075092] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  717.075095] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  717.075098] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  717.075101] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  717.075104] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  717.075107] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  717.075110] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  717.075113] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  717.075116] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  717.075119] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  717.075122] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  717.075125] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  717.075128] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  717.075131] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  717.075169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  717.075192] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  717.076505] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  717.076534] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  717.078521] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  717.078532] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  717.080536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  717.080573] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  717.082535] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  717.082547] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  717.082554] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  717.082952] [IGT] kms_flip: starting subtest 2x-plain-flip-ts-check
>[  717.086359] [IGT] kms_flip: exiting, ret=77
>[  717.122953] Console: switching to colour frame buffer device 240x75
>[  717.245120] Console: switching to colour dummy device 80x25
>[  717.245239] [IGT] kms_flip: executing
>[  717.257294] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  717.257347] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  717.258536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  717.258579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  717.260516] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  717.260528] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  717.262514] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  717.262553] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  717.264516] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  717.264528] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  717.264536] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  717.264567] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  717.264609] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  717.265730] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  717.266654] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  717.266676] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  717.266694] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  717.266712] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  717.267727] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  717.267748] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  717.268865] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  717.268869] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  717.268969] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  717.268972] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  717.268977] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  717.268979] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  717.268984] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  717.268986] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  717.268996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  717.269000] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.269003] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.269006] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.269009] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  717.269012] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  717.269015] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  717.269018] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  717.269021] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.269024] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.269027] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  717.269030] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  717.269033] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  717.269036] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  717.269039] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  717.269041] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  717.269044] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  717.269047] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  717.269050] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  717.269053] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  717.269056] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  717.269059] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  717.269062] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  717.269065] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  717.269068] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  717.269071] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  717.269074] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  717.269077] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  717.269080] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  717.269083] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  717.269086] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  717.269124] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  717.269146] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  717.270480] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  717.270503] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  717.272526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  717.272537] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  717.274512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  717.274551] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  717.276512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  717.276523] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  717.276530] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  717.278611] [IGT] kms_flip: starting subtest 2x-blocking-absolute-wf_vblank-interruptible
>[  717.280433] [IGT] kms_flip: exiting, ret=77
>[  717.306435] Console: switching to colour frame buffer device 240x75
>[  717.428716] Console: switching to colour dummy device 80x25
>[  717.428830] [IGT] kms_flip: executing
>[  717.440306] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  717.440359] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  717.441530] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  717.441571] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  717.443507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  717.443519] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  717.445506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  717.445545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  717.447508] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  717.447520] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  717.447528] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  717.447558] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  717.447601] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  717.448728] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  717.449654] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  717.449675] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  717.449694] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  717.449716] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  717.450734] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  717.450754] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  717.451869] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  717.451872] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  717.451980] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  717.451983] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  717.451988] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  717.451990] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  717.451995] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  717.451998] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  717.452007] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  717.452011] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.452014] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.452017] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.452020] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  717.452023] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  717.452026] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  717.452028] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  717.452031] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.452034] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  717.452037] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  717.452040] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  717.452043] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  717.452046] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  717.452049] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  717.452052] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  717.452055] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  717.452058] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  717.452061] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  717.452064] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  717.452067] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  717.452070] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  717.452073] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  717.452076] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  717.452079] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  717.452082] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  717.452084] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  717.452087] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  717.452090] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  717.452093] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  717.452096] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  717.452135] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  717.452158] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  717.453480] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  717.453508] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  717.455519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  717.455530] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  717.457505] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  717.457544] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  717.459505] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  717.459516] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  717.459523] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  717.459938] [IGT] kms_flip: starting subtest modeset-vs-vblank-race
>[  717.460904] [drm:drm_mode_addfb2] [FB:77]
>[  717.460950] [drm:drm_mode_addfb2] [FB:79]
>[  717.514671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.514734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.523069] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  717.523119] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  717.523193] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  717.540206] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  717.540251] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  717.540284] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  717.540323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.540356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.540391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.540502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.540549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.540600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.540657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.540709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.540760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.540809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.540847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.540874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.540929] [drm:intel_power_well_disable [i915]] disabling display
>[  717.540969] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  717.541009] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.541043] [drm:intel_power_well_disable [i915]] disabling always-on
>[  717.541151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  717.541293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  717.541463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.541480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  717.541566] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  717.541601] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  717.541636] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  717.541671] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  717.541696] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  717.541722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  717.541748] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  717.541773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  717.541799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  717.541824] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  717.541849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  717.541854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.541878] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  717.541883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.541908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  717.541933] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  717.541959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  717.541984] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  717.542010] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  717.542035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  717.542060] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  717.542084] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  717.542109] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  717.542136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.542163] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  717.545542] [drm:intel_power_well_enable [i915]] enabling always-on
>[  717.545561] [drm:intel_power_well_enable [i915]] enabling display
>[  717.545578] [drm:hsw_set_power_well [i915]] Enabling power well
>[  717.545612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.545633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.545651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.545669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.545686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.545705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.545725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.545744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.545763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.545780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.545796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.545820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  717.545844] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  717.547913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  717.547936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  717.547959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.547983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  717.549640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  717.549662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  717.549680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.551240] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  717.551261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  717.553136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  717.556404] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  717.556514] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  717.556541] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  717.556584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  717.556655] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  717.556687] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  717.573293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.573340] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.573403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.590097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.590181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.606641] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  717.606688] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  717.607222] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  717.624243] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  717.624288] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  717.624320] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  717.624359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.624392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.624511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.624556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.624605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.624650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.624706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.624759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.624816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.624849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.624879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.624908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.624960] [drm:intel_power_well_disable [i915]] disabling display
>[  717.625002] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  717.625042] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.625076] [drm:intel_power_well_disable [i915]] disabling always-on
>[  717.625152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.625180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  717.625259] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  717.625286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  717.625316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  717.625350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  717.625375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  717.625416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  717.625477] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  717.625507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  717.625539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  717.625566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  717.625596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  717.625604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.625633] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  717.625641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.625670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  717.625697] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  717.625727] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  717.625753] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  717.625785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  717.625812] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  717.625843] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  717.625870] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  717.625899] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  717.625933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.625967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  717.626059] [drm:intel_power_well_enable [i915]] enabling always-on
>[  717.626092] [drm:intel_power_well_enable [i915]] enabling display
>[  717.626123] [drm:hsw_set_power_well [i915]] Enabling power well
>[  717.626175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.626207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.626235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.626265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.626292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.626322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.626355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.626386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.626442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.626469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.626497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.626529] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  717.626561] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  717.628625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  717.628646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  717.628665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.628683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  717.630243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  717.630263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  717.630281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.631832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  717.631852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  717.633711] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  717.637036] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  717.637078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  717.637097] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  717.637123] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  717.637185] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  717.637210] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  717.653877] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.653928] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.653999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.687263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.687351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.703880] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  717.703926] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  717.704000] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  717.722344] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  717.722389] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  717.722674] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  717.722718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.722760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.722804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.722844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.722879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.722915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.722959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.723001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.723043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.723084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.723131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.723153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.723185] [drm:intel_power_well_disable [i915]] disabling display
>[  717.723210] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  717.723238] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.723258] [drm:intel_power_well_disable [i915]] disabling always-on
>[  717.723309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.723321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  717.723372] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  717.723391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  717.723459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  717.723500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  717.723528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  717.723562] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  717.723592] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  717.723624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  717.723652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  717.723682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  717.723708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  717.723717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.723744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  717.723752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.723781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  717.723808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  717.723837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  717.723865] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  717.723898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  717.723924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  717.723953] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  717.723979] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  717.724008] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  717.724376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.724437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  717.724629] [drm:intel_power_well_enable [i915]] enabling always-on
>[  717.724657] [drm:intel_power_well_enable [i915]] enabling display
>[  717.724685] [drm:hsw_set_power_well [i915]] Enabling power well
>[  717.724732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.724759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.724787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.724812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.724838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.724864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.724893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.724923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.724952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.724976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.725002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.725033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  717.725059] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  717.727144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  717.727166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  717.727184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.727208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  717.728795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  717.728820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  717.728843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.730399] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  717.730433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  717.732294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  717.735584] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  717.735662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  717.735686] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  717.735717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  717.735780] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  717.735805] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  717.752460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.752509] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.752573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.785864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.785953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.802472] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  717.802517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  717.802605] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  717.820997] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  717.821041] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  717.821074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  717.821113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.821146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.821181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.821212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.821241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.821273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.821307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.821340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.821371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.821498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.821540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.821582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.821653] [drm:intel_power_well_disable [i915]] disabling display
>[  717.821709] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  717.821768] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.821814] [drm:intel_power_well_disable [i915]] disabling always-on
>[  717.821938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.821965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  717.822083] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  717.822123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  717.822170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  717.822219] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  717.822258] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  717.822301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  717.822342] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  717.822384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  717.822460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  717.822493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  717.822526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  717.822536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.822569] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  717.822578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.822612] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  717.822643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  717.822676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  717.822706] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  717.822743] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  717.822773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  717.822806] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  717.822835] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  717.822867] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  717.822901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.822938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  717.823037] [drm:intel_power_well_enable [i915]] enabling always-on
>[  717.823072] [drm:intel_power_well_enable [i915]] enabling display
>[  717.823106] [drm:hsw_set_power_well [i915]] Enabling power well
>[  717.823161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.823193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.823226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.823256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.823288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.823320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.823356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.823392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.823460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.823489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.823516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.823551] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  717.823580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  717.825645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  717.825665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  717.825683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.825702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  717.827272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  717.827292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  717.827310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.828863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  717.828883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  717.830744] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  717.834076] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  717.834177] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  717.834207] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  717.834247] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  717.834320] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  717.834351] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  717.850961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.851010] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.851075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.884363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.884524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.900991] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  717.901036] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  717.901126] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  717.918157] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  717.918201] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  717.918233] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  717.918271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.918310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.918354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.918394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.918507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.918556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.918615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.918827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.918849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.918875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.918901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.918927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.918964] [drm:intel_power_well_disable [i915]] disabling display
>[  717.918995] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  717.919028] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.919053] [drm:intel_power_well_disable [i915]] disabling always-on
>[  717.919112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.919125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  717.919184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  717.919210] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  717.919237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  717.919266] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  717.919291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  717.919317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  717.919343] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  717.919369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  717.919398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  717.919457] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  717.919486] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  717.919495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.919523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  717.919531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  717.919559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  717.919587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  717.919615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  717.919641] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  717.919673] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  717.919699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  717.919727] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  717.919753] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  717.919780] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  717.919811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.919844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  717.920103] [drm:intel_power_well_enable [i915]] enabling always-on
>[  717.920123] [drm:intel_power_well_enable [i915]] enabling display
>[  717.920142] [drm:hsw_set_power_well [i915]] Enabling power well
>[  717.920177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  717.920199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  717.920219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  717.920238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  717.920257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  717.920277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  717.920299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  717.920319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  717.920339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.920357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  717.920375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  717.920432] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  717.920461] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  717.922636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  717.922657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  717.922675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.922694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  717.924254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  717.924278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  717.924300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  717.925865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  717.925886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  717.927795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  717.931070] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  717.931110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  717.931129] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  717.931155] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  717.931214] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  717.931236] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  717.947910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  717.947960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  717.948024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  717.981316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  717.981404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  717.997942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  717.997987] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  717.998076] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.015089] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.015132] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.015164] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.015202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.015235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.015269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.015300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.015329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.015360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.015395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.015510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.015563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.015618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.015661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.015707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.015792] [drm:intel_power_well_disable [i915]] disabling display
>[  718.015855] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.015916] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.015969] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.016108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.016128] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.016215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.016244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.016277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.016313] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.016343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.016374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.016429] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.016461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.016490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.016520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.016547] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.016556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.016584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.016592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.016623] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.016652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.016681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.016707] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.016739] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.016765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.016794] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.016820] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.016850] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.016883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.016917] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.017004] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.017035] [drm:intel_power_well_enable [i915]] enabling display
>[  718.017064] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.017113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.017142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.017170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.017197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.017224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.017252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.017283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.017314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.017346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.017372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.017422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.017458] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.017487] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.019550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.019571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.019589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.019608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.021178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.021198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.021217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.022769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.022790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.024651] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.027980] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.028033] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.028065] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.028115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.028197] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.028231] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.044816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.044865] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.044935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.078222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.078308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.094839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.094888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.094979] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.111982] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.112025] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.112057] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.112095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.112128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.112169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.112207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.112247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.112285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.112329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.112381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.112486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.112534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.112572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.112613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.112686] [drm:intel_power_well_disable [i915]] disabling display
>[  718.112739] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.112793] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.112840] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.112962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.112986] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.113100] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.113138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.113181] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.113228] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.113264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.113305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.113343] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.113392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.113463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.113494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.113526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.113535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.113566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.113575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.113607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.113637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.113668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.113697] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.113732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.113761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.113793] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.113822] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.113853] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.113884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.113922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.114017] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.114050] [drm:intel_power_well_enable [i915]] enabling display
>[  718.114083] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.114136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.114166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.114198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.114227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.114257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.114287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.114321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.114355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.114397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.114451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.114480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.114515] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.114545] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.116609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.116629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.116647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.116666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.118236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.118256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.118274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.119838] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.119859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.121728] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.125055] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.125111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.125143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.125186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.125262] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.125296] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.141894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.141943] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.142007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.175300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.175386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.191917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.191964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.192054] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.209073] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.209116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.209149] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.209188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.209221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.209256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.209286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.209314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.209345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.209388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.209499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.209554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.209598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.209628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.209655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.209750] [drm:intel_power_well_disable [i915]] disabling display
>[  718.209791] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.209832] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.209866] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.209958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.209977] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.210069] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.210096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.210126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.210159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.210185] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.210214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.210241] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.210270] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.210297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.210324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.210348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.210355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.210392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.210436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.210468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.210495] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.210526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.210554] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.210589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.210616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.210646] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.210672] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.210700] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.210730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.210764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.210852] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.210883] [drm:intel_power_well_enable [i915]] enabling display
>[  718.210913] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.210963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.210993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.211020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.211049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.211075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.211104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.211137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.211169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.211199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.211227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.211254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.211285] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.211315] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.213427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.213449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.213467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.213486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.215069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.215091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.215110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.216666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.216707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.218575] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.221855] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.221891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.221914] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.221946] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.222008] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.222029] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.238680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.238724] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.238787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.272123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.272210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.288725] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.288774] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.288870] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.305940] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.305984] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.306016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.306054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.306087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.306121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.306151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.306180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.306211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.306253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.306295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.306338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.306379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.306496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.306542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.306631] [drm:intel_power_well_disable [i915]] disabling display
>[  718.306699] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.306771] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.306807] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.306882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.306902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.306988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.307019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.307051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.307087] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.307115] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.307147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.307178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.307208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.307236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.307265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.307290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.307298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.307324] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.307331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.307359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.307413] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.307440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.307469] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.307499] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.307529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.307556] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.307585] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.307611] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.307644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.307679] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.307770] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.307802] [drm:intel_power_well_enable [i915]] enabling display
>[  718.307833] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.307886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.307919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.307949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.307979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.308008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.308036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.308069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.308100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.308131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.308157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.308185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.308215] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.308246] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.310313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.310334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.310356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.310421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.311981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.312005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.312027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.313618] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.313641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.315519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.318855] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.318955] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.318994] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.319021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.319080] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.319110] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.335733] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.335782] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.335846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.369136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.369232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.385767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.385812] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.385911] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.402940] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.402988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.403028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.403072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.403113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.403156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.403196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.403230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.403265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.403309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.403350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.403462] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.403521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.403567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.403616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.403701] [drm:intel_power_well_disable [i915]] disabling display
>[  718.404010] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.404077] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.404130] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.404239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.404257] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.404329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.404349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.404371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.404446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.404479] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.404513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.404544] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.404577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.404606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.404638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.404664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.404891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.404912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.404916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.404935] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.404953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.404970] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.404986] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.405006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.405024] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.405040] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.405063] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.405086] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.405111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.405137] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.405194] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.405214] [drm:intel_power_well_enable [i915]] enabling display
>[  718.405234] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.405270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.405294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.405317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.405341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.405361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.405429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.405468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.405503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.405537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.405566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.405596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.405632] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.405662] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.407981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.408005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.408028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.408052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.409637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.409658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.409677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.411235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.411259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.413135] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.416448] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.416501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.416524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.416555] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.416614] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.416643] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.433301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.433352] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.433636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.466691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.466777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.483323] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.483374] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.483724] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.502286] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.502334] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.502375] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.502499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.502554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.502605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.502645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.502688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.502730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.502779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.502827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.502873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.502919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.502958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.502998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.503077] [drm:intel_power_well_disable [i915]] disabling display
>[  718.503136] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.503194] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.503243] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.503418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.503447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.503569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.503598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.503631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.503667] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.503701] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.503731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.503758] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.503786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.503812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.503838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.503862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.503868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.503894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.503900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.503927] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.503951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.503977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.504000] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.504029] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.504052] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.504078] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.504101] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.504128] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.504158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.504200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.504291] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.504321] [drm:intel_power_well_enable [i915]] enabling display
>[  718.504351] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.504432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.504461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.504491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.504519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.504548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.504576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.504609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.504641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.504674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.504701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.504730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.504761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.504792] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.506879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.506900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.506918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.506941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.508512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.508534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.508553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.510124] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.510146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.512025] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.515325] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.515463] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.515511] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.515580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.515693] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.515738] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.532198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.532248] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.532313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.565597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.565685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.582213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.582262] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.582360] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.599466] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.599510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.599542] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.599580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.599613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.599647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.599677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.599705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.599736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.599780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.599808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.599836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.599872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.599907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.599941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.599993] [drm:intel_power_well_disable [i915]] disabling display
>[  718.600033] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.600079] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.600113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.600190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.600207] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.600288] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.600324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.600360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.600450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.600502] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.600547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.600595] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.600636] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.600680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.600718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.600758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.600770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.600811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.600819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.600849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.600876] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.600906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.600932] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.600965] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.600991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.601020] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.601047] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.601075] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.601109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.601145] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.601638] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.601670] [drm:intel_power_well_enable [i915]] enabling display
>[  718.601700] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.601752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.601782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.601812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.601839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.601868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.601896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.601928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.601960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.601992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.602018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.602046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.602076] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.602107] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.604175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.604197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.604216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.604235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.605816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.605835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.605853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.607428] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.607452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.609361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.612710] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.612808] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.612840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.612882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.612979] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.613008] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.629589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.629641] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.629711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.663011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.663098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.679600] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.679645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.679744] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.696771] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.696815] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.696848] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.696886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.696919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.696953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.696983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.697012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.697042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.697077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.697109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.697140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.697171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.697199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.697226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.697279] [drm:intel_power_well_disable [i915]] disabling display
>[  718.697319] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.697360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.697470] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.697858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.697877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.697964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.697999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.698038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.698066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.698092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.698119] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.698145] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.698171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.698198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.698224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.698249] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.698255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.698279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.698284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.698310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.698336] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.698363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.698418] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.698452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.698482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.698511] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.698539] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.698567] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.698599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.698633] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.698860] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.698879] [drm:intel_power_well_enable [i915]] enabling display
>[  718.698898] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.698933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.698955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.698980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.699005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.699032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.699057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.699086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.699114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.699141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.699167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.699193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.699220] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.699246] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.701306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.701328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.701347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.701413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.703070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.703090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.703108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.704667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.704688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.706559] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.709865] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.709943] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.709975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.710017] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.710110] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.710159] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.726726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.726775] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.726840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.760147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.760233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.776753] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.776799] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.776899] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.793927] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.793971] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.794003] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.794041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.794074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.794109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.794140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.794168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.794199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.794234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.794267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.794298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.794339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.794435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.794472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.794545] [drm:intel_power_well_disable [i915]] disabling display
>[  718.794740] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.794784] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.794818] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.794895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.794912] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.794988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.795022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.795058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.795096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.795129] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.795165] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.795199] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.795234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.795264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.795299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.795332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.795339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.795409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.795417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.795448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.795477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.795506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.795533] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.795564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.795592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.795619] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.795646] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.795673] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.795705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.795737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.796000] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.796020] [drm:intel_power_well_enable [i915]] enabling display
>[  718.796038] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.796074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.796096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.796116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.796135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.796160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.796185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.796214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.796242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.796270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.796295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.796321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.796349] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.796407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.798611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.798632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.798651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.798674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.800245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.800266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.800284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.801844] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.801864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.803880] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.807162] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.807212] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.807245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.807286] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.807380] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.807494] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.823996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.824045] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.824111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.857439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.857524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.874028] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.874073] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.874172] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.891183] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.891227] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.891260] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.891297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.891331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.891450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.891501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.891550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.891601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.891660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.891684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.891705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.891724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.891742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.891760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.891795] [drm:intel_power_well_disable [i915]] disabling display
>[  718.891822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.891850] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.891872] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.891929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.891941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.891993] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.892013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.892036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.892061] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.892080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.892101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.892122] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.892142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.892162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.892180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.892198] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.892203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.892221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.892225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.892245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.892263] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.892288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.892314] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.892341] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.892396] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.892425] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.892452] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.892479] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.892510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.892542] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.892632] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.892664] [drm:intel_power_well_enable [i915]] enabling display
>[  718.892691] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.892741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.892774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.892805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.892835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.892866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.892897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.892932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.892965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.892997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.893027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.893048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.893071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.893096] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.895142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.895164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.895182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.895201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.896763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.896782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.896800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.898352] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.898388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.900257] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  718.903625] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  718.903689] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  718.903722] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  718.903772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  718.903852] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  718.903873] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  718.920468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.920516] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.920578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.953899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.953983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.970504] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  718.970555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  718.970646] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  718.987654] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  718.987700] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  718.987740] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  718.987784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.987825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.987868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.987903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.987943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.987981] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  718.988025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.988066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.988108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.988150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.988189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.988228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.988285] [drm:intel_power_well_disable [i915]] disabling display
>[  718.988331] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  718.988471] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  718.988531] [drm:intel_power_well_disable [i915]] disabling always-on
>[  718.988647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  718.988665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  718.988751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  718.988790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  718.988832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  718.988884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  718.988907] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  718.988932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  718.988955] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  718.988975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  718.988995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  718.989014] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  718.989033] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  718.989038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.989055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  718.989060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  718.989078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  718.989096] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  718.989115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  718.989132] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  718.989155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  718.989173] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  718.989191] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  718.989209] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  718.989228] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  718.989249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  718.989273] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  718.989333] [drm:intel_power_well_enable [i915]] enabling always-on
>[  718.989384] [drm:intel_power_well_enable [i915]] enabling display
>[  718.989412] [drm:hsw_set_power_well [i915]] Enabling power well
>[  718.989461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  718.989490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  718.989518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  718.989546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  718.989573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  718.989601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  718.989632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  718.989662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  718.989693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  718.989719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  718.989748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  718.989782] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  718.989812] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  718.991873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  718.991893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  718.991912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.991936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  718.993514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  718.993535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  718.993553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  718.995100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  718.995121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  718.996983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.000285] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.000424] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.000465] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.000522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.000616] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.000655] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.017129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.017176] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.017239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.050542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.050625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.067171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.067219] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.067295] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.084322] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.084399] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.084432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.084471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.084511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.084554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.084594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.084630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.084666] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.084710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.084752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.084794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.084836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.084875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.084913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.084969] [drm:intel_power_well_disable [i915]] disabling display
>[  719.085015] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.085065] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.085102] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.085175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.085193] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.085288] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.085310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.085333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.085413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.085446] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.085481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.085516] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.085549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.085582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.085612] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.085645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.085653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.085682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.085690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.085720] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.085751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.085781] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.085811] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.085845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.085874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.085905] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.085935] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.085966] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.085999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.086034] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.086125] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.086157] [drm:intel_power_well_enable [i915]] enabling display
>[  719.086188] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.086238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.086269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.086300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.086329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.086381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.086412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.086447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.086481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.086514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.086543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.086572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.086607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.086638] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.088711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.088734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.088757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.088781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.090348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.090385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.090403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.091964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.091985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.093894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.097191] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.097278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.097311] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.097417] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.097618] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.097641] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.114065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.114114] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.114179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.147453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.147540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.164082] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.164131] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.164208] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.181235] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.181278] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.181310] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.181348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.181470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.181531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.181581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.181849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.181884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.181923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.181966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.182008] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.182050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.182088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.182127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.182183] [drm:intel_power_well_disable [i915]] disabling display
>[  719.182229] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.182279] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.182318] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.182597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.182624] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.182706] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.182737] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.182769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.182803] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.182831] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.182862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.182892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.182921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.182950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.182977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.183004] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.183011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.183037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.183044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.183072] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.183099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.183126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.183153] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.183180] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.183207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.183233] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.183258] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.183284] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.183312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.183353] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.183469] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.183502] [drm:intel_power_well_enable [i915]] enabling display
>[  719.183767] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.183804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.183827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.183847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.183867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.183891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.183917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.183945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.183972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.183999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.184024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.184048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.184075] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.184101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.186143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.186164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.186182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.186201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.187777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.187796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.187814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.189459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.189480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.191344] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.194682] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.194720] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.194740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.194765] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.194826] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.194847] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.211520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.211570] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.211634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.244909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.244994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.261543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.261591] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.261668] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.280294] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.280337] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.280454] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.280518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.280706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.280743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.280773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.280790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.280809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.280830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.280849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.280867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.280886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.280902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.280918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.280950] [drm:intel_power_well_disable [i915]] disabling display
>[  719.280975] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.281001] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.281021] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.281071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.281083] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.281131] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.281150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.281171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.281194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.281212] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.281231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.281250] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.281268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.281285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.281307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.281330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.281377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.281409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.281420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.281452] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.281483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.281515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.281545] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.281579] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.281609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.281640] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.281670] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.281701] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.281735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.281770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.282158] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.282190] [drm:intel_power_well_enable [i915]] enabling display
>[  719.282221] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.282274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.282306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.282338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.282391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.282422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.282456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.282492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.282527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.282703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.282731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.282759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.282791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.282820] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.284935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.284956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.284974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.284993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.286591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.286614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.286633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.288185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.288206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.290081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.293393] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.293463] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.293501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.293549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.293626] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.293664] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.310244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.310293] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.310442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.343650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.343736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.360270] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.360317] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.360689] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.379297] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.379340] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.379440] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.379499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.379553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.379609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.379656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.379698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.379746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.379802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.379854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.379905] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.379956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.380002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.380048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.380136] [drm:intel_power_well_disable [i915]] disabling display
>[  719.380178] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.380218] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.380253] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.380383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.380403] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.380483] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.380504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.380527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.380552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.380572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.380602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.380622] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.380641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.380659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.380676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.380693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.380697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.380713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.380717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.380734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.380751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.380767] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.380783] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.380803] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.380819] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.380836] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.380852] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.380868] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.380887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.380909] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.380964] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.380982] [drm:intel_power_well_enable [i915]] enabling display
>[  719.380998] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.381029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.381047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.381070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.381094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.381118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.381141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.381167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.381191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.381216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.381239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.381263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.381287] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.381310] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.383426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.383447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.383466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.383484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.385045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.385065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.385083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.386645] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.386666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.388540] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.391875] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.391974] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.392008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.392051] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.392129] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.392162] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.408757] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.408806] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.408871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.442158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.442246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.458778] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.458826] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.458917] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.475937] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.475981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.476013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.476051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.476083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.476117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.476148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.476177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.476208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.476242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.476275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.476306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.476404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.476434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.476466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.476524] [drm:intel_power_well_disable [i915]] disabling display
>[  719.476727] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.476774] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.476807] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.476889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.476906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.476987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.477016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.477049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.477083] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.477111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.477143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.477173] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.477202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.477231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.477259] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.477286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.477292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.477319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.477367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.477399] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.477430] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.477460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.477490] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.477524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.477555] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.477585] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.477615] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.477646] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.477681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.477716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.477993] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.478013] [drm:intel_power_well_enable [i915]] enabling display
>[  719.478031] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.478069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.478095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.478120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.478143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.478169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.478193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.478220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.478247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.478274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.478300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.478324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.478389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.478424] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.480692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.480714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.480732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.480751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.482322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.482358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.482376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.483947] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.483969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.485863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.488451] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.488541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.488573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.488616] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.488687] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.488709] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.505315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.505395] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.505459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.538732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.538818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.555342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.555411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.555503] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.572506] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.572550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.572581] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.572624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.572665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.572708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.572748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.572782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.572819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.572863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.572904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.572946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.572987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.573026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.573064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.573121] [drm:intel_power_well_disable [i915]] disabling display
>[  719.573167] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.573217] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.573255] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.573418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.573449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.573858] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.573901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.573945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.573992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.574031] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.574073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.574115] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.574155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.574194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.574232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.574269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.574278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.574314] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.574363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.574401] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.574439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.574477] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.574515] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.574557] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.574594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.574635] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.574666] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.574694] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.574729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.574766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.575132] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.575166] [drm:intel_power_well_enable [i915]] enabling display
>[  719.575197] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.575250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.575284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.575317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.575379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.575414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.575449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.575485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.575520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.575703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.575721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.575738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.575763] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.575786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.577836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.577857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.577876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.577899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.579568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.579589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.579607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.581165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.581186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.583060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.586399] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.586494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.586528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.586570] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.586646] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.586680] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.603276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.603325] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.603483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.636682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.636769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.653298] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.653379] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.653457] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.670458] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.670502] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.670534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.670572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.670605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.670639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.670670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.670698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.670730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.670764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.670797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.670836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.670863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.670888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.670912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.670959] [drm:intel_power_well_disable [i915]] disabling display
>[  719.670995] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.671032] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.671061] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.671138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.671155] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.671227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.671254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.671284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.671318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.671417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.671469] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.671516] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.671562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.671606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.671650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.671693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.671706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.671745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.671756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.671797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.671846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.671877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.671906] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.671940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.671970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.672001] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.672030] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.672060] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.672094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.672129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.672612] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.672644] [drm:intel_power_well_enable [i915]] enabling display
>[  719.672675] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.672727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.672761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.672793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.672823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.672854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.672885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.672919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.672952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.672984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.673014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.673043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.673077] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.673108] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.675173] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.675197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.675220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.675244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.676835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.676856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.676875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.678440] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.678461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.680322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.683679] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.683776] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.683809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.683850] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.683928] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.683961] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.700559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.700608] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.700672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.733963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.734051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.750579] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.750627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.750704] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.769266] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.769309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.769432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.769493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.769718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.769755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.769785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.769814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.769846] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.769881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.769913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.769944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.769975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.770003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.770029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.770081] [drm:intel_power_well_disable [i915]] disabling display
>[  719.770121] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.770162] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.770218] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.770351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.770378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.770752] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.770796] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.770842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.770891] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.770932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.770975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.771017] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.771058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.771099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.771137] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.771178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.771188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.771225] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.771244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.771276] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.771308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.771369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.771404] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.771439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.771471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.771504] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.771534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.771568] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.771605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.771644] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.771961] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.771996] [drm:intel_power_well_enable [i915]] enabling display
>[  719.772029] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.772084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.772119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.772153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.772186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.772218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.772259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.772293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.772349] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.772384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.772414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.772445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.772480] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.772512] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.774734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.774755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.774773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.774792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.776464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.776484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.776502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.778049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.778070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.779945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.783238] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.783327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.783423] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.783504] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.783716] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.783736] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.800110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.800160] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.800225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.833518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.833605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.850132] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.850180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.850258] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.867285] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.867413] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.867471] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.867645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.867678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.867714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.867743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.867772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.867802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.867844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.867870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.867895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.867920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.867942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.867964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.868006] [drm:intel_power_well_disable [i915]] disabling display
>[  719.868039] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.868073] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.868099] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.868156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.868171] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.868235] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.868261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.868288] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.868372] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.868410] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.868455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.868497] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.868538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.868578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.868617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.868654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.868665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.868701] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.868711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.868749] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.868786] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.868825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.868864] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.868900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.868930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.868962] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.868993] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.869024] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.869060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.869097] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.869525] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.869559] [drm:intel_power_well_enable [i915]] enabling display
>[  719.869591] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.869645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.869679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.869712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.869744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.869776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.869809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.869853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.869886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.869918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.869948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.869979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.870012] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.870043] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.872114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.872137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.872156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.872179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.873760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.873780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.873798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.875353] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.875374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.877262] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.880609] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.880697] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.880730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.880772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.880848] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.880881] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.897479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.897529] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.897599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.930871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.930958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.947501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  719.947548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  719.947639] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  719.964661] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  719.964705] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  719.964738] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  719.964776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.964809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.964851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.964891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.964927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.964963] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.965007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.965049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.965091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.965133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.965172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.965210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.965267] [drm:intel_power_well_disable [i915]] disabling display
>[  719.965313] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  719.965447] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.965507] [drm:intel_power_well_disable [i915]] disabling always-on
>[  719.965620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  719.965648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  719.965785] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  719.965837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  719.965891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  719.965950] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  719.965992] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  719.966025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  719.966058] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  719.966090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  719.966121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  719.966151] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  719.966180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  719.966187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.966215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  719.966223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  719.966253] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  719.966282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  719.966311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  719.966363] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  719.966397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  719.966427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  719.966458] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  719.966488] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  719.966518] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  719.966551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  719.966586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  719.966678] [drm:intel_power_well_enable [i915]] enabling always-on
>[  719.966710] [drm:intel_power_well_enable [i915]] enabling display
>[  719.966740] [drm:hsw_set_power_well [i915]] Enabling power well
>[  719.966790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  719.966822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  719.966850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  719.966879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  719.966906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  719.966937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  719.966970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  719.967004] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  719.967037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  719.967066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  719.967095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  719.967128] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  719.967160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  719.969251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  719.969272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  719.969290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.969359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  719.970929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  719.970949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  719.970967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  719.972543] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  719.972566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  719.974434] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  719.977773] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  719.977870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  719.977903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  719.977945] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  719.978022] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  719.978055] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  719.994651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  719.994701] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  719.994766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.028041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.028127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.044672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.044720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.044817] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.061831] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.061874] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.061914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.061958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.061998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.062042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.062081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.062121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.062159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.062203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.062253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.062286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.062386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.062433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.062475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.062549] [drm:intel_power_well_disable [i915]] disabling display
>[  720.062867] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.062923] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.062970] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.063081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.063106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.063219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.063249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.063283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.063361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.063396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.063433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.063467] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.063501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.063533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.063565] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.063597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.063605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.063634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.063812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.063834] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.063854] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.063874] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.063892] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.063914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.063933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.063951] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.063969] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.063986] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.064008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.064031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.064089] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.064108] [drm:intel_power_well_enable [i915]] enabling display
>[  720.064126] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.064159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.064179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.064197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.064216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.064234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.064253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.064274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.064295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.064351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.064382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.064411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.064447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.064479] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.066806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.066829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.066852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.066877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.068554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.068576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.068595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.070159] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.070180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.072057] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.075393] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.075500] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.075521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.075552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.075611] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.075642] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.092274] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.092399] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.092610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.125679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.125766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.142274] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.142398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.142600] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.159623] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.159666] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.159698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.159736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.159769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.159804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.159835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.159864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.159895] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.159930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.159962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.159994] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.160025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.160053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.160080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.160133] [drm:intel_power_well_disable [i915]] disabling display
>[  720.160174] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.160215] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.160249] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.160432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.160731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.160829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.160860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.160892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.160927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.160956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.160987] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.161017] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.161046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.161075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.161103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.161131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.161138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.161164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.161171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.161198] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.161225] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.161251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.161277] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.161347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.161379] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.161409] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.161440] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.161471] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.161506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.161541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.161904] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.161934] [drm:intel_power_well_enable [i915]] enabling display
>[  720.161962] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.162009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.162039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.162068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.162096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.162124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.162153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.162184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.162213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.162243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.162270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.162307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.162375] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.162410] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.164472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.164493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.164511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.164530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.166091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.166111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.166129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.167691] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.167712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.169584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.172857] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.172899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.172918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.172944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.173003] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.173024] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.189700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.189749] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.189815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.223103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.223189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.239721] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.239769] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.239847] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.256879] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.256922] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.256954] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.256992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.257026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.257060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.257091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.257121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.257152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.257187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.257220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.257252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.257283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.257388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.257434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.257516] [drm:intel_power_well_disable [i915]] disabling display
>[  720.257917] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.257957] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.257989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.258071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.258089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.258168] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.258199] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.258231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.258265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.258304] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.258370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.258406] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.258439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.258471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.258502] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.258532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.258540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.258571] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.258579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.258609] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.258639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.258843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.258863] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.258885] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.258904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.258923] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.258941] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.258959] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.258980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.259003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.259062] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.259081] [drm:intel_power_well_enable [i915]] enabling display
>[  720.259099] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.259132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.259152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.259170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.259189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.259213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.259238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.259266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.259293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.259352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.259382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.259413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.259450] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.259482] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.261805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.261826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.261845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.261864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.263530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.263550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.263568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.265126] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.265147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.267011] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.270250] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.270383] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.270485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.270516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.270577] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.270602] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.287127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.287177] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.287243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.320531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.320619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.337149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.337198] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.337275] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.354389] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.354432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.354464] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.354502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.354536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.354570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.354600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.354629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.354660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.354695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.354727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.354759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.354789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.354817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.354844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.354896] [drm:intel_power_well_disable [i915]] disabling display
>[  720.354937] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.354978] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.355011] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.355076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.355087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.355135] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.355153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.355174] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.355199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.355222] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.355247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.355270] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.355343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.355376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.355410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.355441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.355450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.355480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.355488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.355518] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.355549] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.355580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.355610] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.355644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.355674] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.355706] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.355736] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.355766] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.355800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.355835] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.355925] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.355956] [drm:intel_power_well_enable [i915]] enabling display
>[  720.355987] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.356036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.356067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.356098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.356130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.356159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.356187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.356220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.356252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.356285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.356342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.356369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.356405] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.356437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.358507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.358529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.358547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.358566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.360136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.360156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.360174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.361728] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.361748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.363624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.366921] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.367007] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.367039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.367082] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.367157] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.367189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.383790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.383839] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.383904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.417196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.417283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.433812] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.433861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.433937] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.450964] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.451007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.451040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.451078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.451111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.451146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.451176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.451204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.451236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.451271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.451392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.451447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.451500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.451548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.451596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.452027] [drm:intel_power_well_disable [i915]] disabling display
>[  720.452092] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.452157] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.452211] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.452350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.452363] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.452441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.452476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.452511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.452542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.452563] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.452585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.452606] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.452627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.452647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.452665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.452683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.452688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.452705] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.452709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.452728] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.452746] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.452763] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.452780] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.452801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.452818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.452836] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.452853] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.452870] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.452891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.452914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.452974] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.452993] [drm:intel_power_well_enable [i915]] enabling display
>[  720.453010] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.453043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.453063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.453082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.453100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.453117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.453137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.453158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.453177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.453197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.453214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.453232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.453254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.453274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.455371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.455392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.455410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.455429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.457011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.457032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.457050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.458603] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.458624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.460499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.463795] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.463879] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.463908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.463946] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.464015] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.464044] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.480665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.480714] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.480779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.514071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.514158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.530687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.530735] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.530811] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.549225] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.549273] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.549392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.549439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.549479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.549525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.549566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.549607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.549647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.549693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.549737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.549779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.549822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.549862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.549903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.549961] [drm:intel_power_well_disable [i915]] disabling display
>[  720.550007] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.550059] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.550098] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.550192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.550212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.550345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.550393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.550454] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.550490] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.550518] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.550549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.550579] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.550609] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.550637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.550665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.550692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.550700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.550725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.550733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.550760] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.550787] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.550816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.550844] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.550875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.550904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.550927] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.550945] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.550964] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.550985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.551010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.551058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.551078] [drm:intel_power_well_enable [i915]] enabling display
>[  720.551096] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.551128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.551148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.551168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.551186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.551204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.551223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.551251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.551280] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.551333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.551361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.551388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.551421] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.551449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.553532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.553555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.553573] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.553593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.555166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.555187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.555205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.556767] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.556788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.558684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.561997] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.562062] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.562092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.562130] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.562199] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.562228] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.578851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.578900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.578965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.612265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.612389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.628855] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.628902] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.628976] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.646017] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.646061] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.646094] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.646132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.646165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.646199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.646230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.646259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.646382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.646442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.646494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.646546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.646588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.646618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.646648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.646703] [drm:intel_power_well_disable [i915]] disabling display
>[  720.646744] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.646785] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.646820] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.646896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.646915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.647005] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.647034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.647065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.647099] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.647127] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.647157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.647187] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.647216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.647245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.647272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.647337] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.647349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.647378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.647387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.647417] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.647447] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.647475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.647504] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.647538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.647567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.647594] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.647626] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.647656] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.647691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.647727] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.647818] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.647851] [drm:intel_power_well_enable [i915]] enabling display
>[  720.647881] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.647931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.647963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.647994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.648024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.648054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.648085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.648118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.648150] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.648181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.648210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.648238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.648272] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.648331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.650395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.650415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.650438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.650462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.652034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.652057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.652080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.653635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.653657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.655531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.658832] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.658899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.658918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.658944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.659005] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.659026] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.675700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.675749] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.675814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.709081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.709168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.725720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.725768] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.725844] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.742872] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.742917] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.742957] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.743002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.743042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.743086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.743126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.743165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.743204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.743248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.743290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.743423] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.743482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.743533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.743583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.743670] [drm:intel_power_well_disable [i915]] disabling display
>[  720.743742] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.743784] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.743818] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.743894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.743913] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.744002] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.744034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.744069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.744106] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.744137] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.744171] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.744203] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.744235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.744268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.744327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.744359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.744368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.744395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.744403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.744434] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.744465] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.744495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.744525] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.744559] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.744589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.744617] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.744647] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.744678] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.744712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.744747] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.744834] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.744866] [drm:intel_power_well_enable [i915]] enabling display
>[  720.744897] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.744946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.744977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.745008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.745039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.745069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.745100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.745134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.745166] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.745198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.745227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.745255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.745313] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.745345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.747410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.747431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.747449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.747467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.749029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.749049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.749068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.750632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.750653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.752526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.755847] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.755909] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.755940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.755966] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.756027] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.756048] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.772679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.772731] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.772802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.806083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.806170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.822737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.822783] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.822873] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.839910] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.839953] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.839986] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.840025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.840058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.840093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.840123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.840152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.840183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.840218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.840250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.840362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.840421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.840469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.840517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.840603] [drm:intel_power_well_disable [i915]] disabling display
>[  720.840667] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.840729] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.840783] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.840915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.840951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.841038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.841071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.841105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.841142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.841173] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.841206] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.841239] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.841271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.841326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.841359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.841389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.841398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.841428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.841436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.841466] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.841497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.841527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.841557] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.841591] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.841621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.841651] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.841681] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.841712] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.841745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.841780] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.841872] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.841904] [drm:intel_power_well_enable [i915]] enabling display
>[  720.841934] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.841984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.842015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.842047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.842077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.842106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.842137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.842171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.842203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.842235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.842265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.842316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.842350] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.842383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.844446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.844467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.844485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.844504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.846075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.846096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.846114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.847676] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.847697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.849572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.852872] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.852955] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.852994] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.853046] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.853128] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.853166] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.869738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.869788] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.869853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.903140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.903228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.919761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  720.919809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  720.919888] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  720.936913] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  720.936957] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  720.936990] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  720.937028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.937061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.937095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.937126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.937155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.937186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.937222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.937254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.937380] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.937436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.937484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.937533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.937618] [drm:intel_power_well_disable [i915]] disabling display
>[  720.937683] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  720.937745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.937799] [drm:intel_power_well_disable [i915]] disabling always-on
>[  720.937936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  720.937965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  720.938099] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  720.938150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  720.938213] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  720.938250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  720.938306] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  720.938339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  720.938372] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  720.938406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  720.938438] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  720.938469] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  720.938499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  720.938508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.938537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  720.938545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  720.938576] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  720.938606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  720.938635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  720.938665] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  720.938695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  720.938723] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  720.938752] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  720.938780] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  720.938809] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  720.938843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  720.938878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  720.938966] [drm:intel_power_well_enable [i915]] enabling always-on
>[  720.938998] [drm:intel_power_well_enable [i915]] enabling display
>[  720.939028] [drm:hsw_set_power_well [i915]] Enabling power well
>[  720.939077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  720.939108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  720.939138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  720.939168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  720.939198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  720.939228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  720.939262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  720.939318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  720.939351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  720.939381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  720.939411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  720.939447] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  720.939478] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  720.941543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  720.941567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  720.941589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.941613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  720.943185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  720.943208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  720.943231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  720.944830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  720.944852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  720.946739] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  720.950077] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  720.950174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  720.950206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  720.950248] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  720.950422] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  720.950456] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  720.966962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  720.967012] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  720.967077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.000474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.017015] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  721.017064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.017156] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  721.035180] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  721.035224] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  721.035256] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.035378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.035425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.035480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.035523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.035569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.035613] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.035667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.035718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.035767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.035816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.035856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.035899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.035980] [drm:intel_power_well_disable [i915]] disabling display
>[  721.036045] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.036107] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  721.036160] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.036530] [drm:drm_mode_addfb2] [FB:77]
>[  721.036560] [drm:drm_mode_addfb2] [FB:78]
>[  721.065427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  721.065534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.065609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  721.065679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.065691] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.065753] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.065777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.065802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.065828] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.065848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.065869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.065891] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.065916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.065940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.065965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.065988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.065993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.066017] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.066021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.066046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.066070] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.066094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.066118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.066143] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.066167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.066191] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.066215] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.066239] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.066315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.066354] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.069771] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.069793] [drm:intel_power_well_enable [i915]] enabling display
>[  721.069814] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.069854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.069879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.069904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.069929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.069951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.069975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.070010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.070036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.070060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.070081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.070100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.070125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.070147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.072214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.072235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.072252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.072330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.073902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.073924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.073943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.075510] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.075532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.077397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.080736] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.080832] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.080865] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.080907] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.097612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.097663] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.097729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.114372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.114457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.114559] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.114602] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.114706] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.131747] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.131785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.131825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.131859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.131894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.131924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.131953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.131984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.132018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.132050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.132081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.132111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.132139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.132166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.132219] [drm:intel_power_well_disable [i915]] disabling display
>[  721.132265] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.132365] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.132395] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.132470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.132489] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.132578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.132607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.132631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.132656] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.132675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.132698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.132719] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.132740] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.132759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.132779] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.132797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.132803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.132821] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.132825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.132844] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.132862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.132881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.132898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.132920] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.132938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.132958] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.132975] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.132993] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.133014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.133038] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.133100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.133119] [drm:intel_power_well_enable [i915]] enabling display
>[  721.133137] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.133171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.133196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.133222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.133248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.133300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.133331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.133362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.133393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.133423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.133450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.133476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.133508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.133537] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.135599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.135620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.135639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.135658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.137254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.137290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.137308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.138861] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.138882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.140780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.144101] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.144163] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.144197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.144239] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.160941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.160994] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.161065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.194337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.194426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.194533] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.194584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.194679] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.211713] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.211750] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.211790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.211824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.211859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.211888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.211917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.211948] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.211983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.212014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.212045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.212076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.212109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.212133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.212180] [drm:intel_power_well_disable [i915]] disabling display
>[  721.212216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.212253] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.212354] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.212455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.212481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.212601] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.212647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.212695] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.212732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.212760] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.212790] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.212820] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.212847] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.212874] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.212900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.212925] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.212932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.212956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.212962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.212988] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.213012] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.213037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.213060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.213090] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.213120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.213138] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.213156] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.213173] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.213194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.213217] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.213318] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.213347] [drm:intel_power_well_enable [i915]] enabling display
>[  721.213374] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.213427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.213458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.213487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.213518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.213547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.213578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.213612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.213645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.213677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.213706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.213734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.213768] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.213794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.215862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.215885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.215908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.215932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.217513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.217535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.217553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.219103] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.219124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.220997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.224346] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.224417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.224440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.224471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.241210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.241261] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.241426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.274613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.274708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.274810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.274851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.274939] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.291975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.292013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.292057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.292098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.292142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.292181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.292216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.292252] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.292383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.292439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.292494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.292547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.292594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.292641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.292702] [drm:intel_power_well_disable [i915]] disabling display
>[  721.292744] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.292788] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.292820] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.292904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.292922] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.292999] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.293026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.293052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.293082] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.293106] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.293133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.293159] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.293185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.293211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.293237] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.293291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.293301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.293331] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.293338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.293369] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.293397] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.293426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.293453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.293484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.293511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.293538] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.293564] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.293591] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.293623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.293656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.293746] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.293778] [drm:intel_power_well_enable [i915]] enabling display
>[  721.293808] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.293861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.293894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.293925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.293955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.293985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.294012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.294035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.294055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.294076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.294093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.294112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.294138] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.294165] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.296203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.296224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.296242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.296308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.298001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.298021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.298039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.299597] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.299617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.301488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.304834] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.304923] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.304957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.304998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.321699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.321750] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.321815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.355125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.355216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.355404] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.355471] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.355747] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.372163] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.372206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.372251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.372377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.372425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.372458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.372488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.372520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.372558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.372592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.372625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.372655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.372685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.372713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.372766] [drm:intel_power_well_disable [i915]] disabling display
>[  721.372807] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.372851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.372883] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.372955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.372968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.373021] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.373041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.373066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.373095] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.373120] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.373147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.373173] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.373200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.373226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.373255] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.373311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.373319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.373348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.373356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.373385] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.373412] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.373440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.373467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.373498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.373525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.373552] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.373579] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.373606] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.373637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.373671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.373761] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.373786] [drm:intel_power_well_enable [i915]] enabling display
>[  721.373804] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.373838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.373859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.373878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.373896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.373924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.373952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.373975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.374000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.374026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.374051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.374078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.374105] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.374131] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.376189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.376211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.376229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.376298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.377996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.378016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.378033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.379599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.379620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.381491] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.384809] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.384877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.384917] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.384968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.401654] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.401704] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.401770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.435079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.435167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.435335] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.435388] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.435488] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.452513] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.452550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.452589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.452622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.452657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.452687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.452716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.452747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.452781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.452822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.452864] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.452906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.452945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.452984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.453041] [drm:intel_power_well_disable [i915]] disabling display
>[  721.453086] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.453137] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.453172] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.453338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.453367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.453494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.453530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.453567] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.453606] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.453637] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.453671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.453705] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.453745] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.453765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.453785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.453803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.453808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.453826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.453830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.453848] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.453866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.453884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.453901] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.453923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.453941] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.453958] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.453976] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.453994] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.454019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.454047] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.454110] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.454132] [drm:intel_power_well_enable [i915]] enabling display
>[  721.454153] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.454193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.454219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.454248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.454302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.454333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.454364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.454396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.454428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.454458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.454485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.454512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.454545] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.454574] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.456634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.456654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.456673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.456692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.458249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.458291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.458310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.459874] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.459895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.461776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.465050] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.465094] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.465118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.465149] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.481889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.481940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.482005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.515356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.515465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.515595] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.515650] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.515769] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.532828] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.532865] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.532904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.532938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.532972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.533002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.533032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.533063] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.533106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.533149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.533191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.533232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.533349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.533394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.533481] [drm:intel_power_well_disable [i915]] disabling display
>[  721.533522] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.533563] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.533595] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.533684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.533703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.533787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.533815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.533847] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.533884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.533912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.533943] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.533972] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.534002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.534029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.534057] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.534084] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.534091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.534117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.534124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.534152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.534178] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.534205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.534230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.534287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.534314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.534343] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.534370] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.534399] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.534430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.534464] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.534552] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.534583] [drm:intel_power_well_enable [i915]] enabling display
>[  721.534612] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.534662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.534692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.534719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.534747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.534772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.534802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.534834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.534865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.534896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.534922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.534949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.534979] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.535008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.537079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.537101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.537120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.537139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.538725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.538747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.538766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.540370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.540392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.542368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.545692] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.545736] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.545759] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.545791] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.562531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.562582] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.562648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.595946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.596032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.596137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.596181] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.596330] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.613360] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.613397] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.613437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.613471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.613507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.613538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.613567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.613599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.613633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.613665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.613696] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.613727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.613755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.613782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.613836] [drm:intel_power_well_disable [i915]] disabling display
>[  721.613880] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.613930] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.613965] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.614054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.614072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.614161] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.614202] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.614242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.614350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.614381] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.614415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.614447] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.614480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.614511] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.614542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.614569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.614578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.614606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.614614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.614645] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.614672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.614703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.614729] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.614762] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.614788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.614818] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.614846] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.614875] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.614909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.615313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.615400] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.615430] [drm:intel_power_well_enable [i915]] enabling display
>[  721.615460] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.615513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.615542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.615573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.615600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.615629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.615658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.615689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.615721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.615753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.615779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.615807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.615837] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.615868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.617949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.617972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.617991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.618010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.619587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.619608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.619626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.621187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.621208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.623119] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.626460] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.626537] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.626556] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.626582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.643332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.643385] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.643457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.676761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.676846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.676947] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.676989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.677088] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.694140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.694177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.694216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.694334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.694384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.694416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.694445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.694478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.694512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.694546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.694577] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.694610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.694638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.694668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.694721] [drm:intel_power_well_disable [i915]] disabling display
>[  721.694761] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.694805] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.694835] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.694924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.694943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.695025] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.695045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.695070] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.695099] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.695124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.695151] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.695177] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.695203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.695228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.695282] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.695312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.695321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.695349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.695357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.695386] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.695413] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.695440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.695467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.695499] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.695526] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.695553] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.695579] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.695606] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.695638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.695671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.695759] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.695786] [drm:intel_power_well_enable [i915]] enabling display
>[  721.695807] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.695846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.695872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.695898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.695924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.695949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.695975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.696002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.696029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.696056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.696082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.696108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.696135] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.696161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.698199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.698221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.698286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.698321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.699896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.699916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.699933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.701509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.701532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.703411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.706757] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.706846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.706879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.706921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.723625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.723676] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.723741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.757033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.757119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.757224] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.757339] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.757448] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.774474] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.774511] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.774551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.774585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.774620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.774659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.774699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.774738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.774788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.774844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.774886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.774928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.774954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.774978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.775025] [drm:intel_power_well_disable [i915]] disabling display
>[  721.775060] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.775097] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.775126] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.775190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.775206] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.775374] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.775419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.775464] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.775498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.775525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.775554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.775582] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.775608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.775635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.775659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.775684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.775691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.775715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.775721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.775745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.775769] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.775793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.775816] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.775845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.775868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.775893] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.775923] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.775941] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.775962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.775986] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.776046] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.776068] [drm:intel_power_well_enable [i915]] enabling display
>[  721.776090] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.776130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.776156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.776182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.776207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.776236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.776290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.776325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.776357] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.776388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.776415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.776442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.776475] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.776505] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.778564] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.778585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.778603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.778622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.780223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.780258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.780276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.781839] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.781860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.783754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.787035] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.787096] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.787115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.787141] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.803857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.803904] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.803967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.837288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.837384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.837485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.837527] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.837626] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.854664] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.854701] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.854741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.854774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.854817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.854854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.854894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.854931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.854975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.855017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.855059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.855100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.855139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.855178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.855234] [drm:intel_power_well_disable [i915]] disabling display
>[  721.855362] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.855434] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.855485] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.855606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.855626] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.855711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.855740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.855774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.855810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.855838] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.855870] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.855900] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.855930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.855958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.855987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.856013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.856020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.856047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.856054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.856082] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.856108] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.856136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.856161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.856192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.856217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.856271] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.856298] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.856327] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.856362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.856397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.856486] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.856516] [drm:intel_power_well_enable [i915]] enabling display
>[  721.856545] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.856595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.856623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.856651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.856678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.856705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.856732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.856764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.856796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.856827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.856852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.856881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.856911] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.856941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.859012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.859035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.859058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.859082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.860658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.860679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.860697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.862273] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.862294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.864165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.867512] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.867601] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.867634] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.867676] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.884379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.884432] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.884503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.917806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.917913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.918042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.918096] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.918213] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  721.935616] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  721.935654] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  721.935693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.935726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.935761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.935790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.935818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.935850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.935884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.935916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.935947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.935978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.936006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.936033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.936087] [drm:intel_power_well_disable [i915]] disabling display
>[  721.936127] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  721.936168] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.936199] [drm:intel_power_well_disable [i915]] disabling always-on
>[  721.936395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.936421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  721.936503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  721.936536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  721.936572] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  721.936610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  721.936630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  721.936650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  721.936672] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  721.936692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  721.936718] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  721.936744] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  721.936770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  721.936775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.936800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  721.936805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  721.936831] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  721.936856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  721.936883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  721.936907] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  721.936932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  721.936957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  721.936984] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  721.937010] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  721.937036] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  721.937063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.937091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  721.937151] [drm:intel_power_well_enable [i915]] enabling always-on
>[  721.937171] [drm:intel_power_well_enable [i915]] enabling display
>[  721.937188] [drm:hsw_set_power_well [i915]] Enabling power well
>[  721.937227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  721.937280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  721.937309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  721.937339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  721.937366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  721.937396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  721.937428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  721.937459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  721.937490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.937517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  721.937544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  721.937577] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  721.937607] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  721.939669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  721.939691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  721.939709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.939728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  721.941330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  721.941351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  721.941369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  721.942918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  721.942939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  721.944802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  721.948090] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  721.948181] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  721.948210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  721.948320] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  721.964945] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  721.964993] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  721.965061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  721.998387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  721.998476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  721.998580] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  721.998629] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  721.998731] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.015772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.015809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.015849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.015883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.015918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.015949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.015978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.016009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.016044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.016076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.016107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.016138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.016166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.016193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.016320] [drm:intel_power_well_disable [i915]] disabling display
>[  722.016380] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.016421] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.016443] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.016499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.016511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.016563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.016584] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.016607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.016632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.016652] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.016673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.016699] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.016725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.016751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.016777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.016802] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.016808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.016833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.016838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.016864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.016890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.016916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.016941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.016967] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.016992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.017017] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.017043] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.017068] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.017095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.017123] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.017185] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.017207] [drm:intel_power_well_enable [i915]] enabling display
>[  722.017256] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.017310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.017341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.017369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.017398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.017425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.017454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.017485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.017516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.017547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.017574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.017600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.017631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.017661] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.019723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.019745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.019763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.019782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.021365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.021387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.021406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.022959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.022981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.024859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.028178] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.028317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.028369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.028442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.045022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.045072] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.045137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.078444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.078531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.078631] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.078673] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.078771] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.095806] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.095844] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.095884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.095918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.095953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.095983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.096012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.096044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.096078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.096110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.096151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.096195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.096229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.096332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.096407] [drm:intel_power_well_disable [i915]] disabling display
>[  722.096468] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.096527] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.096573] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.096677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.096694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.096768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.096797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.096828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.096862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.096890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.096920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.096949] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.096977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.097004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.097029] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.097054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.097061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.097084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.097091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.097116] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.097141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.097167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.097198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.097250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.097277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.097305] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.097331] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.097358] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.097392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.097424] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.097514] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.097544] [drm:intel_power_well_enable [i915]] enabling display
>[  722.097575] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.097628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.097660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.097690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.097721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.097748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.097769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.097791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.097812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.097832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.097850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.097868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.097891] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.097911] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.099958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.099978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.099996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.100016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.101589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.101609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.101627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.103229] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.103267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.105135] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.108520] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.108615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.108643] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.108678] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.125401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.125451] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.125523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.158827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.158913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.159014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.159056] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.159155] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.176218] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.176290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.176330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.176365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.176400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.176430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.176458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.176489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.176524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.176564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.176607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.176649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.176688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.176726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.176783] [drm:intel_power_well_disable [i915]] disabling display
>[  722.176828] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.176879] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.176915] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.177002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.177029] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.177080] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.177100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.177122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.177145] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.177163] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.177182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.177202] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.177275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.177305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.177333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.177360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.177368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.177394] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.177402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.177429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.177456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.177482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.177508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.177539] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.177565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.177592] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.177618] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.177644] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.177675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.177707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.177796] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.177824] [drm:intel_power_well_enable [i915]] enabling display
>[  722.177843] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.177878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.177903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.177929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.177955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.177981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.178006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.178034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.178060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.178087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.178112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.178137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.178165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.178191] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.180263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.180284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.180302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.180321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.181897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.181918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.181936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.183489] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.183509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.185382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.188727] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.188816] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.188849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.188892] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.205585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.205633] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.205697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.239029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.239115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.239217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.239332] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.239438] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.256475] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.256512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.256552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.256586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.256620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.256649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.256678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.256709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.256743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.256775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.256806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.256837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.256865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.256902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.256960] [drm:intel_power_well_disable [i915]] disabling display
>[  722.257003] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.257030] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.257048] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.257102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.257114] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.257163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.257181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.257202] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.257293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.257322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.257355] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.257384] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.257413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.257443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.257470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.257496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.257504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.257530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.257537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.257564] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.257593] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.257622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.257650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.257680] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.257707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.257733] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.257759] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.257787] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.257818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.257853] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.257913] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.257932] [drm:intel_power_well_enable [i915]] enabling display
>[  722.257949] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.257983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.258004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.258022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.258040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.258058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.258077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.258098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.258118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.258144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.258169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.258195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.258247] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.258278] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.260329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.260349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.260367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.260386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.261956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.261976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.261994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.263556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.263576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.265449] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.268785] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.268885] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.268918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.268960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.285661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.285714] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.285785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.319092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.319178] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.319463] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.319513] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.319615] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.336647] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.336689] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.336734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.336775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.336819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.336859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.336894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.336930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.336974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.337016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.337057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.337099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.337138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.337177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.337315] [drm:intel_power_well_disable [i915]] disabling display
>[  722.337383] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.337453] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.337505] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.337595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.337613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.337697] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.337731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.337767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.337807] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.337842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.337870] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.337896] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.337922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.337946] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.337972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.337998] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.338004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.338028] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.338033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.338059] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.338085] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.338111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.338136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.338162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.338187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.338241] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.338272] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.338301] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.338334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.338368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.338458] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.338485] [drm:intel_power_well_enable [i915]] enabling display
>[  722.338504] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.338540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.338560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.338580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.338598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.338617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.338641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.338669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.338696] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.338723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.338748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.338774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.338801] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.338826] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.340982] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.341003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.341021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.341040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.342615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.342635] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.342653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.344202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.344238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.346110] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.349424] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.349491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.349524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.349565] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.366273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.366324] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.366390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.399703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.399788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.399888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.399930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.400029] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.417116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.417153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.417193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.417313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.417370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.417419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.417467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.417509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.417551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.417579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.417606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.417633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.417657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.417681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.417726] [drm:intel_power_well_disable [i915]] disabling display
>[  722.417761] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.417796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.417824] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.417886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.417902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.417971] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.417998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.418029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.418067] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.418101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.418136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.418170] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.418205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.418288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.418327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.418365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.418375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.418412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.418422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.418458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.418493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.418529] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.418565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.418596] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.418623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.418650] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.418676] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.418701] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.418732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.418765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.418857] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.418888] [drm:intel_power_well_enable [i915]] enabling display
>[  722.418918] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.418970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.419003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.419034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.419065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.419095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.419126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.419153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.419175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.419197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.419249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.419277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.419309] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.419338] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.421400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.421421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.421439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.421458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.423027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.423047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.423066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.424630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.424650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.426520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.429807] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.429889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.429913] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.429944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.446686] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.446737] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.446802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.480085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.480180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.480377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.480445] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.480552] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.497584] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.497621] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.497660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.497694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.497728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.497759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.497797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.497836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.497880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.497922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.497964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.498005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.498044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.498083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.498140] [drm:intel_power_well_disable [i915]] disabling display
>[  722.498186] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.498314] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.498348] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.498421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.498436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.498492] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.498514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.498537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.498562] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.498582] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.498604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.498626] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.498646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.498666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.498685] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.498703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.498708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.498727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.498731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.498750] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.498768] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.498787] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.498811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.498837] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.498863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.498889] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.498915] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.498941] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.498968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.498996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.499058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.499081] [drm:intel_power_well_enable [i915]] enabling display
>[  722.499102] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.499142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.499168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.499194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.499256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.499287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.499318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.499351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.499382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.499413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.499441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.499468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.499501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.499530] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.501594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.501616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.501634] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.501653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.503213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.503257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.503276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.504829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.504850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.506745] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.509983] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.510073] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.510102] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.510139] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.526857] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.526908] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.526973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.560270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.560356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.560461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.560511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.560611] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.577642] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.577679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.577719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.577752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.577795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.577835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.577875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.577913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.577958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.578000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.578044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.578076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.578103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.578129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.578176] [drm:intel_power_well_disable [i915]] disabling display
>[  722.578286] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.578345] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.578391] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.578511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.578537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.578655] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.578694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.578741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.578790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.578829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.578874] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.578915] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.578958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.578996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.579040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.579066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.579073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.579099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.579106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.579134] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.579160] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.579187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.579237] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.579270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.579297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.579327] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.579354] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.579383] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.579417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.579452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.579541] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.579571] [drm:intel_power_well_enable [i915]] enabling display
>[  722.579600] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.579650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.579681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.579708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.579737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.579763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.579792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.579825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.579858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.579889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.579915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.579943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.579974] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.580004] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.582071] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.582092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.582110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.582130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.583720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.583743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.583766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.585465] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.585487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.587364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.590663] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.590748] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.590780] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.590822] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.607506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.607555] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.607618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.640930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.641017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.641121] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.641166] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.641537] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.658071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.658108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.658148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.658183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.658296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.658342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.658391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.658437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.658491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.658542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.658591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.658640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.658680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.658723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.658808] [drm:intel_power_well_disable [i915]] disabling display
>[  722.658871] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.658939] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.658970] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.659066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.659084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.659162] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.659189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.659259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.659298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.659326] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.659360] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.659390] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.659422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.659450] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.659481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.659507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.659517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.659544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.659552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.659580] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.659606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.659635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.659661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.659694] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.659719] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.659748] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.659773] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.659800] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.659832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.659867] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.659956] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.659985] [drm:intel_power_well_enable [i915]] enabling display
>[  722.660014] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.660065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.660095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.660122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.660150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.660176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.660227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.660261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.660293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.660327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.660354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.660384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.660420] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.660449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.662512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.662532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.662550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.662569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.664143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.664164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.664186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.665785] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.665805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.667680] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.671004] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.671065] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.671097] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.671145] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.687837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.687885] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.687948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.721257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.721341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.721427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.721468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.721564] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.739128] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.739165] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.739205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.739315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.739478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.739510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.739541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.739573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.739609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.739642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.739674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.739704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.739742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.739760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.739795] [drm:intel_power_well_disable [i915]] disabling display
>[  722.739823] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.739851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.739871] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.739927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.739939] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.739991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.740011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.740034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.740059] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.740078] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.740099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.740120] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.740140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.740160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.740178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.740227] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.740235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.740261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.740269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.740296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.740323] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.740349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.740375] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.740405] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.740431] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.740458] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.740484] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.740511] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.740542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.740574] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.740865] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.740885] [drm:intel_power_well_enable [i915]] enabling display
>[  722.740903] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.740939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.740961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.740981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.741000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.741019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.741039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.741066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.741093] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.741122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.741147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.741173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.741229] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.741259] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.743451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.743472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.743490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.743509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.745079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.745099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.745117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.746678] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.746698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.748603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.751940] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.752021] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.752040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.752066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.768817] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.768869] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.768940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.802242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.802328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.802434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.802484] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.802577] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.819607] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.819644] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.819685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.819718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.819753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.819783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.819813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.819844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.819879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.819912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.819943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.819974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.820001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.820028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.820081] [drm:intel_power_well_disable [i915]] disabling display
>[  722.820122] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.820163] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.820278] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.820423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.820452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.820570] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.820602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.820637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.820674] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.820704] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.820737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.820770] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.820801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.820832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.820862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.820891] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.820898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.820926] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.820933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.820962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.820992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.821021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.821051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.821084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.821113] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.821144] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.821173] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.821224] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.821259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.821292] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.821385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.821415] [drm:intel_power_well_enable [i915]] enabling display
>[  722.821445] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.821496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.821528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.821556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.821586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.821613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.821644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.821678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.821711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.821743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.821773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.821802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.821835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.821867] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.823934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.823955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.823974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.823993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.825557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.825577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.825599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.827189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.827228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.829099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.832402] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.832482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.832520] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.832572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.849263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.849314] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.849380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.882695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.882780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.882882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.882924] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.883014] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.900016] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.900053] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.900093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.900126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.900161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.900191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.900305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.900351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.900413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.900460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.900508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.900554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.900592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.900632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.900711] [drm:intel_power_well_disable [i915]] disabling display
>[  722.900770] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.900827] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.900872] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.901006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.901034] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.901159] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.901201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.901289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.901346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.901396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.901436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.901472] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.901511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.901545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.901583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.901615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.901626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.901658] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.901666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.901699] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.901732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.901766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.901796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.901836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.901866] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.901900] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.901930] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.901963] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.901998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.902037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.902141] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.902178] [drm:intel_power_well_enable [i915]] enabling display
>[  722.902240] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.902302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.902338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.902370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.902411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.902437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.902466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.902500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.902532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.902563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.902591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.902619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.902652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.902681] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.904786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.904807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.904826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.904845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.906412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.906432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.906450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.908006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.908027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.909892] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.913261] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.913324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.913363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.913415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  722.930105] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.930158] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.930314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.963513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.963599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.963704] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  722.963749] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  722.963838] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  722.980870] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  722.980908] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  722.980948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.980981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.981015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.981054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.981094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.981132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  722.981176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.981291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.981348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.981405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.981449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.981496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.981575] [drm:intel_power_well_disable [i915]] disabling display
>[  722.981637] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  722.981700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  722.981748] [drm:intel_power_well_disable [i915]] disabling always-on
>[  722.981889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  722.981918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  722.982042] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  722.982074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  722.982105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  722.982140] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  722.982169] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  722.982225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  722.982257] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  722.982288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  722.982317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  722.982348] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  722.982375] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  722.982384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.982413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  722.982421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  722.982451] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  722.982479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  722.982509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  722.982536] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  722.982568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  722.982595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  722.982624] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  722.982650] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  722.982678] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  722.982711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  722.982745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  722.982834] [drm:intel_power_well_enable [i915]] enabling always-on
>[  722.982864] [drm:intel_power_well_enable [i915]] enabling display
>[  722.982894] [drm:hsw_set_power_well [i915]] Enabling power well
>[  722.982945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  722.982975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  722.983002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  722.983032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  722.983058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  722.983087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  722.983120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  722.983151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  722.983183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  722.983235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  722.983264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  722.983298] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  722.983326] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  722.985389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  722.985412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  722.985435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.985460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  722.987032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  722.987053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  722.987075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  722.988628] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  722.988649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  722.990524] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  722.993825] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  722.993906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  722.993938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  722.993979] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.010688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.010738] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.010804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.044096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.044183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.044372] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.044434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.044548] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.061582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.061619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.061660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.061694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.061728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.061759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.061788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.061819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.061862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.061904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.061946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.061995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.062023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.062050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.062098] [drm:intel_power_well_disable [i915]] disabling display
>[  723.062134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.062173] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.062277] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.062379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.062405] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.062522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.062562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.062608] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.062658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.062697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.062741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.062782] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.062823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.062862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.062901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.062937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.062947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.062983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.063002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.063030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.063056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.063083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.063108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.063140] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.063166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.063219] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.063246] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.063275] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.063309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.063343] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.063432] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.063462] [drm:intel_power_well_enable [i915]] enabling display
>[  723.063492] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.063543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.063574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.063604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.063630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.063658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.063685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.063718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.063749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.063780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.063805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.063833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.063863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.063893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.065961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.065982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.066000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.066019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.067593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.067613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.067631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.069181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.069217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.071089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.074359] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.074405] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.074424] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.074450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.091232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.091283] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.091349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.124603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.124698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.124799] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.124841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.124929] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.141960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.141997] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.142037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.142071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.142106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.142136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.142165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.142277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.142333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.142386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.142438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.142487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.142529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.142575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.142659] [drm:intel_power_well_disable [i915]] disabling display
>[  723.142722] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.142783] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.142841] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.142915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.142934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.143024] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.143053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.143085] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.143118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.143144] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.143184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.143251] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.143283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.143315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.143342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.143370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.143379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.143409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.143417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.143446] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.143473] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.143504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.143530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.143563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.143589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.143619] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.143644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.143673] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.143703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.143736] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.143824] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.143854] [drm:intel_power_well_enable [i915]] enabling display
>[  723.143883] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.143933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.143961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.143991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.144017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.144045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.144072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.144104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.144135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.144167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.144217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.144244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.144278] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.144308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.146371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.146392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.146410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.146428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.147999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.148020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.148040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.149596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.149617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.151486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.154797] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.154868] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.154900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.154941] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.171647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.171697] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.171762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.205041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.205126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.205303] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.205366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.205685] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.224077] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.224114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.224154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.224269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.224324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.224370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.224417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.224463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.224516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.224566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.224615] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.224664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.224705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.224749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.224833] [drm:intel_power_well_disable [i915]] disabling display
>[  723.224873] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.224913] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.224944] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.225038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.225055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.225135] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.225161] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.225234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.225275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.225303] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.225336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.225367] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.225398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.225427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.225457] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.225484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.225493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.225520] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.225528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.225558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.225585] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.225613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.225643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.225672] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.225700] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.225726] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.225754] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.225779] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.225810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.225845] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.225934] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.225964] [drm:intel_power_well_enable [i915]] enabling display
>[  723.225993] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.226044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.226075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.226103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.226131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.226157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.226214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.226247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.226281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.226313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.226340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.226369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.226405] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.226434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.228500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.228521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.228540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.228559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.230174] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.230212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.230231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.231787] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.231808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.233709] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.237033] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.237076] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.237095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.237122] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.253872] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.253921] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.253986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.287310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.287398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.287498] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.287539] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.287627] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.304656] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.304693] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.304733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.304766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.304809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.304849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.304885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.304922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.304966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.305008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.305049] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.305091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.305130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.305168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.305311] [drm:intel_power_well_disable [i915]] disabling display
>[  723.305378] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.305428] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.305460] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.305532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.305544] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.305598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.305620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.305643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.305668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.305688] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.305710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.305731] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.305751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.305771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.305790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.305808] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.305813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.305830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.305835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.305853] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.305871] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.305889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.305906] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.305927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.305945] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.305963] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.305981] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.305999] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.306020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.306044] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.306103] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.306121] [drm:intel_power_well_enable [i915]] enabling display
>[  723.306139] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.306202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.306231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.306260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.306287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.306314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.306342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.306374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.306404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.306434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.306460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.306486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.306520] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.306548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.308601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.308624] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.308644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.308665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.310274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.310295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.310313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.311872] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.311892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.313772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.317092] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.317155] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.317267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.317321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.333936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.333987] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.334052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.367361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.367446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.367548] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.367589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.367688] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.384720] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.384758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.384798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.384831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.384865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.384895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.384924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.384956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.384991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.385023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.385055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.385086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.385115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.385142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.385272] [drm:intel_power_well_disable [i915]] disabling display
>[  723.385342] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.385550] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.385572] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.385628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.385640] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.385693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.385715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.385738] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.385763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.385783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.385805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.385826] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.385846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.385866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.385884] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.385902] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.385907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.385925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.385930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.385948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.385966] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.385984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.386001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.386022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.386041] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.386059] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.386077] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.386094] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.386116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.386139] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.386243] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.386271] [drm:intel_power_well_enable [i915]] enabling display
>[  723.386298] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.386350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.386557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.386578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.386597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.386616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.386636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.386660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.386680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.386702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.386720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.386739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.386761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.386782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.388842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.388864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.388883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.388902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.390491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.390513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.390532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.392091] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.392112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.393976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.397329] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.397412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.397445] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.397487] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.414186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.414268] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.414335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.447617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.447702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.447804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.447846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.447946] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.466113] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.466150] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.466273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.466333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.466390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.466439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.466474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.466506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.466545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.466579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.466610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.466642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.466670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.466699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.466752] [drm:intel_power_well_disable [i915]] disabling display
>[  723.466795] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.466837] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.466868] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.466954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.466973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.467054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.467085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.467129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.467154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.467213] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.467243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.467273] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.467301] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.467330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.467357] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.467383] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.467391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.467417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.467424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.467452] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.467479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.467505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.467531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.467563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.467590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.467616] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.467642] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.467668] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.467697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.467732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.467823] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.467853] [drm:intel_power_well_enable [i915]] enabling display
>[  723.467884] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.467937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.467970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.468001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.468032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.468062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.468093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.468116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.468137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.468164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.468215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.468242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.468275] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.468304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.470367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.470387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.470405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.470424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.471997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.472017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.472035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.473588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.473609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.475478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.478813] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.478913] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.478945] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.478987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.495690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.495744] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.495815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.529125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.529283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.529435] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.529500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.529605] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.546633] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.546675] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.546720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.546761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.546817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.546857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.546892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.546927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.546971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.547013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.547058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.547090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.547117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.547143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.547259] [drm:intel_power_well_disable [i915]] disabling display
>[  723.547317] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.547686] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.547731] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.547853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.547879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.547995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.548036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.548086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.548127] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.548159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.548228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.548267] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.548303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.548337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.548372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.548402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.548413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.548444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.548453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.548487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.548517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.548550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.548580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.548615] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.548645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.548677] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.548707] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.548738] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.548775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.548813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.548913] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.548947] [drm:intel_power_well_enable [i915]] enabling display
>[  723.548980] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.549037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.549076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.549106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.549133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.549162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.549213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.549248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.549282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.549315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.549342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.549371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.549406] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.549435] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.551499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.551523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.551545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.551569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.553154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.553191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.553209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.554781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.554804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.556703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.560000] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.560086] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.560118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.560160] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.576872] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.576923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.576988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.610298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.610384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.610468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.610510] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.610599] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.627636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.627674] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.627714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.627748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.627782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.627812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.627842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.627873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.627908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.627940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.627972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.628002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.628030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.628065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.628110] [drm:intel_power_well_disable [i915]] disabling display
>[  723.628144] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.628250] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.628295] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.628415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.628440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.628551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.628593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.628639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.628687] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.628728] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.628772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.628814] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.628856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.628896] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.628935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.628974] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.628983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.629021] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.629031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.629077] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.629107] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.629136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.629186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.629221] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.629249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.629280] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.629309] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.629339] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.629374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.629410] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.629501] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.629531] [drm:intel_power_well_enable [i915]] enabling display
>[  723.629561] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.629613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.629644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.629677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.629707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.629736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.629767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.629800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.629832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.629865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.629894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.629923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.629957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.629988] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.632061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.632084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.632103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.632122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.633730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.633750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.633768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.635338] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.635359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.637221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.640480] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.640538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.640558] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.640583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.657333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.657383] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.657448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.690767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.690850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.690951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.690993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.691082] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.708074] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.708111] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.708152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.708275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.708332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.708381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.708429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.708476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.708525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.708577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.708626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.708673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.708716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.708758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.708841] [drm:intel_power_well_disable [i915]] disabling display
>[  723.708908] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.708975] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.709007] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.709085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.709104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.709218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.709249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.709282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.709318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.709348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.709380] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.709411] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.709442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.709472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.709501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.709528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.709536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.709562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.709569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.709596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.709623] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.709649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.709674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.709705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.709731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.709758] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.709784] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.709809] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.709841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.709873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.709965] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.709996] [drm:intel_power_well_enable [i915]] enabling display
>[  723.710027] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.710079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.710111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.710142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.710198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.710228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.710260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.710292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.710324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.710354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.710380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.710407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.710441] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.710472] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.712538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.712559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.712577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.712596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.714164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.714198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.714217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.715771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.715795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.717701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.720996] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.721084] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.721116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.721158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.737859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.737907] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.737970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.771256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.771350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.771434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.771482] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.771572] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.788610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.788647] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.788686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.788726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.788770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.788810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.788850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.788888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.788932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.788974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.789016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.789057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.789097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.789135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.789262] [drm:intel_power_well_disable [i915]] disabling display
>[  723.789331] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.789563] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.789597] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.789669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.789686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.789762] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.789783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.789806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.789835] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.789860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.789887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.789913] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.789939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.789965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.789991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.790017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.790022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.790047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.790051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.790078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.790104] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.790130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.790185] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.790219] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.790248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.790278] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.790305] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.790333] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.790365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.790398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.790668] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.790688] [drm:intel_power_well_enable [i915]] enabling display
>[  723.790706] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.790743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.790764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.790784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.790809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.790835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.790861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.790889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.790916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.790944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.790969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.790995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.791022] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.791048] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.793096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.793118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.793136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.793214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.794786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.794808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.794830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.796390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.796411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.798275] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.801611] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.801710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.801743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.801784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.818488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.818538] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.818604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.851864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.851950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.852056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.852099] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.852328] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.869356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.869394] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.869433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.869467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.869501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.869532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.869561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.869592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.869627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.869660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.869691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.869722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.869750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.869778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.869831] [drm:intel_power_well_disable [i915]] disabling display
>[  723.869872] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.869913] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.869944] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.870025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.870042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.870122] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.870153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.870269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.870329] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.870374] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.870427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.870474] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.870524] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.870553] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.870583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.870609] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.870618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.870646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.870653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.870683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.870710] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.870739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.870765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.870797] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.870824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.870853] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.870880] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.870907] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.870939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.870974] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.871065] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.871095] [drm:intel_power_well_enable [i915]] enabling display
>[  723.871124] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.871239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.871269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.871299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.871327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.871356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.871384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.871418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.871450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.871481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.871507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.871536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.871567] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.871597] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.873663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.873684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.873702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.873721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.875317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.875337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.875355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.876906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.876927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.878801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.882094] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.882256] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.882294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.882338] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.898952] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.899000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.899064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.932370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.932456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.932561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  723.932605] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  723.932690] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  723.951131] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  723.951199] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  723.951239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.951273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.951308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.951338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.951367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.951398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.951433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.951465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.951496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.951527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.951555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.951583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.951636] [drm:intel_power_well_disable [i915]] disabling display
>[  723.951676] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  723.951717] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.951748] [drm:intel_power_well_disable [i915]] disabling always-on
>[  723.951832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  723.951850] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  723.951930] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  723.951960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  723.951995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  723.952033] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  723.952064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  723.952096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  723.952128] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  723.952220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  723.952267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  723.952310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  723.952352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  723.952365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.952401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  723.952409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  723.952436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  723.952462] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  723.952489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  723.952515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  723.952547] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  723.952573] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  723.952600] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  723.952626] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  723.952652] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  723.952682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  723.952714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  723.953018] [drm:intel_power_well_enable [i915]] enabling always-on
>[  723.953038] [drm:intel_power_well_enable [i915]] enabling display
>[  723.953056] [drm:hsw_set_power_well [i915]] Enabling power well
>[  723.953092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  723.953117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  723.953145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  723.953199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  723.953232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  723.953261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  723.953293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  723.953326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  723.953480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  723.953500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  723.953519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  723.953542] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  723.953563] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  723.955627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  723.955650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  723.955673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.955698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  723.957411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  723.957433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  723.957452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  723.958997] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  723.959018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  723.960889] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  723.964237] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  723.964324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  723.964358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  723.964400] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  723.981110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  723.981238] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  723.981343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.014510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.014597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.014703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  724.014747] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.014825] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  724.031879] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  724.031916] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.031956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.031995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.032039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.032075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.032114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.032152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.032273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.032330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.032543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.032578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.032608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.032638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.032691] [drm:intel_power_well_disable [i915]] disabling display
>[  724.032732] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.032777] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.032809] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.032897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.032915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.032997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.033030] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.033070] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.033115] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.033166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.033221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.033254] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  724.033283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  724.033312] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.033339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.033365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.033374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.033399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.033407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.033434] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.033461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.033487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.033513] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.033543] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.033569] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.033596] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  724.033622] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  724.033652] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  724.033882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.033907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  724.033968] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.033989] [drm:intel_power_well_enable [i915]] enabling display
>[  724.034011] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.034050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.034076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.034102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.034124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.034177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.034210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.034244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.034276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.034309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.034473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.034492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.034516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  724.034537] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.036581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.036601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.036619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.036638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.038237] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.038257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.038275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.039835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.039857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.041728] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.045067] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  724.045241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.045281] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  724.045325] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.061940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.061990] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.062055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.095351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.095437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.095539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  724.095580] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.095678] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  724.112738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  724.112776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.112816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.112849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.112884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.112913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.112942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.112973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.113008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.113040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.113070] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.113109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.113135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.113230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.113312] [drm:intel_power_well_disable [i915]] disabling display
>[  724.113373] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.113432] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.113462] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.113544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.113562] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.113639] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.113669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.113703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.113740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.113770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.113801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.113832] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  724.113868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  724.113906] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.113945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.113979] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.113986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.114023] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.114030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.114068] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.114112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.114137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.114189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.114222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.114250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.114279] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  724.114305] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  724.114332] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  724.114364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.114397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  724.114488] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.114510] [drm:intel_power_well_enable [i915]] enabling display
>[  724.114528] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.114563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.114584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.114603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.114622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.114639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.114659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.114680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.114700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.114720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.114738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.114756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.114778] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  724.114798] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.116842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.116863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.116882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.116900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.118464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.118484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.118502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.120049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.120070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.121932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.125283] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  724.125362] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.125392] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  724.125428] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.142140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.142222] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.142286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.175539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.175625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.175729] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  724.175773] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.175848] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  724.193011] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  724.193048] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.193088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.193121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.193248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.193300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.193350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.193626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.193666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.193700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.193733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.193772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.193789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.193805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.193837] [drm:intel_power_well_disable [i915]] disabling display
>[  724.193862] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.193888] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.193906] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.193959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.193970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.194019] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.194038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.194058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.194081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.194099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.194118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.194191] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  724.194221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  724.194254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.194285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.194314] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.194323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.194352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.194360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.194390] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.194420] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.194450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.194480] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.194513] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.194543] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.194574] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  724.194603] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  724.194634] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  724.194668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.194704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  724.195058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.195089] [drm:intel_power_well_enable [i915]] enabling display
>[  724.195120] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.195299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.195330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.195359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.195388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.195416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.195445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.195476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.195506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.195536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.195563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.195590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.195621] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  724.195650] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.197747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.197769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.197787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.197811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.199387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.199410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.199433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.200984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.201006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.202879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.206171] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  724.206247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.206266] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  724.206292] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.223042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.223093] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.223249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.256452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.256539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.256645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  724.256696] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.256778] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  724.274796] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  724.274833] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.274873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.274906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.274940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.274970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.274998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.275030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.275065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.275097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.275129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.275228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.275275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.275326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.275413] [drm:intel_power_well_disable [i915]] disabling display
>[  724.275798] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.275837] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.275867] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.275949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.275961] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.276012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.276032] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.276053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.276076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.276095] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.276114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.276186] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  724.276220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  724.276254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.276285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.276317] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.276328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.276358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.276366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.276396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.276427] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.276457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.276487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.276732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.276764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.276796] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  724.276826] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  724.276856] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  724.276889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.276924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  724.277021] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.277050] [drm:intel_power_well_enable [i915]] enabling display
>[  724.277078] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.277125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.277195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.277225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.277257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.277288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.277320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.277356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.277389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.277422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.277452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.277642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.277664] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  724.277683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.279831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.279852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.279870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.279889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.281462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.281482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.281500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.283062] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.283083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.284947] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.288247] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  724.288326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.288355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  724.288393] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.305110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.305194] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.305261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.338520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.338606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.338712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  724.338756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.338835] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  724.355859] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  724.355896] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.355940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.355981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.356025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.356060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.356100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.356138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.356275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.356334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.356389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.356441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.356488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.356534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.356617] [drm:intel_power_well_disable [i915]] disabling display
>[  724.356659] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.356700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.356732] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.356806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.356825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.356909] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.356941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.356976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.357012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.357043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.357076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.357108] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  724.357165] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  724.357196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.357227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.357257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.357267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.357296] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.357304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.357334] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.357364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.357395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.357425] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.357459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.357489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.357520] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  724.357550] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  724.357581] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  724.357612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.357646] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  724.357733] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.357763] [drm:intel_power_well_enable [i915]] enabling display
>[  724.357793] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.357844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.357875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.357906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.357936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.357966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.357997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.358031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.358063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.358095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.358124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.358174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.358209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  724.358241] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.360306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.360329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.360352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.360376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.361939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.361960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.361978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.363545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.363568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.365440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.368786] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  724.368858] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.368878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  724.368904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.385652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.385703] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.385768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.419046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.419133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.419332] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  724.419396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.419504] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  724.436531] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  724.436568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.436608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.436642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.436676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.436706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.436735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.436766] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.436801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.436833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.436864] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.436896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.436924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.436951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.437004] [drm:intel_power_well_disable [i915]] disabling display
>[  724.437044] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.437086] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.437117] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.437295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.437314] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.437396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.437428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.437462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.437499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.437530] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.437562] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.437595] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  724.437626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  724.437657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.437687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.437716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.437723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.437751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.437759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.437788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.437817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.437848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.437876] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.437909] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.437938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.437968] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  724.437997] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  724.438027] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  724.438060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.438094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  724.438207] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.438240] [drm:intel_power_well_enable [i915]] enabling display
>[  724.438272] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.438323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.438354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.438382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.438411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.438440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.438468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.438502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.438535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.438568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.438597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.438626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.438660] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  724.438691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.440760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.440782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.440805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.440829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.442405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.442426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.442444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.443992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.444012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.445888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.449238] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  724.449322] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.449355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  724.449397] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.466100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.466184] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.466251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.499534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.499621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  724.499665] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.499737] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  724.518038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  724.518075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.518115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.518236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.518297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.518346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.518395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.518445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.518502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.518554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.518605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.518656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.518700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.518745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.518832] [drm:intel_power_well_disable [i915]] disabling display
>[  724.518897] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.518961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  724.519011] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.519390] [drm:drm_mode_addfb2] [FB:77]
>[  724.519418] [drm:drm_mode_addfb2] [FB:78]
>[  724.548603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  724.548714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  724.548792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.548863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.548875] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.548934] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.548956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.548979] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.549003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.549022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.549042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.549063] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  724.549082] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  724.549100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.549172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.549202] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.549210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.549237] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.549244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.549273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.549300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.549327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.549354] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.549384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.549411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.549438] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  724.549465] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  724.549493] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  724.549526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.549560] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  724.552811] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.552830] [drm:intel_power_well_enable [i915]] enabling display
>[  724.552846] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.552881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.552902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.552925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.552948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.552972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.552996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.553022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.553046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.553071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.553094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.553117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.553206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  724.553237] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.555316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.555336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.555354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.555373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.556949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.556971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.556990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.558556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.558578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.560449] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.563784] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  724.563885] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.563918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  724.563960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.580665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.580717] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.580783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.597466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.597550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.597635] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  724.597676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.597764] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  724.614790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  724.614827] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.614867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.614900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.614934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.614964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.614993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.615025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.615059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.615091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.615213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.615262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.615304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.615348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.615424] [drm:intel_power_well_disable [i915]] disabling display
>[  724.615481] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.615537] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.615582] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.615709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.615736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.615853] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.615897] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.615944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.616010] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.616053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.616098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.616189] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  724.616226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  724.616265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.616300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.616336] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.616345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.616378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.616387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.616422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.616456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.616491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.616522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.616560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.616594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.616628] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  724.616664] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  724.616697] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  724.616734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.616773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  724.616872] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.616906] [drm:intel_power_well_enable [i915]] enabling display
>[  724.616941] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.616998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.617034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.617069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.617103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.617169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.617210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.617246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.617279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.617312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.617342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.617372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.617406] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  724.617438] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.619503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.619524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.619543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.619561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.621119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.621162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.621180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.622755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.622778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.624657] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.627957] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  724.628040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.628072] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  724.628114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.644814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.644866] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.644933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.678279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.678364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.678465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  724.678505] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.678604] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  724.695685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  724.695722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.695761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.695794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.695828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.695858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.695887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.695918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.695953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.695985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.696016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.696047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.696075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.696103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.696229] [drm:intel_power_well_disable [i915]] disabling display
>[  724.696297] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.696525] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.696558] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.696645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.696662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.696746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.696779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.696819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.696864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.696906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.696930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.696952] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  724.696973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  724.696992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.697012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.697029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.697035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.697052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.697057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.697075] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.697093] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.697141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.697168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.697198] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.697225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.697252] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  724.697279] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  724.697305] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  724.697336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.697368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  724.697635] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.697655] [drm:intel_power_well_enable [i915]] enabling display
>[  724.697674] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.697713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.697737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.697763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.697789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.697815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.697841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.697869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.697897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.697925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.697950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.697977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.698004] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  724.698030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.700085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.700107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.700189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.700225] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.701786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.701807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.701825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.703389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.703410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.705283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.708703] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  724.708784] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.708832] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  724.708899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.725549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.725600] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.725666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.758940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.759027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.759192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  724.759259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.759584] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  724.777946] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  724.777984] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.778023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.778063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.778107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.778226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.778278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.778330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.778387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.778440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.778487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.778522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.778551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.778580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.778634] [drm:intel_power_well_disable [i915]] disabling display
>[  724.778675] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.778718] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.778751] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.778827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.778839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.778892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.778912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.778934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.778959] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.778979] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.779000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.779021] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  724.779041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  724.779061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.779080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.779097] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.779139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.779165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.779175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.779203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.779230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.779256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.779282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.779311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.779338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.779365] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  724.779392] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  724.779419] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  724.779449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.779481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  724.779570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.779601] [drm:intel_power_well_enable [i915]] enabling display
>[  724.779631] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.779685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.779717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.779747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.779777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.779808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.779839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.779867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.779889] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.779909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.779928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.779946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.779970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  724.779990] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.782061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.782082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.782100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.782178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.783742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.783762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.783780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.785344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.785365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.787238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.790556] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  724.790619] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.790652] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  724.790694] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.807379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.807425] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.807489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.840802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.840898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.840999] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  724.841041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.841129] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  724.858542] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  724.858580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.858619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.858652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.858686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.858716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.858745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.858776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.858811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.858843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.858874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.858905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.858933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.858960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.859013] [drm:intel_power_well_disable [i915]] disabling display
>[  724.859053] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.859094] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.859206] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.859707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.859737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.859850] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.859878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.859909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.859942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.859969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.859998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.860025] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  724.860053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  724.860079] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.860116] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.860175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.860184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.860213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.860221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.860251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.860279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.860308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.860335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.860367] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.860394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.860424] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  724.860451] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  724.860482] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  724.860515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.860794] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  724.860889] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.860917] [drm:intel_power_well_enable [i915]] enabling display
>[  724.860944] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.860994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.861014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.861033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.861051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.861068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.861086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.861152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.861188] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.861220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.861248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.861278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.861313] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  724.861342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.863639] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.863659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.863678] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.863696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.865287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.865309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.865329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.866883] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.866904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.868778] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.872065] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  724.872209] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.872245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  724.872289] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.888940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.888993] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.889065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.922334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.922423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.922528] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  724.922578] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  724.922677] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  724.939708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  724.939746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  724.939786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.939826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.939869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.939905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.939945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.939983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.940027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.940068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.940110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.940235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.940282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.940330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.940413] [drm:intel_power_well_disable [i915]] disabling display
>[  724.940488] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  724.940532] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.940565] [drm:intel_power_well_disable [i915]] disabling always-on
>[  724.940643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  724.940656] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  724.940710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  724.940732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  724.940755] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  724.940780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  724.940801] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  724.940822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  724.940844] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  724.940864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  724.940884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  724.940903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  724.940921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  724.940925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.940943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  724.940947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  724.940966] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  724.940984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  724.941002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  724.941020] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  724.941042] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  724.941059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  724.941078] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  724.941096] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  724.941151] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  724.941181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  724.941215] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  724.941305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  724.941333] [drm:intel_power_well_enable [i915]] enabling display
>[  724.941364] [drm:hsw_set_power_well [i915]] Enabling power well
>[  724.941417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  724.941450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  724.941480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  724.941511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  724.941540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  724.941571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  724.941605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  724.941631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  724.941652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  724.941671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  724.941689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  724.941717] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  724.941743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  724.943791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  724.943812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  724.943834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.943858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  724.945434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  724.945454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  724.945472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  724.947031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  724.947052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  724.948919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  724.952260] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  724.952358] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  724.952399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  724.952450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  724.969159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  724.969212] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  724.969284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.002554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.002643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.002744] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.002786] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.002885] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.019963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.020000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.020039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.020072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.020106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.020215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.020260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.020311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.020367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.020418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.020468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.020514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.020540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.020570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.020624] [drm:intel_power_well_disable [i915]] disabling display
>[  725.020667] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.020707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.020739] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.020838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.020856] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.020935] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.020961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.020991] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.021024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.021050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.021079] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.021147] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.021179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.021210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.021238] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.021267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.021275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.021303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.021311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.021341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.021370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.021400] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.021426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.021459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.021485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.021516] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.021548] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.021574] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.021607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.021641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.021730] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.021760] [drm:intel_power_well_enable [i915]] enabling display
>[  725.021790] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.021839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.021870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.021897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.021926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.021952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.021982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.022015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.022047] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.022078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.022130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.022157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.022191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.022221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.024285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.024306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.024324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.024343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.025913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.025933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.025951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.027504] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.027524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.029396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.032732] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.032814] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.032834] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.032860] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.049609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.049660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.049726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.083011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.083096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.083287] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.083349] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.083463] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.100546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.100583] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.100622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.100656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.100691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.100722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.100751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.100783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.100825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.100868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.100910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.100952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.100990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.101029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.101086] [drm:intel_power_well_disable [i915]] disabling display
>[  725.101215] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.101286] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.101335] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.101424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.101443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.101530] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.101560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.101593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.101630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.101658] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.101689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.101719] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.101749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.101777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.101805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.101831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.101838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.101865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.101871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.101900] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.101926] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.101954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.101980] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.102011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.102037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.102065] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.102091] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.102142] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.102172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.102208] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.102298] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.102328] [drm:intel_power_well_enable [i915]] enabling display
>[  725.102358] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.102407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.102435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.102465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.102491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.102519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.102546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.102578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.102609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.102640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.102666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.102694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.102724] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.102754] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.104824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.104846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.104865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.104884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.106453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.106472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.106493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.108109] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.108157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.110041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.113386] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.113480] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.113499] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.113525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.130255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.130309] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.130381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.163687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.163774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.163876] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.163918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.164006] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.181014] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.181052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.181091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.181210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.181253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.181287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.181316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.181348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.181384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.181417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.181450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.181482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.181512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.181540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.181594] [drm:intel_power_well_disable [i915]] disabling display
>[  725.181635] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.181678] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.181709] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.181795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.181813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.181896] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.181928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.181964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.182007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.182047] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.182089] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.182185] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.182225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.182263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.182300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.182335] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.182345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.182379] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.182389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.182424] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.182460] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.182494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.182529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.182569] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.182603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.182638] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.182672] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.182707] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.182749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.182790] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.182903] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.182931] [drm:intel_power_well_enable [i915]] enabling display
>[  725.182959] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.183010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.183045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.183080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.183153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.183183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.183214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.183246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.183279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.183311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.183340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.183368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.183403] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.183435] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.185499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.185523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.185545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.185569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.187135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.187156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.187174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.188737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.188758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.190624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.193945] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.194007] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.194040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.194083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.210785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.210836] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.210903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.244212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.244299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.244404] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.244450] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.244530] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.261554] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.261591] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.261631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.261664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.261707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.261746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.261782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.261819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.261863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.261904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.261946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.261988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.262031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.262060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.262164] [drm:intel_power_well_disable [i915]] disabling display
>[  725.262223] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.262278] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.262322] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.262399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.262416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.262488] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.262517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.262548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.262582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.262609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.262637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.262665] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.262693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.262718] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.262743] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.262767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.262775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.262797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.262803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.262828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.262852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.262876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.262899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.262928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.262960] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.262995] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.263034] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.263054] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.263076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.263130] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.263221] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.263248] [drm:intel_power_well_enable [i915]] enabling display
>[  725.263279] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.263333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.263365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.263396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.263426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.263456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.263487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.263521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.263554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.263587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.263607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.263625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.263648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.263668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.265714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.265735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.265756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.265780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.267345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.267366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.267388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.268936] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.268957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.270819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.274144] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.274202] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.274221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.274247] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.290975] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.291023] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.291086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.324379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.324464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.324567] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.324609] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.324684] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.343180] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.343218] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.343257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.343291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.343325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.343355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.343384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.343415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.343450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.343483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.343514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.343546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.343574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.343602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.343654] [drm:intel_power_well_disable [i915]] disabling display
>[  725.343694] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.343736] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.343767] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.343850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.343862] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.343910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.343929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.343950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.343972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.343990] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.344009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.344028] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.344046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.344064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.344131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.344160] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.344169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.344195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.344203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.344230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.344257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.344284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.344310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.344340] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.344366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.344393] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.344419] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.344445] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.344476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.344508] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.344598] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.344628] [drm:intel_power_well_enable [i915]] enabling display
>[  725.344656] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.344705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.344726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.344745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.344764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.344782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.344801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.344822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.344842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.344863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.344880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.344898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.344920] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.344942] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.346973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.346994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.347012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.347031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.348630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.348653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.348676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.350256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.350279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.352151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.355505] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.355586] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.355619] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.355661] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.372372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.372423] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.372489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.405797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.405883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.405971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.406020] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.406184] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.423224] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.423261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.423301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.423334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.423369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.423398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.423427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.423458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.423493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.423524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.423555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.423585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.423620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.423644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.423692] [drm:intel_power_well_disable [i915]] disabling display
>[  725.423728] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.423765] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.423792] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.423857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.423874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.423946] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.423974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.424009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.424049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.424083] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.424190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.424235] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.424275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.424315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.424353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.424390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.424401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.424438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.424448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.424485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.424522] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.424559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.424595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.424643] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.424669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.424696] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.424725] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.424753] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.424783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.424815] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.424903] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.424935] [drm:intel_power_well_enable [i915]] enabling display
>[  725.424965] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.425018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.425050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.425080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.425136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.425166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.425197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.425230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.425262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.425292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.425319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.425346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.425379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.425411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.427474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.427495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.427513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.427532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.429119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.429139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.429157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.430716] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.430736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.432610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.435902] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.435977] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.435996] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.436021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.452761] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.452810] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.452874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.486192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.486289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.486389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.486431] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.486529] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.503565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.503603] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.503642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.503676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.503711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.503741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.503769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.503800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.503835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.503867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.503907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.503949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.503988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.504027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.504084] [drm:intel_power_well_disable [i915]] disabling display
>[  725.504206] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.504276] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.504328] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.504443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.504472] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.504603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.504633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.504666] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.504702] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.504730] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.504761] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.504791] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.504821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.504848] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.504877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.504903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.504910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.504936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.504943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.504972] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.504998] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.505025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.505050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.505082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.505134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.505161] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.505192] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.505219] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.505253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.505288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.505378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.505408] [drm:intel_power_well_enable [i915]] enabling display
>[  725.505438] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.505488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.505518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.505547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.505574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.505602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.505630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.505663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.505695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.505727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.505753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.505780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.505811] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.505841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.507924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.507947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.507966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.507985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.509569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.509590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.509608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.511188] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.511209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.513073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.516424] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.516527] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.516567] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.516619] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.533309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.533361] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.533427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.566697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.566783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.566887] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.566932] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.567028] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.584038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.584075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.584319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.584355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.584398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.584427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.584454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.584484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.584517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.584548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.584586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.584625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.584663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.584699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.584752] [drm:intel_power_well_disable [i915]] disabling display
>[  725.584795] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.584842] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.584876] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.584957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.584974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.585056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.585154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.585210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.585269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.585315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.585365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.585414] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.585447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.585479] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.585510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.585540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.585550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.585578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.585586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.585617] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.585648] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.585679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.585708] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.585742] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.585770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.585799] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.585828] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.585859] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.585892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.585927] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.586015] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.586045] [drm:intel_power_well_enable [i915]] enabling display
>[  725.586075] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.586153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.586186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.586218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.586248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.586278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.586309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.586344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.586377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.586409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.586438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.586469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.586502] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.586534] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.588604] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.588625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.588644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.588663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.590241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.590263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.590282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.591847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.591868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.593735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.597035] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.597190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.597236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.597301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.613904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.613958] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.614030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.647329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.647417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.647518] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.647560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.647658] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.664691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.664729] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.664768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.664802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.664837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.664875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.664915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.664954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.664999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.665040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.665082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.665211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.665257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.665300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.665373] [drm:intel_power_well_disable [i915]] disabling display
>[  725.665427] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.665481] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.665524] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.665639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.665664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.665777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.665819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.665865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.665913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.665954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.665997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.666040] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.666080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.666160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.666193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.666223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.666234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.666263] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.666271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.666302] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.666333] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.666363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.666393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.666423] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.666453] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.666484] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.666513] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.666539] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.666572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.666608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.666694] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.666725] [drm:intel_power_well_enable [i915]] enabling display
>[  725.666754] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.666806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.666838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.666868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.666898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.666928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.666959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.666992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.667024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.667056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.667110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.667140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.667176] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.667208] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.669273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.669293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.669312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.669331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.670904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.670927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.670950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.672506] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.672527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.674403] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.677628] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.677670] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.677693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.677725] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.694453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.694501] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.694565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.727873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.727959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.728063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.728178] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.728303] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.745339] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.745377] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.745417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.745451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.745486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.745516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.745545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.745576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.745611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.745643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.745674] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.745705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.745732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.745759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.745813] [drm:intel_power_well_disable [i915]] disabling display
>[  725.745853] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.745898] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.745934] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.746023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.746034] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.746160] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.746195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.746233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.746270] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.746301] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.746334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.746364] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.746396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.746428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.746458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.746487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.746495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.746523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.746530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.746559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.746588] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.746617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.746646] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.746678] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.746708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.746737] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.746768] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.746796] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.746828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.746862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.746953] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.746984] [drm:intel_power_well_enable [i915]] enabling display
>[  725.747015] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.747065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.747121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.747152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.747183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.747211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.747243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.747278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.747312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.747345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.747375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.747406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.747439] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.747472] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.749561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.749582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.749601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.749620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.751213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.751234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.751252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.752814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.752835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.754698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.758018] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.758082] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.758196] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.758257] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.774862] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.774913] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.774979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.808289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.808375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.808477] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.808519] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.808610] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.825663] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.825701] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.825740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.825774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.825809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.825839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.825868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.825899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.825934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.825965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.825996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.826026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.826054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.826162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.826248] [drm:intel_power_well_disable [i915]] disabling display
>[  725.826314] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.826376] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.826426] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.826566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.826594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.826730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.826782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.826835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.826892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.826941] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.826974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.827006] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.827039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.827070] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.827123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.827154] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.827163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.827195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.827203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.827233] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.827264] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.827296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.827328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.827361] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.827392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.827422] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.827453] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.827479] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.827512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.827547] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.827638] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.827669] [drm:intel_power_well_enable [i915]] enabling display
>[  725.827695] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.827746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.827778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.827809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.827839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.827868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.827900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.827934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.827967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.827999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.828030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.828059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.828116] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.828149] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.830212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.830233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.830251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.830270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.831841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.831861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.831884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.833450] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.833472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.835345] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.838690] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.838779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.838812] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.838855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.855558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.855609] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.855675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.888966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.889052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.889250] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.889314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.889415] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.906444] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.906482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.906521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.906555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.906589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.906619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.906648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.906685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.906730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.906772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.906814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.906856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.906895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.906933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.906990] [drm:intel_power_well_disable [i915]] disabling display
>[  725.907034] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.907063] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.907154] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.907247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.907266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.907352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.907385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.907419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.907457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.907488] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.907521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.907554] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.907585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.907616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.907646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.907675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.907683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.907710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.907717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.907747] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.907776] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.907805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.907835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.907869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.907898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.907928] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.907957] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.907986] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.908019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.908054] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.908168] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.908199] [drm:intel_power_well_enable [i915]] enabling display
>[  725.908230] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.908285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.908316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.908346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.908377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.908404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.908434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.908468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.908500] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.908531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.908560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.908587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.908620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.908650] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.910722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.910744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.910763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.910786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.912366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.912389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.912412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.913975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.913996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.915878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.919234] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.919297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.919316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  725.919342] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  725.936122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.936173] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.936239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.969522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.969606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.969707] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  725.969749] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  725.969836] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  725.986911] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  725.986953] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  725.986997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.987038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.987162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.987212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.987263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.987308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  725.987364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.987415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.987465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.987514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.987555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.987599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.987680] [drm:intel_power_well_disable [i915]] disabling display
>[  725.987742] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  725.987799] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  725.987830] [drm:intel_power_well_disable [i915]] disabling always-on
>[  725.987930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  725.987948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  725.988026] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  725.988053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  725.988122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  725.988163] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  725.988192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  725.988225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  725.988256] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  725.988288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  725.988317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  725.988348] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  725.988374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  725.988383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.988411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  725.988419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  725.988449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  725.988474] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  725.988504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  725.988529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  725.988561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  725.988586] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  725.988615] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  725.988640] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  725.988668] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  725.988700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  725.988734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  725.988822] [drm:intel_power_well_enable [i915]] enabling always-on
>[  725.988853] [drm:intel_power_well_enable [i915]] enabling display
>[  725.988882] [drm:hsw_set_power_well [i915]] Enabling power well
>[  725.988933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  725.988961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  725.988990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  725.989017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  725.989045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  725.989098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  725.989131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  725.989165] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  725.989198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  725.989225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  725.989255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  725.989290] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  725.989319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  725.991381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  725.991402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  725.991420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.991439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  725.993001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  725.993021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  725.993039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  725.994635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  725.994657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  725.996542] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  725.999850] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  725.999927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  725.999970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.000010] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.016693] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.016739] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.016803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.050182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.050267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.050368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.050411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.050500] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.067562] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.067599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.067638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.067672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.067706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.067735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.067763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.067794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.067828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.067861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.067892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.067923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.067951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.067978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.068031] [drm:intel_power_well_disable [i915]] disabling display
>[  726.068161] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.068229] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.068281] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.068400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.068429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.068561] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.068606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.068662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.068697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.068725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.068756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.068785] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.068815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.068843] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.068871] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.068897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.068904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.068931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.068938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.068967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.068993] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.069020] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.069045] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.069103] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.069130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.069161] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.069188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.069219] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.069253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.069288] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.069378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.069408] [drm:intel_power_well_enable [i915]] enabling display
>[  726.069438] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.069487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.069515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.069544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.069570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.069598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.069625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.069659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.069691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.069723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.069750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.069779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.069809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.069839] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.071919] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.071941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.071960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.071979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.073574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.073595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.073613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.075278] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.075299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.077166] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.080488] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.080549] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.080581] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.080623] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.097318] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.097366] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.097435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.130725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.130814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.130920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.130965] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.131061] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.148418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.148456] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.148495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.148528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.148562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.148592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.148620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.148652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.148686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.148718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.148750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.148781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.148809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.148837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.148891] [drm:intel_power_well_disable [i915]] disabling display
>[  726.148931] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.148979] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.149015] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.149181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.149210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.149348] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.149401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.149454] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.149513] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.149561] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.149615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.149647] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.149675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.149705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.149731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.149759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.149766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.149794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.149800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.149829] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.149855] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.149882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.149907] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.149939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.149965] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.149993] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.150019] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.150047] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.150106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.150142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.150232] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.150263] [drm:intel_power_well_enable [i915]] enabling display
>[  726.150295] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.150348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.150381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.150412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.150442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.150472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.150501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.150534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.150566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.150598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.150624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.150651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.150682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.150712] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.152781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.152801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.152820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.152839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.154404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.154424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.154442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.156001] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.156025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.157931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.161272] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.161366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.161399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.161441] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.178144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.178194] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.178260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.211539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.211625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.211729] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.211773] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.211868] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.228887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.228929] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.228973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.229013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.229057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.229181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.229234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.229286] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.229345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.229398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.229439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.229460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.229478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.229497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.229532] [drm:intel_power_well_disable [i915]] disabling display
>[  726.229559] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.229592] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.229615] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.229673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.229686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.229744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.229770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.229797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.229826] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.229851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.229878] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.229904] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.229930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.229956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.229982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.230007] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.230013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.230038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.230067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.230100] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.230130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.230158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.230188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.230219] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.230246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.230274] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.230301] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.230328] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.230359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.230392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.230481] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.230509] [drm:intel_power_well_enable [i915]] enabling display
>[  726.230541] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.230594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.230626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.230657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.230687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.230717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.230747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.230782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.230814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.230846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.230865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.230889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.230917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.230943] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.232991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.233012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.233031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.233098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.234737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.234759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.234778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.236323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.236343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.238206] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.241510] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.241602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.241623] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.241650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.258368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.258420] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.258485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.291792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.291879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.291982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.292031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.292200] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.309255] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.309305] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.309358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.309391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.309424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.309453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.309480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.309509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.309542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.309572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.309601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.309630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.309656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.309682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.309735] [drm:intel_power_well_disable [i915]] disabling display
>[  726.309778] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.309825] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.309859] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.309942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.309959] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.310045] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.310153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.310204] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.310263] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.310291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.310323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.310353] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.310382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.310412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.310439] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.310466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.310474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.310500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.310507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.310537] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.310565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.310593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.310621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.310654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.310676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.310694] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.310712] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.310731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.310752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.310776] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.310836] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.310856] [drm:intel_power_well_enable [i915]] enabling display
>[  726.310873] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.310908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.310928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.310947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.310966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.310984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.311004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.311025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.311075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.311106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.311133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.311160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.311192] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.311221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.313284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.313307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.313330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.313354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.314926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.314947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.314965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.316526] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.316547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.318452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.321765] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.321832] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.321861] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.321899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.338615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.338667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.338733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.372028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.372149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.372252] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.372293] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.372393] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.389424] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.389462] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.389501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.389541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.389585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.389624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.389659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.389695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.389739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.389781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.389822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.389864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.389903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.389942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.389999] [drm:intel_power_well_disable [i915]] disabling display
>[  726.390044] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.390164] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.390198] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.390287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.390306] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.390390] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.390422] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.390454] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.390490] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.390518] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.390550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.390579] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.390611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.390639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.390668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.390694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.390701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.390728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.390734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.390763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.390789] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.390817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.390842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.390873] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.390899] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.390926] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.390952] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.390979] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.391011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.391046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.391155] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.391187] [drm:intel_power_well_enable [i915]] enabling display
>[  726.391216] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.391268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.391299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.391326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.391355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.391381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.391410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.391444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.391475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.391507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.391532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.391560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.391591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.391622] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.393688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.393708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.393726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.393745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.395321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.395341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.395359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.396920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.396941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.398815] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.402163] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.402250] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.402292] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.402318] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.419029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.419113] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.419180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.452436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.452522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.452626] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.452676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.452775] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.469816] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.469854] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.469893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.469927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.469962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.469992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.470022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.470134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.470191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.470246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.470297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.470347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.470389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.470432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.470517] [drm:intel_power_well_disable [i915]] disabling display
>[  726.470584] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.470645] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.470694] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.470833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.470862] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.470962] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.470989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.471020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.471092] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.471124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.471159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.471190] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.471222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.471251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.471281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.471308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.471317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.471345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.471353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.471383] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.471410] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.471438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.471465] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.471497] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.471523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.471551] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.471577] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.471605] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.471638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.471672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.471761] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.471791] [drm:intel_power_well_enable [i915]] enabling display
>[  726.471821] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.471870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.471899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.471929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.471956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.471985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.472012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.472046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.472101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.472133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.472160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.472190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.472225] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.472255] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.474317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.474338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.474356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.474375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.475936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.475956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.475974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.477558] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.477579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.479458] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.482893] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.482990] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.483019] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.483106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.499764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.499815] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.499882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.533169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.533262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.533353] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.533395] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.533489] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.551727] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.551764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.551804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.551838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.551873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.551912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.551949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.551987] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.552031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.552148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.552204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.552258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.552302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.552351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.552667] [drm:intel_power_well_disable [i915]] disabling display
>[  726.552708] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.552756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.552787] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.552865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.552877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.552931] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.552955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.552979] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.553006] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.553029] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.553099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.553137] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.553166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.553199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.553228] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.553258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.553266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.553295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.553303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.553334] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.553361] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.553391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.553417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.553749] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.553777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.553806] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.553832] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.553859] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.553889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.553921] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.554005] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.554044] [drm:intel_power_well_enable [i915]] enabling display
>[  726.554102] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.554155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.554304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.554325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.554345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.554363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.554383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.554406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.554427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.554447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.554465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.554489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.554516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.554541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.556623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.556646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.556669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.556693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.558284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.558306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.558325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.559889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.559910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.561786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.565089] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.565165] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.565194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.565231] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.581946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.581995] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.582157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.615385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.615472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.615577] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.615622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.615727] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.632771] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.632809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.632849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.632888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.632932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.632972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.633007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.633042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.633181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.633240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.633294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.633348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.633394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.633443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.633499] [drm:intel_power_well_disable [i915]] disabling display
>[  726.633541] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.633582] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.633615] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.633708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.633727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.633819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.633848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.633880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.633914] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.633942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.633973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.634004] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.634043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.634102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.634135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.634167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.634175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.634206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.634214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.634246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.634277] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.634304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.634334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.634368] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.634399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.634430] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.634460] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.634491] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.634523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.634559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.634650] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.634680] [drm:intel_power_well_enable [i915]] enabling display
>[  726.634710] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.634761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.634792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.634823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.634849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.634879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.634909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.634943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.634975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.635007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.635036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.635090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.635126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.635158] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.637238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.637262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.637286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.637310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.638882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.638904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.638922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.640476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.640497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.642371] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.645705] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.645738] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.645757] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.645783] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.662535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.662586] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.662652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.695949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.696033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.696232] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.696298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.696411] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.713425] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.713462] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.713501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.713541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.713585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.713625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.713659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.713695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.713739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.713781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.713823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.713865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.713904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.713942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.713999] [drm:intel_power_well_disable [i915]] disabling display
>[  726.714113] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.714181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.714228] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.714481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.714494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.714551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.714574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.714598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.714624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.714644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.714667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.714689] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.714711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.714731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.714751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.714769] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.714775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.714792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.714797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.714816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.714834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.714853] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.714870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.714891] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.714915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.714942] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.714967] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.714993] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.715020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.715083] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.715173] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.715387] [drm:intel_power_well_enable [i915]] enabling display
>[  726.715406] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.715443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.715465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.715487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.715506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.715526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.715546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.715569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.715590] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.715611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.715629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.715647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.715673] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.715699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.717723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.717746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.717766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.717787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.719328] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.719350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.719369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.720896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.720919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.722762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.725783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.725828] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.725848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.725876] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.742621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.742670] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.742735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.776007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.776113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.776216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.776258] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.776347] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.793459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.793496] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.793540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.793580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.793624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.793664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.793704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.793742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.793786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.793828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.793869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.793911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.793951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.793995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.794096] [drm:intel_power_well_disable [i915]] disabling display
>[  726.794141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.794186] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.794219] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.794292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.794311] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.794378] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.794400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.794424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.794449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.794468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.794491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.794512] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.794532] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.794552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.794571] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.794589] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.794594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.794611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.794615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.794635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.794653] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.794671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.794689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.794711] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.794729] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.794748] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.794765] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.794783] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.794804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.794828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.794887] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.794905] [drm:intel_power_well_enable [i915]] enabling display
>[  726.794923] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.794957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.794977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.794997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.795015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.795066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.795095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.795128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.795161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.795193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.795220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.795247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.795279] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.795308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.797373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.797394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.797412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.797432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.799025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.799063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.799081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.800652] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.800675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.802582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.805881] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.805969] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.806009] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.806135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.822745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.822796] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.822862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.856121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.856207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.856311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.856355] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.856447] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.873568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.873610] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.873654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.873695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.873738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.873778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.873818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.873856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.873900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.873942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.873990] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.874024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.874120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.874162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.874236] [drm:intel_power_well_disable [i915]] disabling display
>[  726.874294] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.874351] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.874396] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.874511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.874537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.874654] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.874698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.874746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.874798] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.874841] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.874887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.874932] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.874976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.875020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.875074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.875103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.875111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.875141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.875149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.875180] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.875210] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.875241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.875272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.875305] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.875335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.875365] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.875396] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.875427] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.875460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.875495] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.875586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.875617] [drm:intel_power_well_enable [i915]] enabling display
>[  726.875647] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.875699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.875731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.875763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.875793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.875822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.875853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.875887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.875920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.875953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.875982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.876011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.876072] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.876105] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.878169] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.878190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.878208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.878227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.879798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.879818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.879836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.881390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.881410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.883283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.886592] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.886661] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.886692] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.886731] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.903447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.903497] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.903563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.936848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.936936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.937103] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  726.937170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  726.937283] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  726.954321] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  726.954359] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  726.954398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.954432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.954466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.954496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.954525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.954557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.954591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.954623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.954654] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.954694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.954719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.954743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.954790] [drm:intel_power_well_disable [i915]] disabling display
>[  726.954827] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  726.954864] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.954891] [drm:intel_power_well_disable [i915]] disabling always-on
>[  726.954967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  726.954983] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  726.955150] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  726.955196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  726.955247] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  726.955299] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  726.955342] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  726.955390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  726.955434] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  726.955478] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  726.955520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  726.955561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  726.955601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  726.955612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.955650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  726.955660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  726.955701] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  726.955741] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  726.955770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  726.955799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  726.955831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  726.955860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  726.955889] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  726.955919] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  726.955947] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  726.955980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  726.956014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  726.956128] [drm:intel_power_well_enable [i915]] enabling always-on
>[  726.956160] [drm:intel_power_well_enable [i915]] enabling display
>[  726.956190] [drm:hsw_set_power_well [i915]] Enabling power well
>[  726.956243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  726.956275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  726.956302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  726.956332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  726.956362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  726.956393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  726.956427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  726.956460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  726.956493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  726.956522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  726.956551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  726.956585] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  726.956617] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  726.958708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  726.958730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  726.958749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.958768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  726.960344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  726.960365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  726.960383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  726.961941] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  726.961962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  726.963838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  726.967094] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  726.967154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  726.967174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  726.967200] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  726.983949] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  726.984001] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  726.984172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.017356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.017443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.017547] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.017591] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.017682] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.034742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.034779] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.034819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.034853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.034888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.034918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.034947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.034979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.035014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.035130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.035187] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.035240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.035287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.035335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.035421] [drm:intel_power_well_disable [i915]] disabling display
>[  727.035489] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.035544] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.035576] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.035665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.035685] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.035770] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.035802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.035836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.035873] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.035904] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.035937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.035969] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.036001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.036055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.036087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.036115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.036123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.036152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.036160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.036191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.036221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.036252] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.036281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.036311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.036342] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.036372] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.036402] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.036433] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.036466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.036500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.036587] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.036618] [drm:intel_power_well_enable [i915]] enabling display
>[  727.036648] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.036699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.036731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.036762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.036792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.036822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.036853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.036887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.036920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.036952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.036981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.037010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.037070] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.037103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.039170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.039190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.039208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.039227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.040788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.040808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.040826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.042383] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.042406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.044279] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.047614] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.047727] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.047749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.047781] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.064492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.064543] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.064609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.097898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.097984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.098181] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.098245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.098353] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.115356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.115398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.115443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.115483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.115527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.115561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.115601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.115638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.115682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.115724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.115766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.115807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.115846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.115885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.115942] [drm:intel_power_well_disable [i915]] disabling display
>[  727.115987] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.116123] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.116177] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.116317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.116344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.116458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.116491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.116526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.116563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.116594] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.116628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.116660] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.116692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.116723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.116753] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.116783] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.116790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.116818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.116825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.116854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.116883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.116913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.116942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.116975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.117005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.117065] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.117094] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.117125] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.117159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.117195] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.117286] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.117317] [drm:intel_power_well_enable [i915]] enabling display
>[  727.117347] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.117398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.117429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.117461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.117491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.117522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.117552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.117585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.117618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.117650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.117680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.117710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.117744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.117775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.119842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.119863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.119881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.119900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.121479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.121500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.121518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.123107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.123128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.125010] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.128362] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.128460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.128493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.128536] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.145239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.145290] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.145356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.178646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.178732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.178837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.178886] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.178979] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.196293] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.196331] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.196370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.196404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.196438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.196467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.196505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.196544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.196588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.196630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.196672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.196714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.196752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.196791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.196848] [drm:intel_power_well_disable [i915]] disabling display
>[  727.196893] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.196943] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.196979] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.197176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.197206] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.197333] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.197365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.197400] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.197436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.197464] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.197496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.197526] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.197556] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.197584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.197613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.197638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.197646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.197672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.197679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.197707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.197733] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.197761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.197786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.197816] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.197842] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.197870] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.197895] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.197922] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.197951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.197984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.198097] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.198128] [drm:intel_power_well_enable [i915]] enabling display
>[  727.198158] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.198210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.198241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.198268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.198298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.198325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.198354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.198387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.198418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.198449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.198475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.198503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.198534] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.198564] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.200630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.200650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.200668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.200687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.202267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.202288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.202307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.203869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.203890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.205754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.209103] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.209190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.209223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.209265] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.225968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.226019] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.226178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.259376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.259462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.259566] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.259611] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.259700] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.276793] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.276830] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.276870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.276904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.276939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.276978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.277018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.277131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.277193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.277241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.277286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.277331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.277369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.277407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.277480] [drm:intel_power_well_disable [i915]] disabling display
>[  727.277536] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.277593] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.277636] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.277762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.277787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.277908] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.277948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.277994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.278080] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.278129] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.278178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.278211] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.278240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.278272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.278300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.278328] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.278337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.278365] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.278373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.278402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.278428] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.278457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.278484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.278515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.278541] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.278568] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.278593] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.278622] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.278651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.278685] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.278772] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.278801] [drm:intel_power_well_enable [i915]] enabling display
>[  727.278830] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.278880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.278910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.278937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.278965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.278991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.279042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.279075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.279109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.279142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.279169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.279197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.279232] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.279261] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.281323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.281344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.281366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.281390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.283000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.283037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.283056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.284629] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.284653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.286555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.289839] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.289938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.289971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.290079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.306717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.306768] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.306835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.340135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.340222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.340327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.340372] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.340450] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.357469] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.357506] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.357545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.357578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.357612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.357642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.357671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.357702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.357737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.357769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.357799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.357829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.357857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.357884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.357944] [drm:intel_power_well_disable [i915]] disabling display
>[  727.357969] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.357994] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.358060] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.358138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.358157] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.358244] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.358273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.358307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.358342] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.358372] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.358403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.358433] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.358462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.358490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.358518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.358544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.358551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.358577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.358584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.358612] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.358638] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.358665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.358691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.358721] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.358746] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.358774] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.358800] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.358827] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.358856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.358888] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.358976] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.359006] [drm:intel_power_well_enable [i915]] enabling display
>[  727.359058] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.359110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.359141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.359170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.359201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.359228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.359259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.359293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.359326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.359358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.359385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.359413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.359449] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.359478] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.361575] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.361596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.361615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.361634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.363226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.363249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.363268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.364841] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.364864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.366735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.370082] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.370166] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.370185] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.370211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.386948] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.386999] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.387161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.420343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.420430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.420534] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.420578] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.420668] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.437711] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.437749] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.437788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.437822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.437856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.437886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.437915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.437946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.437980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.438092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.438144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.438195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.438237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.438284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.438503] [drm:intel_power_well_disable [i915]] disabling display
>[  727.438566] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.438628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.438677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.438786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.438805] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.438882] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.438902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.438926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.438953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.438976] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.439000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.439067] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.439100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.439129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.439158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.439185] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.439193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.439220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.439227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.439264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.439288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.439314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.439337] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.439366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.439390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.439415] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.439439] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.439464] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.439494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.439536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.439623] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.439653] [drm:intel_power_well_enable [i915]] enabling display
>[  727.439682] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.439733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.439763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.439790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.439818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.439844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.439874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.439906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.439937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.439967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.439993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.440044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.440077] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.440109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.442175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.442196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.442215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.442234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.443805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.443825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.443843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.445399] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.445419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.447294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.450622] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.450680] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.450719] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.450771] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.467455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.467507] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.467573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.500852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.500938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.501109] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.501162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.501264] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.518286] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.518324] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.518367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.518408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.518451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.518491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.518526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.518562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.518606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.518648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.518693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.518725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.518753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.518779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.518828] [drm:intel_power_well_disable [i915]] disabling display
>[  727.518864] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.518903] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.518931] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.519077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.519102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.519211] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.519242] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.519274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.519309] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.519337] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.519367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.519397] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.519425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.519453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.519479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.519512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.519520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.519555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.519561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.519597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.519633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.519679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.519702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.519726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.519751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.519777] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.519803] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.519829] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.519856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.519884] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.519946] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.519968] [drm:intel_power_well_enable [i915]] enabling display
>[  727.519990] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.520070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.520102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.520132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.520160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.520188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.520217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.520250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.520281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.520313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.520339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.520366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.520398] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.520427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.522492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.522513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.522531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.522550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.524122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.524143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.524160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.525717] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.525738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.527612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.530934] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.530988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.531078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.531135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.547772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.547826] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.547898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.581202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.581290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.581391] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.581434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.581532] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.598657] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.598695] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.598734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.598768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.598802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.598832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.598861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.598892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.598927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.598959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.598995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.599109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.599152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.599196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.599279] [drm:intel_power_well_disable [i915]] disabling display
>[  727.599347] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.599411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.599456] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.599522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.599534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.599588] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.599608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.599634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.599663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.599688] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.599715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.599740] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.599766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.599793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.599819] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.599844] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.599849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.599873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.599878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.599904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.599930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.599955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.599981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.600038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.600071] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.600101] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.600130] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.600158] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.600190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.600223] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.600314] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.600344] [drm:intel_power_well_enable [i915]] enabling display
>[  727.600375] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.600430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.600463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.600494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.600525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.600550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.600575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.600605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.600633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.600661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.600686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.600711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.600738] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.600761] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.602818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.602839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.602858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.602877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.604453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.604473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.604491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.606042] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.606065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.607934] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.611280] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.611369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.611402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.611444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.628147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.628198] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.628264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.661573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.661661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.661761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.661803] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.661902] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.678885] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.678922] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.678961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.678995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.679111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.679157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.679205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.679251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.679304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.679356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.679398] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.679439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.679473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.679509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.679578] [drm:intel_power_well_disable [i915]] disabling display
>[  727.679630] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.679682] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.679722] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.679837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.679861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.679971] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.680048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.680098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.680145] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.680184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.680227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.680267] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.680308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.680354] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.680386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.680415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.680425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.680453] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.680461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.680491] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.680520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.680551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.680582] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.680615] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.680643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.680674] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.680702] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.680731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.680765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.680802] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.680896] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.680927] [drm:intel_power_well_enable [i915]] enabling display
>[  727.680959] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.681044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.681076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.681109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.681139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.681171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.681203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.681241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.681276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.681310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.681339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.681377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.681409] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.681438] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.683499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.683520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.683538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.683557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.685210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.685233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.685256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.686806] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.686828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.688692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.691984] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.692073] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.692105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.692147] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.708862] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.708934] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.709245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.742262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.742349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.742453] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.742497] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.742594] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.759646] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.759683] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.759723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.759763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.759807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.759847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.759882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.759918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.759962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.760078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.760132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.760186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.760230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.760276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.760341] [drm:intel_power_well_disable [i915]] disabling display
>[  727.760379] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.760422] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.760453] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.760529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.760546] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.760622] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.760658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.760692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.760730] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.760763] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.760799] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.760833] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.760867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.760902] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.760936] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.760969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.761006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.761049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.761059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.761102] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.761141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.761178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.761214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.761255] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.761292] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.761321] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.761347] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.761374] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.761406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.761438] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.761521] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.761540] [drm:intel_power_well_enable [i915]] enabling display
>[  727.761559] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.761593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.761613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.761633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.761652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.761671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.761695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.761723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.761751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.761780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.761805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.761831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.761858] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.761883] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.763934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.763956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.763975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.764048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.765605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.765625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.765643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.767204] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.767226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.769117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.772461] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.772535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.772554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.772580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.789331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.789383] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.789449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.822756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.822841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.822926] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.822968] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.823151] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.839864] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.839901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.839941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.839976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.840098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.840148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.840195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.840247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.840303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.840339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.840370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.840403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.840431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.840460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.840514] [drm:intel_power_well_disable [i915]] disabling display
>[  727.840555] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.840598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.840630] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.840717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.840738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.840819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.840851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.840887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.840925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.840956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.840991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.841085] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.841124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.841162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.841198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.841234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.841245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.841279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.841289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.841325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.841360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.841396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.841431] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.841471] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.841505] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.841540] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.841575] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.841610] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.841651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.841693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.841810] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.841851] [drm:intel_power_well_enable [i915]] enabling display
>[  727.841891] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.841959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.842036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.842085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.842118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.842150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.842185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.842219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.842253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.842286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.842315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.842344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.842379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.842413] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.844483] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.844507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.844530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.844554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.846231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.846252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.846270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.847828] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.847848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.849722] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.853075] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.853158] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.853191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.853232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.869937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.869987] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.870156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.903362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.903446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.903585] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.903631] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.903719] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  727.920777] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  727.920814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  727.920853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.920887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.920922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.920952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.920981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.921091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.921150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.921205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.921257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.921307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.921354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.921401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.921468] [drm:intel_power_well_disable [i915]] disabling display
>[  727.921510] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  727.921555] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.921587] [drm:intel_power_well_disable [i915]] disabling always-on
>[  727.921676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  727.921695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  727.921777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  727.921809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  727.921844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  727.921883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  727.921913] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  727.921947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  727.921981] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  727.922032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  727.922061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  727.922089] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  727.922115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  727.922123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.922151] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  727.922159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  727.922186] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  727.922215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  727.922244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  727.922272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  727.922302] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  727.922328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  727.922355] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  727.922383] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  727.922409] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  727.922440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.922471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  727.922561] [drm:intel_power_well_enable [i915]] enabling always-on
>[  727.922592] [drm:intel_power_well_enable [i915]] enabling display
>[  727.922622] [drm:hsw_set_power_well [i915]] Enabling power well
>[  727.922675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  727.922707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  727.922738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  727.922768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  727.922798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  727.922826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  727.922849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  727.922869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  727.922890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.922908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  727.922926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  727.922952] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  727.922981] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  727.925070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  727.925091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  727.925109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.925131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  727.926691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  727.926711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  727.926730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  727.928282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  727.928303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  727.930177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  727.933486] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  727.933560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  727.933595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  727.933641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  727.950340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  727.950392] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  727.950458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  727.983791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  727.983878] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  727.983922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  727.984061] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  728.001077] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  728.001115] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  728.001154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  728.001187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  728.001222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  728.001252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  728.001282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  728.001314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  728.001350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  728.001382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  728.001415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  728.001446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  728.001474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  728.001512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  728.001570] [drm:intel_power_well_disable [i915]] disabling display
>[  728.001617] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  728.001666] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  728.001703] [drm:intel_power_well_disable [i915]] disabling always-on
>[  728.004874] [IGT] kms_flip: exiting, ret=0
>[  728.027875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  728.027911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  728.027947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  728.027984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  728.028046] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  728.028086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  728.028125] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  728.028162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  728.028201] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  728.028238] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  728.028276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  728.028283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  728.028321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  728.028327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  728.028361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  728.028407] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  728.028428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  728.028446] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  728.028466] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  728.028484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  728.028500] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  728.028516] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  728.028532] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  728.028552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  728.028573] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  728.028634] [drm:intel_power_well_enable [i915]] enabling always-on
>[  728.028652] [drm:intel_power_well_enable [i915]] enabling display
>[  728.028668] [drm:hsw_set_power_well [i915]] Enabling power well
>[  728.028701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  728.028718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  728.028735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  728.028751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  728.028766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  728.028784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  728.028803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  728.028821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  728.028839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  728.028860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  728.028883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  728.028907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  728.028929] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  728.031022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  728.031042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  728.031059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  728.031080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  728.032662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  728.032680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  728.032697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  728.034265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  728.034284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  728.036164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  728.039686] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  728.039733] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  728.039751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  728.039778] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  728.039843] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  728.039863] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  728.056538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  728.056586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  728.056655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  728.056894] Console: switching to colour frame buffer device 240x75
>[  728.167172] Console: switching to colour dummy device 80x25
>[  728.167289] [IGT] kms_flip: executing
>[  728.178856] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  728.178908] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  728.181022] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  728.181060] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  728.183174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  728.183186] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  728.185285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  728.185322] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  728.187436] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  728.187448] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  728.187455] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  728.187485] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  728.187527] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  728.188694] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  728.189629] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  728.189651] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  728.189669] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  728.189687] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  728.190704] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  728.190725] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  728.191835] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  728.191838] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  728.191936] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  728.191939] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  728.191944] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  728.191946] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  728.191998] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  728.192003] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  728.192019] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  728.192025] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  728.192033] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.192040] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.192047] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  728.192052] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  728.192058] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  728.192065] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  728.192072] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.192079] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.192084] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  728.192090] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  728.192097] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  728.192104] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  728.192110] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  728.192116] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  728.192122] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  728.192129] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  728.192136] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  728.192142] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  728.192148] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  728.192154] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  728.192161] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  728.192168] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  728.192174] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  728.192180] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  728.192186] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  728.192193] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  728.192199] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  728.192207] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  728.192213] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  728.192283] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  728.192319] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  728.194195] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  728.194230] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  728.196058] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  728.196069] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  728.198061] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  728.198100] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  728.200058] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  728.200069] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  728.200076] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  728.202128] [IGT] kms_flip: starting subtest 2x-plain-flip-interruptible
>[  728.204166] [IGT] kms_flip: exiting, ret=77
>[  728.240209] Console: switching to colour frame buffer device 240x75
>[  728.349640] Console: switching to colour dummy device 80x25
>[  728.349754] [IGT] kms_flip: executing
>[  728.360861] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  728.360907] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  728.363055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  728.363091] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  728.365206] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  728.365217] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  728.367334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  728.367373] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  728.369487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  728.369498] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  728.369505] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  728.369536] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  728.369579] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  728.370700] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  728.371626] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  728.371648] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  728.371666] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  728.371684] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  728.372701] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  728.372725] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  728.373851] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  728.373855] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  728.374014] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  728.374017] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  728.374024] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  728.374026] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  728.374032] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  728.374034] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  728.374044] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  728.374048] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  728.374051] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.374055] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.374058] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  728.374062] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  728.374065] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  728.374068] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  728.374071] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.374075] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.374079] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  728.374082] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  728.374085] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  728.374088] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  728.374091] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  728.374095] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  728.374098] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  728.374102] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  728.374105] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  728.374109] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  728.374112] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  728.374115] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  728.374119] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  728.374122] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  728.374126] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  728.374129] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  728.374132] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  728.374135] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  728.374139] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  728.374142] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  728.374146] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  728.374188] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  728.374215] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  728.376048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  728.376084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  728.378063] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  728.378074] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  728.380053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  728.380093] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  728.382054] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  728.382065] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  728.382072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  728.382497] [IGT] kms_flip: starting subtest 2x-vblank-vs-dpms-suspend
>[  728.385459] [IGT] kms_flip: exiting, ret=77
>[  728.423681] Console: switching to colour frame buffer device 240x75
>[  728.532536] Console: switching to colour dummy device 80x25
>[  728.532655] [IGT] kms_flip: executing
>[  728.543820] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  728.543866] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  728.545420] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  728.545459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  728.547041] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  728.547052] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  728.549041] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  728.549081] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  728.551044] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  728.551055] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  728.551063] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  728.551093] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  728.551134] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  728.552263] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  728.553196] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  728.553218] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  728.553237] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  728.553254] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  728.554274] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  728.554294] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  728.555415] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  728.555418] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  728.555516] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  728.555519] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  728.555524] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  728.555526] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  728.555531] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  728.555533] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  728.555542] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  728.555546] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  728.555549] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.555552] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.555555] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  728.555558] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  728.555561] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  728.555564] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  728.555567] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.555570] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  728.555573] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  728.555576] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  728.555578] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  728.555581] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  728.555584] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  728.555587] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  728.555590] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  728.555593] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  728.555596] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  728.555599] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  728.555602] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  728.555605] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  728.555608] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  728.555611] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  728.555614] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  728.555617] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  728.555620] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  728.555623] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  728.555626] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  728.555628] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  728.555631] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  728.555670] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  728.555693] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  728.557014] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  728.557039] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  728.559068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  728.559079] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  728.561046] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  728.561085] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  728.563046] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  728.563057] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  728.563064] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  728.563466] [IGT] kms_flip: starting subtest nonexisting-fb
>[  728.564406] [drm:drm_mode_addfb2] [FB:58]
>[  728.564449] [drm:drm_mode_addfb2] [FB:79]
>[  728.617718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.617782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  728.623611] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  728.623657] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  728.623728] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  728.640740] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  728.640784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  728.640816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  728.640854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  728.640888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  728.640923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  728.640961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  728.641086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  728.641141] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  728.641200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  728.641254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  728.641305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  728.641355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  728.641384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  728.641413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  728.641469] [drm:intel_power_well_disable [i915]] disabling display
>[  728.641511] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  728.641552] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  728.641587] [drm:intel_power_well_disable [i915]] disabling always-on
>[  728.641680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  728.641823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  728.641895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.641906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  728.642015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  728.642052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  728.642089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  728.642128] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  728.642160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  728.642195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  728.642229] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  728.642263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  728.642296] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  728.642329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  728.642358] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  728.642368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  728.642398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  728.642405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  728.642435] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  728.642465] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  728.642494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  728.642523] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  728.642553] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  728.642582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  728.642612] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  728.642641] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  728.642668] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  728.642701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  728.642735] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  728.646150] [drm:intel_power_well_enable [i915]] enabling always-on
>[  728.646168] [drm:intel_power_well_enable [i915]] enabling display
>[  728.646184] [drm:hsw_set_power_well [i915]] Enabling power well
>[  728.646219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  728.646243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  728.646267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  728.646288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  728.646312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  728.646334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  728.646359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  728.646384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  728.646409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  728.646432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  728.646455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  728.646479] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  728.646503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  728.648569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  728.648592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  728.648611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  728.648630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  728.650201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  728.650221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  728.650239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  728.651792] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  728.651813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  728.653683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  728.657006] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  728.657065] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  728.657097] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  728.657139] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  728.657235] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  728.657286] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  728.673855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  728.673905] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  728.674052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  728.690535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.690902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.690907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.691977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.691987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.692922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.692928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.693980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.693988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.694975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.694981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.695957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.695964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.696913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.696993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.697983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.697990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.698973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.698980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.699927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.699964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.700981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.700989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.701983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.701991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.702980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.702987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.703973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.703979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.704956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.704962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.705966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.705972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.706915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.706920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.707919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.707994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.708001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.708049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.708055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.708102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.708108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.708157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.708162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.708211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.708217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.708268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.708273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.709991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.709998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.710969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.710976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.711972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.711979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.712925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.712953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.713966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.713973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.714974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.714981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.715965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.715999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.716991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.716998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.717971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.717978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.718927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.718966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.719992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.719999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.720973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.720980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.721975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.721981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.722927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.722965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.723967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.723974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.724988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.724995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.725964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.725998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.726972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.726979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.727963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.727970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.728969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.728976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.729974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.729981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.730977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.730984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.731975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.731982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732924] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.732984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.732990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.733918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.733923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.734970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.734977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.735980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.735987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.736975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.736983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.737960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.737967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.738989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.738996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.739974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.739982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.740950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.740957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.741926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.741963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.742979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.742986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.743979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.743987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.744969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.744976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.745975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.745982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.746914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.746920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.747963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.747970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.748947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.748994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.749966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.749974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.750982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.750989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.751916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.751993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.752969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.752977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.753965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.753972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.754965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.754972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.755918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.755923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.756919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.756999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.757983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.757990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.758989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.758996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.759965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.759972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.760926] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.760963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.761917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.761997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.762981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.762988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.763968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.763975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.764957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.764964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.765917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.765996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.766978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.766985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.767963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.767970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.768917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.768996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.769991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.769998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.770969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.770976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.771968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.771975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.772964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.772971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.773981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.773988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.774975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.774982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.775971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.775977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.776964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.776971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.777923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.777957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.778964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.778970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.779924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.779995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.780914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.780920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.781979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.781986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.782981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.782988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.783968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.783975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.784960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.784967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.785913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.785919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.786992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.786998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.787949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.787997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.788973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.788981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.789988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.789995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.790914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.790918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.791948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.791955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.792990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.792997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.793990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.793997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.794923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.794960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.795965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.795972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.796979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.796986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.797971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.797978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.798920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.798966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.799960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.799967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.800971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.800979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.801962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.801968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.802974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.802982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.803977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.803984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.804967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.804975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.805962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.805969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.806958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.806964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.807916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.807996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.808959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.808965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.809922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.809997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.810961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.810968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.811967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.811974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.812975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.812982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.813977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.813985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.814982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.814989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.815980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.815987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.816989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.816997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.817947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.817994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.818921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.818956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.819976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.819984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.820983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.820990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.821915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.821920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.822959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.822966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.823922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.823957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.824988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.824995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.825965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.825972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826922] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.826983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.826991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.827953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.827960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.828964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.828998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.829985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.829992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.830977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.830984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.831989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.831997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.832987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.832994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.833946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.833952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.834959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.834966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.835947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.835993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.836982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.836989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.837963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.837970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.838987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.838995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.839967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.839974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.840973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.840981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.841961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.841968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.842991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.842999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.843966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.843973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.844959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.844966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.845959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.845967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.846975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.846982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.847958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.847966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848918] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.848943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.848995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.849967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.849974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.850965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.850970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.851920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.851999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.852976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.852982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.853920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.853957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.854978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.854986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.855978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.855985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.856984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.856991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.857957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.857964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.858969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.858975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.859984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.859991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.860958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.860965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.861958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.861965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.862921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.862968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.863987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.863995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.864966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.864973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.865987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.865994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.866944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.866950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.867982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.867989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.868966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.868973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.869988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.869996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.870986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.870993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.871965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.871973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.872947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.872997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.873969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.873977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.874943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.874951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.875974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.875981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.876948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.876955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.877982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.877989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.878960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.878966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.879915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.879992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.880991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.880999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.881981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.881989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.882966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.882973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.883943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.883950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.884973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.884980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.885958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.885965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.886944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.886997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.887968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.887975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.888946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.888952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.889975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.889982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.890983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.890989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.891963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.891999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.892971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.892979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.893964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.893971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.894957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.894963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.895912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.895993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.896981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.896988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.897967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.897974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.898958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.898964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.899917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.899953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.900914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.900993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.901986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.901994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.902960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.902967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.903942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.903992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.904971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.904978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.905948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.905955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.906990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.906996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.907988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.907996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.908916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.908998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.909989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.909997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.910965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.910972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.911969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.911977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.912915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.912953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.913952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.913957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.914974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.914982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.915979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.915986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.916915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.916954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.917968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.917975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.918982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.918990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.919966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.919974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.920968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.920976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.921916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.921953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.922951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.922958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.923974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.923981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.924974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.924981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.925913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.925996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.926919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.926997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.927964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.927972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.928960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.928967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.929991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.929998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.930982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.930989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.931969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.931976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.932981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.932987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.933956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.933963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.934975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.934982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.935988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.935995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.936987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.936993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.937974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.937981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.938973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.938980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.939964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.939971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.940968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.940976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.941947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.941998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.942983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.942991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.943955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.943963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.944962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.944998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.945970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.945978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.946972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.946979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.947985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.947992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.948942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.948949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.949961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.949968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.950983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.950990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.951916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.951992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952154] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.952960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.952967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.953978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.953985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.954991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.954999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.955974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.955982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.956969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.956977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957662] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.957991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.957999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.958971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.958979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.959963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.959998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.960914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.960994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.961994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.961999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.962992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.962999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.963953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.963960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.964989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.964996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.965983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.965990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.966954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.966962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.967967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.967975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.968984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.968991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.969916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.969996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.970990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.970997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.971986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.971993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.972978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.972985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973556] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.973966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.973973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.974973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.974980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.975983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.975991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.976981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.976988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.977972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.977979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.978906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.978911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.979970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.979978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.980987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.980994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.981915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.981954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.982963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.982996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.983967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.983974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984170] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.984978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.984985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.985914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.985996] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.986961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.986994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.987915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.987999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.988959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.988966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.989916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.989997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.990992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.990999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.991916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.991957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.992986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.992993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.993984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.993992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994041] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.994972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.994978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.995962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.995968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.996952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.996959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.997989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.997996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.998962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.998968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  728.999987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  728.999994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.000960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.000967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.001984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.001991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.002957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.002963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.003983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.003991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.004958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.004965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.005988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.005995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.006958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.006965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.007979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.007986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.008951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.008958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.009984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.009991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.010957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.010963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.011960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.011967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.012946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.012998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.013952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.013959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.014956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.014962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.015949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.015955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.016954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.016960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.017947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.017955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.018964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.018972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.019976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.019983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.020911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.020993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.021951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.021958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.022966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.022973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.023971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.023978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024904] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.024989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.024997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.025963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.025997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.026952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.026957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.027978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.027986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.028976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.028984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029377] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.029964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.029971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.030914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.030950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.031983] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.031989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.032968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.032976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033267] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.033957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.033964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.034949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.034997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035499] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.035986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.035994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036169] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.036959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.036966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037914] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.037990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.037997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.038959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.038967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.039988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.039995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.040985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.040992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.041956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.041963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.042947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.042993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.043962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.043969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.044992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.044999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.045960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.045967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.046989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.046996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.047959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.047967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.048989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.048996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.049958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.049965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.050992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.050999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.051960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.051967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052589] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.052989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.052995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.053957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.053963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.054966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.054974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.055942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.055950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.056962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.056968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057362] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.057966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.057973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.058967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.058973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.059965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.059973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.060965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.060972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.061964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.061971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.062965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.062972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.063970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.063977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.064979] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.064986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.065974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.065981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.066947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.066954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.067989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.067997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.068955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.068962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.069989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.069996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.070965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.070972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.071954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.071961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072142] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072913] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.072950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.072997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.073969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.073973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.074949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.074956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.075955] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.075963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076066] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.076976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.076983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.077990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.077996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.078948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.078956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.079982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.079989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.080974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.080982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.081970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.081976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082101] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.082949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.082999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.083980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.083986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.084963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.084971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.085981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.085988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.086958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.086994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087138] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087191] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.087961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.087968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.088980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.088987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089061] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089456] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.089984] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.089992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.090954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.090960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091141] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091536] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.091964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.091971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.092978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.092985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093436] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.093963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.093971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.094994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.094999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.095946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.095995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096394] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.096965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.096973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.097957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.097964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098119] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.098949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.098955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.099953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.099960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.100969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.100975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.101986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.101993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102624] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.102964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.102971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.103959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.103967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.104991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.104998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105070] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105848] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.105973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.105980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106750] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.106967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.106974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107706] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.107971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.107978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108293] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.108964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.108971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.109960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.109967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110461] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110713] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.110970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.110977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111085] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111711] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.111982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.111989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.112944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.112994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113233] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113785] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.113963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.113970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.114962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.114970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.115992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.115999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116240] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116477] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116771] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.116980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.116988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117226] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.117977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.117985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118587] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118607] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.118960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.118967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119472] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.119952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.119960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.120986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.120993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121043] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121496] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.121972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.121980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122373] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.122947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.122998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123715] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.123970] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.123977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124024] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124816] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.124946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.124998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125581] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.125959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.125966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126807] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.126960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.126967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127197] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.127950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.127998] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128297] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128425] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128897] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.128956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.128964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129361] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.129982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.129989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130571] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130625] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.130982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.130989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131039] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131225] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131825] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.131960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.131967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132092] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132307] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.132959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.132966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133071] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.133985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.133993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134064] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134383] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.134990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.134996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135247] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135387] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135600] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135716] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135764] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.135944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.135950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.136947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.136995] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137104] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137340] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.137945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.137950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138133] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138474] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138685] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.138950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.138957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139745] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.139971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.139978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140116] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140168] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140839] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140887] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.140967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.140972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141216] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141660] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.141966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.141973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142097] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142404] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142593] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142861] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.142946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.142994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.143968] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.143975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.144986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.144994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145195] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145495] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.145947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.145993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146047] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.146956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.146963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147804] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.147975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.147982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148136] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148338] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148426] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148695] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148829] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.148956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.148963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149564] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149959] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.149966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.149999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150322] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150397] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.150966] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.150973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151264] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151460] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151674] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.151981] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.151987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.152950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.152958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153147] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153249] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153356] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153430] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153458] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153486] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153667] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153755] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.153978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.153983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154115] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154271] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154902] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.154972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.154980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155134] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155319] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155679] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155714] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155808] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.155992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.155998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156281] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156389] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156621] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156673] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156727] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.156989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.156996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157042] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157150] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.157958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.157966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158305] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158544] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158809] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.158960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.158968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159014] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159121] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159285] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159623] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159753] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159800] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.159977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.159984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160379] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160434] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160566] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160834] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.160959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.160993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161207] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161393] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161871] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.161953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.161961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162252] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162519] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162594] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162950] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.162958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.162992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163033] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163086] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163189] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163354] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163613] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.163963] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.163970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164238] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164314] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164670] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164707] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.164944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.164997] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165093] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165182] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165235] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165630] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.165947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.165955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166555] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.166961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.166968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167511] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.167969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.167976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168078] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168130] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168402] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168498] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168735] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168791] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.168951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.168999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.169973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.169980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170032] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170109] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170428] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170553] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170601] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170749] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170801] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170835] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170870] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.170947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.170955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171348] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171617] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171654] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.171976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.171984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172213] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172548] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172796] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172830] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172944] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.172951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.172999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173256] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173844] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.173972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.173979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174210] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174316] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174435] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174505] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174798] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174833] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.174945] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.174953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175742] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.175977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.175985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176036] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176369] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176582] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176783] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176899] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.176982] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.176990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177204] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177381] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177634] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.177952] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.177959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178403] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178431] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178538] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178558] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178585] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178669] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.178986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.178993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179067] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179224] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179514] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179671] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179907] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.179980] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.179987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180035] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180198] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180376] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180595] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180629] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.180942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.180994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181676] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181824] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.181947] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.181953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182221] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182876] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.182961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.182968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183457] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183703] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183890] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.183957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.183964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184278] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184358] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184454] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184675] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.184951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.184959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185485] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185534] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.185946] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.185953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186110] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186258] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186398] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186504] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186741] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.186977] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.186984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187037] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187075] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187113] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187471] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187509] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187682] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187736] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187822] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187900] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.187976] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.187984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188057] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188107] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188160] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188413] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188551] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188657] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188806] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188843] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188894] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.188964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.188971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189019] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189074] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189261] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189612] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189838] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.189973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.189981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190318] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190375] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.190455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.190598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  729.190868] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  729.190898] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  729.191013] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  729.208043] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  729.208087] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  729.208121] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  729.208160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  729.208193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  729.208229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  729.208260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  729.208289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  729.208321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  729.208356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  729.208389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  729.208421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  729.208452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  729.208490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  729.208529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  729.208587] [drm:intel_power_well_disable [i915]] disabling display
>[  729.208634] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  729.208684] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  729.208723] [drm:intel_power_well_disable [i915]] disabling always-on
>[  729.209184] [drm:drm_mode_addfb2] [FB:58]
>[  729.209269] [drm:drm_mode_addfb2] [FB:78]
>[  729.242410] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.242512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.242583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.242649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.242660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  729.242718] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  729.242740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  729.242763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  729.242786] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  729.242805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  729.242825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  729.242845] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  729.242863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  729.242881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  729.242898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  729.242915] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  729.242963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  729.242994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  729.243002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  729.243032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  729.243061] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  729.243089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  729.243118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  729.243149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  729.243179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  729.243206] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  729.243236] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  729.243262] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  729.243296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  729.243334] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  729.246654] [drm:intel_power_well_enable [i915]] enabling always-on
>[  729.246677] [drm:intel_power_well_enable [i915]] enabling display
>[  729.246698] [drm:hsw_set_power_well [i915]] Enabling power well
>[  729.246738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  729.246764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  729.246788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  729.246810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  729.246835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  729.246859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  729.246886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  729.246912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  729.246993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  729.247027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  729.247059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  729.247108] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  729.247146] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  729.249231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  729.249252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  729.249270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  729.249289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  729.250847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  729.250868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  729.250886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  729.252471] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  729.252492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  729.254365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  729.257700] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  729.257798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  729.257829] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  729.257869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  729.274573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  729.274621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  729.274684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  729.291297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.291884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.291997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.292986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.292997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.293940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.293997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.294983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.294990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.295979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.295986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.296981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.296988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.297965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.297973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.298985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.298992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.299956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.299963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.300959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.300994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.301988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.301993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.302986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.302993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.303984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.303991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.304984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.304990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.305983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.305990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.306987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.306993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.307947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.307954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.308965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.308972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.309968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.309975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.310952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.310960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.311972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.311979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.312951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.312957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.313973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.313981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.314949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.314956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.315989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.315996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.316952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.316959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.317946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.317954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.318955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.318962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.319941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.319948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.320954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.320960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.321970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.321977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.322957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.322965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.323977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.323983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.324946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.324953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.325964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.325969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.326971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.326979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.327981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.327988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.328950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.328999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.329984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.329991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.330946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.330995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.331978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.331985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.332947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.332953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.333947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.333999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.334969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.334976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.335985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.335992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.336943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.336994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.337971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.337977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.338973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.338981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.339951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.339958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.340944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.340996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.341958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.341965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.342973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.342980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.343966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.343974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.344957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.344964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.345989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.345996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.346980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.346987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347900] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.347981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.347987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.348990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.348998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.349943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.349950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.350951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.350958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.351970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.351977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.352947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.352994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.353957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.353964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.354968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.354976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.355959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.355967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356898] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.356970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.356978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.357946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.357995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.358979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.358986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.359951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.359999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.360943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.360950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.361962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.361969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.362946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.362953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.363949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.363997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.364940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.364948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.365983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.365990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.366960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.366967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.367948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.367955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.368989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.368995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.369987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.369994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.370948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.370955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.371970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.371978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.372991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.372999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.373949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.373956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.374984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.374989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.375955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.375962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.376986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.376993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.377962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.377969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.378975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.378982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.379979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.379986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.380941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.380994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.381944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.381996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.382953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.382960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.383978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.383985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.384963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.384998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.385963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.385969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.386962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.386969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.387944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.387951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.388953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.388959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.389969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.389976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.390954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.390962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.391950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.391958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.392947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.392999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.393952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.393960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.394982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.394990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.395949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.395957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.396944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.396951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.397949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.397957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.398945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.398997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.399944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.399992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.400980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.400987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.401979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.401987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.402955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.402962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.403982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.403989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.404943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.404950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.405950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.405957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.406955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.406962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.407969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.407976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.408982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.408989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.409991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.409998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.410957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.410965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.411952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.411959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.412957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.412964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.413980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.413988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.414964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.414972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.415978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.415986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.416980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.416987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.417964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.417996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.418962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.418970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.419959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.419966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.420945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.420951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.421991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.421999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.422968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.422975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.423947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.423953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.424982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.424990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.425967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.425974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.426947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.426953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.427991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.427999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.428957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.428964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.429941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.429948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.430959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.430966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.431983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.431991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.432963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.432970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.433979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.433986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.434966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.434974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.435963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.435970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.436949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.436956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.437948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.437997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.438947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.438999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.439981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.439988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.440959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.440966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.441971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.441978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.442944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.442951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.443985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.443992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.444966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.444973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.445967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.445974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.446988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.446995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.447959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.447994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.448958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.448966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.449965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.449972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.450968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.450975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.451989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.451996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.452988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.452993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.453982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.453989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.454982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.454988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.455983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.455990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.456958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.456966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.457946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.457998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.458980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.458988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.459950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.459958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.460990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.460998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461895] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.461977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.461983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.462961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.462967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.463945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.463998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.464981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.464988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.465956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.465964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.466961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.466968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.467979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.467986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.468987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.468994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.469949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.469957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.470958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.470965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.471962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.471969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472896] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.472988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.472995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.473956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.473964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.474972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.474979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.475978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.475985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.476947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.476999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.477974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.477981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.478989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.478997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.479982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.479989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.480981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.480989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.481973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.481980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.482945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.482952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.483989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.483995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484892] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.484975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.484982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.485973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.485979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.486990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.486997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.487964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.487971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.488982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.488989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.489986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.489992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.490990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.490998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.491985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.491992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.492991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.492997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.493942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.493992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.494984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.494992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.495984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.495991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.496984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.496990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.497945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.497953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.498963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.498998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.499976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.499982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.500944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.500994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.501991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.501998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.502979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.502986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.503978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.503985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.504957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.504965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.505945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.505997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.506971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.506978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.507947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.507954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.508979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.508985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.509963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.509970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.510948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.510997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.511981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.511989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.512958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.512966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.513970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.513977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.514988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.514996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.515981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.515988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.516947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.516995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.517988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.517995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.518963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.518970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.519988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.519995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.520948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.520955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.521987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.521995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.522949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.522997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.523967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.523972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.524946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.524954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.525982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.525989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.526946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.526996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.527978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.527985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.528989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.528996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.529958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.529966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.530979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.530987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.531961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.531969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.532987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.532995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.533949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.533999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.534951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.534999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.535947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.535999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.536984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.536992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.537967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.537975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.538991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.538997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.539972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.539979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.540988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.540995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.541984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.541991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.542974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.542981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.543972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.543978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.544989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.544996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.545952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.545959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.546975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.546983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.547984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.547990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.548986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.548994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.549957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.549964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.550977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.550983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.551944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.551994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.552990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.552996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.553980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.553986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.554992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.554999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.555978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.555984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.556981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.556987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557891] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.557975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.557983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.558985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.558992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.559953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.559961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.560983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.560990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.561946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.561994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.562960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.562967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.563970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.563977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.564961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.564968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.565948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.565956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.566983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.566988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.567950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.567997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.568982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.568989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.569987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.569994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.570945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.570952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.571960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.571967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.572989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.572995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573891] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.573978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.573985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.574965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.574973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.575949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.575999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.576986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.576994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.577959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.577966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.578946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.578998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.579945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.579999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.580945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.580953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.581985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.581992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582684] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.582947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.582993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.583969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.583975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.584976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.584983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.585953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.585961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.586977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.586984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.587948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.587998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588205] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.588974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.588981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.589983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.589991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.590985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.590993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.591991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.591998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.592973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.592980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.593950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.593998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.594982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.594988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.595972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.595999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.596961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.596995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.597944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.597993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.598965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.598999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.599963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.599969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600889] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.600979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.600986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.601981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.601988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.602944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.602951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.603969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.603977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.604987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.604993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.605969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.605976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.606962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.606997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607140] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.607990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.607993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.608984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.608992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609195] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.609977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.609985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.610978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.610985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.611962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.611969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.612965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.612973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.613945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.613952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.614953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.614961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.615947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.615998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616239] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.616960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.616993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.617989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.617996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.618988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.618995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.619989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.619994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.620983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.620991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.621976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.621983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622031] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.622980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.622986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.623978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.623984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.624963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.624970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.625984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.625989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.626980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.626986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.627964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.627972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.628971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.628977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.629942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.629950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.630978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.630984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631194] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.631955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.631963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.632946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.632992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.633976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.633983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.634966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.634972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.635948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.635998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.636974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.636981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.637965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.637998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.638975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.638982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.639991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.639998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.640958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.640965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.641946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.641953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.642967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.642975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.643986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.643992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.644955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.644962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.645970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.645977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646888] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.646958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.646967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.647945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.647952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.648968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.648974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649619] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.649986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.649992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.650986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.650992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.651946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.651953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.652960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.652968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.653967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.653974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.654983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.654990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.655964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.655971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.656954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.656962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.657951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.657959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658798] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.658991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.658997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659137] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.659952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.659959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.660990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.660996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.661945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.661953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.662990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.662996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.663950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.663957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664886] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.664970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.664974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665064] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.665991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.665998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.666979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.666986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.667978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.667986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.668980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.668988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.669968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.669975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670624] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.670957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.670964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.671951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.671957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672170] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.672944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.672995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.673949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.673997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674273] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.674984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.674991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675175] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.675962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.675996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.676968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.676974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.677959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.677994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.678956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.678962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.679961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.679968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.680981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.680989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681597] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.681942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.681950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.682966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.682974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683333] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.683989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.683997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684105] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.684987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.684994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685132] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.685963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.685971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.686986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.686992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.687986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.687993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.688943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.688950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.689955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.689961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.690971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.690978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691288] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.691960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.691993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.692953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.692999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.693979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.693986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694320] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694804] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.694989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.694996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695379] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.695977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.695984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.696973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.696980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.697946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.697997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.698969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.698975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.699942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.699949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700609] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.700966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.700973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.701971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.701977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702864] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.702967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.702973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703448] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.703944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.703995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704121] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.704960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.704966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705513] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.705966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.705973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706254] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.706968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.706973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.707962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.707969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708250] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.708949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.708994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.709991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.709996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.710945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.710996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.711952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.711998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.712977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.712983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713213] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.713950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.713956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714002] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714347] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.714984] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.714991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715041] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715323] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.715985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.715992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.716944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.716995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717336] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.717964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.717971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718877] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.718943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.718994] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.719964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.719971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.720989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.720995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.721962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.721968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.722947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.722999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723291] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.723982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.723989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.724980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.724986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725518] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.725992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.725999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726912] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.726964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.726971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727019] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.727975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.727982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728268] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.728986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.728993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729256] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.729971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.729978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730266] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730581] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.730972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.730979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731052] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731158] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731375] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731713] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.731947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.731954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732168] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.732991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.732998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733181] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733286] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733618] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.733955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.733962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.734948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.734998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735535] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.735979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.735986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736765] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.736980] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.736986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737651] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737755] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.737993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.737999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738906] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.738958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.738964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.739959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.739965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740073] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740729] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740879] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.740987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.740993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741296] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.741950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.741957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.742983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.742989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743112] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743165] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743488] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743827] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.743977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.743985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.744947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.744997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745572] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745706] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.745987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.745994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746392] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.746948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.746955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747529] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747677] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.747983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.747989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748330] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748871] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.748972] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.748977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749376] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749527] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.749947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.749954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750408] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750879] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750882] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.750975] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.750982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.751951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.751958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752628] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.752990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.752997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753244] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.753958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.753965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754182] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754404] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754875] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754878] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.754947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.754998] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755346] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755403] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.755990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.755996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756501] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.756951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.756958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757066] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757248] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757300] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.757987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.757994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758093] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758203] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758353] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758425] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758921] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.758977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.758984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759478] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759638] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.759970] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.759975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760050] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760101] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760686] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.760947] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.760954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761222] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761350] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761399] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761622] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761711] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.761989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.761996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762047] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762463] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762484] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762631] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.762982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.762989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763089] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763348] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763589] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763697] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763910] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.763966] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.763972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764469] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764540] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764881] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.764990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.764997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765243] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765298] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765593] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.765963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.765970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766314] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766700] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.766971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.766977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767265] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767437] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767486] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.767982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.767989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768146] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.768950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.768957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769063] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769198] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769301] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769427] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769748] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769866] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769927] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.769969] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.769976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770604] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770771] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770802] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770934] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.770990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.770996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771197] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771788] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771818] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771847] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.771946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.771953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772241] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772295] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772405] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772428] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772817] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.772973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.772980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773326] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773378] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773457] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773548] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773570] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773769] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.773986] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.773992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774412] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774950] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.774991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.774997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775150] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775355] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775458] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775738] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775820] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.775987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.775993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776042] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776497] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776519] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776740] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.776967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.776973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777099] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777316] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777411] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777645] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777782] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777843] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.777963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.777969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778559] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778695] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778800] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.778965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.778973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779079] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779211] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779372] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779664] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779853] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779903] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.779985] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.779992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780038] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780352] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780391] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780596] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780922] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.780979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.780985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781583] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781774] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781833] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781920] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.781979] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.781985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782496] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782526] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782586] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782661] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782689] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782718] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.782954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.782960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783117] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783307] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783566] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783594] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783682] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783764] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783938] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.783945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.783996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784094] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784237] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784517] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.784992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.784998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785206] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785390] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785477] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785590] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785612] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785835] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785863] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.785974] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.785980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786608] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786637] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786799] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.786971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.786978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787263] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787374] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787493] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787634] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787742] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787877] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787880] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.787957] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.787964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788233] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788362] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788430] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788543] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788592] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788741] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.788988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.788994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789087] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789283] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789461] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789482] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789510] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789629] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789849] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789880] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.789978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.789984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790029] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790138] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790247] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790381] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790502] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790532] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790585] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790635] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790752] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790805] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790826] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790883] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.790955] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.790960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.791010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.791016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.791067] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.791072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.791123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.791128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.791163] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.791168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.791201] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.791206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.791346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  729.791422] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  729.791451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  729.791515] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  729.810346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  729.810370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  729.810398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  729.810420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  729.810444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  729.810464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  729.810483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  729.810504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  729.810527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  729.810549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  729.810569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  729.810590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  729.810609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  729.810627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  729.810666] [drm:intel_power_well_disable [i915]] disabling display
>[  729.810694] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  729.810723] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  729.810743] [drm:intel_power_well_disable [i915]] disabling always-on
>[  729.811003] [drm:drm_mode_addfb2] [FB:58]
>[  729.811056] [drm:drm_mode_addfb2] [FB:78]
>[  729.846439] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  729.846546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  729.846621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.846691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.846703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  729.846760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  729.846783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  729.846806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  729.846830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  729.846848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  729.846869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  729.846889] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  729.846962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  729.846993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  729.847022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  729.847049] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  729.847057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  729.847084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  729.847091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  729.847119] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  729.847145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  729.847172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  729.847199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  729.847229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  729.847257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  729.847285] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  729.847311] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  729.847338] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  729.847373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  729.847408] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  729.850802] [drm:intel_power_well_enable [i915]] enabling always-on
>[  729.850823] [drm:intel_power_well_enable [i915]] enabling display
>[  729.850842] [drm:hsw_set_power_well [i915]] Enabling power well
>[  729.850879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  729.850967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  729.850997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  729.851029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  729.851057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  729.851089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  729.851124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  729.851156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  729.851188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  729.851214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  729.851242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  729.851277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  729.851306] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  729.853396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  729.853416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  729.853434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  729.853453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  729.855023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  729.855042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  729.855060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  729.856615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  729.856636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  729.858500] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  729.861802] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  729.861883] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  729.861973] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  729.862020] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  729.878658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  729.878711] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  729.878784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  729.895368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.895875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.895939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.896991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.896996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.897978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.897986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.898943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.898997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.899966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.899972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.900972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.900979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.901969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.901977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.902968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.902975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.903955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.903963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.904950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.904998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.905989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.905996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.906962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.906996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.907963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.907970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.908960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.908968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.909970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.909977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.910975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.910981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.911983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.911986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.912980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.912987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.913962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.913969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.914966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.914974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.915949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.915956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.916975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.916982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.917951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.917958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.918986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.918991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.919960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.919967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.920978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.920986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.921976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.921983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.922964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.922971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.923953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.923960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.924952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.924958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.925989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.925995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.926982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.926988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.927981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.927988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.928950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.928998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.929957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.929964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.930986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.930992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.931944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.931998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.932960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.932966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.933962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.933969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934876] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.934984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.934991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.935989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.935995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.936981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.936989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.937970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.937977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.938974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.938982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.939957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.939963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.940979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.940986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.941955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.941962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.942944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.942951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.943991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.943998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.944967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.944974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.945979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.945987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.946969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.946977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.947978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.947984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.948943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.948997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.949970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.949978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.950970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.950977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.951993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.951999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.952989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.952995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.953987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.953995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.954967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.954974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.955949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.955958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.956953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.956961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.957966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.957973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.958969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.958977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.959958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.959993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.960947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.960954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.961959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.961966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.962965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.962972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963872] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.963991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.963998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.964986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.964993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.965985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.965992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.966956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.966964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.967974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.967981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.968982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.968989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.969977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.969984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.970991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.970997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.971947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.971996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.972962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.972969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.973965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.973973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974873] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.974946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.974953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.975988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.975994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.976956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.976964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.977963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.977970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978875] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.978961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.978967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.979966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.979972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.980986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.980992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.981958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.981965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982875] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.982957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.982963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.983987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.983994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.984994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.984999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.985953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.985960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.986966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.986974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.987984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.987990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.988982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.988988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.989986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.989992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.990977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.990985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.991974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.991981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.992969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.992976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.993957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.993964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.994947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.994999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.995952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.995959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.996985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.996992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.997983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.997990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.998990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.998996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  729.999940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  729.999947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.000962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.000970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.001977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.001985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.002959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.002966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003874] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.003942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.003950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004874] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.004968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.004974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.005988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.005994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.006941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.006949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.007965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.007973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.008984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.008990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.009993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.009999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.010952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.010959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.011956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.011963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.012953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.012959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.013976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.013983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.014985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.014992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.015986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.015992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.016987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.016993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.017963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.017971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.018991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.018998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.019977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.019983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.020978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.020986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.021964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.021971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.022951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.022959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.023979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.023985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.024985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.024992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.025949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.025957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.026976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.026982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.027965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.027971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.028950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.028957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.029963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.029969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030098] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.030980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.030987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.031986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.031991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.032958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.032966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.033949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.033957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.034968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.034975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.035975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.035982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.036967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.036972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.037975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.037981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.038948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.038997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.039947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.039999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.040971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.040977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.041956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.041963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.042993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.042999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.043982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.043989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.044941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.044949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.045949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.045956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.046970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.046976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.047956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.047962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.048955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.048962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.049945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.049998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.050974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.050979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051870] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.051950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.051957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.052971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.052977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053767] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.053973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.053980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.054944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.054997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.055948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.055996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.056944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.056996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.057962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.057970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.058968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.058975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.059945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.059998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.060990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.060998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.061991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.061996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.062963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.062970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.063981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.063986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.064944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.064998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065242] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.065967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.065974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066871] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.066945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.066994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.067984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.067991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068865] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.068973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.068979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.069949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.069955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.070974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.070980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071536] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.071992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.071999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.072965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.072970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.073964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.073971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.074958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.074965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.075946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.075953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.076945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.076998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.077979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.077985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.078969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.078976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.079977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.079984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.080990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.080996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.081993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.081999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.082960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.082996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.083993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.083998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.084992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.084997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085755] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.085962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.085969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.086957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.086964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.087992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.087999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.088983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.088989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.089989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.089995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.090952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.090960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.091949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.091957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.092988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.092995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.093975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.093983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.094948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.094955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.095975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.095982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.096952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.096959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.097956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.097964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.098969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.098975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.099972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.099980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.100943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.100992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.101948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.101956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.102964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.102971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.103979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.103985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.104982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.104988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.105956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.105962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.106989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.106996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.107962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.107970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.108962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.108969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.109993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.109998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.110966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.110971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.111974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.111980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.112993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.112999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.113949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.113957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.114955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.114962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.115958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.115965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.116976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.116982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.117974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.117980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.118966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.118974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.119966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.119973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120369] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.120949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.120997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.121989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.121994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.122958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.122966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.123994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.123999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.124979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.124986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.125989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.125994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.126943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.126996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127867] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.127951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.127958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.128973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.128981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.129971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.129977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.130988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.130993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.131950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.131957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.132956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.132963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.133973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.133980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.134947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.134998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.135993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.135998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.136969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.136976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.137983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.137989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138869] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.138991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.138996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139937] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.139987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.139992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140868] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.140978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.140984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.141976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.141981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.142984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.142990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.143990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.143996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.144990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.144995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.145985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.145992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.146981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.146988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.147962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.147997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.148990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.148996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.149969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.149976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150216] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.150945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.150993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.151982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.151989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152689] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.152952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.152958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.153974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.153981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.154960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.154967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.155982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.155989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.156941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.156949] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.157949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.157955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158177] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.158950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.158957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.159946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.159954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160868] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.160943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.160950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.161964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.161999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.162967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.162974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.163984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.163990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164866] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.164987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.164993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.165984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.165989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.166988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.166995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.167983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.167988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.168959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.168967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.169984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.169989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.170960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.170967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.171987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.171992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172593] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172864] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.172951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.172958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.173985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.173991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.174969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.174976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.175988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.175993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.176984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.176991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.177948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.177956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.178948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.178995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.179992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.179997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.180979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.180986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181482] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181905] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.181954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.181960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.182960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.182968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.183983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.183989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.184978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.184984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185228] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.185968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.185974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.186943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.186951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.187945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.187997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188646] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.188970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.188977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.189952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.189959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.190959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.190966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.191973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.191980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.192977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.192982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.193969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.193975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194842] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.194969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.194975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.195953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.195961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.196988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.196993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.197984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.197990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198342] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198642] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.198959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.198967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.199991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.199996] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.200945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.200952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.201957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.201964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202130] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.202959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.202966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203830] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.203974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.203981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204649] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.204973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.204978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.205992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.205998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.206952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.206959] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.207985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.207991] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.208975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.208979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.209971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.209978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.210970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.210976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.211992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.211997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.212948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.212997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.213958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.213966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.214953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.214958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215361] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.215950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.215957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.216988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.216994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217247] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.217965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.217972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218172] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.218985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.218993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219401] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219648] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219865] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.219957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.219965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.220995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.220998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221537] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.221960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.221966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222671] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.222986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.222992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223811] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.223946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.223953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224050] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.224974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.224979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.225988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.225993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.226962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.226997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227618] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227888] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.227946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.227994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.228974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.228982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229312] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.229974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.229980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.230951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.230998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.231989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.231994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232641] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232863] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.232989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.232994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233703] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.233960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.233967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.234972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.234979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235076] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235327] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.235978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.235984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.236970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.236977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237279] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.237978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.237984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.238988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.238994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239399] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239615] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.239943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.239950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240864] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.240945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.240951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241046] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.241978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.241983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242337] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.242949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.242955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243800] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.243974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.243981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244344] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244774] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.244985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.244990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.245987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.245993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246150] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246342] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246400] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.246974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.246981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.247966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.247972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.248979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.248984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249438] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249492] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249713] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.249952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.249960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250071] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250184] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.250942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.250950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251596] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251700] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.251980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.251987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.252968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.252974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253129] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253528] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.253973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.253980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254965] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.254992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.254995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255103] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255426] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.255971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.255978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256137] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256142] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256386] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.256970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.256975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257131] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.257960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.257968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.258959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.258966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259077] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259421] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259427] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.259967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.259974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.260982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.260988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261043] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261155] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261928] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.261980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.261986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262913] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.262949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.262956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.263969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.263975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264536] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.264966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.264971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265082] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265178] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265809] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.265987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.265993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266032] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.266946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.266954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267173] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267417] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.267971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.267978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268440] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268912] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.268967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.268974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269029] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269691] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269736] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.269965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.269970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270931] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270938] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.270973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.270980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271348] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271546] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.271969] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.271974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272321] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272346] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272398] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272519] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.272961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.272966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273471] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273786] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.273950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.273956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274898] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.274952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.274958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275887] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275931] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.275978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.275984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276299] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276338] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276497] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.276971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.276978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277036] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277166] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277171] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277435] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277784] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277924] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.277960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.277967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278517] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.278948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.278997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279209] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279749] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.279987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.279992] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280031] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280283] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280684] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280907] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.280956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.280963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281182] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281318] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.281944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.281951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282009] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282289] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282317] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282590] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.282977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.282984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283448] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283561] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283691] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283862] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.283944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.283951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284240] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284309] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284579] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.284946] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.284995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285223] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285886] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285942] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.285994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.285999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286354] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286496] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.286994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.286999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287457] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287883] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.287990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.287995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288051] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288237] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.288960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.288995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289770] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289791] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289813] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.289947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.289954] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290360] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290529] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.290990] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.290995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291086] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291298] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291763] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291847] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291932] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.291981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.291989] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292290] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292343] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292508] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292565] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292695] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292856] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.292987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.292995] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293126] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293751] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293817] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.293971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.293978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294083] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294088] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.294955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.294961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295203] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295293] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295314] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295698] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.295978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.295986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296045] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296079] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296123] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.296951] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.296958] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297286] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297364] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297850] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.297984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.297990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298047] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298282] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298510] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298544] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298640] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298694] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298748] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.298991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.298997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299030] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299087] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299584] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299589] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.299945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.299952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300525] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.300949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.300956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301139] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301633] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.301944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.301952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302232] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.302943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.302950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303008] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303060] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303065] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303105] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303144] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303248] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303595] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303693] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.303948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.303995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304466] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304845] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.304965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.304972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305014] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305420] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305826] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305884] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305940] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.305989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.305994] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306048] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306160] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306252] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306257] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306297] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306611] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306643] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306909] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306915] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.306968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.306975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307073] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307382] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.307960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.307968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308239] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308478] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308700] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.308955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.308962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309069] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309074] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309262] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309425] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.309963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.309969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310207] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.310948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.310997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311641] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311826] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311829] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311857] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311860] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.311958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.311964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312476] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.312946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.312952] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313121] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313359] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313414] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313606] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313663] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313712] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313812] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.313993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.313998] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314308] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314919] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.314968] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.314974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315135] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315140] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315197] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315236] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315544] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315723] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315728] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.315964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.315970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316062] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316067] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316106] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316211] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316506] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.316948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.316995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317276] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317568] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.317977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.317983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318503] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.318978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.318985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319248] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319322] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319351] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319540] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319658] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319710] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.319967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.319974] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320461] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320566] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.320947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.320995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321456] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321634] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321754] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.321992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.321997] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322129] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322134] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322232] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322291] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322347] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322403] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322460] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322539] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322861] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322935] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.322970] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.322976] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323193] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323345] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.323963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.323971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324027] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324175] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324180] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324271] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324587] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324785] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324790] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.324979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.324985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325430] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325576] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325729] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325777] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325854] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.325985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.325990] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326044] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326292] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326391] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326397] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326445] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326450] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326659] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326697] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326807] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.326945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.326996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327332] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327365] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327493] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327520] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327584] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327654] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.327953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.327960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328016] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328185] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328224] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328309] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328417] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328422] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328599] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328720] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.328956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.328963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329100] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329260] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329315] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329371] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329559] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.329978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.329984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330038] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330198] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330711] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330838] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330843] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.330977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.330983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331135] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331445] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331509] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331545] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331629] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331831] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.331957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.331964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332372] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332515] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332906] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.332955] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.332963] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333018] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333072] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333128] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333317] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333370] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333475] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333480] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333621] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333753] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333802] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.333988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.333993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334127] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334156] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334287] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334344] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334404] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334477] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334533] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334562] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334622] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334696] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334902] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.334980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.334987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335396] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335801] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335853] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.335977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.335982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336151] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336190] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336229] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336280] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336442] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336684] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336783] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.336976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.336983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337160] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337514] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337901] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.337950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.337957] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338470] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338673] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.338943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.338995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339000] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339240] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339294] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339349] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339541] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339592] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339640] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339645] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339944] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.339979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.339985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340145] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340256] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340452] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340601] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340653] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340743] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340903] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340910] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.340960] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.340967] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341374] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341620] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341724] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341838] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.341975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.341981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342163] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342217] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342395] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342560] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342665] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.342971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.342977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343080] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343085] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343376] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343381] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343548] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343692] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343793] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343913] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.343974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.343981] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344035] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344040] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344080] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344170] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344676] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344788] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.344964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.344972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345132] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345339] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345378] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345437] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345486] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345535] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345585] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345726] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345762] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345859] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.345947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.345998] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346351] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346467] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346564] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346912] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.346967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.346975] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347054] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347161] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347269] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347387] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347423] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347605] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347761] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347833] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347916] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.347966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.347973] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348023] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348028] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348083] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348196] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348235] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348326] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348379] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348577] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348676] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348731] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348837] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348890] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.348947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.348997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349003] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349052] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349116] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349173] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349251] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349573] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349578] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349612] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349617] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349656] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349814] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.349948] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.349955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350008] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350013] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350052] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350086] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350091] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350195] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350694] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350699] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350750] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350803] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.350956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.350962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351119] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351124] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351176] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351181] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351233] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351238] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351421] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351475] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351643] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351721] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351773] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351778] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351827] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.351963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.351969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352026] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352078] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352084] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352117] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352162] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352370] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352614] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352664] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352709] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352714] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352764] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352844] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.352949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.352956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353064] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353119] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353233] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353415] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353469] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353638] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353888] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353894] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.353946] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.353953] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354011] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354068] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354249] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354254] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354303] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354361] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354408] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354425] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354428] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354503] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354505] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354532] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354626] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354731] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354759] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354787] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354806] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354822] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354848] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354927] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.354977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.354984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355089] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355094] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355146] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355191] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355224] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355230] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355334] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355388] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355558] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355597] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355688] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355741] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355794] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355925] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.355978] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.355983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356166] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356220] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356468] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.356948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.356997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357163] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357356] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357409] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357574] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357632] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.357949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.357955] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358108] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358199] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358307] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358418] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358484] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358556] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358652] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358702] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358804] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358930] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.358966] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.358972] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359020] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359025] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359188] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359244] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359301] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359380] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359650] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359746] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359840] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359916] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.359972] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.359978] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360090] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360187] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360221] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360226] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360326] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360331] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360496] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360501] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360591] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360675] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360723] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360768] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360773] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360909] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.360964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.360970] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361010] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361044] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361049] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361101] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361149] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361154] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361203] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361208] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361319] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361411] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361416] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361450] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361455] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361507] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361613] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.361950] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.361999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362004] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362114] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362169] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362266] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362305] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362410] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362479] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362506] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362534] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362573] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362598] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362624] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362733] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362752] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362794] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362823] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362923] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.362975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.362983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363122] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363227] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363281] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363392] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363444] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363449] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363527] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363633] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363687] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363917] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.363953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.363960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364012] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364066] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364120] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364231] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364472] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364526] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364637] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364908] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.364958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.364966] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365079] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365136] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365176] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365210] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365215] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365262] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365267] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365429] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365618] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365765] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365816] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365894] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365900] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365954] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.365961] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.365996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366002] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366041] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366195] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366200] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366363] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366368] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366551] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366604] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366716] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366774] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366779] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366810] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366815] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366851] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366927] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366934] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.366983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.366988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367097] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367210] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367244] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367249] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367288] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367448] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367453] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367550] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367555] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367608] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367639] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367644] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367679] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367727] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367771] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367776] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367820] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.367964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.367971] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368030] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368069] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368107] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368159] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368212] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368260] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368265] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368320] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368376] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368428] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368433] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368512] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368563] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368611] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368616] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368822] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368849] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368907] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368914] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.368961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.368969] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369078] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369128] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369133] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369285] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369325] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369431] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369481] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369636] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369672] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369805] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.369974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.369979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370022] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370147] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370152] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370205] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370258] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370363] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370382] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370434] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370491] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370520] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370550] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370581] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370602] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370738] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370768] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370799] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370841] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370903] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.370953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.370960] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371009] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371015] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371064] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371070] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371120] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371125] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371183] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371366] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371419] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371474] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371530] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371588] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371824] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.371957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.371962] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372019] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372157] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372301] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372306] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372447] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372483] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372531] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372580] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372681] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372821] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372857] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372945] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.372994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.372999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373048] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373053] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373109] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373352] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373405] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373453] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373458] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373666] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373705] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373757] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373885] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.373943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.373995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374058] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374098] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374132] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374137] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374189] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374241] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374295] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374504] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374543] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374594] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374647] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374701] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374766] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374904] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.374982] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.374987] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375034] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375092] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375146] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375253] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375259] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375316] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375394] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375454] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375552] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375655] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375744] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375911] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.375963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.375968] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376024] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376081] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376139] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376179] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376270] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376323] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376377] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376426] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376432] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376489] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376541] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376586] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376677] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376739] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376788] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376839] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376926] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.376979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.376984] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377023] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377168] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377217] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377222] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377328] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377473] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377521] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377670] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377722] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377775] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377846] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.377977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.377983] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378032] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378037] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378148] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378245] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378284] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378336] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378389] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378498] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378612] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378651] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378795] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378853] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378858] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.378941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.378948] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379063] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379102] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379136] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379141] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379196] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379201] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379250] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379402] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379451] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379456] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379492] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379523] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379528] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379575] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379625] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379674] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379720] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379725] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379777] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379899] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379934] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379941] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.379988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.379993] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380046] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380104] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380158] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380194] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380246] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380268] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380324] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380353] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380410] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380443] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380485] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380513] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380539] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380542] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380571] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380600] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380630] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380658] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380661] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380680] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380682] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380704] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380732] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380760] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380789] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380819] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380849] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380957] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.380964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.380999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381107] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381221] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381278] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381335] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381369] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381375] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381408] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381413] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381627] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381683] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381740] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.381945] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.381951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382001] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382007] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382062] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382118] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382170] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382175] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382214] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382253] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382299] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382304] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382357] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382466] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382517] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382522] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382579] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382613] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382709] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382769] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382818] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382911] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382918] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.382971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.382977] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383035] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383075] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383115] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383161] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383273] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383451] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383482] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383487] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383518] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383523] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383570] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383619] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383669] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383719] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383771] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383825] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383893] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383929] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383936] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.383983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.383988] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384095] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384150] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384201] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384206] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384263] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384302] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384336] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384341] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384388] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384393] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384441] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384446] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384494] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384500] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384667] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384706] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384745] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384797] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384855] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384943] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.384993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.384999] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385056] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385108] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385113] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385148] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385153] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385192] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385238] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385243] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385296] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385355] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385407] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385454] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385459] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385511] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385542] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385547] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385583] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385626] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385631] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385680] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385724] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385730] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385780] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385832] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.385964] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.385999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386005] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386104] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386110] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386275] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386333] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386373] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386412] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386465] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386513] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386572] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386628] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386679] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386685] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386742] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386781] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386820] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386887] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386895] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.386944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.386951] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387006] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387061] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387117] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387169] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387174] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387213] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387252] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387313] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387362] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387411] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387462] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387514] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387562] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387567] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387835] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387920] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.387973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.387980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388014] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388020] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388059] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388164] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388212] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388218] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388267] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388272] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388328] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388380] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388385] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388464] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388516] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388569] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388623] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388678] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388734] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388792] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388830] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388892] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.388947] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.388996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389001] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389050] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389055] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389111] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389167] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389264] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389358] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389406] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389436] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389488] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389490] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389518] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389538] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389554] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389557] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389582] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389606] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389635] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389662] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389687] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389690] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389715] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389718] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389737] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389782] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389808] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389834] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389897] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.389950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.389956] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390017] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390057] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390096] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390149] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390202] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390305] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390310] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390362] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390367] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390419] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390424] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390463] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390502] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390607] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390655] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390715] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390772] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390828] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390889] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390933] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.390980] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.390986] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391039] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391093] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391204] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391261] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391300] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391340] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391391] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391444] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391493] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391499] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391549] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391554] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391610] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391668] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391708] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391747] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391798] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391852] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391921] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391929] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.391979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.391985] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392042] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392099] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392138] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392171] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392234] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392282] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392327] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392332] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392384] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392435] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392488] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392519] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392524] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392560] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392609] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392657] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392707] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392758] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392810] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392896] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392939] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.392974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.392980] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393027] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393034] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393143] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393198] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393255] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393311] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393350] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393390] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393441] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393494] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393543] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393549] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393603] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393654] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393660] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393717] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393751] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393756] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393796] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393848] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393922] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.393973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.393979] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394033] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394084] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394089] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394147] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394181] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394186] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394225] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394271] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394277] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394329] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394383] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394439] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394495] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394553] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394593] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394639] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394681] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394686] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394735] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394785] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394836] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394921] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.394976] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.394982] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.395021] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395055] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.395060] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395106] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.395112] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.395165] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.395219] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.395274] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.395330] [drm:drm_mode_setcrtc] Unknown FB ID-16
>[  730.395483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.395556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  730.395584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  730.395646] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  730.414735] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  730.414773] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  730.414814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.414848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.414884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.415011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.415062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.415116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.415170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.415223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.415274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.415324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.415370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.415415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.415504] [drm:intel_power_well_disable [i915]] disabling display
>[  730.415569] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  730.415633] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  730.415684] [drm:intel_power_well_disable [i915]] disabling always-on
>[  730.419288] [IGT] kms_flip: exiting, ret=0
>[  730.441694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.441733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.441770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.441810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.441842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.441877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.441954] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.441987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.442019] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.442049] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.442083] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.442091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.442129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.442135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.442175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.442215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.442255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.442294] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.442334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.442373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.442413] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  730.442452] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.442492] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.442534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.442587] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.442653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  730.442674] [drm:intel_power_well_enable [i915]] enabling display
>[  730.442694] [drm:hsw_set_power_well [i915]] Enabling power well
>[  730.442732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.442756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.442780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.442804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.442828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.442851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.442918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.442941] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.442960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.442976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.442993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.443014] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  730.443032] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  730.445100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  730.445122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  730.445144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.445167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  730.446729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  730.446749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  730.446768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.448312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  730.448330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  730.450220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  730.453719] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  730.453803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  730.453825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  730.453858] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  730.453939] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  730.453959] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  730.470602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.470649] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.470719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.470999] Console: switching to colour frame buffer device 240x75
>[  730.596030] Console: switching to colour dummy device 80x25
>[  730.596146] [IGT] kms_flip: executing
>[  730.607759] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  730.607813] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  730.609949] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  730.609984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  730.612100] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  730.612112] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  730.614231] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  730.614270] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  730.616385] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  730.616396] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  730.616404] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  730.616436] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  730.616480] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  730.617589] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  730.618524] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  730.618553] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  730.618586] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  730.618606] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  730.619633] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  730.619653] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  730.620762] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  730.620766] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  730.620946] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  730.620949] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  730.620954] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  730.620957] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  730.620962] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  730.620965] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  730.620974] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  730.620978] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.620981] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  730.620985] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  730.620988] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  730.620991] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  730.620994] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  730.620997] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  730.621001] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  730.621004] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  730.621007] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  730.621010] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  730.621013] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  730.621016] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  730.621020] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  730.621023] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  730.621026] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  730.621030] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  730.621033] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  730.621036] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  730.621039] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  730.621042] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  730.621046] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  730.621049] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  730.621052] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  730.621056] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  730.621059] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  730.621062] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  730.621065] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  730.621068] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  730.621072] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  730.621112] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  730.621137] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  730.622907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  730.622934] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  730.624966] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  730.624977] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  730.626958] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  730.626997] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  730.628963] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  730.628974] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  730.628981] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  730.631042] [IGT] kms_flip: starting subtest dpms-vs-vblank-race-interruptible
>[  730.631562] [drm:drm_mode_addfb2] [FB:77]
>[  730.631590] [drm:drm_mode_addfb2] [FB:79]
>[  730.685301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  730.685364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.687430] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  730.687480] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  730.687555] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  730.705686] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  730.705731] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  730.705764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  730.705803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.705835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.705870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.705962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.706007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.706052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.706111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.706159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.706212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.706272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.706308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.706345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.706410] [drm:intel_power_well_disable [i915]] disabling display
>[  730.706453] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  730.706488] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.706516] [drm:intel_power_well_disable [i915]] disabling always-on
>[  730.706598] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  730.706748] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  730.706846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  730.706905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  730.707011] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.707054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.707098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.707138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.707164] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.707192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.707224] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.707256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.707294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.707315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.707335] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.707340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.707358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.707362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.707381] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.707399] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.707418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.707435] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.707458] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.707476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.707495] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  730.707513] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.707531] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.707552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.707576] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.710867] [drm:intel_power_well_enable [i915]] enabling always-on
>[  730.710914] [drm:intel_power_well_enable [i915]] enabling display
>[  730.710933] [drm:hsw_set_power_well [i915]] Enabling power well
>[  730.710977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.710998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.711016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.711039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.711061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.711085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.711110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.711135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.711160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.711183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.711206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.711231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  730.711254] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  730.713321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  730.713344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  730.713362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.713382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  730.714978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  730.714999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  730.715017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.716565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  730.716586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  730.718463] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  730.721736] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  730.721780] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  730.721799] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  730.721825] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  730.721931] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  730.721965] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  730.738575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.738625] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.738689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.755551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.755589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.755626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.755665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.755695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.755729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.755763] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.755795] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.755825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.755853] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.755959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.755974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.756018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.756032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.756078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.756122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.756169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.756213] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.756265] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.756307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.756353] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  730.756379] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.756407] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.756438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.756471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.771921] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  730.771970] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  730.772067] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  730.789079] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  730.789123] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  730.789156] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  730.789194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.789227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.789257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.789287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.789316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.789347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.789381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.789412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.789443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.789471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.789498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.789551] [drm:intel_power_well_disable [i915]] disabling display
>[  730.789591] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  730.789621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.789654] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.789688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.789717] [drm:intel_power_well_disable [i915]] disabling always-on
>[  730.790303] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.790334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.790368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.790404] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.790432] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.790463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.790493] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.790523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.790551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.790580] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.790606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.790614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.790641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.790647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.790676] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.790703] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.790730] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.790756] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.790787] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.790813] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.790844] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  730.790894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.790924] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.790956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.790990] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.791315] [drm:intel_power_well_enable [i915]] enabling always-on
>[  730.791344] [drm:intel_power_well_enable [i915]] enabling display
>[  730.791372] [drm:hsw_set_power_well [i915]] Enabling power well
>[  730.791419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.791449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.791474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.791501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.791526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.791553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.791585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.791614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.791643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.791667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.791693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.791725] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  730.791751] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  730.793822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  730.793843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  730.793919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.793952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  730.795521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  730.795541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  730.795564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.797128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  730.797150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  730.799022] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  730.802306] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  730.802339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  730.802358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  730.802384] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  730.802444] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  730.802473] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  730.802547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.802584] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.802623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.852596] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.852637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.852677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.852719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.852752] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.852788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.852824] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.852858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.852971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.853019] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.853067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.853083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.853130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.853142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.853191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.853238] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.853286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.853614] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.853645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.853675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.853705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  730.853733] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.853760] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.853789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.853820] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.869161] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  730.869211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  730.869298] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  730.886318] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  730.886361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  730.886393] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  730.886433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.886472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.886512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.886548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.886587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.886625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.886668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.886710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.886751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.886790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.886828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.886953] [drm:intel_power_well_disable [i915]] disabling display
>[  730.887026] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  730.887092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.887131] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.887170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.887406] [drm:intel_power_well_disable [i915]] disabling always-on
>[  730.887776] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.887798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.887819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.887852] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.887917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.887951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.887985] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.888018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.888225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.888244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.888262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.888266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.888283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.888287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.888304] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.888321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.888337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.888353] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.888373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.888389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.888407] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  730.888423] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.888438] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.888458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.888479] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.888533] [drm:intel_power_well_enable [i915]] enabling always-on
>[  730.888550] [drm:intel_power_well_enable [i915]] enabling display
>[  730.888567] [drm:hsw_set_power_well [i915]] Enabling power well
>[  730.888601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.888625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.888660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.888685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.888718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.888738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.888759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.888778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.888796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.888812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.888828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.888860] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  730.888929] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  730.890997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  730.891018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  730.891037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.891056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  730.892616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  730.892638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  730.892657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.894209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  730.894230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  730.896094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  730.899377] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  730.899409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  730.899428] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  730.899454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  730.899512] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  730.899542] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  730.899616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.899654] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.899692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.949686] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.949729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.949772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.949819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.949860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.949984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.950046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.950097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.950148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.950197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.950245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.950554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.950590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.950594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.950613] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.950631] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.950649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.950665] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.950685] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.950702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.950720] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  730.950736] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.950752] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.950772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.950793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.966234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  730.966282] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  730.966369] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  730.983387] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  730.983431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  730.983464] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  730.983503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.983536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.983567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.983598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.983636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.983675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.983718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.983760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.983802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.983841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.983956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.984043] [drm:intel_power_well_disable [i915]] disabling display
>[  730.984110] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  730.984343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.984380] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.984418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.984449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  730.984841] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  730.984910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  730.984948] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  730.984987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  730.985114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  730.985135] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  730.985156] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  730.985175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  730.985193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  730.985210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  730.985226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  730.985231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.985247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  730.985251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  730.985268] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  730.985284] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  730.985306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  730.985330] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  730.985354] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  730.985376] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  730.985401] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  730.985424] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  730.985448] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  730.985472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  730.985497] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  730.985553] [drm:intel_power_well_enable [i915]] enabling always-on
>[  730.985573] [drm:intel_power_well_enable [i915]] enabling display
>[  730.985593] [drm:hsw_set_power_well [i915]] Enabling power well
>[  730.985629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  730.985653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  730.985676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  730.985697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  730.985721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  730.985743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  730.985768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  730.985792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  730.985817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  730.985851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  730.985920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  730.985960] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  730.985993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  730.988066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  730.988087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  730.988106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.988126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  730.989688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  730.989710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  730.989729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  730.991283] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  730.991303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  730.993167] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  730.996497] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  730.996535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  730.996559] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  730.996590] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  730.996650] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  730.996691] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  730.996776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  730.996815] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  730.996908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.046773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.046813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.046853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.046973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.047020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.047076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.047341] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.047374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.047406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.047435] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.047463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.047470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.047498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.047505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.047534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.047561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.047588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.047615] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.047648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.047675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.047705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.047733] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.047766] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.047787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.047818] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.063358] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.063406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.063492] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.080510] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.080558] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.080599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.080643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.080683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.080722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.080762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.080801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.080840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.080962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.081023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.081079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.081128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.081177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.081535] [drm:intel_power_well_disable [i915]] disabling display
>[  731.081574] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.081606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.081639] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.081685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.081724] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.082134] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.082157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.082181] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.082206] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.082226] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.082248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.082270] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.082291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.082310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.082329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.082346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.082351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.082368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.082372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.082398] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.082423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.082449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.082474] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.082500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.082525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.082551] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.082576] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.082602] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.082628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.082655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.082714] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.082736] [drm:intel_power_well_enable [i915]] enabling display
>[  731.082758] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.082796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.082822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.082850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.082912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.082945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.082978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.083015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.083050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.083085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.083115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.083146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.083182] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.083216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.085292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.085313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.085332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.085351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.086952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.086972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.086990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.088559] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.088580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.090454] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.093726] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.093771] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.093791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.093817] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.094058] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.094089] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.094164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.094214] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.094283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.144047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.144085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.144122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.144161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.144192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.144225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.144259] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.144290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.144321] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.144350] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.144387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.144395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.144434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.144440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.144480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.144520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.144559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.144598] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.144638] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.144676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.144718] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.144752] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.144792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.144834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.144950] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.160590] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.160636] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.160707] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.177750] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.177794] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.177827] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.177953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.178006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.178058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.178106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.178146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.178179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.178223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.178267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.178311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.178350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.178390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.178449] [drm:intel_power_well_disable [i915]] disabling display
>[  731.178494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.178536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.178580] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.178617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.178638] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.179057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.179080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.179113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.179137] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.179155] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.179175] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.179195] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.179214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.179232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.179250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.179266] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.179271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.179287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.179291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.179308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.179324] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.179341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.179356] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.179375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.179391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.179408] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.179425] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.179441] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.179460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.179481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.179533] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.179551] [drm:intel_power_well_enable [i915]] enabling display
>[  731.179567] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.179598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.179616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.179639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.179663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.179687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.179710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.179735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.179760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.179785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.179808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.179833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.179905] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.179927] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.181956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.181977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.181996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.182015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.183582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.183602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.183620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.185170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.185193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.187052] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.190361] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.190436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.190469] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.190512] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.190587] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.190619] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.190698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.190739] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.190807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.240702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.240742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.240781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.240822] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.240929] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.240979] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.241034] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.241080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.241129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.241172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.241525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.241533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.241564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.241570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.241601] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.241631] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.241660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.241688] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.241721] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.241750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.241780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.241807] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.241834] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.241921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.241979] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.257243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.257290] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.257361] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.274784] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.274828] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.274941] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.274999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.275196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.275237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.275277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.275313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.275352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.275395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.275437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.275478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.275517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.275555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.275610] [drm:intel_power_well_disable [i915]] disabling display
>[  731.275656] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.275697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.275739] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.275777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.275795] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.276459] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.276481] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.276504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.276527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.276546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.276566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.276586] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.276605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.276623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.276640] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.276663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.276668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.276691] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.276695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.276719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.276742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.276765] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.276788] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.276812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.276845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.276906] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.276940] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.276970] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.277005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.277042] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.277418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.277449] [drm:intel_power_well_enable [i915]] enabling display
>[  731.277479] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.277530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.277560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.277590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.277617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.277646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.277674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.277707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.277739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.277770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.277797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.277825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.277883] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.277915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.280190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.280211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.280229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.280248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.281815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.281840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.281922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.283569] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.283590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.285462] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.288753] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.288845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.288954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.289025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.289114] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.289144] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.289229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.289266] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.289325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.339108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.339148] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.339187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.339229] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.339262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.339298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.339334] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.339367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.339401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.339432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.339462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.339470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.339499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.339506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.339536] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.339566] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.339596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.339624] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.339659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.339689] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.339720] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.339750] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.339784] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.339828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.339946] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.355649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.355697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.355767] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.372779] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.372827] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.372959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.373020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.373209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.373241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.373272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.373310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.373349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.373393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.373435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.373476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.373515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.373554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.373609] [drm:intel_power_well_disable [i915]] disabling display
>[  731.373654] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.373696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.373738] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.373783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.373816] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.374522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.374544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.374566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.374589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.374608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.374628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.374648] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.374667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.374686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.374703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.374720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.374725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.374741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.374745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.374762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.374779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.374796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.374812] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.374842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.374907] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.374936] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.374966] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.374996] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.375029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.375064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.375153] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.375186] [drm:intel_power_well_enable [i915]] enabling display
>[  731.375216] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.375265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.375297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.375329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.375358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.375389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.375417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.375451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.375484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.375516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.375545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.375574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.375608] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.375640] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.377701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.377724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.377743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.377767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.379329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.379349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.379367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.380948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.380969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.382826] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.386121] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.386172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.386214] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.386239] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.386298] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.386319] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.386373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.386400] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.386447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.436425] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.436466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.436505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.436546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.436579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.436615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.436651] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.436684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.436717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.436748] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.436778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.436786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.436815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.436889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.436943] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.436992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.437041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.437084] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.437137] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.437186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.437238] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.437286] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.437333] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.437388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.437452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.452980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.453032] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.453107] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.470130] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.470178] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.470218] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.470263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.470303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.470343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.470382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.470417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.470455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.470498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.470540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.470582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.470621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.470659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.470716] [drm:intel_power_well_disable [i915]] disabling display
>[  731.470762] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.470803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.470845] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.470971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.471026] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.471777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.471801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.471830] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.471905] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.471932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.471960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.471988] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.472016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.472042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.472069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.472102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.472110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.472144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.472152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.472185] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.472217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.472247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.472277] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.472306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.472325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.472345] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.472369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.472395] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.472422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.472449] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.472510] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.472533] [drm:intel_power_well_enable [i915]] enabling display
>[  731.472555] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.472593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.472619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.472644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.472670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.472692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.472717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.472744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.472771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.472798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.472827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.472871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.472897] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.472920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.474964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.474987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.475007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.475027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.476594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.476614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.476631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.478182] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.478212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.480082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.483364] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.483397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.483417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.483442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.483501] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.483522] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.483575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.483602] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.483650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.533663] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.533703] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.533743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.533784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.533817] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.533929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.533980] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.534031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.534077] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.534124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.534166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.534181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.534223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.534502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.534539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.534564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.534591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.534615] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.534645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.534669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.534697] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.534721] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.534747] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.534776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.534808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.550220] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.550269] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.550340] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.568775] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.568819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.568933] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.568989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.569259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.569290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.569318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.569344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.569372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.569401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.569428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.569455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.569479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.569503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.569547] [drm:intel_power_well_disable [i915]] disabling display
>[  731.569581] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.569607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.569635] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.569664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.569688] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.570432] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.570461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.570492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.570526] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.570551] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.570581] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.570609] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.570638] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.570664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.570690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.570714] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.570721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.570746] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.570752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.570779] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.570803] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.570839] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.570899] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.570930] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.570958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.570986] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.571015] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.571040] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.571071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.571105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.571192] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.571222] [drm:intel_power_well_enable [i915]] enabling display
>[  731.571252] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.571301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.571329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.571358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.571385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.571413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.571440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.571471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.571503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.571535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.571561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.571589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.571619] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.571649] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.573705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.573728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.573747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.573772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.575350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.575372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.575400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.576965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.576988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.578867] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.582222] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.582311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.582343] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.582385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.582479] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.582519] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.582609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.582647] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.582685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.632583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.632624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.632663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.632705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.632740] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.632775] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.632811] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.632931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.632979] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.633028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.633077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.633092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.633138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.633151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.633199] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.633245] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.633293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.633341] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.633392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.633439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.633488] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.633533] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.633573] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.633619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.633655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.649133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.649181] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.649268] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.666357] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.666401] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.666434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.666472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.666506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.666537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.666566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.666595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.666633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.666676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.666717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.666759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.666798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.666836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.666974] [drm:intel_power_well_disable [i915]] disabling display
>[  731.667042] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.667099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.667156] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.667215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.667263] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.667791] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.667833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.667904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.667945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.667977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.668012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.668046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.668079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.668110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.668139] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.668167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.668175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.668205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.668212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.668241] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.668271] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.668300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.668330] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.668360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.668388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.668419] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.668448] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.668478] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.668511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.668546] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.668638] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.668670] [drm:intel_power_well_enable [i915]] enabling display
>[  731.668700] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.668751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.668783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.668814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.668871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.668899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.668932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.668968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.669001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.669034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.669063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.669093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.669129] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.669160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.671223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.671244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.671263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.671282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.672864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.672884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.672902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.674466] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.674489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.676367] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.679637] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.679685] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.679708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.679740] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.679802] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.679884] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.679966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.680007] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.680069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.729943] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.729981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.730024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.730084] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.730121] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.730155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.730198] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.730247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.730291] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.730321] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.730348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.730356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.730383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.730390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.730418] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.730445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.730473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.730500] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.730532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.730559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.730588] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.730615] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.730642] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.730675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.730710] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.746502] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.746550] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.746623] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.763663] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.763711] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.763751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.763810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.763906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.763948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.763990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.764030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.764070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.764114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.764157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.764201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.764240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.764281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.764340] [drm:intel_power_well_disable [i915]] disabling display
>[  731.764386] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.764427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.764469] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.764519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.764539] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.764964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.764988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.765012] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.765037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.765065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.765085] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.765105] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.765124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.765142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.765159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.765176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.765180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.765196] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.765200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.765217] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.765233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.765249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.765265] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.765284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.765300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.765318] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.765334] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.765350] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.765369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.765390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.765443] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.765461] [drm:intel_power_well_enable [i915]] enabling display
>[  731.765478] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.765508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.765531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.765554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.765576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.765599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.765622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.765647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.765672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.765696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.765719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.765742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.765767] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.765790] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.767902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.767926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.767954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.767973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.769540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.769560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.769578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.771135] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.771156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.773021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.776363] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.776457] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.776489] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.776531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.776610] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.776644] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.776722] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.776748] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.776788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.826716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.826756] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.826796] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.826921] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.826962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.827005] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.827046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.827088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.827129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.827170] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.827211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.827225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.827276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.827290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.827325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.827356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.827385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.827414] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.827448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.827477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.827506] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.827536] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.827563] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.827597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.827635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.843263] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.843315] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.843391] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.861733] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.861777] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.861809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.861930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.861989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.862038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.862086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.862134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.862184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.862224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.862257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.862289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.862319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.862347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.862402] [drm:intel_power_well_disable [i915]] disabling display
>[  731.862443] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.862475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.862509] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.862553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.862589] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.862985] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.863007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.863031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.863056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.863075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.863104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.863124] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.863143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.863161] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.863178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.863195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.863199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.863215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.863219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.863236] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.863252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.863280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.863304] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.863324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.863340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.863357] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.863373] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.863389] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.863408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.863429] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.863483] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.863500] [drm:intel_power_well_enable [i915]] enabling display
>[  731.863517] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.863548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.863571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.863595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.863618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.863642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.863665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.863690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.863715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.863740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.863763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.863786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.863821] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.863886] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.865945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.865966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.865985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.866004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.867565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.867585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.867603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.869153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.869173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.871043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.874388] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.874479] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.874512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.874553] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.874630] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.874662] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.874741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.874782] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.874893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.924743] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.924781] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.924818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.924941] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.924977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.925012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.925047] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.925089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.925130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.925171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.925210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.925220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.925259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.925267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.925308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.925348] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.925389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.925428] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.925469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.925508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.925551] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.925591] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.925632] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.925674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.925719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.941283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  731.941331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  731.941400] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  731.959652] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  731.959696] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  731.959729] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  731.959767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.959800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.959911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.960077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.960109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.960142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.960184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.960229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.960273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.960312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.960353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.960409] [drm:intel_power_well_disable [i915]] disabling display
>[  731.960455] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  731.960496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.960541] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.960586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.960621] [drm:intel_power_well_disable [i915]] disabling always-on
>[  731.961102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  731.961124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  731.961146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  731.961169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  731.961187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  731.961207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  731.961227] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  731.961246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  731.961269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  731.961292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  731.961315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  731.961320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.961343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  731.961347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  731.961371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  731.961394] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  731.961418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  731.961440] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  731.961464] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  731.961487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  731.961511] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  731.961534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  731.961557] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  731.961582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  731.961607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  731.961662] [drm:intel_power_well_enable [i915]] enabling always-on
>[  731.961682] [drm:intel_power_well_enable [i915]] enabling display
>[  731.961702] [drm:hsw_set_power_well [i915]] Enabling power well
>[  731.961738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  731.961761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  731.961785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  731.961814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  731.961897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  731.961929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  731.961966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  731.962002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  731.962038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  731.962065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  731.962095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  731.962132] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  731.962161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  731.964230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  731.964251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  731.964269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.964288] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  731.965967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  731.965988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  731.966006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  731.967552] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  731.967573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  731.969434] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  731.972749] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  731.972828] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  731.972943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  731.973083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  731.973144] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  731.973165] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  731.973227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  731.973270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  731.973309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.023078] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.023118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.023157] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.023198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.023232] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.023269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.023311] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.023353] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.023395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.023435] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.023475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.023483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.023524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.023530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.023572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.023612] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.023653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.023693] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.023735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.023775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.023817] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.023934] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.023984] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.024040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.024098] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.039622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.039669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.039740] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.056771] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.056814] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.056937] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.056996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.057047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.057096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.057132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.057161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.057193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.057227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.057260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.057291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.057319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.057346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.057401] [drm:intel_power_well_disable [i915]] disabling display
>[  732.057442] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.057472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.057505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.057540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.057570] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.057992] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.058025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.058055] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.058080] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.058100] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.058121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.058143] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.058163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.058183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.058202] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.058220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.058225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.058243] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.058247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.058265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.058283] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.058300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.058317] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.058338] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.058356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.058374] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.058392] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.058409] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.058430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.058452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.058510] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.058529] [drm:intel_power_well_enable [i915]] enabling display
>[  732.058550] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.058588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.058614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.058640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.058665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.058688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.058712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.058740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.058766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.058793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.058858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.058889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.058922] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.058952] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.061017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.061038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.061057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.061076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.062627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.062649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.062668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.064220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.064241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.066112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.069428] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.069494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.069533] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.069584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.069666] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.069706] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.069793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.070046] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.070089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.119769] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.119806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.119932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.119992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.120041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.120094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.120147] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.120196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.120245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.120291] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.120336] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.120348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.120392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.120403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.120448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.120493] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.120538] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.120579] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.120630] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.120675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.120723] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.120764] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.120808] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.120894] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.120951] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.136302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.136347] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.136416] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.153780] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.153856] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.153887] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.153925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.153958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.153989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.154018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.154048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.154080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.154114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.154146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.154177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.154205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.154233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.154286] [drm:intel_power_well_disable [i915]] disabling display
>[  732.154326] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.154357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.154390] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.154424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.154452] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.155039] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.155071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.155105] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.155142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.155170] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.155203] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.155233] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.155263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.155294] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.155322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.155348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.155356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.155383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.155390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.155420] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.155447] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.155475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.155501] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.155534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.155560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.155589] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.155615] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.155643] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.155672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.155705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.155771] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.155803] [drm:intel_power_well_enable [i915]] enabling display
>[  732.155863] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.155916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.155946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.155977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.156005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.156035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.156063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.156097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.156130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.156164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.156191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.156221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.156256] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.156285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.158394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.158415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.158433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.158451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.160023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.160043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.160062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.161610] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.161633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.163501] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.166815] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.166930] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.166950] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.166975] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.167037] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.167062] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.167116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.167147] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.167198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.217231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.217269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.217308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.217353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.217392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.217432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.217472] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.217511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.217551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.217590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.217629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.217637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.217675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.217682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.217722] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.217761] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.217800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.217924] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.217976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.218030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.218079] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.218128] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.218172] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.218228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.218264] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.233739] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.233790] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.234118] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.251151] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.251198] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.251239] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.251284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.251324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.251364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.251399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.251439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.251476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.251518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.251559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.251601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.251640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.251679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.251735] [drm:intel_power_well_disable [i915]] disabling display
>[  732.251781] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.251902] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.251949] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.251987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.252020] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.252467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.252499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.252532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.252567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.252596] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.252627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.252648] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.252667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.252688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.252712] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.252735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.252739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.252762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.252766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.252800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.252861] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.252895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.252924] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.252958] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.252987] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.253020] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.253047] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.253077] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.253112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.253148] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.253241] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.253272] [drm:intel_power_well_enable [i915]] enabling display
>[  732.253302] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.253351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.253380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.253410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.253436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.253464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.253492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.253524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.253555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.253587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.253612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.253640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.253670] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.253701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.255771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.255794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.255873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.255909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.257574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.257594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.257611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.259184] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.259205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.261074] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.264345] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.264393] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.264425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.264456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.264517] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.264547] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.264622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.264658] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.264697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.314664] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.314705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.314744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.314785] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.314892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.314942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.314992] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.315043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.315088] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.315135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.315481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.315488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.315515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.315521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.315549] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.315574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.315600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.315624] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.315654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.315679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.315705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.315730] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.315753] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.315783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.315863] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.331213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.331261] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.331349] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.348368] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.348412] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.348445] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.348483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.348516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.348547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.348576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.348605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.348636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.348669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.348700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.348732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.348760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.348797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.348940] [drm:intel_power_well_disable [i915]] disabling display
>[  732.349008] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.349059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.349112] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.349161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.349191] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.349750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.349791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.349861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.349901] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.349933] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.349967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.350001] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.350033] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.350066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.350097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.350126] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.350135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.350163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.350171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.350201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.350230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.350258] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.350286] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.350318] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.350346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.350376] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.350404] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.350432] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.350463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.350498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.350590] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.350622] [drm:intel_power_well_enable [i915]] enabling display
>[  732.350652] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.350704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.350735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.350765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.350795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.350852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.350883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.350918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.350951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.350985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.351014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.351043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.351078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.351109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.353187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.353217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.353245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.353275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.354860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.354890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.354918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.356478] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.356505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.358361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.361396] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.361479] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.361500] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.361527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.361594] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.361626] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.361702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.361744] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.361794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.411744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.411784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.411906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.411952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.411985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.412020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.412055] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.412087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.412119] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.412149] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.412177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.412186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.412214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.412220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.412261] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.412301] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.412342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.412384] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.412424] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.412463] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.412510] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.412541] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.412570] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.412604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.412639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.428314] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.428362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.428452] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.446605] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.446649] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.446680] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.446719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.446752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.446783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.446896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.446941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.446991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.447047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.447096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.447145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.447194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.447221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.447275] [drm:intel_power_well_disable [i915]] disabling display
>[  732.447316] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.447346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.447378] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.447412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.447442] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.447791] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.447860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.447895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.447934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.447965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.447999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.448032] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.448065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.448096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.448127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.448157] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.448165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.448194] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.448201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.448230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.448260] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.448290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.448316] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.448349] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.448378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.448409] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.448437] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.448466] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.448500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.448534] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.448627] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.448659] [drm:intel_power_well_enable [i915]] enabling display
>[  732.448689] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.448741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.448773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.448837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.448869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.448901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.448934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.448969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.449003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.449036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.449067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.449098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.449133] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.449165] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.451231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.451252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.451270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.451290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.452887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.452907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.452924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.454479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.454502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.456367] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.459653] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.459745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.459771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.459878] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.459961] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.460003] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.460101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.460153] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.460207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.510056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.510096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.510134] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.510172] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.510207] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.510247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.510287] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.510327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.510367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.510406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.510444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.510452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.510491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.510497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.510538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.510577] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.510616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.510655] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.510695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.510733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.510774] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.510897] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.510945] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.510996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.511050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.526537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.526590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.526665] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.543705] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.543748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.543781] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.543915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.543966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.544017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.544064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.544112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.544161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.544213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.544245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.544278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.544308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.544337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.544392] [drm:intel_power_well_disable [i915]] disabling display
>[  732.544434] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.544466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.544500] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.544536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.544567] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.545038] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.545070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.545098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.545121] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.545140] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.545160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.545181] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.545203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.545227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.545251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.545274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.545278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.545301] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.545305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.545329] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.545352] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.545376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.545399] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.545423] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.545446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.545470] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.545493] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.545516] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.545541] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.545566] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.545622] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.545643] [drm:intel_power_well_enable [i915]] enabling display
>[  732.545663] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.545698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.545722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.545745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.545769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.545847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.545878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.545916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.545952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.545986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.546017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.546049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.546085] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.546118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.548195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.548215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.548234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.548253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.549844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.549865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.549884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.551447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.551469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.554466] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.557756] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.557906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.557953] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.558021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.558234] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.558266] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.558344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.558384] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.558441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.608070] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.608111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.608151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.608193] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.608225] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.608261] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.608297] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.608337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.608379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.608419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.608459] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.608467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.608507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.608514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.608556] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.608597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.608637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.608677] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.608719] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.608758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.608801] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.608919] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.608978] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.609037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.609095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.624660] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.624708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.624778] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.641877] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.641920] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.641952] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.641991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.642024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.642063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.642103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.642139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.642178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.642221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.642263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.642305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.642351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.642373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.642405] [drm:intel_power_well_disable [i915]] disabling display
>[  732.642430] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.642451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.642472] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.642494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.642512] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.642890] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.642920] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.642945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.642969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.642989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.643011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.643032] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.643053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.643078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.643103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.643128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.643134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.643158] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.643163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.643189] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.643214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.643239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.643264] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.643290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.643314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.643341] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.643366] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.643392] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.643419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.643445] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.643506] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.643529] [drm:intel_power_well_enable [i915]] enabling display
>[  732.643550] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.643589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.643615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.643640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.643665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.643691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.643716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.643743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.643770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.643831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.643861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.643889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.643923] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.643952] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.646041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.646063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.646081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.646101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.647654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.647675] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.647695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.649246] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.649267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.651136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.654473] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.654554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.654574] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.654600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.654661] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.654682] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.654735] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.654762] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.654853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.704863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.704903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.704942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.704984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.705017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.705053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.705089] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.705124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.705157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.705189] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.705219] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.705227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.705256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.705263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.705293] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.705322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.705352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.705381] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.705415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.705444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.705475] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.705504] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.705533] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.705568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.705606] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.721379] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.721427] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.721497] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.738523] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.738571] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.738611] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.738656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.738696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.738736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.738775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.738896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.738949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.739006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.739042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.739075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.739105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.739134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.739186] [drm:intel_power_well_disable [i915]] disabling display
>[  732.739227] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.739260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.739294] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.739336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.739354] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.739737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.739761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.739850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.739889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.739918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.739951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.739983] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.740012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.740041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.740069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.740099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.740107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.740133] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.740141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.740168] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.740198] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.740218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.740235] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.740257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.740276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.740295] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.740313] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.740330] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.740352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.740378] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.740440] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.740463] [drm:intel_power_well_enable [i915]] enabling display
>[  732.740484] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.740524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.740550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.740577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.740602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.740629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.740655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.740683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.740709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.740737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.740763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.740823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.740857] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.740887] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.742949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.742970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.742988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.743007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.744573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.744593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.744612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.746168] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.746189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.748059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.751382] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.751441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.751474] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.751516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.751599] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.751620] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.751673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.751699] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.751738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.801679] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.801720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.801759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.801879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.802068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.802104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.802140] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.802172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.802203] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.802232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.802260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.802268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.802296] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.802302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.802331] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.802359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.802387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.802414] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.802447] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.802475] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.802504] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.802531] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.802558] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.802591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.802627] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.818234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.818280] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.818348] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.836726] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.836770] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.836885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.836951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.837003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.837053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.837089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.837118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.837150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.837200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.837245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.837279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.837308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.837338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.837391] [drm:intel_power_well_disable [i915]] disabling display
>[  732.837432] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.837452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.837474] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.837496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.837514] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.837902] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.837927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.837951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.837975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.837995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.838016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.838045] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.838064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.838082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.838100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.838116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.838121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.838137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.838141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.838158] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.838180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.838204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.838227] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.838251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.838274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.838298] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.838319] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.838343] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.838368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.838393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.838449] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.838469] [drm:intel_power_well_enable [i915]] enabling display
>[  732.838489] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.838524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.838548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.838572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.838595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.838616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.838639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.838664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.838689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.838714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.838737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.838760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.838835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.838865] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.840930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.840952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.840971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.840990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.842560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.842580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.842598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.844161] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.844181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.846054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.849370] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.849437] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.849469] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.849511] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.849587] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.849620] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.849711] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.849741] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.849842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.899702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.899742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.899782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.899903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.899944] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.899980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.900014] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.900047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.900079] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.900108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.900136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.900145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.900173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.900180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.900211] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.900239] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.900269] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.900296] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.900331] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.900359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.900390] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.900417] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.900446] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.900480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.900517] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.916244] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  732.916296] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  732.916370] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  732.933392] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  732.933436] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  732.933468] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  732.933507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.933539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.933570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.933599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.933637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.933677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.933720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.933761] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.933883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.933929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.933978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.934062] [drm:intel_power_well_disable [i915]] disabling display
>[  732.934127] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  732.934174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.934225] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.934279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.934325] [drm:intel_power_well_disable [i915]] disabling always-on
>[  732.934833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.934875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.934908] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.934942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.934961] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.934982] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.935005] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.935029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.935053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.935076] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.935099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.935104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.935127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.935131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.935155] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.935178] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.935202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.935225] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.935248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.935271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.935296] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.935317] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.935340] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.935365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.935390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  732.935447] [drm:intel_power_well_enable [i915]] enabling always-on
>[  732.935468] [drm:intel_power_well_enable [i915]] enabling display
>[  732.935488] [drm:hsw_set_power_well [i915]] Enabling power well
>[  732.935524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  732.935547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  732.935571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  732.935595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  732.935615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  732.935638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  732.935663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  732.935688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  732.935713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.935736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  732.935769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  732.935834] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  732.935865] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  732.937938] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  732.937961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  732.937983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.938007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  732.939575] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  732.939596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  732.939615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  732.941189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  732.941214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  732.943086] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  732.946375] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  732.946474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  732.946514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  732.946565] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  732.946664] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  732.946715] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  732.946855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  732.946897] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  732.946940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  732.996736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  732.996775] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  732.996893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  732.996948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  732.996996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  732.997046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  732.997096] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  732.997142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  732.997189] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  732.997230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  732.997273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  732.997285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.997329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  732.997340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  732.997384] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  732.997424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  732.997469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  732.997508] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  732.997557] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  732.997597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  732.997642] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  732.997681] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  732.997723] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  732.997775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  732.997869] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.013288] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.013336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.013423] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.032234] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.032278] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.032310] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.032349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.032381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.032412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.032442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.032472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.032503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.032537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.032568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.032599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.032627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.032655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.032707] [drm:intel_power_well_disable [i915]] disabling display
>[  733.032748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.032871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.032906] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.032943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.032974] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.033462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.033484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.033510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.033545] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.033563] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.033583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.033603] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.033621] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.033640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.033657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.033673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.033678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.033694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.033698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.033715] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.033731] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.033747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.033821] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.033853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.033884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.033917] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.033949] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.033979] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.034014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.034049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.034141] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.034173] [drm:intel_power_well_enable [i915]] enabling display
>[  733.034203] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.034253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.034285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.034316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.034346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.034373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.034405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.034438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.034471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.034503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.034532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.034561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.034595] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.034626] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.036704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.036727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.036746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.036808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.038364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.038394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.038411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.039973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.039996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.041876] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.045224] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.045294] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.045314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.045340] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.045401] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.045422] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.045475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.045501] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.045549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.095558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.095602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.095646] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.095694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.095734] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.095776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.095892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.095942] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.095994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.096037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.096083] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.096096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.096142] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.096153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.096197] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.096238] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.096284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.096326] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.096376] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.096423] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.096471] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.096517] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.096544] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.096573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.096606] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.112117] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.112165] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.112234] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.129295] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.129338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.129370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.129408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.129447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.129487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.129528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.129567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.129606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.129648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.129690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.129731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.129770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.129868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.129959] [drm:intel_power_well_disable [i915]] disabling display
>[  733.130024] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.130347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.130383] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.130419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.130449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.130808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.130833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.130857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.130882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.130903] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.130926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.130948] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.130968] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.130988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.131013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.131043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.131048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.131065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.131069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.131091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.131115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.131139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.131162] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.131185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.131208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.131233] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.131256] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.131279] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.131304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.131329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.131384] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.131405] [drm:intel_power_well_enable [i915]] enabling display
>[  733.131424] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.131460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.131484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.131507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.131539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.131563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.131585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.131617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.131637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.131661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.131684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.131707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.131732] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.131766] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.133851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.133873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.133891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.133911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.135480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.135504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.135527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.137089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.137111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.138977] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.142300] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.142361] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.142400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.142426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.142487] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.142508] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.142562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.142589] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.142628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.192618] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.192657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.192697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.192738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.192771] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.192881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.192934] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.192984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.193035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.193078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.193124] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.193138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.193182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.193195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.193241] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.193623] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.193642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.193665] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.193689] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.193712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.193736] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.193757] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.193825] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.193864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.193900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.209165] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.209212] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.209282] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.228202] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.228245] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.228278] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.228316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.228349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.228380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.228410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.228439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.228471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.228505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.228537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.228569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.228597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.228625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.228678] [drm:intel_power_well_disable [i915]] disabling display
>[  733.228718] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.228750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.228872] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.228925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.228969] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.229509] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.229532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.229556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.229581] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.229601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.229622] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.229644] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.229665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.229685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.229704] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.229722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.229727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.229747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.229786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.229816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.229845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.229873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.229900] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.229931] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.229958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.229987] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.230013] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.230039] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.230069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.230103] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.230194] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.230227] [drm:intel_power_well_enable [i915]] enabling display
>[  733.230257] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.230310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.230343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.230374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.230401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.230420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.230441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.230463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.230485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.230505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.230524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.230542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.230565] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.230586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.232620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.232640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.232659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.232678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.234252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.234272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.234290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.235848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.235870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.237748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.241094] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.241147] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.241185] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.241238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.241336] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.241386] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.241501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.241563] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.241629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.291291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.291331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.291373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.291420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.291461] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.291502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.291544] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.291585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.291626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.291667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.291707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.291715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.291755] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.291833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.291887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.291935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.291982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.292025] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.292074] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.292118] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.292164] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.292212] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.292536] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.292573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.292611] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.307950] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.308014] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.308089] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.325347] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.325391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.325424] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.325463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.325497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.325536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.325576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.325611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.325650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.325693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.325735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.325856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.325903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.325948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.326033] [drm:intel_power_well_disable [i915]] disabling display
>[  733.326103] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.326156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.326211] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.326270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.326317] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.326835] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.326864] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.326894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.326927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.326953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.326994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.327024] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.327053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.327085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.327104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.327122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.327127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.327145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.327149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.327176] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.327193] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.327209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.327225] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.327245] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.327261] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.327278] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.327294] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.327310] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.327329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.327350] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.327392] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.327409] [drm:intel_power_well_enable [i915]] enabling display
>[  733.327427] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.327463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.327487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.327511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.327534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.327558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.327581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.327606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.327631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.327656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.327679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.327702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.327726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.327754] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.329844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.329865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.329883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.329902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.331469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.331490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.331508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.333050] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.333073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.334929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.338265] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.338367] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.338407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.338459] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.338541] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.338580] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.338667] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.338715] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.338855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.388648] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.388688] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.388728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.388841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.388889] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.388945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.388994] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.389044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.389094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.389141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.389188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.389201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.389245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.389256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.389301] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.389343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.389387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.389426] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.389476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.389517] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.389562] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.389602] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.389644] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.389690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.389740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.405170] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.405219] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.405290] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.422714] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.422758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.422874] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.422932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.422978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.423024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.423066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.423111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.423155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.423205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.423254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.423303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.423343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.423385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.423467] [drm:intel_power_well_disable [i915]] disabling display
>[  733.423528] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.423578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.423629] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.423682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.423736] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.424095] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.424115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.424137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.424164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.424187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.424211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.424252] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.424274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.424302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.424319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.424335] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.424339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.424356] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.424360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.424377] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.424393] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.424415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.424438] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.424462] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.424485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.424509] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.424530] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.424553] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.424578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.424603] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.424657] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.424678] [drm:intel_power_well_enable [i915]] enabling display
>[  733.424698] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.424733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.424802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.424838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.424868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.424899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.424928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.424962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.424995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.425031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.425058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.425088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.425123] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.425153] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.427248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.427270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.427288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.427308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.429009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.429030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.429049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.430599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.430622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.432477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.435766] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.435864] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.435904] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.435955] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.436036] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.436076] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.436149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.436186] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.436224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.486092] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.486133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.486175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.486223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.486263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.486305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.486347] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.486388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.486429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.486470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.486510] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.486518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.486558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.486565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.486607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.486647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.486688] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.486728] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.486844] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.486897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.486951] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.486997] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.487046] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.487101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.487158] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.502636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.502680] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.502745] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.519818] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.519862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.519895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.519934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.519968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.519999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.520029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.520059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.520090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.520124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.520157] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.520188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.520226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.520265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.520321] [drm:intel_power_well_disable [i915]] disabling display
>[  733.520367] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.520408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.520450] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.520495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.520528] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.521344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.521379] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.521414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.521461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.521490] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.521521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.521552] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.521581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.521610] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.521648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.521678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.521687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.521723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.521730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.521797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.521825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.521856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.521887] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.521921] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.521952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.521985] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.522015] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.522045] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.522080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.522116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.522207] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.522238] [drm:intel_power_well_enable [i915]] enabling display
>[  733.522268] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.522319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.522351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.522382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.522412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.522441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.522472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.522506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.522538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.522570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.522600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.522629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.522664] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.522695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.524788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.524810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.524828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.524848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.526424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.526446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.526465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.528025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.528046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.529930] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.533277] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.533367] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.533398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.533423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.533484] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.533505] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.533558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.533585] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.533625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.583622] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.583662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.583702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.583743] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.583864] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.583924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.583979] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.584031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.584080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.584128] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.584175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.584187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.584232] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.584243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.584291] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.584337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.584383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.584428] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.584475] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.584521] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.584569] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.584624] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.584650] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.584683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.584718] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.600159] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.600208] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.600281] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.618698] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.618742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.618856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.619049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.619084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.619115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.619145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.619174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.619205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.619239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.619271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.619302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.619330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.619357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.619414] [drm:intel_power_well_disable [i915]] disabling display
>[  733.619439] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.619457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.619477] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.619497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.619514] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.619891] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.619924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.619959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.619996] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.620027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.620061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.620094] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.620125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.620156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.620186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.620216] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.620224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.620252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.620259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.620288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.620319] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.620348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.620378] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.620411] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.620440] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.620472] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.620501] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.620531] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.620564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.620599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.620690] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.620722] [drm:intel_power_well_enable [i915]] enabling display
>[  733.620769] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.620819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.620852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.620884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.620914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.620944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.620973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.621006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.621039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.621072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.621101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.621127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.621162] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.621193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.623261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.623282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.623300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.623319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.624982] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.625007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.625030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.626595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.626617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.628494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.631782] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.631862] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.631881] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.631907] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.631971] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.631997] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.632051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.632082] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.632134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.682147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.682187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.682226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.682267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.682300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.682335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.682371] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.682405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.682438] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.682469] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.682499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.682507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.682536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.682543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.682580] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.682626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.682668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.682696] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.682728] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.682845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.682887] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.682926] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.682965] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.683009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.683058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.698700] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.698748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.699009] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.716031] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.716074] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.716107] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.716145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.716178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.716209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.716239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.716268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.716299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.716333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.716364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.716395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.716423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.716451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.716528] [drm:intel_power_well_disable [i915]] disabling display
>[  733.716564] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.716590] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.716618] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.716647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.716671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.717283] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.717314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.717346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.717379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.717405] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.717435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.717463] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.717498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.717518] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.717537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.717555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.717561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.717578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.717582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.717602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.717620] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.717638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.717655] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.717677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.717695] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.717715] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.717742] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.717803] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.717835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.717867] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.717957] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.717983] [drm:intel_power_well_enable [i915]] enabling display
>[  733.718002] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.718035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.718056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.718075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.718093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.718110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.718130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.718152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.718172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.718192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.718210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.718229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.718251] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.718272] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.720330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.720352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.720371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.720390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.721976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.722001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.722024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.723577] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.723599] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.725472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.728820] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.728900] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.728926] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.728960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.729038] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.729077] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.729175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.729226] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.729277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.779171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.779211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.779251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.779293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.779326] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.779361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.779398] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.779431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.779465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.779496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.779527] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.779535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.779564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.779570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.779610] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.779652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.779692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.779733] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.779857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.779913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.779970] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.780001] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.780033] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.780070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.780106] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.795710] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.795835] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.796129] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.814699] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.814742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.814856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.814917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.815144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.815184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.815224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.815264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.815303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.815346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.815388] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.815429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.815468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.815506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.815564] [drm:intel_power_well_disable [i915]] disabling display
>[  733.815590] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.815612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.815635] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.815657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.815674] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.816272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.816293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.816317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.816344] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.816377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.816411] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.816433] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.816462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.816480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.816497] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.816514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.816519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.816535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.816539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.816555] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.816572] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.816588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.816604] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.816623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.816640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.816658] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.816674] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.816690] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.816713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.816789] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.816880] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.817154] [drm:intel_power_well_enable [i915]] enabling display
>[  733.817185] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.817237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.817270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.817303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.817334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.817364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.817396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.817430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.817463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.817496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.817526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.817555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.817590] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.817622] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.819705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.819728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.819803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.819836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.821487] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.821510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.821533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.823095] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.823116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.824981] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.828301] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.828364] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.828397] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.828439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.828517] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.828550] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.828629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.828670] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.828730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.878614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.878655] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.878694] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.878735] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.878856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.878908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.878963] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.879182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.879232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.879278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.879324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.879336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.879381] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.879391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.879437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.879482] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.879526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.879570] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.879620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.879666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.879715] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.879800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.879850] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.879892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.879929] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.895184] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.895231] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.895300] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  733.913663] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  733.913706] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  733.913739] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  733.913863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.914067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.914100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.914131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.914159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.914191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.914224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.914256] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.914287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.914315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.914342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.914393] [drm:intel_power_well_disable [i915]] disabling display
>[  733.914434] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  733.914465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.914505] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.914551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.914584] [drm:intel_power_well_disable [i915]] disabling always-on
>[  733.915104] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.915138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.915175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.915212] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.915243] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.915285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.915316] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.915345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.915375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.915403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.915431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.915438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.915465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.915471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.915499] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.915528] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.915556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.915583] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.915610] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.915637] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.915666] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.915694] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.915728] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.915793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.915830] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.915921] [drm:intel_power_well_enable [i915]] enabling always-on
>[  733.915952] [drm:intel_power_well_enable [i915]] enabling display
>[  733.915983] [drm:hsw_set_power_well [i915]] Enabling power well
>[  733.916034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  733.916065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  733.916096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  733.916126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  733.916155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  733.916187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  733.916220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  733.916253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  733.916286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.916315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  733.916344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  733.916378] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  733.916409] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  733.918474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  733.918495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  733.918513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.918532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  733.920104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  733.920123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  733.920141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  733.921723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  733.921760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  733.923610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  733.926904] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  733.926978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  733.926998] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  733.927025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  733.927084] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  733.927106] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  733.927159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  733.927199] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  733.927237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  733.977230] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  733.977271] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  733.977311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  733.977352] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  733.977385] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  733.977421] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  733.977456] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  733.977490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  733.977523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  733.977554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  733.977584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  733.977592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.977621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  733.977629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  733.977659] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  733.977688] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  733.977717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  733.977824] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  733.977877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  733.977924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  733.977976] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  733.978024] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  733.978072] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  733.978119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  733.978155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  733.993801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  733.993850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  733.993920] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  734.010953] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  734.010996] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  734.011028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.011067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.011100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.011138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.011178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.011213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.011252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.011295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.011337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.011378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.011417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.011455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.011513] [drm:intel_power_well_disable [i915]] disabling display
>[  734.011558] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.011600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.011642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  734.011686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.011720] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.012586] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.012619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.012652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.012688] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.012718] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.012817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.012855] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  734.012891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  734.012926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.012960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.012992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.013191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.013217] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.013222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.013244] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.013265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.013284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.013303] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  734.013325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.013344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.013364] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.013383] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  734.013401] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  734.013424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.013447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  734.013508] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.013531] [drm:intel_power_well_enable [i915]] enabling display
>[  734.013553] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.013593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.013621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.013648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.013674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.013700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.013726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.013802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.013848] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.013884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.013916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.013948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.013985] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  734.014017] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.016338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.016359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.016378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.016397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.017971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.017991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.018009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.019549] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.019571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.021424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.024725] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  734.024809] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.024848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  734.024899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.024992] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  734.025014] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  734.025069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.025097] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  734.025144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.075067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.075111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.075154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.075201] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.075241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.075284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.075325] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  734.075366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  734.075407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.075448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.075488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.075496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.075535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.075542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.075584] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.075625] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.075666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.075706] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  734.075831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.075890] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.075946] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.075999] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  734.076048] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  734.076104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.076160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  734.091614] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  734.091662] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.091732] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  734.108811] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  734.108872] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  734.108920] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.108975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.109032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.109068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.109095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.109121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.109155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.109193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.109230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.109267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.109302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.109337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.109388] [drm:intel_power_well_disable [i915]] disabling display
>[  734.109428] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.109465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.109502] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  734.109542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.109571] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.109843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.109934] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.109985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.110030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.110074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.110104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.110134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.110167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.110200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.110234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.110268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.110300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.110330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.110359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.110400] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  734.110436] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.110758] [drm:drm_mode_addfb2] [FB:77]
>[  734.110809] [drm:drm_mode_addfb2] [FB:78]
>[  734.143687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  734.143874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  734.143971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  734.144033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  734.144046] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  734.144104] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.144125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.144148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.144172] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.144191] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.144211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.144231] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.144250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.144268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.144285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.144302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.144306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.144323] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.144327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.144350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.144374] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.144397] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.144429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.144451] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.144476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.144506] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  734.144524] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.144542] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.144562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.144588] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.147854] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.147874] [drm:intel_power_well_enable [i915]] enabling display
>[  734.147891] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.147926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.147949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.147973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.147997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.148020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.148044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.148069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.148094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.148118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.148142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.148164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.148189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.148213] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.150340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.150362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.150381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.150400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.151984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.152005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.152023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.153583] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.153605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.155478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.158822] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.158914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.158948] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.158990] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.175692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.175818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.175922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.192557] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.192598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.192637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.192680] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.192713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.192808] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.192863] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.192911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.192963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.193009] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.193055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.193069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.193113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.193124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.193171] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.193220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.193265] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.193311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.193362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.193404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.193451] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.193493] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.193535] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.193582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.193632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.193821] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.193889] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.194215] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.210609] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.210646] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.210687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.210727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.210846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.210888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.210920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.210953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.210988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.211022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.211053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.211083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.211111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.211165] [drm:intel_power_well_disable [i915]] disabling display
>[  734.211217] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.211237] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.211259] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.211279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.211297] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.211442] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.211467] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.211494] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.211524] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.211549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.211576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.211602] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.211628] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.211654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.211680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.211705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.211738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.211771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.211778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.211810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.211839] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.211867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.211894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.211926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.211953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.211981] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.212009] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.212035] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.212067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.212099] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.212193] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.212215] [drm:intel_power_well_enable [i915]] enabling display
>[  734.212237] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.212276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.212303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.212329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.212355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.212381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.212407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.212431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.212458] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.212486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.212511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.212537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.212564] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.212590] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.214664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.214688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.214711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.214790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.216347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.216368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.216389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.217948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.217969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.219841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.223174] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.223278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.223311] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.223353] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.223478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.223517] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.223577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.273534] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.273571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.273609] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.273654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.273693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.273733] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.273849] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.273902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.274166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.274206] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.274247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.274255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.274304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.274317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.274361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.274394] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.274425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.274454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.274488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.274519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.274549] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.274579] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.274617] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.274661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.274696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.274947] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.274975] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.275033] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.292058] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.292095] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.292135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.292169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.292200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.292229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.292258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.292288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.292322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.292354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.292385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.292413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.292441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.292493] [drm:intel_power_well_disable [i915]] disabling display
>[  734.292533] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.292564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.292597] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.292628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.292657] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.293437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.293461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.293485] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.293510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.293535] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.293561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.293587] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.293612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.293638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.293663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.293688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.293693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.293725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.293767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.293802] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.293832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.293865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.293893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.293927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.293955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.293987] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.294014] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.294043] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.294077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.294346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.294430] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.294458] [drm:intel_power_well_enable [i915]] enabling display
>[  734.294485] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.294534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.294562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.294589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.294615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.294639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.294667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.294697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.294766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.294800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.294827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.294856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.294891] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.294921] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.297166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.297187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.297205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.297224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.298826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.298847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.298865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.300407] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.300428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.302285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.305502] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.305550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.305569] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.305595] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.305679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.305729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.305834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.355844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.355884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.355927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.355974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.356015] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.356058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.356099] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.356140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.356181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.356222] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.356262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.356270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.356310] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.356317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.356358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.356399] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.356439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.356480] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.356521] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.356561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.356611] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.356644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.356673] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.356705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.356795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.356916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.356970] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.357056] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.374101] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.374138] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.374178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.374212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.374243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.374272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.374310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.374350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.374392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.374435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.374476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.374515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.374554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.374611] [drm:intel_power_well_disable [i915]] disabling display
>[  734.374657] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.374698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.374822] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.374877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.374923] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.375336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.375361] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.375388] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.375418] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.375443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.375469] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.375495] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.375521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.375547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.375572] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.375597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.375604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.375628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.375633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.375659] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.375685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.375717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.375777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.375812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.375841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.375872] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.375900] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.375928] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.375960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.375993] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.376082] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.376109] [drm:intel_power_well_enable [i915]] enabling display
>[  734.376129] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.376163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.376184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.376204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.376223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.376242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.376261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.376284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.376304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.376324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.376342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.376360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.376383] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.376404] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.378457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.378479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.378498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.378517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.380073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.380095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.380114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.381654] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.381675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.383580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.386894] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.386962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.387001] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.387052] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.387162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.387210] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.387253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.437242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.437282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.437322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.437364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.437399] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.437435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.437471] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.437505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.437538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.437569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.437599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.437607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.437637] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.437643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.437674] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.437704] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.437814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.437856] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.437904] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.437947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.437992] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.438034] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.438076] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.438123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.438173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.438319] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.438360] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.438446] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.455528] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.455565] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.455605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.455638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.455670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.455699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.455806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.455866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.456030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.456064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.456094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.456123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.456150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.456201] [drm:intel_power_well_disable [i915]] disabling display
>[  734.456241] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.456271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.456303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.456339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.456385] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.456850] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.456891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.456923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.456958] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.456978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.457000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.457030] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.457048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.457067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.457084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.457101] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.457106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.457122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.457126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.457142] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.457159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.457175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.457191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.457210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.457226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.457244] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.457260] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.457276] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.457295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.457316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.457370] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.457387] [drm:intel_power_well_enable [i915]] enabling display
>[  734.457404] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.457435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.457453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.457471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.457488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.457504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.457521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.457540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.457559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.457577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.457593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.457608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.457629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.457647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.459750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.459772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.459791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.459810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.461381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.461403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.461422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.462975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.462997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.464870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.468032] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.468107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.468134] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.468167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.468257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.468292] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.468342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.518349] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.518391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.518434] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.518480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.518521] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.518563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.518604] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.518646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.518687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.518801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.518849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.518862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.518906] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.518918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.518963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.519010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.519057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.519098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.519150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.519184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.519216] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.519244] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.519273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.519307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.519345] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.519432] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.519459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.519513] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.536540] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.536577] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.536618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.536658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.536698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.536813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.536865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.537116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.537160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.537203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.537244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.537284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.537322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.537378] [drm:intel_power_well_disable [i915]] disabling display
>[  734.537425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.537466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.537509] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.537551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.537584] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.538092] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.538123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.538145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.538169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.538187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.538207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.538228] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.538247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.538265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.538283] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.538299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.538304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.538320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.538324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.538341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.538357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.538373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.538389] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.538412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.538435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.538460] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.538481] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.538504] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.538529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.538554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.538611] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.538631] [drm:intel_power_well_enable [i915]] enabling display
>[  734.538650] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.538687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.538763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.538797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.538826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.538854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.538884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.538918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.538950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.538981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.539008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.539036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.539069] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.539098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.541160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.541181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.541199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.541218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.542821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.542841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.542859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.544415] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.544435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.546301] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.549644] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.549803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.549956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.550002] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.550107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.550147] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.550208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.599996] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.600036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.600076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.600117] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.600150] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.600186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.600222] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.600256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.600289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.600320] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.600359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.600371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.600416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.600425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.600455] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.600483] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.600511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.600537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.600570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.600597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.600625] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.600652] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.600679] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.600787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.600838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.600994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.601052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.601141] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.618169] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.618207] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.618247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.618281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.618312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.618341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.618370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.618401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.618434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.618466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.618498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.618526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.618553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.618607] [drm:intel_power_well_disable [i915]] disabling display
>[  734.618648] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.618678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.618784] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.618833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.618878] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.619547] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.619580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.619614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.619651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.619680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.619744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.619777] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.619806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.619835] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.619863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.619890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.619898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.619927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.620070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.620091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.620116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.620142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.620167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.620193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.620218] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.620244] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.620270] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.620295] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.620322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.620349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.620411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.620433] [drm:intel_power_well_enable [i915]] enabling display
>[  734.620454] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.620493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.620517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.620542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.620568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.620593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.620618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.620645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.620672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.620704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.620759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.620788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.620822] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.620852] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.623188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.623209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.623227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.623246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.624810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.624831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.624853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.626410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.626431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.628302] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.631621] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.631685] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.631808] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.631929] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.632025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.632064] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.632125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.681941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.681985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.682029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.682075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.682116] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.682158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.682199] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.682240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.682282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.682322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.682363] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.682370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.682410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.682417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.682458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.682499] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.682539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.682579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.682621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.682660] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.682703] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.682816] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.682864] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.682917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.682952] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.683056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.683098] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.683158] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.700179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.700217] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.700261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.700302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.700342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.700377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.700416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.700453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.700496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.700538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.700579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.700618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.700656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.700776] [drm:intel_power_well_disable [i915]] disabling display
>[  734.700840] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.700899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.700951] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.701008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.701040] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.701524] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.701550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.701577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.701606] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.701631] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.701658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.701685] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.701743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.701775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.701804] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.701831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.701840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.701866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.701874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.701902] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.701928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.701955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.701985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.702017] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.702044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.702075] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.702103] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.702121] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.702143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.702166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.702224] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.702243] [drm:intel_power_well_enable [i915]] enabling display
>[  734.702260] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.702296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.702316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.702336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.702355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.702373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.702393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.702414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.702434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.702454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.702472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.702496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.702523] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.702552] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.704601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.704623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.704641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.704661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.706271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.706291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.706309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.707873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.707893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.709779] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.713133] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.713215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.713248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.713289] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.713393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.713436] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.713503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.763448] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.763488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.763541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.763583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.763618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.763654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.763690] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.763842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.763893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.763942] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.763988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.764001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.764043] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.764050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.764082] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.764110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.764140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.764168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.764203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.764230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.764262] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.764289] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.764318] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.764351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.764388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.764493] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.764541] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.764627] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.781609] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.781647] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.781686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.781805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.781856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.781905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.781953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.781996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.782032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.782064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.782097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.782144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.782164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.782199] [drm:intel_power_well_disable [i915]] disabling display
>[  734.782226] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.782246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.782268] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.782289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.782307] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.782628] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.782650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.782673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.782740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.782770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.782803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.782834] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.782863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.782891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.782919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.782945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.782955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.782981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.782988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.783015] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.783041] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.783068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.783093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.783124] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.783150] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.783181] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.783209] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.783235] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.783268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.783302] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.783394] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.783425] [drm:intel_power_well_enable [i915]] enabling display
>[  734.783456] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.783509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.783541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.783562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.783581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.783599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.783618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.783641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.783668] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.783697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.783752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.783780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.783813] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.783842] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.785905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.785926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.785943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.785962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.787527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.787549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.787569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.789114] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.789134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.790998] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.794291] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.794383] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.794402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.794427] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.794517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.794555] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.794616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.844635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.844675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.844793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.844853] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.844897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.844948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.844995] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.845044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.845088] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.845132] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.845175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.845187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.845229] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.845239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.845284] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.845324] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.845367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.845407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.845457] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.845497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.845542] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.845568] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.845595] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.845625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.845658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.845785] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.845823] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.845886] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.862599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.862636] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.862676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.862789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.862994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.863026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.863056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.863088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.863123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.863155] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.863187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.863225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.863264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.863320] [drm:intel_power_well_disable [i915]] disabling display
>[  734.863366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.863407] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.863449] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.863491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.863525] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.864298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.864320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.864342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.864365] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.864383] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.864407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.864431] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.864454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.864478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.864501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.864524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.864529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.864552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.864556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.864580] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.864603] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.864627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.864649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.864673] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.864756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.864789] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.864818] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.864846] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.864880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.864913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.865000] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.865020] [drm:intel_power_well_enable [i915]] enabling display
>[  734.865038] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.865073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.865094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.865118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.865148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.865171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.865192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.865215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.865241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.865269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.865294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.865319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.865346] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.865372] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.867416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.867438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.867456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.867475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.869049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.869069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.869086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.870674] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.870708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.872568] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.875935] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.876003] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.876037] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.876073] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.876155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.876182] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.876223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.926224] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.926264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.926304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.926346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.926380] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.926416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.926456] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.926498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.926547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.926597] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.926629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.926637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.926665] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.926671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.926777] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.926823] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.926865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.926906] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.926955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.926997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.927043] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.927086] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.927131] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.927185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.927218] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.927303] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  734.927329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  734.927384] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  734.944411] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  734.944449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  734.944489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.944522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.944553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.944582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.944610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.944641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.944675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.944781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.944832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.944879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.945142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.945195] [drm:intel_power_well_disable [i915]] disabling display
>[  734.945236] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  734.945269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.945305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.945337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.945367] [drm:intel_power_well_disable [i915]] disabling always-on
>[  734.945892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  734.945913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  734.945937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  734.945964] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  734.945987] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  734.946011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  734.946035] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  734.946059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  734.946082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  734.946105] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  734.946128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  734.946133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.946156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  734.946160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  734.946183] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  734.946207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  734.946230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  734.946253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  734.946276] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  734.946299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  734.946323] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  734.946347] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  734.946370] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  734.946395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  734.946420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  734.946474] [drm:intel_power_well_enable [i915]] enabling always-on
>[  734.946494] [drm:intel_power_well_enable [i915]] enabling display
>[  734.946514] [drm:hsw_set_power_well [i915]] Enabling power well
>[  734.946550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  734.946574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  734.946598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  734.946621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  734.946645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  734.946668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  734.946747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  734.946784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  734.946820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  734.946848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  734.946880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  734.946916] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  734.946945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  734.949010] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  734.949031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  734.949049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.949069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  734.950627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  734.950647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  734.950665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  734.952257] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  734.952278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  734.954157] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  734.957262] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  734.957340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  734.957373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  734.957415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  734.957561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  734.957626] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  734.957794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.007593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.007633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.007673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.007792] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.007839] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.007893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.008113] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.008146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.008178] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.008207] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.008235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.008243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.008270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.008277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.008305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.008333] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.008360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.008388] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.008420] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.008448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.008477] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.008504] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.008543] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.008585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.008628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.008800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.008862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.009205] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.025378] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.025415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.025459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.025500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.025540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.025575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.025615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.025652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.025695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.025815] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.025873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.025919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.025951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.026005] [drm:intel_power_well_disable [i915]] disabling display
>[  735.026065] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.026109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.026152] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.026196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.026230] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.026640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.026676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.026750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.026778] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.026800] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.026824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.026848] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.026869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.026892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.026911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.026932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.026937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.026958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.026962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.026981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.027002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.027020] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.027039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.027061] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.027080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.027099] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.027126] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.027155] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.027188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.027223] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.027290] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.027311] [drm:intel_power_well_enable [i915]] enabling display
>[  735.027329] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.027364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.027389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.027416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.027442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.027468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.027493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.027522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.027550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.027578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.027604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.027629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.027656] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.027688] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.029767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.029790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.029809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.029828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.031390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.031411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.031429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.032992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.033014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.034886] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.038219] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.038322] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.038355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.038397] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.038502] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.038550] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.038619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.088559] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.088599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.088640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.088681] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.088805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.088851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.088888] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.088920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.088962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.089001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.089042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.089050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.089089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.089096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.089138] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.089179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.089220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.089259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.089300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.089339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.089382] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.089422] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.089464] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.089505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.089577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.089697] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.089792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.089890] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.106923] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.106959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.106999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.107031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.107062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.107091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.107120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.107151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.107184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.107215] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.107246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.107274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.107301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.107353] [drm:intel_power_well_disable [i915]] disabling display
>[  735.107388] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.107406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.107426] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.107444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.107461] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.107889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.107916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.107943] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.107972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.107998] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.108026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.108063] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.108095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.108126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.108155] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.108183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.108190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.108218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.108224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.108253] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.108281] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.108308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.108336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.108367] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.108395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.108424] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.108451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.108479] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.108511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.108544] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.108630] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.108660] [drm:intel_power_well_enable [i915]] enabling display
>[  735.108706] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.108759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.108789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.108819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.108847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.108875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.108904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.108936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.108968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.109000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.109028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.109048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.109070] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.109091] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.111132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.111154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.111172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.111192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.112785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.112805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.112824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.114382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.114403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.116278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.119617] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.119743] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.119778] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.119890] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.119982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.120021] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.120081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.169975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.170017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.170061] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.170108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.170148] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.170190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.170232] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.170273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.170320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.170372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.170413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.170421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.170451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.170458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.170488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.170516] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.170544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.170571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.170605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.170633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.170663] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.170774] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.170802] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.170833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.170866] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.170967] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.170994] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.171049] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.188065] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.188103] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.188143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.188184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.188224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.188259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.188299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.188337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.188379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.188421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.188462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.188501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.188540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.188596] [drm:intel_power_well_disable [i915]] disabling display
>[  735.188642] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.188683] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.188802] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.188857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.188903] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.189482] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.189505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.189530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.189558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.189583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.189609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.189635] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.189661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.189722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.189752] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.189780] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.189789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.189816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.189824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.189852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.189882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.190044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.190063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.190085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.190104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.190125] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.190143] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.190161] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.190183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.190206] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.190267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.190286] [drm:intel_power_well_enable [i915]] enabling display
>[  735.190305] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.190342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.190369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.190395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.190421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.190447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.190472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.190501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.190529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.190556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.190582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.190608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.190635] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.190661] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.192751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.192772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.192791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.192811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.194381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.194401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.194419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.195982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.196003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.197866] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.201181] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.201250] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.201283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.201325] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.201415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.201453] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.201514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.251500] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.251541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.251581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.251622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.251656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.251765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.251813] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.251866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.252081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.252113] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.252143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.252152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.252181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.252187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.252219] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.252247] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.252277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.252315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.252357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.252400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.252421] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.252441] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.252459] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.252482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.252505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.252576] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.252602] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.252656] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.269667] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.269734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.269788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.269834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.269866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.269897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.269927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.269958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.270000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.270042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.270084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.270123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.270162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.270219] [drm:intel_power_well_disable [i915]] disabling display
>[  735.270265] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.270306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.270348] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.270390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.270423] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.271206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.271239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.271271] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.271306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.271335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.271366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.271396] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.271425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.271455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.271483] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.271511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.271518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.271544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.271550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.271578] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.271605] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.271629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.271655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.271727] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.271757] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.271792] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.271822] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.271853] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.271886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.271922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.272251] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.272279] [drm:intel_power_well_enable [i915]] enabling display
>[  735.272296] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.272330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.272350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.272369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.272387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.272404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.272422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.272442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.272460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.272479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.272495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.272511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.272532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.272555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.274615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.274638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.274657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.274719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.276383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.276410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.276429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.277989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.278011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.279874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.283188] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.283240] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.283260] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.283285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.283377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.283415] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.283476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.333510] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.333551] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.333590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.333631] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.333664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.333776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.333829] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.333881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.333933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.333983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.334030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.334045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.334089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.334404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.334432] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.334451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.334468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.334486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.334506] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.334523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.334541] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.334558] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.334574] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.334593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.334615] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.334731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.334776] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.335031] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.352079] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.352117] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.352157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.352190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.352229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.352267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.352307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.352345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.352388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.352430] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.352472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.352511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.352549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.352605] [drm:intel_power_well_disable [i915]] disabling display
>[  735.352651] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.352758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.352793] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.352830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.352863] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.353462] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.353484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.353506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.353532] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.353555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.353579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.353602] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.353626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.353650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.353682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.353753] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.353763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.353795] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.353804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.353838] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.353869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.353901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.353931] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.353964] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.353995] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.354028] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.354288] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.354318] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.354350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.354383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.354467] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.354496] [drm:intel_power_well_enable [i915]] enabling display
>[  735.354524] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.354573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.354603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.354631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.354669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.354735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.354768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.354803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.354837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.354870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.354901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.354930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.354965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.355168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.357256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.357278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.357301] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.357325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.358900] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.358922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.358941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.360502] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.360523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.362395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.365685] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.365778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.365810] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.365851] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.365966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.366003] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.366055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.416049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.416090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.416129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.416171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.416204] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.416241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.416283] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.416321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.416365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.416406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.416446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.416454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.416493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.416500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.416541] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.416582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.416623] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.416662] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.416790] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.416840] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.416894] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.416940] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.416989] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.417045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.417100] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.417243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.417281] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.417522] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.433555] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.433592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.433632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.433665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.433771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.433818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.433866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.433911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.433964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.434014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.434065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.434106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.434149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.434232] [drm:intel_power_well_disable [i915]] disabling display
>[  735.434294] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.434343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.434395] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.434445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.434491] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.435001] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.435025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.435050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.435077] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.435100] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.435124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.435148] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.435171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.435195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.435218] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.435241] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.435245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.435268] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.435272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.435296] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.435320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.435352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.435374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.435407] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.435426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.435445] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.435462] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.435479] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.435499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.435520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.435574] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.435591] [drm:intel_power_well_enable [i915]] enabling display
>[  735.435608] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.435639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.435662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.435740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.435770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.435801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.435830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.435863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.435896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.435929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.435956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.435985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.436020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.436050] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.438107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.438128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.438146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.438165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.439755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.439784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.439802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.441365] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.441388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.443265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.446564] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.446649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.446757] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.446818] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.446927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.446956] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.447001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.496869] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.496913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.496956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.497003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.497044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.497086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.497127] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.497168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.497210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.497250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.497290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.497298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.497337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.497344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.497386] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.497426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.497467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.497508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.497549] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.497589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.497631] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.497672] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.497802] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.497864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.497921] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.498087] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.498127] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.498194] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.515215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.515252] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.515292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.515325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.515357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.515386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.515415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.515446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.515480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.515511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.515543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.515571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.515599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.515652] [drm:intel_power_well_disable [i915]] disabling display
>[  735.515776] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.515829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.515883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.515938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.515987] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.516758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.516779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.516802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.516825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.516844] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.516863] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.516883] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.516902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.516920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.516938] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.516954] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.516959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.516975] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.516979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.516996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.517012] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.517028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.517044] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.517063] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.517080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.517098] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.517114] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.517129] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.517149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.517170] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.517222] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.517239] [drm:intel_power_well_enable [i915]] enabling display
>[  735.517255] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.517286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.517304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.517321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.517344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.517366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.517389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.517414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.517439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.517464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.517487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.517510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.517535] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.517558] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.519625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.519657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.519741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.519776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.521337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.521357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.521375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.522929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.522950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.524814] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.528149] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.528260] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.528310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.528355] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.528494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.528560] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.528660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.578523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.578568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.578611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.578658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.578777] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.578829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.578885] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.578932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.579232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.579282] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.579323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.579331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.579361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.579367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.579396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.579424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.579451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.579478] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.579511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.579539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.579568] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.579595] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.579622] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.579654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.579744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.580123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.580163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.580228] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.596562] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.596599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.596639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.596737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.596790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.596842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.596892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.596941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.596995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.597047] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.597098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.597144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.597175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.597238] [drm:intel_power_well_disable [i915]] disabling display
>[  735.597268] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.597295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.597322] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.597349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.597371] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.597741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.597763] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.597785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.597808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.597826] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.597846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.597866] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.597884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.597903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.597920] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.597937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.597942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.597958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.597961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.597978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.598006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.598023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.598050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.598082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.598110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.598141] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.598169] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.598200] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.598232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.598266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.598357] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.598387] [drm:intel_power_well_enable [i915]] enabling display
>[  735.598417] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.598468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.598499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.598530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.598560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.598590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.598620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.598653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.598720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.598755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.598785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.598816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.598851] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.598883] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.600956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.600977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.600996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.601015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.602567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.602592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.602616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.604192] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.604214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.606185] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.609491] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.609554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.609573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.609599] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.609728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.609772] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.609837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.659843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.659883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.659923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.659965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.659998] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.660034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.660069] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.660103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.660136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.660167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.660197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.660206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.660235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.660241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.660271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.660301] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.660330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.660359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.660394] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.660423] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.660459] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.660500] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.660541] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.660584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.660623] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.660758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.660802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.660884] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.677914] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.677952] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.677996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.678037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.678077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.678111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.678151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.678188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.678231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.678273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.678315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.678354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.678392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.678449] [drm:intel_power_well_disable [i915]] disabling display
>[  735.678494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.678535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.678577] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.678623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.678673] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.679442] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.679464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.679486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.679513] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.679536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.679560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.679584] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.679608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.679632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.679664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.679723] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.679732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.679766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.679774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.679806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.679834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.679865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.679893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.679926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.680184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.680215] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.680241] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.680268] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.680298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.680331] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.680413] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.680441] [drm:intel_power_well_enable [i915]] enabling display
>[  735.680468] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.680515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.680544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.680569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.680596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.680621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.680659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.680719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.680753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.680786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.680813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.680844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.680876] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.680907] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.683176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.683206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.683227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.683247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.684832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.684856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.684879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.686437] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.686459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.688327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.691672] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.691762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.691801] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.691853] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.691969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.692013] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.692081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.742020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.742061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.742100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.742142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.742176] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.742213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.742249] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.742283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.742316] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.742347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.742377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.742385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.742414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.742421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.742451] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.742481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.742512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.742542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.742577] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.742607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.742637] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.742746] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.742789] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.742844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.742900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.743055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.743113] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.743210] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.759537] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.759573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.759614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.759648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.759759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.759805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.759855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.759901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.759955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.760239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.760274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.760303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.760332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.760383] [drm:intel_power_well_disable [i915]] disabling display
>[  735.760424] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.760456] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.760490] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.760522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.760551] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.761103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.761135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.761168] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.761203] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.761226] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.761247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.761270] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.761294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.761318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.761341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.761364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.761369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.761391] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.761395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.761429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.761451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.761473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.761498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.761519] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.761536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.761554] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.761571] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.761587] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.761607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.761628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.761749] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.761780] [drm:intel_power_well_enable [i915]] enabling display
>[  735.761811] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.761863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.761895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.761924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.761954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.761981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.762013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.762045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.762077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.762109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.762135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.762162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.762196] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.762224] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.764390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.764411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.764430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.764449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.766013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.766033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.766051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.767627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.767650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.769537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.772881] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.772976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.773016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.773069] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.773155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.773183] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.773225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.823190] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.823228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.823266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.823305] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.823343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.823384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.823424] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.823463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.823503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.823542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.823581] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.823588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.823627] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.823634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.823749] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.823805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.823852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.823900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.823950] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.823998] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.824051] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.824095] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.824142] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.824198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.824253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.824414] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.824456] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.824520] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.841565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.841603] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.841643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.841756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.841808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.841857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.841905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.841954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.842004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.842056] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.842107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.842149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.842192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.842275] [drm:intel_power_well_disable [i915]] disabling display
>[  735.842338] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.842386] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.842437] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.842487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.842534] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.843044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.843067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.843098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.843121] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.843139] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.843159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.843179] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.843198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.843216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.843233] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.843255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.843260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.843283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.843287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.843311] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.843334] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.843358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.843380] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.843404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.843427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.843451] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.843472] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.843495] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.843519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.843545] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.843599] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.843619] [drm:intel_power_well_enable [i915]] enabling display
>[  735.843649] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.843733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.843765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.843798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.843827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.843858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.843888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.843922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.843955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.843990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.844017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.844047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.844082] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.844112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.846181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.846201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.846220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.846239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.847823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.847843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.847862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.849411] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.849432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.851298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.854615] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.854750] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.854919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.854965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.855072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.855100] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.855141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.904949] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.904988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.905028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.905069] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.905102] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.905138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.905174] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.905207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.905241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.905273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.905303] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.905310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.905340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.905347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.905377] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.905418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.905460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.905501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.905542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.905582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.905624] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.905661] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.905772] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.905825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.905881] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.906393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.906433] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.906498] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  735.922510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  735.922547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  735.922586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.922619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.922650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.922755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.922801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.922852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.922907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.922959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.923260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.923291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.923320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.923372] [drm:intel_power_well_disable [i915]] disabling display
>[  735.923412] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  735.923444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.923478] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.923519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.923552] [drm:intel_power_well_disable [i915]] disabling always-on
>[  735.924115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.924138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.924160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.924184] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.924202] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.924222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.924246] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.924269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.924302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.924322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.924352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.924356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.924373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.924377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.924394] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.924417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.924440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.924464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.924487] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.924510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.924534] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.924558] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.924581] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.924606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.924632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.924755] [drm:intel_power_well_enable [i915]] enabling always-on
>[  735.925057] [drm:intel_power_well_enable [i915]] enabling display
>[  735.925089] [drm:hsw_set_power_well [i915]] Enabling power well
>[  735.925142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  735.925175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  735.925204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  735.925233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  735.925260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  735.925291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  735.925324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  735.925356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  735.925388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.925414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  735.925442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  735.925472] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  735.925503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  735.927579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  735.927602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  735.927622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.927643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  735.929250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  735.929270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  735.929288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  735.930873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  735.930896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  735.932772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  735.936058] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  735.936141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  735.936160] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  735.936186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  735.936268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  735.936296] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  735.936337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  735.986406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  735.986447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  735.986487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  735.986528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  735.986562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  735.986598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  735.986634] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  735.986744] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  735.986793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  735.986843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  735.986886] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  735.986901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.986945] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  735.986957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  735.987005] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  735.987047] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  735.987091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  735.987143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  735.987189] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  735.987231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  735.987276] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  735.987317] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  735.987356] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  735.987402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  735.987450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  735.987593] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  735.987647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  735.987771] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.004800] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.004838] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.004878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.004912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.004942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.004972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.005001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.005033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.005067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.005107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.005148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.005188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.005226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.005283] [drm:intel_power_well_disable [i915]] disabling display
>[  736.005329] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.005370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.005412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.005464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.005491] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.006171] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.006204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.006236] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.006272] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.006300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.006332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.006363] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.006392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.006421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.006449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.006473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.006480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.006506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.006513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.006540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.006567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.006591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.006617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.006659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.006712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.006746] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.006779] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.006811] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.006846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.006882] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.006973] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.007190] [drm:intel_power_well_enable [i915]] enabling display
>[  736.007211] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.007250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.007276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.007302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.007327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.007350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.007375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.007402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.007429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.007456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.007481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.007506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.007533] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.007558] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.009585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.009608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.009628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.009690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.011388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.011409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.011427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.012977] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.013000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.014855] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.018175] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.018238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.018271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.018314] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.018424] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.018471] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.018535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.068494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.068535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.068574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.068616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.068650] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.068764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.068819] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.068873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.068924] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.068976] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.069321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.069333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.069380] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.069391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.069440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.069487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.069533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.069579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.069626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.069715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.069764] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.069814] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.069862] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.069916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.069971] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.070264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.070290] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.070343] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.087382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.087420] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.087461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.087495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.087526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.087555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.087585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.087616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.087731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.087791] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.087845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.087892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.087940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.088340] [drm:intel_power_well_disable [i915]] disabling display
>[  736.088383] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.088420] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.088445] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.088470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.088490] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.088958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.088980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.089002] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.089025] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.089043] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.089063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.089083] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.089102] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.089120] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.089137] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.089154] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.089159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.089175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.089179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.089196] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.089212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.089229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.089244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.089264] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.089280] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.089297] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.089313] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.089329] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.089348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.089369] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.089432] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.089458] [drm:intel_power_well_enable [i915]] enabling display
>[  736.089476] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.089507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.089526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.089543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.089560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.089577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.089595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.089614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.089644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.089709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.089738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.089768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.089804] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.089836] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.091908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.091929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.091947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.091966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.093518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.093539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.093560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.095107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.095129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.096999] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.100329] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.100380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.100411] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.100452] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.100562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.100607] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.100699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.150642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.150714] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.150754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.150796] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.150830] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.150866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.150903] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.150937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.150971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.151003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.151033] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.151041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.151070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.151077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.151107] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.151137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.151166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.151195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.151230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.151259] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.151290] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.151319] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.151348] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.151382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.151419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.151526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.151569] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.151634] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.168724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.168761] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.168801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.168840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.168881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.168917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.168956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.168995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.169038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.169084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.169123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.169160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.169196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.169249] [drm:intel_power_well_disable [i915]] disabling display
>[  736.169292] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.169331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.169370] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.169410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.169441] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.170128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.170162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.170198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.170235] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.170266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.170300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.170334] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.170366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.170397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.170429] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.170458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.170466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.170495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.170502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.170532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.170563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.170593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.170623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.170669] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.170699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.170728] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.170758] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.170788] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.170822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.170856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.170948] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.170978] [drm:intel_power_well_enable [i915]] enabling display
>[  736.171010] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.171061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.171092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.171124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.171154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.171185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.171216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.171250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.171283] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.171316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.171345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.171373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.171407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.171438] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.173508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.173530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.173549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.173568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.175169] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.175189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.175207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.176805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.176826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.178694] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.182030] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.182132] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.182172] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.182223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.182326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.182364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.182413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.232364] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.232403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.232442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.232483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.232515] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.232552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.232588] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.232622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.232730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.232777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.232819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.232832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.232876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.232888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.232934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.232976] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.233019] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.233060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.233112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.233159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.233209] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.233255] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.233300] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.233353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.233408] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.233526] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.233553] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.233609] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.250618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.250677] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.250717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.250751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.250782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.250812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.250841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.250872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.250906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.250938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.250969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.250997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.251024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.251077] [drm:intel_power_well_disable [i915]] disabling display
>[  736.251117] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.251148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.251181] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.251212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.251241] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.251764] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.251821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.251855] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.251892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.251922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.251957] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.251989] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.252021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.252052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.252083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.252111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.252119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.252148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.252155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.252184] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.252204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.252227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.252256] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.252281] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.252300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.252319] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.252337] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.252354] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.252376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.252399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.252460] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.252478] [drm:intel_power_well_enable [i915]] enabling display
>[  736.252498] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.252538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.252564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.252591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.252614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.252670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.252702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.252736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.252768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.252799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.252826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.252852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.252884] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.252914] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.254989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.255013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.255036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.255060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.256760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.256781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.256800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.258347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.258370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.260233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.263549] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.263616] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.263740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.263811] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.263978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.264007] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.264048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.313883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.313923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.313963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.314004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.314038] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.314074] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.314110] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.314143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.314179] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.314220] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.314260] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.314268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.314309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.314316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.314357] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.314398] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.314439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.314480] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.314521] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.314561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.314603] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.314644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.314767] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.314831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.314889] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.315365] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.315403] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.315477] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.332502] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.332545] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.332589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.332630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.332753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.332810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.332861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.332914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.332969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.333190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.333224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.333263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.333302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.333357] [drm:intel_power_well_disable [i915]] disabling display
>[  736.333403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.333444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.333482] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.333503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.333521] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.333975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.334001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.334027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.334056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.334090] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.334114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.334138] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.334161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.334185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.334208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.334231] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.334235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.334258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.334262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.334286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.334310] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.334333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.334356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.334379] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.334402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.334426] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.334447] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.334470] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.334495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.334520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.334576] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.334595] [drm:intel_power_well_enable [i915]] enabling display
>[  736.334615] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.334712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.334747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.334781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.334814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.334846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.334878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.334914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.334948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.334982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.335012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.335043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.335079] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.335112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.337214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.337235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.337253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.337273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.338844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.338868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.338888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.340442] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.340463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.342325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.345620] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.345707] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.345740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.345766] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.345873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.345911] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.345971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.395967] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.396007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.396047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.396089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.396123] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.396159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.396195] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.396229] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.396262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.396293] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.396324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.396331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.396361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.396367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.396398] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.396428] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.396457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.396496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.396538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.396578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.396620] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.396741] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.396790] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.396841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.396893] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.397029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.397056] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.397111] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.414183] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.414220] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.414260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.414293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.414324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.414353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.414391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.414431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.414473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.414515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.414557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.414596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.414634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.414787] [drm:intel_power_well_disable [i915]] disabling display
>[  736.414852] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.414909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.414966] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.415020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.415068] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.415620] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.415690] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.415727] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.415765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.415798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.415830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.415862] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.415895] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.415928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.415958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.415987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.415996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.416025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.416032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.416062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.416092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.416121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.416150] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.416180] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.416209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.416241] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.416270] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.416297] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.416330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.416364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.416462] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.416491] [drm:intel_power_well_enable [i915]] enabling display
>[  736.416519] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.416567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.416596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.416636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.416696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.416725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.416757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.416793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.416827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.416861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.416891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.416922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.416957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.416989] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.419054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.419075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.419094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.419113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.420679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.420699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.420717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.422281] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.422304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.424168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.427475] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.427555] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.427595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.427724] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.427847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.427903] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.427988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.477829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.477870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.477910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.477952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.477985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.478021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.478057] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.478094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.478135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.478176] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.478217] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.478225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.478265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.478272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.478314] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.478355] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.478396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.478436] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.478477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.478518] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.478560] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.478601] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.478642] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.478769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.478824] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.479122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.479150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.479207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.496243] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.496280] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.496324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.496365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.496404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.496440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.496479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.496517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.496560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.496602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.496729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.496783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.496835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.496921] [drm:intel_power_well_disable [i915]] disabling display
>[  736.496986] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.497037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.497092] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.497144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.497234] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.497719] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.497754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.497789] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.497827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.497858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.497892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.497925] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.497956] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.497996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.498024] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.498051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.498058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.498084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.498091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.498118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.498145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.498172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.498195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.498225] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.498251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.498281] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.498305] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.498332] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.498362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.498393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.498477] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.498505] [drm:intel_power_well_enable [i915]] enabling display
>[  736.498533] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.498581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.498610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.498681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.498714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.498747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.498779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.498814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.498849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.498883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.498913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.498943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.498979] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.499011] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.501074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.501094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.501112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.501131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.502749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.502773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.502795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.504353] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.504375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.506235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.509575] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.509703] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.509740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.509784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.509874] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.509902] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.509943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.559921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.559960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.560000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.560041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.560074] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.560110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.560146] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.560179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.560212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.560243] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.560273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.560281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.560310] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.560317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.560347] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.560377] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.560406] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.560435] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.560470] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.560499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.560530] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.560559] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.560588] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.560623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.560746] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.560851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.561104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.561170] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.578196] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.578234] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.578274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.578306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.578337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.578375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.578415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.578454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.578497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.578539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.578580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.578619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.578731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.578817] [drm:intel_power_well_disable [i915]] disabling display
>[  736.579132] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.579192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.579241] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.579286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.579327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.579933] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.579964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.579995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.580028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.580054] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.580082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.580110] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.580136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.580161] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.580195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.580215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.580220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.580239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.580244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.580263] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.580282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.580301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.580320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.580343] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.580361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.580381] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.580400] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.580418] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.580441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.580465] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.580527] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.580547] [drm:intel_power_well_enable [i915]] enabling display
>[  736.580565] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.580601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.580666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.580700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.580735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.580768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.580800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.580839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.580875] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.580911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.580943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.580976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.581015] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.581050] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.583133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.583154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.583177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.583201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.584810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.584833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.584851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.586413] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.586435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.588310] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.591538] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.591576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.591600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.591695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.591889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.591918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.591959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.641841] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.641880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.641919] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.641962] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.642004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.642047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.642088] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.642129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.642170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.642210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.642250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.642258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.642298] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.642305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.642346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.642387] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.642427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.642468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.642509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.642549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.642591] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.642642] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.642728] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.642768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.642806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.643181] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.643222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.643305] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.659497] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.659535] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.659575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.659609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.659727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.659773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.659822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.659873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.660084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.660128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.660171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.660210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.660249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.660319] [drm:intel_power_well_disable [i915]] disabling display
>[  736.660356] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.660383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.660412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.660439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.660463] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.660978] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.661001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.661026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.661051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.661072] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.661095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.661117] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.661138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.661157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.661175] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.661194] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.661200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.661218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.661223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.661249] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.661275] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.661300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.661326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.661352] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.661377] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.661403] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.661429] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.661454] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.661481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.661509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.661569] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.661591] [drm:intel_power_well_enable [i915]] enabling display
>[  736.661612] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.661702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.661736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.661769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.661800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.661831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.661863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.661897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.661931] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.661964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.661994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.662023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.662058] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.662089] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.664188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.664209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.664228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.664247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.665821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.665845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.665868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.667445] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.667468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.669346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.672702] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.672782] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.672814] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.672857] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.672965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.673007] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.673069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.723041] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.723082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.723121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.723162] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.723196] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.723233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.723275] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.723316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.723358] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.723398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.723438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.723447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.723487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.723494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.723535] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.723576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.723616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.723779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.723836] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.723891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.723947] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.723997] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.724045] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.724100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.724154] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.724311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.724352] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.724418] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.741610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.741677] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.741722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.741763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.741803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.741842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.741882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.741921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.741964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.742005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.742047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.742085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.742124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.742181] [drm:intel_power_well_disable [i915]] disabling display
>[  736.742227] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.742268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.742310] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.742352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.742385] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.743197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.743219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.743242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.743265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.743284] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.743304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.743327] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.743351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.743384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.743406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.743426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.743441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.743458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.743462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.743480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.743497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.743513] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.743529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.743548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.743564] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.743582] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.743599] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.743672] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.743704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.743740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.743827] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.743857] [drm:intel_power_well_enable [i915]] enabling display
>[  736.743888] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.743938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.743967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.743996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.744023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.744051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.744078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.744111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.744143] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.744174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.744200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.744228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.744258] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.744289] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.746366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.746390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.746413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.746437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.748013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.748034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.748053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.749605] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.749661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.751515] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.754867] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.754936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.754960] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.754991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.755078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.755108] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.755149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.805113] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.805157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.805200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.805247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.805288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.805330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.805372] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.805413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.805454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.805495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.805535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.805542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.805582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.805589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.805630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.805764] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.805819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.805871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.805927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.805977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.806030] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.806079] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.806122] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.806157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.806192] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.806296] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.806336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.806572] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.822491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.822529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.822569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.822602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.822715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.822770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.822819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.822871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.822924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.823222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.823255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.823284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.823312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.823363] [drm:intel_power_well_disable [i915]] disabling display
>[  736.823403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.823434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.823473] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.823492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.823509] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.824091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.824114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.824136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.824159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.824177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.824197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.824217] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.824236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.824254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.824270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.824287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.824292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.824308] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.824312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.824328] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.824345] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.824360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.824376] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.824396] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.824412] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.824429] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.824445] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.824461] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.824485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.824511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.824567] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.824587] [drm:intel_power_well_enable [i915]] enabling display
>[  736.824617] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.824703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.824738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.824771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.824804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.824836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.824868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.824904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.824937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.824971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.825001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.825031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.825067] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.825099] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.827476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.827498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.827518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.827538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.829102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.829125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.829148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.830730] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.830752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.832702] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.835937] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.835968] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.835987] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.836013] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.836096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.836124] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.836164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.886242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.886282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.886322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.886364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.886397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.886433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.886468] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.886502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.886534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.886565] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.886595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.886670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.886722] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.886735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.886783] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.886832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.886880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.886922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.886976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.887024] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.887079] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.887109] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.887140] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.887410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.887446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.887553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.887590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.887694] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.904736] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.904773] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.904813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.904846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.904885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.904925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.904964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.905003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.905046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.905088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.905129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.905168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.905207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.905263] [drm:intel_power_well_disable [i915]] disabling display
>[  736.905309] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.905350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.905392] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.905443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.905461] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.905996] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.906021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.906045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.906070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.906090] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.906115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.906141] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.906166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.906192] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.906218] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.906242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.906248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.906272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.906277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.906303] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.906328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.906353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.906378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.906404] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.906429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.906456] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.906481] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.906506] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.906533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.906560] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.906643] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.906671] [drm:intel_power_well_enable [i915]] enabling display
>[  736.906698] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.906752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.906783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.906813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.906841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.906869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.906897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.906932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.907150] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.907172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.907190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.907209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.907232] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.907252] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.909285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.909306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.909325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.909344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.910910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.910933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.910956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.912497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.912521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.914376] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.917702] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.917744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.917768] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.917799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.917885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.917914] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.917955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.968029] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.968067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.968108] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.968153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.968193] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.968233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.968273] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.968313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.968352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.968392] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.968430] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.968438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.968477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.968483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.968524] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.968563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.968602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.968719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.968770] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.968817] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.968848] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.968876] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.968905] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.968937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.968969] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.969064] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  736.969092] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  736.969146] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  736.986176] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  736.986214] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  736.986253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.986286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.986325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.986362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.986402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.986440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.986483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.986525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.986566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.986606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.986704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.986791] [drm:intel_power_well_disable [i915]] disabling display
>[  736.987089] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  736.987129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.987168] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.987207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.987227] [drm:intel_power_well_disable [i915]] disabling always-on
>[  736.987681] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  736.987723] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  736.987750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  736.987775] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  736.987795] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  736.987816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  736.987846] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  736.987865] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  736.987883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  736.987900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  736.987916] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  736.987921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.987937] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  736.987940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  736.987963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  736.987987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  736.988011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  736.988034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  736.988057] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  736.988080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  736.988105] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  736.988126] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  736.988149] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  736.988174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  736.988199] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  736.988255] [drm:intel_power_well_enable [i915]] enabling always-on
>[  736.988274] [drm:intel_power_well_enable [i915]] enabling display
>[  736.988294] [drm:hsw_set_power_well [i915]] Enabling power well
>[  736.988330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  736.988354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  736.988378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  736.988401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  736.988422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  736.988445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  736.988470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  736.988495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  736.988520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  736.988542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  736.988565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  736.988591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  736.988668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  736.990722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  736.990743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  736.990762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.990781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  736.992339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  736.992361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  736.992380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  736.993938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  736.993958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  736.995825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  736.998482] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  736.998535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  736.998554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  736.998580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  736.998732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  736.998775] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  736.998840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.048810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.048850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.048890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.048931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.048965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.049001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.049037] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.049071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.049104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.049135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.049164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.049171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.049201] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.049207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.049237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.049267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.049296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.049326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.049361] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.049391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.049422] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.049452] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.049481] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.049516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.049554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.049736] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  737.049955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.050012] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  737.067043] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  737.067080] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.067121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.067160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.067200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.067240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.067280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.067331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.067374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.067416] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.067457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.067496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.067534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.067591] [drm:intel_power_well_disable [i915]] disabling display
>[  737.067726] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.068003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.068044] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.068081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.068116] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.068485] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.068509] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.068533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.068560] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.068583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.068664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.068697] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.068727] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.068758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.068785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.068812] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.068823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.068849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.068857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.068887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.069054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.069073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.069092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.069114] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.069133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.069152] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.069170] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.069188] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.069210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.069234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.069293] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.069315] [drm:intel_power_well_enable [i915]] enabling display
>[  737.069338] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.069377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.069403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.069434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.069467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.069489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.069510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.069533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.069553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.069574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.069600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.069653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.069686] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  737.069715] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.071949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.071969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.071987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.072006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.073602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.073641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.073660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.075227] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.075247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.077130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.080445] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  737.080499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.080522] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  737.080554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.080704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.080748] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.080812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.130793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.130839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.130894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.130940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.130972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.131006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.131040] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.131079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.131119] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.131158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.131197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.131204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.131243] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.131250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.131290] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.131329] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.131369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.131408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.131448] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.131486] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.131530] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.131558] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.131585] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.131664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.131709] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.132052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  737.132090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.132162] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  737.149216] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  737.149254] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.149294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.149327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.149359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.149397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.149437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.149476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.149519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.149561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.149603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.149722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.149780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.149870] [drm:intel_power_well_disable [i915]] disabling display
>[  737.149912] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.149947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.149983] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.150017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.150048] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.150472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.150496] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.150520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.150547] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.150570] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.150604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.150677] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.150711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.150746] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.150778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.150809] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.150817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.150847] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.150855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.150885] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.150917] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.150947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.150974] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.151006] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.151036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.151067] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.151096] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.151125] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.151159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.151193] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.151284] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.151314] [drm:intel_power_well_enable [i915]] enabling display
>[  737.151345] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.151397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.151428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.151459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.151489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.151518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.151549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.151583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.151643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.151675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.151706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.151737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.151772] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  737.151804] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.153869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.153891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.153914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.153938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.155506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.155528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.155547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.157124] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.157145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.159026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.162259] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  737.162291] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.162310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  737.162346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.162416] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.162443] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.162483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.212589] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.212664] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.212704] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.212746] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.212779] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.212815] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.212851] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.212885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.212918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.212950] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.212981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.212988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.213018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.213025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.213055] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.213085] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.213115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.213144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.213179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.213220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.213263] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.213304] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.213333] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.213366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.213402] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.213503] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  737.213543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.213663] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  737.230699] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  737.230737] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.230777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.230810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.230841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.230870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.230898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.230929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.230970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.231012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.231054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.231093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.231131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.231188] [drm:intel_power_well_disable [i915]] disabling display
>[  737.231234] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.231275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.231317] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.231359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.231393] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.232284] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.232306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.232328] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.232362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.232386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.232420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.232443] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.232467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.232491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.232514] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.232537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.232542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.232565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.232569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.232603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.232672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.232708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.232741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.232777] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.232810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.232844] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.232875] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.232906] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.232942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.232977] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.233068] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.233099] [drm:intel_power_well_enable [i915]] enabling display
>[  737.233130] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.233182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.233214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.233245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.233275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.233305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.233336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.233371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.233404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.233436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.233466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.233495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.233530] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  737.233561] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.235650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.235672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.235691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.235711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.237276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.237296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.237314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.238867] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.238888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.240755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.244004] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  737.244072] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.244092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  737.244118] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.244209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.244247] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.244308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.294337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.294377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.294417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.294458] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.294492] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.294528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.294564] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.294597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.294709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.294753] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.294798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.294813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.294857] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.294868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.294915] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.294957] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.295003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.295037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.295079] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.295105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.295131] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.295157] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.295181] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.295211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.295243] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.295339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  737.295375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.295448] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  737.312466] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  737.312504] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.312544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.312577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.312688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.312865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.312897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.312930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.312967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.313000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.313031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.313060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.313088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.313141] [drm:intel_power_well_disable [i915]] disabling display
>[  737.313183] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.313214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.313248] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.313281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.313310] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.313804] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.313828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.313860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.313883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.313902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.313925] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.313949] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.313973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.313997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.314019] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.314043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.314047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.314070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.314074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.314098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.314121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.314145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.314168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.314191] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.314214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.314238] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.314259] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.314283] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.314308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.314333] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.314387] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.314407] [drm:intel_power_well_enable [i915]] enabling display
>[  737.314427] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.314463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.314486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.314510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.314533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.314554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.314578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.314651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.314675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.314698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.314723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.314750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.314778] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  737.314809] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.316865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.316889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.316919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.316938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.318489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.318515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.318539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.320110] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.320132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.322113] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.325459] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  737.325549] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.325581] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  737.325704] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.325932] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.325960] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.325998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.375781] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.375821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.375860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.375902] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.375936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.375972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.376008] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.376042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.376074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.376110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.376150] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.376158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.376198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.376205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.376252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.376301] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.376334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.376362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.376396] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.376433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.376474] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.376510] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.376549] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.376590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.376707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.377002] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  737.377030] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.377088] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  737.394134] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  737.394171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.394212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.394245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.394277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.394306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.394336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.394367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.394401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.394433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.394464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.394493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.394521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.394574] [drm:intel_power_well_disable [i915]] disabling display
>[  737.394696] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.394747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.395020] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.395068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.395088] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.395480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.395501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.395523] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.395546] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.395569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.395650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.395682] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.395712] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.395742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.395769] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.395795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.395804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.395830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.395838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.395867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.396034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.396053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.396071] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.396093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.396112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.396133] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.396151] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.396170] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.396195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.396224] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.396285] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.396306] [drm:intel_power_well_enable [i915]] enabling display
>[  737.396328] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.396367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.396393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.396420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.396445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.396472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.396498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.396525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.396552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.396584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.396643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.396672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.396706] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  737.396736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.398963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.398986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.399009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.399033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.400592] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.400636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.400655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.402215] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.402236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.404126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.407380] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  737.407443] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.407467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  737.407498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.407602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.407695] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.407875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.457746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.457787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.457827] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.457869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.457902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.457939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.457975] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.458009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.458043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.458075] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.458114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.458122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.458163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.458169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.458211] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.458252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.458293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.458334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.458375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.458415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.458464] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.458500] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.458536] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.458574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.458707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.459096] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  737.459136] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.459212] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  737.476219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  737.476256] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.476296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.476330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.476361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.476391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.476420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.476452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.476486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.476518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.476549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.476578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.476678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.476764] [drm:intel_power_well_disable [i915]] disabling display
>[  737.476954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.476978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.477001] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.477023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.477042] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.477347] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.477368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.477392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.477416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.477436] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.477457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.477479] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.477504] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.477530] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.477555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.477580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.477623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.477653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.477661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.477691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.477719] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.477746] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.477774] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.477805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.477832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.477862] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.477889] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.477916] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.477951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.478183] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.478244] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.478266] [drm:intel_power_well_enable [i915]] enabling display
>[  737.478287] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.478327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.478353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.478379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.478404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.478431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.478456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.478484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.478512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.478540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.478565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.478623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.478658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  737.478688] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.480891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.480911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.480930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.480949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.482502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.482524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.482543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.484107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.484128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.486074] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.489299] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  737.489339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.489359] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  737.489384] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.489474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.489513] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.489584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.539569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.539639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.539679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.539724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.539762] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.539803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.539843] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  737.539883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  737.539922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.539961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.539999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.540007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.540045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.540052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.540092] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.540131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.540170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.540208] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.540253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.540285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.540316] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.540343] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  737.540369] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  737.540399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.540432] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  737.540528] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  737.540564] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.540689] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  737.556729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  737.556767] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.556807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.556839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.556870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.556899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.556928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.556959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.556993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.557024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.557054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.557082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.557109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.557162] [drm:intel_power_well_disable [i915]] disabling display
>[  737.557201] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.557231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.557264] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.557295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.557324] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.557519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.557575] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.557660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.557688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.557721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.557748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.557778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.557806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.557838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.557872] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.557905] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.557938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.557964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.557993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.558034] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  737.558067] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.558400] [drm:drm_mode_addfb2] [FB:77]
>[  737.558449] [drm:drm_mode_addfb2] [FB:78]
>[  737.587951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  737.588059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  737.588134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  737.588204] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  737.588216] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  737.588275] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.588298] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.588322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.588346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.588364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.588385] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.588405] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.588424] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.588443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.588461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.588477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.588482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.588498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.588502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.588519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.588536] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.588553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.588569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.588644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.588674] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.588704] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  737.588734] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.588766] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.588800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.588836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.592166] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.592187] [drm:intel_power_well_enable [i915]] enabling display
>[  737.592207] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.592247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.592272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.592297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.592319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.592343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.592366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.592393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.592419] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.592444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.592468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.592492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.592518] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  737.592542] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.594658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.594680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.594699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.594718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.596290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.596310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.596328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.597884] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.597905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.599776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.603116] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  737.603215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.603255] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  737.603307] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.619990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.620041] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.620108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.636903] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.636941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.636978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.637017] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.637049] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.637083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.637117] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.637149] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.637180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.637209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.637237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.637245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.637272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.637279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.637307] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.637335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.637363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.637390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.637428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.637467] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.637508] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.637547] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.637586] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.637703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.637757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.637915] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  737.637980] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.638091] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  737.655135] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  737.655173] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.655214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.655248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.655279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.655309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.655338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.655376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.655419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.655461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.655503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.655542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.655581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.655695] [drm:intel_power_well_disable [i915]] disabling display
>[  737.655737] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.655773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.655810] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.655845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.655875] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.656091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.656122] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.656155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.656192] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.656220] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.656252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.656281] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.656311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.656340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.656369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.656394] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.656402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.656428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.656435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.656464] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.656489] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.656517] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.656542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.656574] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.656628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.656656] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.656686] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.656713] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.656747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.656782] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.656876] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.656906] [drm:intel_power_well_enable [i915]] enabling display
>[  737.656935] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.656985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.657013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.657043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.657069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.657097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.657124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.657156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.657189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.657220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.657246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.657274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.657304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  737.657335] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.659411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.659434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.659453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.659473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.661051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.661072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.661090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.662679] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.662700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.664559] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.667881] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  737.667951] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.667971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  737.667997] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.668077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.668106] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.668146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.718216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.718260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.718302] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.718349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.718389] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.718431] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.718473] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.718514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.718557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.718678] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.718738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.718752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.718802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.718814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.718865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.718914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.718963] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.719010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.719064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.719351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.719383] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.719411] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.719438] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.719470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.719503] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.719638] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  737.719681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.719834] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  737.736870] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  737.736907] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.736947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.736980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.737011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.737049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.737089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.737128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.737170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.737212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.737254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.737293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.737331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.737387] [drm:intel_power_well_disable [i915]] disabling display
>[  737.737425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.737448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.737482] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.737504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.737531] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.738053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.738087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.738131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.738165] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.738194] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.738225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.738255] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.738285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.738314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.738342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.738369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.738376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.738403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.738409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.738437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.738464] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.738489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.738515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.738545] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.738583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.738642] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.738676] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.738706] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.738741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.738777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.738867] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.738898] [drm:intel_power_well_enable [i915]] enabling display
>[  737.738929] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.738980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.739012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.739043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.739074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.739103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.739134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.739168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.739201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.739233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.739262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.739291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.739324] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  737.739356] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.741410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.741442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.741463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.741483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.743043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.743063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.743081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.744787] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.744811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.746694] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.749276] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  737.749372] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.749405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  737.749448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.749596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.749689] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.749755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.799675] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.799716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.799755] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.799797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.799831] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.799867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.799903] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.799937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.799970] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.800001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.800031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.800038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.800068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.800075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.800105] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.800135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.800164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.800193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.800228] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.800263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.800306] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.800347] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.800388] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.800430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.800475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.800589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  737.800708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.801047] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  737.818526] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  737.818563] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.818691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.818728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.818761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.818792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.818821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.818853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.818889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.818921] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.818954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.818982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.819011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.819064] [drm:intel_power_well_disable [i915]] disabling display
>[  737.819105] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.819136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.819169] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.819210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.819245] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.819685] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.819709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.819733] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.819759] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.819779] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.819801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.819822] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.819843] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.819862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.819887] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.819912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.819917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.819942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.819946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.819972] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.819998] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.820023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.820048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.820073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.820098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.820125] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.820156] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.820183] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.820207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.820231] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.820289] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.820308] [drm:intel_power_well_enable [i915]] enabling display
>[  737.820326] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.820360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.820381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.820400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.820419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.820436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.820456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.820477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.820498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.820518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.820536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.820555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.820620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  737.820648] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.822710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.822731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.822749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.822768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.824335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.824356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.824373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.825922] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.825942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.827810] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.831180] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  737.831244] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.831276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  737.831318] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.831430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.831474] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.831536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.881498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.881538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.881577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.881690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.881738] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.881790] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.882006] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.882039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.882071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.882101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.882131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.882139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.882167] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.882175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.882204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.882242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.882284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.882324] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.882366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.882404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.882447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.882487] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.882527] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.882569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.882656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.882988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  737.883025] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.883099] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  737.900134] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  737.900171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.900212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.900244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.900274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.900303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.900331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.900362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.900396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.900427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.900458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.900487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.900514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.900567] [drm:intel_power_well_disable [i915]] disabling display
>[  737.900694] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.900745] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.901026] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.901061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.901091] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.901514] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.901538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.901568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.901657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.901688] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.901722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.901754] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.901787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.901816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.902011] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.902030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.902035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.902052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.902056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.902074] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.902091] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.902108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.902124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.902144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.902161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.902179] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.902195] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.902211] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.902231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.902252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.902306] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.902323] [drm:intel_power_well_enable [i915]] enabling display
>[  737.902340] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.902372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.902390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.902407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.902423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.902439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.902457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.902476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.902494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.902518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.902541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.902567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.902639] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  737.902671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.904738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.904760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.904778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.904797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.906364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.906384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.906402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.907942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.907964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.909814] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.913123] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  737.913199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.913239] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  737.913290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.913432] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.913489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.913575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.963437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.963475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.963513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.963553] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.963663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.963826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.963862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.963895] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.963926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.963956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.963985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.963993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.964021] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.964028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.964058] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.964086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.964126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.964165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.964208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.964247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.964290] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.964331] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.964376] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.964434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.964484] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.964555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  737.964619] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  737.964686] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  737.981675] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  737.981713] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  737.981753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.981787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.981817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.981847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.981876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.981908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.981942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.981974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.982005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.982034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.982061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.982114] [drm:intel_power_well_disable [i915]] disabling display
>[  737.982154] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  737.982185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.982218] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.982250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.982278] [drm:intel_power_well_disable [i915]] disabling always-on
>[  737.982902] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  737.982937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  737.982972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  737.982998] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  737.983018] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  737.983041] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  737.983063] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  737.983083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  737.983104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  737.983123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  737.983141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  737.983147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.983165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  737.983169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  737.983188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  737.983206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  737.983225] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  737.983242] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  737.983264] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  737.983281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  737.983304] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  737.983334] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  737.983355] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  737.983376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  737.983400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  737.983459] [drm:intel_power_well_enable [i915]] enabling always-on
>[  737.983477] [drm:intel_power_well_enable [i915]] enabling display
>[  737.983495] [drm:hsw_set_power_well [i915]] Enabling power well
>[  737.983529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  737.983552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  737.983607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  737.983635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  737.983663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  737.983692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  737.983724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  737.983754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  737.983785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  737.983812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  737.983838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  737.983869] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  737.983898] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  737.985957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  737.985978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  737.985997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.986016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  737.987606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  737.987627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  737.987646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  737.989211] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  737.989232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  737.991111] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  737.994457] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  737.994546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  737.994636] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  737.994709] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  737.994879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  737.994952] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  737.995028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.044849] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.044886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.044923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.044962] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.044992] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.045026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.045060] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.045090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.045121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.045149] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.045187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.045195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.045234] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.045241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.045281] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.045320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.045359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.045399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.045438] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.045477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.045518] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.045553] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.045670] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.045724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.045783] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.045939] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.045999] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.046089] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.062450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.062487] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.062527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.062561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.062672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.062716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.062764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.062810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.062862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.063160] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.063193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.063223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.063251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.063303] [drm:intel_power_well_disable [i915]] disabling display
>[  738.063343] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.063375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.063422] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.063442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.063459] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.064033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.064055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.064077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.064100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.064119] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.064139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.064159] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.064178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.064197] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.064219] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.064242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.064247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.064270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.064274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.064298] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.064322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.064346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.064369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.064392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.064415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.064439] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.064463] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.064486] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.064511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.064536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.064654] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.064687] [drm:intel_power_well_enable [i915]] enabling display
>[  738.064718] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.064773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.064808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.064837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.064868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.064896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.064928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.064962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.065287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.065320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.065348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.065376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.065411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.065440] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.067498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.067522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.067547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.067607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.069175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.069195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.069213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.070782] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.070804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.072663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.075980] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.076045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.076080] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.076127] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.076255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.076316] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.076407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.126302] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.126342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.126383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.126424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.126458] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.126494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.126530] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.126564] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.126676] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.126721] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.126763] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.126776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.126823] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.127068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.127101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.127131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.127160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.127188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.127222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.127250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.127280] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.127308] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.127337] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.127374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.127428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.127541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.127633] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.127734] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.145002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.145039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.145080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.145113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.145144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.145174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.145203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.145241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.145292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.145323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.145353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.145379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.145404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.145451] [drm:intel_power_well_disable [i915]] disabling display
>[  738.145487] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.145523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.145560] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.145663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.145703] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.146351] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.146382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.146419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.146449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.146470] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.146492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.146515] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.146535] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.146603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.146631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.146660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.146668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.146695] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.146703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.146733] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.146898] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.146923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.146949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.146975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.147000] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.147027] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.147053] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.147079] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.147106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.147134] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.147195] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.147218] [drm:intel_power_well_enable [i915]] enabling display
>[  738.147240] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.147280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.147306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.147332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.147358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.147384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.147410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.147438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.147466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.147494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.147519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.147545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.147610] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.147641] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.149898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.149919] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.149938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.149961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.151539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.151585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.151604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.153167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.153191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.155083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.158400] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.158474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.158493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.158519] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.158671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.158715] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.158780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.208748] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.208788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.208827] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.208868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.208901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.208938] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.208974] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.209008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.209041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.209073] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.209103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.209111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.209141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.209147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.209178] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.209208] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.209237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.209266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.209301] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.209330] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.209361] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.209390] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.209419] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.209453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.209491] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.209645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.209686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.209938] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.226455] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.226492] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.226531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.226638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.226689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.226739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.226789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.226839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.227063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.227092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.227112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.227129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.227146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.227177] [drm:intel_power_well_disable [i915]] disabling display
>[  738.227205] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.227229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.227254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.227280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.227299] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.227867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.227899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.227932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.227967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.227996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.228028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.228058] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.228089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.228117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.228146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.228173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.228180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.228206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.228213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.228240] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.228268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.228295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.228318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.228348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.228374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.228403] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.228428] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.228454] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.228484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.228516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.228643] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.228675] [drm:intel_power_well_enable [i915]] enabling display
>[  738.228707] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.228759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.229007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.229029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.229048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.229073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.229099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.229127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.229154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.229181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.229207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.229231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.229258] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.229283] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.231338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.231360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.231379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.231398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.232971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.232991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.233009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.234662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.234683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.236537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.239882] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.239984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.240016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.240058] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.240168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.240211] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.240272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.290201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.290241] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.290281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.290322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.290356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.290392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.290428] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.290462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.290495] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.290532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.290643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.290660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.290708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.290722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.290771] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.290820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.290869] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.290917] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.290971] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.291018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.291069] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.291515] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.291544] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.291619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.291658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.291838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.291864] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.291919] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.308447] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.308485] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.308524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.308557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.308859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.308903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.308946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.308989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.309037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.309082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.309127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.309167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.309207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.309276] [drm:intel_power_well_disable [i915]] disabling display
>[  738.309333] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.309377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.309423] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.309468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.309510] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.310077] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.310107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.310137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.310170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.310198] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.310227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.310256] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.310285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.310314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.310342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.310370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.310375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.310403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.310408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.310438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.310466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.310495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.310523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.310552] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.310631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.310669] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.310702] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.310735] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.310771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.310809] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.310919] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.310950] [drm:intel_power_well_enable [i915]] enabling display
>[  738.310980] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.311034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.311066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.311098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.311125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.311151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.311176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.311205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.311234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.311261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.311287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.311312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.311340] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.311365] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.313397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.313420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.313440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.313466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.315031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.315052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.315070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.316718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.316739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.318619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.321952] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.322061] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.322094] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.322134] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.322217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.322246] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.322286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.372314] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.372354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.372394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.372436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.372469] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.372510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.372552] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.372660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.372711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.372756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.372804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.373076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.373110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.373118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.373150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.373191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.373232] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.373270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.373297] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.373322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.373349] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.373375] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.373401] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.373428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.373456] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.373529] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.373592] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.373660] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.390766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.390803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.390844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.390877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.390907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.390937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.390965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.390997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.391038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.391080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.391122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.391160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.391199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.391255] [drm:intel_power_well_disable [i915]] disabling display
>[  738.391301] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.391342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.391384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.391425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.391459] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.392146] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.392168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.392191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.392217] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.392240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.392264] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.392288] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.392312] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.392335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.392359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.392382] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.392386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.392409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.392413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.392437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.392461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.392484] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.392507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.392531] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.392609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.392643] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.392672] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.392702] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.392733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.392767] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.392995] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.393014] [drm:intel_power_well_enable [i915]] enabling display
>[  738.393033] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.393069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.393090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.393117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.393141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.393167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.393192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.393221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.393249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.393277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.393303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.393329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.393356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.393382] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.395419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.395441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.395461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.395485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.397078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.397099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.397118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.398762] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.398783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.400659] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.403921] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.403976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.403995] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.404021] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.404104] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.404132] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.404173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.454228] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.454269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.454308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.454354] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.454395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.454437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.454479] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.454520] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.454562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.454682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.454729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.454745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.454791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.454803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.454852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.454896] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.454950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.454987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.455033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.455391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.455435] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.455473] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.455513] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.455555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.455636] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.455914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.455963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.456017] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.473025] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.473063] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.473103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.473137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.473168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.473198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.473227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.473258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.473292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.473324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.473364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.473391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.473418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.473467] [drm:intel_power_well_disable [i915]] disabling display
>[  738.473505] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.473534] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.473632] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.473683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.473732] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.474546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.474607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.474732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.474755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.474774] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.474794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.474815] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.474834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.474853] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.474870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.474887] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.474891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.474907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.474911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.474928] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.474951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.474975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.474998] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.475021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.475044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.475069] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.475092] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.475115] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.475139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.475164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.475220] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.475241] [drm:intel_power_well_enable [i915]] enabling display
>[  738.475260] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.475297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.475320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.475344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.475367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.475391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.475414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.475439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.475464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.475489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.475512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.475546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.475609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.475644] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.477710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.477731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.477750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.477770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.479330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.479350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.479367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.480930] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.480951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.482817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.486162] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.486252] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.486285] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.486328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.486439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.486482] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.486548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.536514] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.536555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.536669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.536729] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.536964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.537000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.537035] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.537067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.537098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.537127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.537155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.537163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.537190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.537196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.537225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.537253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.537280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.537306] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.537339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.537366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.537395] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.537422] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.537448] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.537481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.537517] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.537709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.538008] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.538074] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.553471] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.553509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.553553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.553658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.553711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.553765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.553815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.553867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.553920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.553971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.554023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.554069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.554114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.554170] [drm:intel_power_well_disable [i915]] disabling display
>[  738.554212] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.554244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.554278] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.554311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.554342] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.554767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.554793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.554826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.554850] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.554868] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.554888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.554908] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.554931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.554955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.554988] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.555008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.555014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.555042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.555046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.555064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.555082] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.555099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.555115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.555135] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.555151] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.555169] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.555186] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.555202] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.555221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.555246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.555302] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.555322] [drm:intel_power_well_enable [i915]] enabling display
>[  738.555342] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.555378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.555401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.555425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.555446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.555469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.555492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.555517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.555601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.555635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.555666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.555695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.555727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.555757] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.557817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.557838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.557857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.557875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.559428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.559450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.559469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.561010] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.561032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.562890] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.566235] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.566327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.566347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.566372] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.566451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.566479] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.566520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.616644] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.616683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.616723] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.616765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.616798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.616834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.616870] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.616904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.616937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.616968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.616998] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.617006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.617035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.617041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.617071] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.617099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.617129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.617157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.617192] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.617221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.617252] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.617281] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.617309] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.617343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.617386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.617490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.617526] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.617849] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.634445] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.634482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.634521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.634642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.634693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.634742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.634788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.634846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.634895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.634935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.634974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.635010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.635046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.635097] [drm:intel_power_well_disable [i915]] disabling display
>[  738.635138] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.635175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.635214] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.635253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.635283] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.635875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.635896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.635918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.635941] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.635959] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.635980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.635999] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.636018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.636036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.636053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.636070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.636074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.636090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.636094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.636111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.636127] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.636143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.636158] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.636178] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.636194] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.636211] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.636227] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.636243] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.636262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.636283] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.636335] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.636352] [drm:intel_power_well_enable [i915]] enabling display
>[  738.636368] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.636400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.636418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.636435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.636452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.636468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.636486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.636505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.636527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.636607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.636638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.636668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.636704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.636736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.638818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.638841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.638859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.638878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.640429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.640451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.640471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.642022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.642046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.643959] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.647196] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.647277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.647296] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.647322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.647406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.647435] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.647475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.697537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.697608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.697648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.697689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.697724] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.697767] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.697808] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.697850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.697891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.697932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.697972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.697980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.698020] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.698027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.698069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.698110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.698151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.698191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.698241] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.698275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.698309] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.698338] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.698366] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.698397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.698432] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.698535] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.698626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.698711] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.715425] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.715462] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.715501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.715534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.715642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.715806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.715847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.715889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.715933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.715976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.716020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.716060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.716114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.716175] [drm:intel_power_well_disable [i915]] disabling display
>[  738.716217] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.716253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.716291] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.716326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.716355] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.717025] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.717054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.717084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.717115] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.717140] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.717167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.717194] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.717219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.717243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.717266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.717287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.717293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.717315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.717320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.717351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.717383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.717415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.717446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.717477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.717509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.717549] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.717644] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.717676] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.717710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.717747] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.718109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.718140] [drm:intel_power_well_enable [i915]] enabling display
>[  738.718170] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.718224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.718253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.718284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.718311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.718341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.718370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.718402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.718434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.718466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.718492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.718520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.718579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.718608] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.720879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.720900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.720919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.720938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.722533] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.722569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.722588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.724162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.724183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.726077] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.729390] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.729461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.729493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.729547] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.729906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.729939] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.729991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.779718] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.779759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.779798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.779840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.779872] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.779908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.779943] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.779977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.780010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.780041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.780071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.780079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.780108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.780115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.780145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.780175] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.780205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.780233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.780268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.780298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.780329] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.780358] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.780387] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.780421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.780458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.780632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.780693] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.780793] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.797422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.797460] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.797499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.797532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.797642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.797687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.797736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.797781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.797836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.798080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.798130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.798172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.798216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.798296] [drm:intel_power_well_disable [i915]] disabling display
>[  738.798349] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.798378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.798409] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.798439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.798468] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.798863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.798897] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.798933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.798972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.799003] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.799036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.799069] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.799101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.799121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.799140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.799158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.799163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.799181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.799185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.799203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.799221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.799238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.799255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.799276] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.799293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.799312] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.799329] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.799347] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.799367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.799390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.799448] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.799466] [drm:intel_power_well_enable [i915]] enabling display
>[  738.799484] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.799517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.799577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.799610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.799638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.799668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.799696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.799730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.799762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.799795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.799822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.799851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.799886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.799915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.801983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.802004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.802022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.802041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.803628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.803647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.803665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.805225] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.805246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.807114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.810429] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.810497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.810517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.810598] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.810801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.810830] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.810871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.860716] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.860759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.860803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.860850] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.860890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.860932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.860974] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.861014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.861056] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.861096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.861136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.861144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.861184] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.861191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.861232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.861273] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.861314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.861354] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.861396] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.861435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.861478] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.861515] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.861622] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.861660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.861697] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.862074] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.862114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.862180] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.879475] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.879513] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.879638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.879676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.879708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.879739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.879779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.879821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.879866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.879918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.879951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.879979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.880004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.880050] [drm:intel_power_well_disable [i915]] disabling display
>[  738.880084] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.880112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.880143] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.880171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.880196] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.880742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.880777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.880811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.880849] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.880881] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.880915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.880948] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.880972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.880995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.881018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.881041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.881046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.881069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.881073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.881096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.881120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.881153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.881176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.881208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.881227] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.881246] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.881263] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.881280] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.881300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.881321] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.881362] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.881379] [drm:intel_power_well_enable [i915]] enabling display
>[  738.881396] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.881427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.881445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.881462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.881479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.881496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.881517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.881597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.881631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.881666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.881697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.881727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.881760] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.881794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.883858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.883879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.883899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.883923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.885529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.885573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.885592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.887165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.887189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.889082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.892369] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.892460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.892487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.892529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.892700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.892738] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.892792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.942768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.942805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.942843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.942881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.942912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.942946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.942979] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.943011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.943042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.943080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.943119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.943127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.943165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.943172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.943212] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.943252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.943291] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.943330] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.943370] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.943408] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.943449] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.943488] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.943527] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.943649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.943703] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.944171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  738.944219] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  738.944277] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  738.961356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  738.961394] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  738.961434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.961467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.961498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.961622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.961679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.961728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.961778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.961822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.961854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.961881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.961909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.961959] [drm:intel_power_well_disable [i915]] disabling display
>[  738.961998] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  738.962027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.962059] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.962089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.962117] [drm:intel_power_well_disable [i915]] disabling always-on
>[  738.962753] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  738.962777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  738.962801] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  738.962833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  738.962851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  738.962871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  738.962891] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  738.962910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  738.962928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  738.962945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  738.962961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  738.962966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.962982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  738.962986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  738.963003] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  738.963020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  738.963036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  738.963058] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  738.963082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  738.963105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  738.963129] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  738.963153] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  738.963176] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  738.963201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  738.963226] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  738.963269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  738.963289] [drm:intel_power_well_enable [i915]] enabling display
>[  738.963308] [drm:hsw_set_power_well [i915]] Enabling power well
>[  738.963344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  738.963368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  738.963392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  738.963415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  738.963438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  738.963461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  738.963487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  738.963515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  738.963592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  738.963624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  738.963652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  738.963686] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  738.963715] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  738.965764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  738.965784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  738.965802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.965821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  738.967385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  738.967405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  738.967427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  738.968988] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  738.969010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  738.970870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  738.974148] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  738.974195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  738.974222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  738.974257] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  738.974351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  738.974387] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  738.974440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.024431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.024471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.024510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.024632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.024675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.024713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.024748] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.024781] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.024812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.024843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.024871] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.024880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.024908] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.024915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.024945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.024972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.025001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.025028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.025063] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.025100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.025152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.025181] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.025210] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.025242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.025278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.025377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.025415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.025495] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.042522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.042592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.042632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.042666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.042697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.042727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.042756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.042787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.042821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.042852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.042892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.042931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.042970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.043027] [drm:intel_power_well_disable [i915]] disabling display
>[  739.043073] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.043114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.043156] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.043198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.043231] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.043948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.043972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.043996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.044021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.044061] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.044096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.044121] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.044146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.044173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.044198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.044224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.044230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.044255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.044260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.044286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.044312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.044338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.044363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.044390] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.044415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.044442] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.044469] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.044494] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.044528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.044579] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.044640] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.044661] [drm:intel_power_well_enable [i915]] enabling display
>[  739.044680] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.044723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.044756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.044788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.044820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.044849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.044880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.044915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.044948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.044981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.045004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.045023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.045047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.045067] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.047123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.047144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.047163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.047193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.048764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.048784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.048802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.050362] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.050383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.052259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.055629] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.055693] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.055726] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.055776] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.055890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.055929] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.055990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.105955] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.105995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.106035] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.106076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.106110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.106146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.106181] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.106215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.106248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.106279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.106310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.106317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.106347] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.106353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.106384] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.106413] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.106443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.106473] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.106522] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.106629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.106662] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.106692] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.106722] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.106756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.106796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.106912] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.106972] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.107058] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.124047] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.124084] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.124124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.124158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.124189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.124228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.124265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.124304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.124347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.124397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.124431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.124466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.124500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.124629] [drm:intel_power_well_disable [i915]] disabling display
>[  739.124874] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.124909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.124945] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.124978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.125005] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.125384] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.125423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.125450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.125480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.125513] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.125596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.125631] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.125665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.125698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.125730] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.125763] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.125905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.125947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.125956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.125990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.126016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.126037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.126057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.126082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.126103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.126125] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.126145] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.126165] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.126189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.126220] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.126291] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.126316] [drm:intel_power_well_enable [i915]] enabling display
>[  739.126341] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.126386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.126421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.126442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.126462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.126481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.126502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.126557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.126589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.126619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.126646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.126673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.126706] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.126734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.128974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.128995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.129017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.129041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.130733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.130754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.130772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.132331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.132355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.134232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.137577] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.137652] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.137671] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.137698] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.137788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.137827] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.137888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.187916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.187956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.187996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.188037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.188071] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.188106] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.188142] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.188176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.188209] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.188241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.188271] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.188279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.188308] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.188314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.188345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.188375] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.188404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.188433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.188468] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.188497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.188610] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.188652] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.188694] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.188741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.188793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.188910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.188950] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.189005] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.206063] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.206100] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.206140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.206174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.206205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.206234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.206264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.206295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.206329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.206369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.206410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.206449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.206488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.206613] [drm:intel_power_well_disable [i915]] disabling display
>[  739.206681] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.206961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.207000] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.207037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.207067] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.207512] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.207597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.207632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.207669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.207816] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.207837] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.207857] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.207876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.207893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.207910] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.207927] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.207931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.207948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.207952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.207968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.207984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.208000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.208016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.208036] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.208063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.208082] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.208100] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.208125] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.208144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.208165] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.208220] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.208237] [drm:intel_power_well_enable [i915]] enabling display
>[  739.208254] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.208285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.208303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.208320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.208337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.208354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.208371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.208395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.208420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.208445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.208468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.208491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.208570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.208604] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.210669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.210691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.210709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.210728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.212296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.212318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.212341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.213896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.213918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.215787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.219096] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.219170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.219202] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.219243] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.219394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.219433] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.219493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.269435] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.269475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.269515] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.269635] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.269692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.269740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.269791] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.269834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.269881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.269922] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.269970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.269982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.270025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.270036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.270080] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.270121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.270164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.270204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.270252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.270293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.270340] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.270380] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.270423] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.270471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.270502] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.270638] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.270676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.270740] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.286739] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.286776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.286816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.286849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.286879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.286909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.286937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.286968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.287001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.287033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.287064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.287092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.287119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.287172] [drm:intel_power_well_disable [i915]] disabling display
>[  739.287212] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.287243] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.287276] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.287307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.287335] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.287871] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.287894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.287918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.287947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.287972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.287999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.288025] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.288052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.288077] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.288103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.288128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.288134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.288159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.288164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.288190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.288215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.288241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.288267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.288292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.288317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.288344] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.288369] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.288395] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.288422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.288449] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.288496] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.288552] [drm:intel_power_well_enable [i915]] enabling display
>[  739.288581] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.288635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.288666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.288695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.288724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.288752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.288780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.288813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.288846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.288879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.288906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.288935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.288969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.289001] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.291097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.291119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.291137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.291156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.292733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.292754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.292772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.294327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.294348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.296223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.299522] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.299607] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.299640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.299682] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.299787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.299831] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.299892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.349879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.349919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.349959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.349999] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.350033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.350069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.350105] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.350145] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.350187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.350228] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.350268] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.350276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.350317] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.350323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.350365] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.350406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.350447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.350486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.350607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.350658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.350710] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.350754] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.350797] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.350847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.350899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.351048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.351090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.351163] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.368063] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.368101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.368142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.368175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.368206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.368235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.368264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.368296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.368329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.368360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.368391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.368419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.368447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.368509] [drm:intel_power_well_disable [i915]] disabling display
>[  739.368598] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.368628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.368663] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.368694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.368727] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.369127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.369150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.369173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.369198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.369218] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.369240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.369262] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.369282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.369301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.369319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.369337] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.369342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.369360] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.369364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.369382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.369401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.369418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.369435] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.369456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.369474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.369498] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.369560] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.369590] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.369621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.369652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.369723] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.369752] [drm:intel_power_well_enable [i915]] enabling display
>[  739.369784] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.369837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.369870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.369901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.369931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.369961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.369991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.370014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.370035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.370055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.370074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.370099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.370128] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.370154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.372202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.372226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.372247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.372268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.373834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.373858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.373881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.375434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.375456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.377337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.380673] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.380764] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.380784] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.380810] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.380893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.380924] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.380970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.431007] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.431051] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.431094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.431140] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.431181] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.431222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.431264] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.431304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.431346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.431386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.431426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.431433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.431474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.431481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.431522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.431632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.431681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.431725] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.431774] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.431820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.431872] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.431899] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.431927] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.431959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.431994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.432253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.432281] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.432339] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.449346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.449389] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.449434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.449474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.449514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.449632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.449799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.449834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.449877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.449921] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.449965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.450003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.450044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.450100] [drm:intel_power_well_disable [i915]] disabling display
>[  739.450146] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.450188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.450231] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.450269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.450289] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.450712] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.450736] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.450768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.450791] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.450810] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.450830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.450850] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.450869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.450887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.450904] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.450921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.450925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.450941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.450945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.450962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.450978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.450994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.451010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.451030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.451047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.451064] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.451080] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.451096] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.451135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.451158] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.451221] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.451238] [drm:intel_power_well_enable [i915]] enabling display
>[  739.451254] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.451286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.451304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.451322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.451338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.451355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.451377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.451403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.451427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.451452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.451475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.451502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.451573] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.451595] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.453628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.453649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.453667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.453686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.455234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.455259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.455284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.456835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.456856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.458724] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.462048] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.462106] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.462139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.462181] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.462329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.462396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.462482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.512403] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.512447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.512490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.512618] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.512672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.512883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.512921] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.512953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.512984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.513013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.513042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.513049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.513077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.513084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.513112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.513139] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.513166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.513193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.513226] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.513253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.513282] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.513309] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.513336] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.513369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.513404] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.513506] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.513613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.513718] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.530760] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.530797] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.530837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.530870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.530908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.530946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.530986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.531024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.531067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.531108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.531159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.531191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.531220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.531267] [drm:intel_power_well_disable [i915]] disabling display
>[  739.531303] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.531334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.531365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.531395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.531420] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.532360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.532387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.532414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.532442] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.532464] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.532489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.532562] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.532599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.532636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.532673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.532708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.532718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.532751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.532760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.532794] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.533047] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.533083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.533118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.533152] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.533192] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.533221] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.533250] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.533288] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.533320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.533361] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.533446] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.533475] [drm:intel_power_well_enable [i915]] enabling display
>[  739.533547] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.533601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.533635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.533667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.533836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.533856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.533876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.533903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.533930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.533957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.533982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.534007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.534034] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.534059] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.536117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.536138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.536157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.536178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.537756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.537777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.537795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.539334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.539356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.541217] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.544466] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.544613] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.544715] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.544742] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.544837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.544877] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.544951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.594789] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.594835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.594872] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.594911] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.594942] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.594975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.595014] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.595054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.595094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.595133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.595172] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.595179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.595218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.595225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.595265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.595304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.595344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.595382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.595422] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.595460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.595507] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.595617] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.595671] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.595726] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.595780] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.596320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.596380] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.596477] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.613570] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.613607] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.613647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.613680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.613710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.613750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.613794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.613826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.613860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.613892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.613933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.613958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.613994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.614042] [drm:intel_power_well_disable [i915]] disabling display
>[  739.614078] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.614106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.614135] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.614162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.614188] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.615076] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.615108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.615141] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.615176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.615204] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.615234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.615264] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.615293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.615322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.615350] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.615377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.615384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.615411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.615417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.615445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.615471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.615509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.615569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.615604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.615635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.615667] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.615699] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.615730] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.615765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.615800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.616119] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.616148] [drm:intel_power_well_enable [i915]] enabling display
>[  739.616177] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.616225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.616255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.616284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.616312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.616340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.616369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.616401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.616431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.616462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.616500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.616578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.616617] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.616649] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.618848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.618870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.618888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.618907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.620483] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.620520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.620538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.622100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.622132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.624017] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.627288] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.627332] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.627352] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.627377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.627484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.627579] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.627647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.677596] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.677636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.677675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.677717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.677753] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.677796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.677837] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.677879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.677920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.677961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.678001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.678009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.678049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.678056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.678098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.678139] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.678179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.678220] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.678261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.678301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.678344] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.678381] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.678420] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.678466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.678501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.678672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.678724] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.679026] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.695401] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.695437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.695477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.695586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.695634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.695683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.695727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.695776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.696036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.696067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.696096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.696122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.696147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.696192] [drm:intel_power_well_disable [i915]] disabling display
>[  739.696228] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.696256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.696287] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.696315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.696344] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.696920] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.696956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.696993] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.697034] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.697066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.697104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.697139] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.697171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.697205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.697228] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.697248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.697253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.697273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.697278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.697298] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.697318] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.697337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.697357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.697380] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.697400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.697421] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.697440] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.697460] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.697483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.697559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.697660] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.697691] [drm:intel_power_well_enable [i915]] enabling display
>[  739.697711] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.697751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.697774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.697803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.697830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.697864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.697886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.697908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.697928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.697948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.697966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.697984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.698007] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.698031] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.700096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.700118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.700140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.700164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.701733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.701754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.701773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.703331] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.703353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.705228] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.708986] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.709067] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.709116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.709144] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.709224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.709253] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.709293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.759333] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.759373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.759413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.759460] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.759501] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.759621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.759670] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.759721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.759765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.759810] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.759857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.759869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.759912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.759923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.759967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.760008] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.760051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.760091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.760140] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.760179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.760225] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.760265] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.760310] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.760363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.760397] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.760522] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.760562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.760628] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.776359] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.776396] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.776436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.776476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.776602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.776657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.776716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.776780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.776830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.776878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.776926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.776968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.777011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.777091] [drm:intel_power_well_disable [i915]] disabling display
>[  739.777152] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.777199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.777248] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.777297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.777342] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.777860] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.777892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.777925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.777949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.777968] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.777988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.778008] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.778027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.778045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.778062] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.778079] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.778083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.778106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.778110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.778134] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.778157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.778181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.778204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.778227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.778250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.778275] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.778298] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.778322] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.778346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.778371] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.778426] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.778446] [drm:intel_power_well_enable [i915]] enabling display
>[  739.778466] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.778558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.778595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.778629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.778661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.778694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.778726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.778763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.778797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.778830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.778862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.778893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.778929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.778961] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.781052] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.781075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.781095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.781115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.782709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.782731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.782750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.784301] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.784323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.786189] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.789539] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.789625] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.789658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.789701] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.789849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.789921] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.789982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.839884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.839928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.839971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.840018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.840058] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.840100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.840141] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.840182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.840223] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.840263] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.840303] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.840311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.840351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.840358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.840400] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.840440] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.840481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.840598] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.840660] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.840713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.840771] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.840821] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.840871] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.840926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.840979] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.841328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.841366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.841442] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.857775] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.857812] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.857853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.857887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.857918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.857949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.857978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.858010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.858044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.858076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.858107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.858135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.858162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.858215] [drm:intel_power_well_disable [i915]] disabling display
>[  739.858256] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.858287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.858320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.858338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.858358] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.858772] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.858803] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.858835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.858869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.858898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.858928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.858958] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.858988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.859017] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.859045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.859074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.859081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.859107] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.859113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.859141] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.859168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.859195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.859219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.859249] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.859275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.859304] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.859331] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.859357] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.859387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.859419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.859495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.859549] [drm:intel_power_well_enable [i915]] enabling display
>[  739.859581] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.859633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.859666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.859698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.859729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.859759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.859790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.859824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.859862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.859892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.859919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.859945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.859976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.860005] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.862088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.862110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.862133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.862157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.863729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.863769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.863790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.865360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.865383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.867282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.870608] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.870649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.870669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.870695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.870778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.870806] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.870851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.920920] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.920959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.920998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.921039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.921072] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.921108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.921145] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.921179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.921212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.921243] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.921274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.921282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.921311] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.921317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.921348] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.921377] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.921406] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.921435] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.921469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.921576] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.921622] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.921665] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.921707] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.921754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.921816] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.921915] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  739.921943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  739.921996] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  739.939032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  739.939070] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  739.939110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.939143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.939173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.939203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.939232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.939263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.939296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.939327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.939357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.939385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.939412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.939465] [drm:intel_power_well_disable [i915]] disabling display
>[  739.939591] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  739.939642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.939875] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.939911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.939943] [drm:intel_power_well_disable [i915]] disabling always-on
>[  739.940418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  739.940440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  739.940461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  739.940544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  739.940574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  739.940606] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  739.940637] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  739.940666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  739.940696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  739.940725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  739.940755] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  739.940902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.940923] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  739.940927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  739.940947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  739.940965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  739.940984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  739.941002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  739.941023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  739.941041] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  739.941060] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  739.941078] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  739.941095] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  739.941116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  739.941139] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  739.941197] [drm:intel_power_well_enable [i915]] enabling always-on
>[  739.941216] [drm:intel_power_well_enable [i915]] enabling display
>[  739.941234] [drm:hsw_set_power_well [i915]] Enabling power well
>[  739.941268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  739.941288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  739.941313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  739.941338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  739.941364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  739.941389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  739.941417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  739.941444] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  739.941473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  739.941534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  739.941564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  739.941597] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  739.941626] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  739.943967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  739.943988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  739.944007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.944026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  739.945721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  739.945746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  739.945780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  739.947336] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  739.947357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  739.949227] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  739.952520] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  739.952595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  739.952615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  739.952641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  739.952732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  739.952772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  739.952844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.002860] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.002900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.002939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.002980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.003013] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.003049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.003085] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.003118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.003151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.003182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.003212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.003220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.003249] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.003256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.003286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.003316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.003345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.003374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.003409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.003438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.003469] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.003583] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.003621] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.003666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.003711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.003850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.003888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.003971] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.021023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.021077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.021118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.021152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.021183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.021213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.021242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.021274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.021308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.021339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.021370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.021398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.021426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.021479] [drm:intel_power_well_disable [i915]] disabling display
>[  740.021604] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.021650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.021706] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.021942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.021978] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.022280] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.022303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.022326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.022352] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.022373] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.022396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.022417] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.022439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.022458] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.022508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.022535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.022544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.022571] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.022578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.022606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.022633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.022660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.022686] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.022716] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.022743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.022774] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.022969] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.022989] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.023011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.023035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.023093] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.023121] [drm:intel_power_well_enable [i915]] enabling display
>[  740.023152] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.023191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.023212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.023231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.023250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.023268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.023288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.023309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.023329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.023349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.023368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.023386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.023409] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.023434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.025530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.025551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.025569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.025588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.027154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.027178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.027201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.028765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.028788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.030650] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.034003] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.034086] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.034119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.034161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.034276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.034313] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.034366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.084341] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.084381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.084420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.084462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.084578] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.084628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.084679] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.084730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.084774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.084821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.084863] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.084875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.084917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.084928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.084974] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.085015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.085058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.085098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.085146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.085187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.085233] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.085273] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.085317] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.085362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.085407] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.085531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.085571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.085635] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.102377] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.102414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.102454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.102562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.102610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.102659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.102710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.102758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.103027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.103059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.103090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.103118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.103145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.103194] [drm:intel_power_well_disable [i915]] disabling display
>[  740.103232] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.103269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.103309] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.103349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.103380] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.104024] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.104057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.104084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.104107] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.104126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.104158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.104180] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.104209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.104228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.104245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.104262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.104266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.104283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.104287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.104304] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.104320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.104336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.104352] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.104371] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.104388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.104405] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.104421] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.104437] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.104456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.104524] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.104616] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.104647] [drm:intel_power_well_enable [i915]] enabling display
>[  740.104678] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.104728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.104759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.104786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.104815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.104841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.104871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.104903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.104934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.104966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.104992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.105020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.105050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.105080] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.107163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.107185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.107204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.107223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.108780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.108812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.108830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.110377] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.110418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.112275] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.115623] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.115710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.115742] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.115784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.115895] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.115933] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.115974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.165924] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.165963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.166004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.166045] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.166079] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.166115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.166151] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.166185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.166218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.166249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.166279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.166287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.166317] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.166324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.166355] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.166384] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.166414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.166442] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.166477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.166585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.166631] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.166679] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.166721] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.166774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.166829] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.167302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.167343] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.167409] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.184438] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.184475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.184605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.184804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.184838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.184877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.184917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.184956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.184999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.185041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.185083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.185121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.185160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.185215] [drm:intel_power_well_disable [i915]] disabling display
>[  740.185260] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.185301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.185343] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.185385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.185418] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.186087] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.186109] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.186133] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.186160] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.186183] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.186207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.186230] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.186254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.186277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.186300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.186323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.186328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.186351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.186355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.186378] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.186402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.186425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.186448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.186482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.186550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.186587] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.186621] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.186653] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.186689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.186725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.187051] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.187083] [drm:intel_power_well_enable [i915]] enabling display
>[  740.187113] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.187174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.187204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.187234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.187262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.187291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.187320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.187352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.187383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.187412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.187439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.187477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.187545] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.187579] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.189858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.189879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.189897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.189917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.191578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.191599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.191617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.193167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.193188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.195064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.198357] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.198452] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.198556] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.198628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.198773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.198802] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.198843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.248704] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.248744] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.248784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.248825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.248859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.248895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.248930] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.248964] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.248997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.249027] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.249057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.249065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.249095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.249101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.249131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.249161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.249191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.249220] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.249255] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.249285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.249316] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.249346] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.249374] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.249409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.249446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.249660] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.250015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.250081] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.267147] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.267186] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.267230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.267271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.267311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.267351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.267390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.267430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.267472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.267593] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.267651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.267702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.267753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.267839] [drm:intel_power_well_disable [i915]] disabling display
>[  740.268144] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.268206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.268239] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.268271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.268300] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.268673] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.268714] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.268747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.268783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.268808] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.268829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.268849] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.268868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.268886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.268903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.268920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.268924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.268941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.268945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.268961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.268978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.269000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.269024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.269047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.269070] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.269095] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.269118] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.269141] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.269166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.269191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.269247] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.269267] [drm:intel_power_well_enable [i915]] enabling display
>[  740.269286] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.269334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.269356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.269377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.269403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.269420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.269438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.269469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.269532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.269566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.269598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.269630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.269666] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.269699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.271774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.271796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.271814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.271833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.273385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.273406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.273426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.274994] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.275015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.276963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.280278] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.280347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.280380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.280422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.280587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.280616] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.280657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.330608] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.330647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.330687] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.330732] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.330771] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.330812] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.330852] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.330891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.330930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.330969] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.331007] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.331015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.331054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.331060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.331100] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.331140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.331179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.331217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.331257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.331295] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.331336] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.331375] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.331415] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.331456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.331562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.331703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.331744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.331809] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.348841] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.348878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.348919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.348952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.348983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.349022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.349062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.349101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.349144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.349186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.349228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.349267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.349305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.349362] [drm:intel_power_well_disable [i915]] disabling display
>[  740.349407] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.349448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.349576] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.349629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.349674] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.350192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.350215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.350239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.350267] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.350292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.350319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.350344] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.350369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.350395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.350420] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.350445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.350487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.350521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.350529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.350561] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.350590] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.350618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.350645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.350677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.350704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.350734] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.350761] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.350791] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.350822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.350857] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.350916] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.350935] [drm:intel_power_well_enable [i915]] enabling display
>[  740.350953] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.350987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.351008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.351027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.351046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.351064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.351083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.351105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.351131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.351159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.351184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.351210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.351237] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.351263] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.353310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.353334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.353355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.353376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.354941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.354961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.354979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.356577] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.356597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.358462] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.361841] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.361921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.361954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.361996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.362140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.362183] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.362250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.412197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.412238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.412277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.412318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.412351] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.412387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.412422] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.412455] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.412565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.412609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.412652] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.412666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.412707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.412719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.412766] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.412807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.412849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.412889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.412939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.412975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.413006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.413034] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.413061] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.413095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.413130] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.413240] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.413280] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.413369] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.430384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.430422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.430462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.430580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.430640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.430690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.430738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.430784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.430827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.430856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.430884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.430910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.430935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.430983] [drm:intel_power_well_disable [i915]] disabling display
>[  740.431020] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.431047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.431077] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.431106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.431131] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.431558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.431600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.431646] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.431693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.431732] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.431776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.431819] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.431864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.431894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.431913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.431931] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.431936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.431954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.431958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.431984] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.432001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.432017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.432033] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.432052] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.432069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.432086] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.432102] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.432118] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.432137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.432158] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.432221] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.432250] [drm:intel_power_well_enable [i915]] enabling display
>[  740.432267] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.432299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.432322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.432346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.432370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.432393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.432417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.432442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.432521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.432555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.432585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.432613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.432646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.432675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.434745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.434768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.434791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.434815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.436380] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.436406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.436431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.438012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.438034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.439901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.442808] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.442881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.442914] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.442955] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.443066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.443113] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.443171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.493132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.493173] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.493212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.493254] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.493288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.493324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.493360] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.493394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.493427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.493458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.493565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.493579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.493621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.493633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.493676] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.493718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.493759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.493804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.493854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.493896] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.493946] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.493981] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.494013] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.494035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.494058] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.494130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.494156] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.494210] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.511284] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.511327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.511367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.511399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.511430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.511459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.511573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.511777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.511814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.511847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.511878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.511907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.511935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.511987] [drm:intel_power_well_disable [i915]] disabling display
>[  740.512028] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.512059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.512093] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.512125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.512154] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.512590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.512616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.512643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.512672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.512697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.512723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.512749] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.512774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.512800] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.512825] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.512849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.512854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.512879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.512884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.512910] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.512935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.512960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.512986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.513011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.513036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.513062] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.513087] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.513113] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.513139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.513167] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.513226] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.513248] [drm:intel_power_well_enable [i915]] enabling display
>[  740.513269] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.513308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.513337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.513372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.513400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.513420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.513441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.513500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.513532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.513563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.513590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.513618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.513650] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.513680] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.515748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.515769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.515788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.515808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.517359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.517380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.517400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.518952] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.518974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.520937] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.524270] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.524373] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.524405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.524446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.524726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.524767] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.524827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.574661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.574701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.574742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.574801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.574843] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.574878] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.574912] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.574943] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.574973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.575012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.575051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.575059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.575098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.575105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.575145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.575184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.575224] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.575262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.575302] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.575341] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.575388] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.575419] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.575447] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.575531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.575579] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.575959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.575998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.576074] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.593119] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.593155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.593195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.593229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.593259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.593289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.593317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.593348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.593382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.593414] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.593444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.593544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.593588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.593671] [drm:intel_power_well_disable [i915]] disabling display
>[  740.593871] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.593895] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.593918] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.593939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.593959] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.594219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.594240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.594263] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.594288] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.594308] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.594329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.594351] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.594371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.594390] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.594408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.594426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.594431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.594449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.594484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.594513] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.594541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.594569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.594595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.594626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.594652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.594681] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.594707] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.594734] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.594767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.594799] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.595061] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.595080] [drm:intel_power_well_enable [i915]] enabling display
>[  740.595098] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.595134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.595156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.595176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.595196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.595215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.595235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.595257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.595278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.595299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.595317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.595335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.595358] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.595379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.597403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.597425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.597444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.597499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.599144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.599165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.599194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.600751] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.600772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.602630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.605947] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.606014] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.606052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.606078] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.606167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.606207] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.606268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.656269] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.656310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.656350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.656392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.656426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.656462] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.656578] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.656634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.656687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.656737] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.656784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.656800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.656845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.656858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.656903] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.657260] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.657309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.657358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.657410] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.657456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.657551] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.657600] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.657650] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.657705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.657759] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.658081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.658116] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.658188] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.675271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.675309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.675349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.675382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.675414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.675444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.675558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.675612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.675667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.675720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.676006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.676053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.676100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.676183] [drm:intel_power_well_disable [i915]] disabling display
>[  740.676226] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.676259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.676293] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.676326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.676354] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.676810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.676833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.676859] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.676887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.676918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.676939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.676959] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.676977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.676995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.677011] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.677027] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.677032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.677047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.677051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.677068] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.677084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.677100] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.677116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.677135] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.677151] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.677168] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.677184] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.677200] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.677220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.677241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.677293] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.677313] [drm:intel_power_well_enable [i915]] enabling display
>[  740.677332] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.677369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.677392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.677416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.677450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.677513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.677547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.677584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.677620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.677655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.677685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.677716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.677753] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.677786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.679859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.679880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.679899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.679918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.681600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.681621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.681639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.683187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.683208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.685085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.688375] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.688563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.688629] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.688673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.688764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.688793] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.688834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.738719] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.738760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.738800] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.738842] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.738875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.738911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.738948] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.738982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.739015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.739046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.739076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.739084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.739114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.739120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.739151] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.739180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.739209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.739239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.739273] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.739303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.739334] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.739363] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.739392] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.739426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.739544] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.739654] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.739694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.739757] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.756362] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.756400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.756444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.756573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.756627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.756671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.756717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.756762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.756814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.756864] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.756913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.756957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.757000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.757066] [drm:intel_power_well_disable [i915]] disabling display
>[  740.757107] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.757145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.757175] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.757205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.757233] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.757662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.757694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.757718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.757745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.757767] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.757791] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.757815] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.757839] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.757862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.757886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.757908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.757913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.757936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.757940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.757964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.757987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.758010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.758033] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.758057] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.758080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.758104] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.758128] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.758151] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.758175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.758200] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.758244] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.758264] [drm:intel_power_well_enable [i915]] enabling display
>[  740.758284] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.758319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.758343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.758367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.758390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.758414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.758447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.758519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.758557] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.758593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.758624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.758656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.758693] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.758726] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.760792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.760813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.760831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.760850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.762421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.762442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.762529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.764079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.764102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.765978] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.768752] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.768805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.768838] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.768879] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.768992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.769035] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.769097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.819105] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.819145] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.819185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.819227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.819261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.819296] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.819333] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.819367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.819400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.819432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.819540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.819554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.819597] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.819609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.819652] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.819695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.819736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.819781] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.819830] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.819872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.819923] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.819968] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.820014] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.820065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.820120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.820228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.820255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.820310] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.837327] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.837363] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.837403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.837436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.837550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.837595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.837626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.837657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.837694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.837728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.837761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.837799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.837840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.837898] [drm:intel_power_well_disable [i915]] disabling display
>[  740.837944] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.837985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.838030] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.838073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.838107] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.838618] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.838644] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.838670] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.838699] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.838724] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.838757] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.838778] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.838797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.838815] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.838832] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.838848] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.838853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.838869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.838873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.838889] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.838905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.838922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.838937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.838957] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.838974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.838991] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.839007] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.839023] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.839042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.839063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.839103] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.839120] [drm:intel_power_well_enable [i915]] enabling display
>[  740.839137] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.839168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.839196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.839215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.839233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.839260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.839277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.839297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.839320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.839345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.839368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.839391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.839416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.839450] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.841535] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.841559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.841582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.841606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.843170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.843191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.843210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.844770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.844791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.846652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.849891] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.849971] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.849994] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.850025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.850112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.850142] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.850184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.900204] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.900244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.900285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.900326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.900359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.900394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.900431] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.900542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.900591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.900635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.900677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.900690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.900735] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.900748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.900792] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.900838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.900884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.900929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.900981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.901027] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.901075] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.901121] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.901154] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.901187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.901225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.901331] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.901370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.901454] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.918539] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.918576] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.918616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.918648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.918680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.918711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.918739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.918770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.918804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.918844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.918886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.918925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.918964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.919021] [drm:intel_power_well_disable [i915]] disabling display
>[  740.919066] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  740.919106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.919129] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.919150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.919168] [drm:intel_power_well_disable [i915]] disabling always-on
>[  740.919589] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.919614] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.919638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.919663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.919683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.919706] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.919728] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.919749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.919769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.919788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.919806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.919813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.919831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.919836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.919855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.919872] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.919890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.919908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.919929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.919947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.919967] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.919984] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.920003] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.920024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.920048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.920104] [drm:intel_power_well_enable [i915]] enabling always-on
>[  740.920123] [drm:intel_power_well_enable [i915]] enabling display
>[  740.920140] [drm:hsw_set_power_well [i915]] Enabling power well
>[  740.920174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.920194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.920213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.920232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.920250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.920270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.920291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.920331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.920356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.920380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  740.920406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  740.920437] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  740.920477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  740.922521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  740.922544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  740.922567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.922591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  740.924161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  740.924182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  740.924200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  740.925759] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  740.925779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  740.927649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  740.930983] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  740.931083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  740.931115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  740.931156] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  740.931302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  740.931371] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  740.931442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.981344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  740.981384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  740.981424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  740.981544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  740.981723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  740.981768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  740.981804] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  740.981836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  740.981867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  740.981896] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  740.981925] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  740.981933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.981961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  740.981968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  740.981997] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  740.982024] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  740.982052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  740.982079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  740.982114] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  740.982142] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  740.982173] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  740.982200] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  740.982227] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  740.982259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  740.982301] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  740.982370] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  740.982396] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  740.982473] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  740.999529] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  740.999566] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  740.999606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  740.999646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  740.999686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  740.999725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  740.999765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  740.999803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  740.999845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  740.999887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  740.999929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  740.999968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.000006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.000063] [drm:intel_power_well_disable [i915]] disabling display
>[  741.000109] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.000150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.000192] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  741.000234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.000267] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.000542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.000642] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.000696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.000741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.000772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.000800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.000831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.000863] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.000896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.000931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.000965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.000998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.001028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.001052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.001081] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  741.001102] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.002696] [IGT] kms_flip: exiting, ret=0
>[  741.023331] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.023373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.023415] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.023506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.023546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.023588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.023628] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.023668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.023708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.023747] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.023786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.023793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.023832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.023838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.023878] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.023917] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.023956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.023995] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.024035] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.024074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.024113] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.024152] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.024187] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.024222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.024248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.024323] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.024343] [drm:intel_power_well_enable [i915]] enabling display
>[  741.024360] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.024397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.024420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.024477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.024498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.024517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.024536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.024561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.024587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.024612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.024633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.024656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.024682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.024705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.026777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.026796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.026814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.026832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.028404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.028422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.028450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.030005] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.030032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.031924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.035404] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.035482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.035508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.035545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.035616] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.035647] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.052254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.052302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.052371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.052647] Console: switching to colour frame buffer device 240x75
>[  741.157996] Console: switching to colour dummy device 80x25
>[  741.158110] [IGT] kms_flip: executing
>[  741.169312] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  741.169363] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  741.170526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.170565] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.172524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.172535] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  741.174525] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.174563] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.176536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.176547] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.176554] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  741.176586] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  741.176628] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  741.177754] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  741.178698] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  741.178720] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  741.178739] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  741.178756] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  741.179775] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  741.179796] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  741.180917] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  741.180920] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  741.181018] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.181020] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.181025] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  741.181028] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  741.181032] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.181035] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.181044] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  741.181047] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.181050] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.181053] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.181056] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.181059] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.181062] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.181065] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  741.181068] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.181071] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.181074] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.181077] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.181080] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.181083] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  741.181086] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.181089] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.181092] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  741.181095] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.181098] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.181101] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  741.181104] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  741.181106] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  741.181110] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  741.181113] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  741.181115] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  741.181118] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.181121] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.181124] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  741.181127] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.181130] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.181133] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  741.181171] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  741.181193] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  741.182483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.182506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.184538] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.184549] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  741.186532] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.186569] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.188524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.188534] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.188542] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  741.188955] [IGT] kms_flip: starting subtest 2x-flip-vs-blocking-wf-vblank
>[  741.192141] [IGT] kms_flip: exiting, ret=77
>[  741.219228] Console: switching to colour frame buffer device 240x75
>[  741.324616] Console: switching to colour dummy device 80x25
>[  741.324731] [IGT] kms_flip: executing
>[  741.336314] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  741.336367] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  741.338512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.338549] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.340663] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.340676] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  741.342793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.342835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.344950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.344961] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.344969] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  741.345000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  741.345043] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  741.346164] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  741.347117] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  741.347140] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  741.347159] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  741.347176] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  741.348182] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  741.348203] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  741.349321] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  741.349325] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  741.349483] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.349486] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.349492] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  741.349495] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  741.349500] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.349503] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.349513] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  741.349517] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.349520] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.349525] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.349528] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.349532] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.349535] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.349538] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  741.349541] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.349545] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.349549] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.349552] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.349556] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.349559] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  741.349562] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.349565] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.349569] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  741.349573] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.349576] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.349579] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  741.349583] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  741.349587] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  741.349590] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  741.349593] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  741.349598] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  741.349601] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.349604] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.349607] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  741.349610] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.349614] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.349618] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  741.349660] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  741.349684] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  741.351496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.351519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.353517] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.353528] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  741.355518] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.355557] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.357500] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.357510] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.357517] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  741.359565] [IGT] kms_flip: starting subtest 2x-modeset-vs-vblank-race-interruptible
>[  741.361318] [IGT] kms_flip: exiting, ret=77
>[  741.402698] Console: switching to colour frame buffer device 240x75
>[  741.506886] Console: switching to colour dummy device 80x25
>[  741.507001] [IGT] kms_flip: executing
>[  741.522306] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  741.522358] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  741.523532] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.523573] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.525512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.525525] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  741.527511] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.527554] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.529513] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.529524] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.529532] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  741.529564] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  741.529607] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  741.530686] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  741.531606] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  741.531628] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  741.531647] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  741.531665] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  741.532681] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  741.532701] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  741.533821] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  741.533825] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  741.533926] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.533929] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.533934] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  741.533936] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  741.533941] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.533943] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.533953] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  741.533956] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.533959] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.533962] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.533965] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.533968] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.533971] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.533974] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  741.533977] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.533980] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.533983] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.533986] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.533989] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.533992] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  741.533995] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.533998] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.534001] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  741.534004] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.534007] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.534010] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  741.534013] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  741.534016] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  741.534019] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  741.534022] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  741.534025] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  741.534028] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.534031] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.534033] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  741.534036] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.534039] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.534042] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  741.534081] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  741.534103] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  741.535475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.535498] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.537522] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.537533] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  741.539510] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.539552] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.541510] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.541521] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.541528] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  741.541923] [IGT] kms_flip: starting subtest 2x-plain-flip
>[  741.545228] [IGT] kms_flip: exiting, ret=77
>[  741.569529] Console: switching to colour frame buffer device 240x75
>[  741.674331] Console: switching to colour dummy device 80x25
>[  741.674523] [IGT] kms_flip: executing
>[  741.686301] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  741.686353] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  741.687510] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.687550] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.689517] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  741.689530] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  741.691506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.691548] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  741.693506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  741.693517] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.693526] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  741.693558] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  741.693603] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  741.694719] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  741.695668] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  741.695699] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  741.695725] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  741.695750] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  741.696772] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  741.696792] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  741.697914] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  741.697917] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  741.698024] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.698027] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.698032] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  741.698035] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  741.698039] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  741.698042] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  741.698051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  741.698055] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.698058] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.698060] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.698064] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.698066] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  741.698069] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.698072] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  741.698075] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.698078] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  741.698081] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  741.698084] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.698087] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  741.698090] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  741.698093] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.698096] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  741.698099] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  741.698102] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.698105] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  741.698108] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  741.698111] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  741.698113] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  741.698116] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  741.698119] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  741.698122] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  741.698125] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.698128] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  741.698131] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  741.698134] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.698137] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  741.698140] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  741.698178] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  741.698201] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  741.699474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.699495] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.701517] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  741.701529] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  741.703502] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.703544] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  741.705502] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  741.705513] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  741.705520] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  741.705896] [IGT] kms_flip: starting subtest wf_vblank-ts-check
>[  741.706856] [drm:drm_mode_addfb2] [FB:77]
>[  741.706902] [drm:drm_mode_addfb2] [FB:79]
>[  741.760162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.760224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.769488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  741.769538] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  741.769615] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  741.788135] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  741.788180] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  741.788212] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  741.788251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.788284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.788319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.788349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.788378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.788410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.788533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.788588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.788641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.788693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.788739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.788795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.788851] [drm:intel_power_well_disable [i915]] disabling display
>[  741.788893] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  741.788936] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.788970] [drm:intel_power_well_disable [i915]] disabling always-on
>[  741.789068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  741.789227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  741.789321] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  741.789333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  741.789385] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  741.789455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  741.789489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  741.789529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  741.789562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  741.789597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  741.789631] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  741.789665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  741.789698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  741.789729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  741.789759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  741.789768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.789796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  741.789804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  741.789836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  741.789867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  741.789896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  741.789925] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  741.789956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  741.789984] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  741.790014] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  741.790042] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  741.790071] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  741.790104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  741.790140] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  741.793442] [drm:intel_power_well_enable [i915]] enabling always-on
>[  741.793461] [drm:intel_power_well_enable [i915]] enabling display
>[  741.793478] [drm:hsw_set_power_well [i915]] Enabling power well
>[  741.793512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  741.793532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  741.793551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  741.793568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  741.793585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  741.793604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  741.793624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  741.793642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  741.793660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  741.793677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  741.793693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  741.793714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  741.793733] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  741.795788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  741.795812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  741.795835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.795859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  741.797451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  741.797473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  741.797491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  741.799065] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  741.799088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  741.800962] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  741.804242] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  741.804287] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  741.804315] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  741.804350] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  741.804488] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  741.804527] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  741.821072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  741.821120] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  741.821183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.129600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  752.145952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  752.146083] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  752.146192] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  752.163162] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  752.163206] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  752.163239] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  752.163278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  752.163312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  752.163347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  752.163378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  752.163407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  752.163439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  752.163474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  752.163507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  752.163547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  752.163574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.163598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  752.163622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  752.163670] [drm:intel_power_well_disable [i915]] disabling display
>[  752.163706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  752.163745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  752.163775] [drm:intel_power_well_disable [i915]] disabling always-on
>[  752.164201] [drm:drm_mode_addfb2] [FB:77]
>[  752.164272] [drm:drm_mode_addfb2] [FB:78]
>[  752.194002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  752.194111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  752.194238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  752.194250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  752.194313] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  752.194337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  752.194362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  752.194388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  752.194408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  752.194430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  752.194452] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  752.194473] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  752.194493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  752.194513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  752.194531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  752.194535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  752.194554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  752.194557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  752.194576] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  752.194594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  752.194612] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  752.194632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  752.194657] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  752.194681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  752.194705] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  752.194729] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  752.194754] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  752.194780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  752.194806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  752.198220] [drm:intel_power_well_enable [i915]] enabling always-on
>[  752.198241] [drm:intel_power_well_enable [i915]] enabling display
>[  752.198260] [drm:hsw_set_power_well [i915]] Enabling power well
>[  752.198298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  752.198321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  752.198341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  752.198360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  752.198378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  752.198400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  752.198426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  752.198452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  752.198478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  752.198502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  752.198526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  752.198552] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  752.198577] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  752.200644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  752.200666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  752.200685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  752.200707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  752.202272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  752.202293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  752.202310] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  752.203862] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  752.203883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  752.205753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  752.209102] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  752.209189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  752.209221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  752.209264] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  752.225967] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  752.226050] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  752.226116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.534489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.534867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  762.535001] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  762.535220] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  762.552432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  762.552470] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  762.552511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.552545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.552675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.552726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.552775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.552826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.552884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.552922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.552955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.552988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.553016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.553044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.553101] [drm:intel_power_well_disable [i915]] disabling display
>[  762.553150] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  762.553179] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  762.553200] [drm:intel_power_well_disable [i915]] disabling always-on
>[  762.553408] [drm:drm_mode_addfb2] [FB:77]
>[  762.553441] [drm:drm_mode_addfb2] [FB:78]
>[  762.582632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  762.582735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  762.582806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  762.582873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  762.582885] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  762.582944] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  762.582965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  762.582988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  762.583014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  762.583038] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  762.583062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  762.583086] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  762.583110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  762.583134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  762.583157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  762.583180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  762.583184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.583207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  762.583211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  762.583235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  762.583258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  762.583281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  762.583304] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  762.583328] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  762.583351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  762.583374] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  762.583398] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  762.583421] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  762.583445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  762.583471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  762.586776] [drm:intel_power_well_enable [i915]] enabling always-on
>[  762.586798] [drm:intel_power_well_enable [i915]] enabling display
>[  762.586819] [drm:hsw_set_power_well [i915]] Enabling power well
>[  762.586859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  762.586885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  762.586909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  762.586934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  762.586958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  762.586982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  762.587009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  762.587035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  762.587061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  762.587085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  762.587109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  762.587135] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  762.587159] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  762.589229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  762.589251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  762.589269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.589289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  762.590853] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  762.590873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  762.590893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  762.592452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  762.592473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  762.594347] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  762.597697] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  762.597782] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  762.597815] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  762.597859] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  762.614559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  762.614645] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  762.614717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  772.923083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  772.923456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  772.923592] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  772.923811] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  772.940845] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  772.940884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  772.940925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  772.940958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  772.940994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  772.941024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  772.941053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  772.941085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  772.941127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  772.941256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  772.941316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  772.941361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  772.941402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  772.941441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  772.941514] [drm:intel_power_well_disable [i915]] disabling display
>[  772.941570] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  772.941624] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  772.941667] [drm:intel_power_well_disable [i915]] disabling always-on
>[  772.944831] [IGT] kms_flip: exiting, ret=0
>[  772.964075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  772.964116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  772.964182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  772.964228] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  772.964267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  772.964308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  772.964348] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  772.964388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  772.964429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  772.964468] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  772.964507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  772.964514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  772.964553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  772.964559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  772.964599] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  772.964638] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  772.964678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  772.964717] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  772.964758] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  772.964806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  772.964838] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  772.964865] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  772.964891] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  772.964924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  772.964959] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  772.965047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  772.965076] [drm:intel_power_well_enable [i915]] enabling display
>[  772.965103] [drm:hsw_set_power_well [i915]] Enabling power well
>[  772.965182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  772.965215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  772.965247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  772.965279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  772.965311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  772.965342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  772.965378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  772.965411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  772.965445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  772.965476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  772.965508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  772.965541] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  772.965573] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  772.967653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  772.967673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  772.967691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  772.967710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  772.969294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  772.969312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  772.969329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  772.970903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  772.970925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  772.972810] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  772.976251] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  772.976329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  772.976348] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  772.976375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  772.976438] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  772.976458] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  772.993132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  772.993219] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  772.993296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  772.993588] Console: switching to colour frame buffer device 240x75
>[  773.098866] Console: switching to colour dummy device 80x25
>[  773.098980] [IGT] kms_flip: executing
>[  773.123544] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  773.123597] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  773.125203] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  773.125242] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  773.127211] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  773.127222] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  773.129201] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  773.129240] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  773.131218] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  773.131230] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  773.131237] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  773.131267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  773.131306] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  773.132399] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  773.133343] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  773.133369] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  773.133391] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  773.133411] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  773.134432] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  773.134452] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  773.135573] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  773.135576] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  773.135675] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  773.135678] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  773.135683] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  773.135685] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  773.135690] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  773.135693] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  773.135702] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  773.135705] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.135708] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  773.135711] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  773.135714] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  773.135717] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  773.135720] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  773.135723] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  773.135726] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  773.135729] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  773.135732] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  773.135735] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  773.135738] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  773.135741] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  773.135744] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  773.135747] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  773.135750] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  773.135752] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  773.135755] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  773.135758] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  773.135761] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  773.135764] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  773.135767] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  773.135770] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  773.135773] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  773.135776] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  773.135779] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  773.135782] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  773.135785] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  773.135787] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  773.135790] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  773.135828] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  773.135851] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  773.137159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  773.137181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  773.139217] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  773.139228] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  773.141203] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  773.141241] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  773.143223] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  773.143234] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  773.143242] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  773.143648] [IGT] kms_flip: starting subtest single-buffer-flip-vs-dpms-off-vs-modeset
>[  773.144607] [drm:drm_mode_addfb2] [FB:58]
>[  773.144633] [drm:drm_mode_addfb2] [FB:79]
>[  773.197614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.197678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.209956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.210005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.210078] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.227176] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.227220] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.227253] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.227292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.227325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.227360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.227399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.227439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.227477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.227521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.227563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.227608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.227639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.227665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.227689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.227737] [drm:intel_power_well_disable [i915]] disabling display
>[  773.227772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.227808] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.227837] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.227899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  773.228013] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  773.228166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.228191] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.228310] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.228346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.228378] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.228411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.228439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.228467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.228495] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.228522] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.228548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.228577] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.228612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.228617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.228636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.228640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.228660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.228679] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.228704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.228730] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.228756] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.228782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.228808] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  773.228834] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.228860] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.228887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.228916] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.232304] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.232326] [drm:intel_power_well_enable [i915]] enabling display
>[  773.232344] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.232380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.232402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.232423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.232442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.232461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.232481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.232502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.232523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.232543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.232561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.232578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.232601] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  773.232621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.234740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.234761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.234779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.234799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.236389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.236411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.236430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.237981] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.238003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.239880] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.243195] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  773.243260] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.243290] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  773.243329] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.243403] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  773.243433] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  773.260045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.260095] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.260258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.276857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.276895] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.276935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.276980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.277019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.277059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.277099] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.277219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.277268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.277313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.277361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.277378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.277423] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.277435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.277483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.277524] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.277568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.277609] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.277670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.277696] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.277726] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  773.277752] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.277779] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.277809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.277843] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.293390] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.293435] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.293504] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.311248] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.311291] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.311323] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.311361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.311394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.311425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.311455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.311484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.311515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.311556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.311599] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.311641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.311681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.311719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.311777] [drm:intel_power_well_disable [i915]] disabling display
>[  773.311822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.311864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.311906] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.311951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.311984] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.312077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.312165] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.312308] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.312362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.312417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.312475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.312506] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.312540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.312571] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.312602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.312632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.312661] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.312686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.312693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.312720] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.312726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.312756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.312782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.312809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.312834] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.312866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.312892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.312922] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  773.312947] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.312975] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.313004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.313036] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.313158] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.313190] [drm:intel_power_well_enable [i915]] enabling display
>[  773.313221] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.313271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.313300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.313330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.313358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.313387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.313417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.313450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.313482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.313515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.313544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.313573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.313607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  773.313639] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.315716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.315738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.315757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.315776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.317361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.317384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.317403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.318950] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.318971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.320835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.324184] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  773.324271] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.324303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  773.324345] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.324422] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  773.324455] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  773.324537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.324588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.324649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.341232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.341314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.374395] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.374445] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.374520] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.391681] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.391724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.391757] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.391795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.391829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.391864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.391894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.391933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.391972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.392016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.392058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.392100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.392213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.392260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.392300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.392516] [drm:intel_power_well_disable [i915]] disabling display
>[  773.392544] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.392574] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.392597] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.392718] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.392730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.392788] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.392811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.392833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.392859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.392879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.392901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.392922] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.392948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.392974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.392999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.393024] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.393029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.393055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.393059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.393086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.393143] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.393174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.393202] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.393234] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.393262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.393290] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  773.393317] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.393345] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.393376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.393409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.393665] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.393685] [drm:intel_power_well_enable [i915]] enabling display
>[  773.393703] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.393738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.393760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.393780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.393800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.393818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.393839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.393860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.393881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.393901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.393919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.393937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.393959] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  773.393980] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.396036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.396057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.396080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.396148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.397806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.397826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.397844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.399407] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.399428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.401301] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.404610] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  773.404668] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.404691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  773.404723] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.404784] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  773.404806] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  773.421467] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.421516] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.421581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.421769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.421847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.454791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.454838] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.454908] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.471912] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.471959] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.472000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.472043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.472084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.472209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.472269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.472318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.472366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.472413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.472447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.472478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.472508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.472543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.472582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.472636] [drm:intel_power_well_disable [i915]] disabling display
>[  773.472680] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.472728] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.472764] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.472962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.472978] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.473067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.473109] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.473195] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.473252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.473281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.473313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.473344] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.473375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.473403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.473431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.473457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.473466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.473492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.473500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.473527] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.473554] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.473581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.473607] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.473640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.473669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.473697] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  773.473726] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.473755] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.473788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.473823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.473912] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.473945] [drm:intel_power_well_enable [i915]] enabling display
>[  773.473975] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.474026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.474048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.474068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.474088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.474140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.474170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.474202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.474233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.474264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.474290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.474319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.474351] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  773.474380] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.476442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.476464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.476486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.476510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.478093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.478130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.478148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.479712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.479733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.481619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.484918] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  773.485006] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.485046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  773.485097] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.485491] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  773.485513] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  773.501774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.501820] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.501883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.502157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.502274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.535160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.535211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.535287] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.552290] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.552334] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.552366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.552404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.552437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.552471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.552501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.552530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.552561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.552595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.552627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.552659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.552689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.552717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.552744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.552796] [drm:intel_power_well_disable [i915]] disabling display
>[  773.552836] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.552878] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.552911] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.553200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.553218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.553308] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.553342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.553377] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.553414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.553445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.553478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.553511] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.553543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.553574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.553605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.553635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.553642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.553670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.553677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.553707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.553736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.553765] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.553793] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.553825] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.553855] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.553884] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  773.553913] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.553939] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.553972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.554006] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.554097] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.554156] [drm:intel_power_well_enable [i915]] enabling display
>[  773.554185] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.554236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.554269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.554301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.554332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.554363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.554395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.554430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.554465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.554500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.554530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.554560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.554593] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  773.554625] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.556700] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.556722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.556741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.556761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.558349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.558372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.558391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.559951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.559972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.561847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.565194] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  773.565281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.565323] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  773.565348] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.565407] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  773.565428] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  773.582063] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.582194] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.582268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.582475] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.582552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.615407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.615459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.615533] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.632619] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.632663] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.632694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.632732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.632765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.632807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.632844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.632883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.632921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.632966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.633014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.633045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.633074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.633159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.633198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.633271] [drm:intel_power_well_disable [i915]] disabling display
>[  773.633506] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.633547] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.633577] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.633704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.633719] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.633795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.633824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.633855] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.633892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.633926] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.633961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.633995] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.634030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.634068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.634121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.634150] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.634160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.634188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.634195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.634226] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.634253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.634281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.634307] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.634338] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.634365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.634392] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  773.634418] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.634445] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.634479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.634707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.634766] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.634785] [drm:intel_power_well_enable [i915]] enabling display
>[  773.634803] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.634839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.634860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.634880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.634900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.634918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.634938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.634959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.634979] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.635000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.635018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.635036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.635058] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  773.635079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.637170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.637191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.637209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.637228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.638799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.638820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.638843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.640409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.640430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.642304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.645597] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  773.645684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.645714] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  773.645754] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.645825] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  773.645855] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  773.662469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.662518] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.662583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.662779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.662857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.695814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.695861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.695931] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.712921] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.712968] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.713008] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.713052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.713092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.713221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.713277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.713330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.713382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.713441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.713494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.713544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.713594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.713639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.713685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.713769] [drm:intel_power_well_disable [i915]] disabling display
>[  773.713833] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.713898] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.713945] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.714212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.714229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.714313] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.714334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.714356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.714379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.714397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.714417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.714437] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  773.714456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  773.714475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.714492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.714509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.714513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.714529] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.714533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.714550] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.714566] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.714583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.714599] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  773.714618] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.714634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.714650] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  773.714666] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  773.714682] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  773.714706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.714731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  773.714789] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.714809] [drm:intel_power_well_enable [i915]] enabling display
>[  773.714829] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.714865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.714889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.714913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.714936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.714959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.714982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.715007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.715032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.715056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.715079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.715152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.715187] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  773.715221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.717296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.717317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.717336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.717355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.718914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.718935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.718953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.720506] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.720526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.722399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.725718] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  773.725781] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.725814] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  773.725856] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.725933] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  773.725966] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  773.742563] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.742612] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.742677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.742878] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.742957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.775909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  773.775956] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.776026] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  773.793063] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  773.793139] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  773.793172] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.793209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.793243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.793285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.793325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.793364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.793402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.793446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.793488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.793529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.793571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.793610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.793648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.793704] [drm:intel_power_well_disable [i915]] disabling display
>[  773.793750] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.793800] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  773.793838] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.794048] [drm:drm_mode_addfb2] [FB:58]
>[  773.794135] [drm:drm_mode_addfb2] [FB:78]
>[  773.823513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  773.823626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  773.823705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  773.823770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  773.823781] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.823841] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.823863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.823886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.823910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.823928] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.823949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.823969] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  773.823988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  773.824007] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.824024] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.824041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.824046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.824062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.824114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.824147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.824179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.824209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.824239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  773.824273] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.824303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.824334] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  773.824365] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  773.824395] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  773.824430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.824467] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  773.827752] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.827771] [drm:intel_power_well_enable [i915]] enabling display
>[  773.827788] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.827823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.827844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.827862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.827880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.827897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.827916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.827937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.827955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.827974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.827991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.828007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.828028] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  773.828047] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.830168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.830190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.830209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.830232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.831805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.831825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.831843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.833398] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.833418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.835290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.838640] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  773.838726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.838758] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  773.838795] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.855493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.855541] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  773.855604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.872345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.872383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.872420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.872459] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.872490] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.872524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.872558] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  773.872589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  773.872620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.872649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.872677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.872685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.872712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.872719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.872747] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.872775] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.872802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.872828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  773.872861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.872888] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.872917] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  773.872945] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  773.872971] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  773.873004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.873040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  773.873242] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  773.873307] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.873408] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  773.889989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  773.890027] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.890066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.890188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.890236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.890286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.890333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.890383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.890436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.890487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.890538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.890583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.890629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.890707] [drm:intel_power_well_disable [i915]] disabling display
>[  773.890771] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.890820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.890872] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  773.890923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.890979] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.891103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  773.891123] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.891215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.891248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.891282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.891319] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.891350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.891383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.891416] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  773.891448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  773.891479] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.891509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.891539] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.891546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.891574] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.891581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.891610] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.891639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.891669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.891694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  773.891727] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.891756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.891788] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  773.891817] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  773.891846] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  773.891879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.891913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  773.892007] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.892038] [drm:intel_power_well_enable [i915]] enabling display
>[  773.892068] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.892154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.892187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.892219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.892250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.892281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.892313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.892348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.892383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.892416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.892446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.892476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.892511] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  773.892543] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.894619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.894641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.894660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.894679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.896261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.896281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.896299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.897859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.897879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.899753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.903075] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  773.903192] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.903212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  773.903238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.903319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.903354] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  773.903395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.920147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  773.920232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.936643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  773.936691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  773.936760] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  773.953787] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  773.953824] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  773.953864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.953897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.953931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.953961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.953989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.954021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.954063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.954183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.954237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.954285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.954327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.954373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.954430] [drm:intel_power_well_disable [i915]] disabling display
>[  773.954460] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  773.954493] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  773.954517] [drm:intel_power_well_disable [i915]] disabling always-on
>[  773.954658] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  773.954670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  773.954732] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  773.954759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  773.954785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  773.954814] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  773.954840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  773.954867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  773.954893] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  773.954919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  773.954945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  773.954970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  773.954996] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  773.955001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.955025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  773.955030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  773.955057] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  773.955112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  773.955143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  773.955172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  773.955203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  773.955231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  773.955260] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  773.955287] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  773.955314] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  773.955346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.955378] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  773.955466] [drm:intel_power_well_enable [i915]] enabling always-on
>[  773.955492] [drm:intel_power_well_enable [i915]] enabling display
>[  773.955510] [drm:hsw_set_power_well [i915]] Enabling power well
>[  773.955545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  773.955565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  773.955584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  773.955603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  773.955627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  773.955652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  773.955680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  773.955709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  773.955737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.955763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  773.955788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  773.955815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  773.955841] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  773.957891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  773.957912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  773.957930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.957950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  773.959515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  773.959538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  773.959561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  773.961118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  773.961140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  773.963010] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  773.966347] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  773.966464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  773.966502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  773.966545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  773.983224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  773.983274] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  773.983339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  773.983538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  773.983617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  773.999898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  773.999945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.000014] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  774.017054] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  774.017130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.017175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.017215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.017258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.017298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.017337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.017375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.017418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.017460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.017502] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.017543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.017582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.017621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.017678] [drm:intel_power_well_disable [i915]] disabling display
>[  774.017724] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.017774] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.017810] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.017960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.017971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.018025] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.018045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.018067] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.018147] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.018177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.018209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.018240] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  774.018270] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  774.018299] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.018326] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.018353] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.018361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.018387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.018395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.018422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.018448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.018475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.018501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.018532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.018558] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.018585] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  774.018611] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  774.018641] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  774.018673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.018705] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  774.018779] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.018810] [drm:intel_power_well_enable [i915]] enabling display
>[  774.018841] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.018894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.018925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.018956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.018986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.019016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.019046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.019081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.019132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.019163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.019190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.019216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.019247] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  774.019277] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.021339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.021360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.021378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.021397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.022958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.022977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.022995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.024557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.024578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.026480] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.029812] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  774.029865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.029898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  774.029939] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.046641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.046691] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.046757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.046952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.047031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.063320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  774.063367] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.063436] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  774.080467] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  774.080504] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.080543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.080577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.080611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.080640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.080668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.080700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.080741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.080784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.080826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.080868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.080907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.080946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.081003] [drm:intel_power_well_disable [i915]] disabling display
>[  774.081048] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.081177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.081224] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.081474] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.081486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.081546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.081569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.081592] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.081621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.081646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.081673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.081699] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  774.081726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  774.081752] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.081778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.081803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.081809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.081833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.081838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.081864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.081890] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.081916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.081942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.081968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.081993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.082020] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  774.082045] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  774.082073] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  774.082132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.082166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  774.082255] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.082283] [drm:intel_power_well_enable [i915]] enabling display
>[  774.082315] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.082370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.082403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.082435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.082466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.082496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.082529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.082553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.082573] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.082595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.082613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.082632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.082655] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  774.082675] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.084721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.084742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.084760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.084779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.086341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.086361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.086379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.087926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.087949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.089814] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.093123] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  774.093195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.093228] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  774.093269] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.109971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.110019] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.110154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.110410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.110487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.126648] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  774.126694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.126763] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  774.145021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  774.145058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.145178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.145225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.145279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.145322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.145367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.145412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.145465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.145515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.145564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.145613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.145654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.145699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.145751] [drm:intel_power_well_disable [i915]] disabling display
>[  774.145801] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.145838] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.145868] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.146051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.146106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.146194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.146227] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.146261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.146299] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.146330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.146365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.146397] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  774.146419] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  774.146439] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.146458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.146476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.146481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.146498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.146503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.146520] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.146538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.146556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.146573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.146594] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.146612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.146630] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  774.146647] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  774.146669] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  774.146696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.146723] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  774.146787] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.146808] [drm:intel_power_well_enable [i915]] enabling display
>[  774.146830] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.146869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.146895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.146920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.146946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.146971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.146995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.147023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.147050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.147111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.147144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.147173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.147210] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  774.147240] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.149307] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.149331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.149354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.149378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.150939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.150960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.150982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.152535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.152556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.154433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.157766] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  774.157870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.157905] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  774.157931] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.174648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.174698] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.174764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.174935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.175014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.191301] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  774.191344] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.191410] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  774.208440] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  774.208477] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.208518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.208551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.208586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.208617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.208646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.208678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.208713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.208746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.208776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.208808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.208835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.208863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.208916] [drm:intel_power_well_disable [i915]] disabling display
>[  774.208957] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.208998] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.209029] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.209259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.209278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.209369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.209397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.209422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.209447] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.209468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.209493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.209519] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  774.209546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  774.209572] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.209598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.209624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.209630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.209655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.209660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.209685] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.209711] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.209737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.209762] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.209789] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.209814] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.209841] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  774.209866] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  774.209893] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  774.209919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.209948] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  774.210011] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.210033] [drm:intel_power_well_enable [i915]] enabling display
>[  774.210054] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.210130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.210160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.210190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.210218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.210245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.210274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.210306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.210337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.210368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.210394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.210423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.210456] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  774.210485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.212571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.212592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.212611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.212630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.214227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.214247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.214264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.215823] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.215844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.217720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.221013] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  774.221174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.221223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  774.221283] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.237883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.237933] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.238002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.238321] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.238408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.254581] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  774.254627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.254713] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  774.271710] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  774.271747] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.271787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.271820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.271855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.271886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.271915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.271947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.271982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.272014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.272046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.272152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.272196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.272237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.272523] [drm:intel_power_well_disable [i915]] disabling display
>[  774.272551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.272581] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.272602] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.272733] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.272745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.272802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.272827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.272854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.272883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.272908] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.272935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.272961] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  774.272983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  774.273009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.273034] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.273060] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.273094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.273127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.273135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.273167] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.273196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.273226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.273253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.273283] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.273311] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.273338] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  774.273365] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  774.273391] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  774.273422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.273455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  774.273712] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.273731] [drm:intel_power_well_enable [i915]] enabling display
>[  774.273749] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.273785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.273807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.273827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.273847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.273865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.273886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.273907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.273928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.273948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.273966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.273984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.274006] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  774.274027] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.276103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.276123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.276141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.276160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.277734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.277755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.277772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.279321] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.279342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.281220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.284559] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  774.284655] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.284688] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  774.284731] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.301427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.301475] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.301538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.301731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.301806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.318134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  774.318180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.318249] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  774.335259] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  774.335297] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.335336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.335369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.335404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.335435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.335464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.335496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.335531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.335563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.335594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.335625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.335653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.335680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.335734] [drm:intel_power_well_disable [i915]] disabling display
>[  774.335775] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.335817] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.335847] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.336016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.336027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.336154] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.336185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.336220] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.336258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.336285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.336319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.336349] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  774.336380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  774.336407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.336436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.336462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.336470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.336496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.336503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.336532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.336559] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.336586] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.336612] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.336643] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.336668] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.336697] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  774.336722] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  774.336750] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  774.336779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.336812] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  774.336900] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.336931] [drm:intel_power_well_enable [i915]] enabling display
>[  774.336960] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.337010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.337041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.337093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.337125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.337153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.337185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.337218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.337251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.337284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.337311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.337340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.337375] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  774.337404] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.339469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.339489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.339507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.339526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.341120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.341140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.341158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.342726] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.342747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.344624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.347918] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  774.348007] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.348038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  774.348156] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.364787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.364840] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.364912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.365190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.365309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.381462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  774.381509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.381578] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  774.400012] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  774.400049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.400167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.400215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.400461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.400491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.400518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.400547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.400585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.400622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.400660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.400697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.400731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.400765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.400815] [drm:intel_power_well_disable [i915]] disabling display
>[  774.400855] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.400899] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  774.400931] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.401531] [drm:drm_mode_addfb2] [FB:58]
>[  774.401562] [drm:drm_mode_addfb2] [FB:78]
>[  774.430542] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  774.430650] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  774.430722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.430790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.430801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.430861] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.430883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.430906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.430929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.430948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.430968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.430988] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.431007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.431025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.431043] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.431118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.431126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.431156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.431166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.431196] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.431226] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.431256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.431287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.431320] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.431352] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.431383] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.431413] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.431444] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.431477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.431513] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.434790] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.434809] [drm:intel_power_well_enable [i915]] enabling display
>[  774.434826] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.434861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.434885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.434909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.434933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.434956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.434979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.435005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.435030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.435055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.435139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.435172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.435209] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.435238] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.437312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.437332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.437351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.437369] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.438933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.438953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.438972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.440547] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.440570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.442482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.445823] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.445918] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.445951] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.445993] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.462697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.462748] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.462814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.479507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.479547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.479587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.479629] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.479662] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.479698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.479734] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.479768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.479801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.479833] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.479863] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.479871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.479900] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.479907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.479937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.479967] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.479996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.480025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.480059] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.480167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.480221] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  774.480265] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.480312] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.480366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.480423] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.480578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.480639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.481023] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.498000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.498037] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.498163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.498217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.498270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.498461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.498488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.498515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.498544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.498571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.498597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.498628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.498661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.498709] [drm:intel_power_well_disable [i915]] disabling display
>[  774.498748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.498783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.498819] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.498854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.498882] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.498958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.498973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.499052] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.499143] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.499196] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.499247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.499289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.499334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.499378] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.499422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.499467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.499499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.499530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.499539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.499568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.499576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.499606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.499637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.499668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.499697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.499998] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.500030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.500091] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  774.500121] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.500153] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.500187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.500316] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.500413] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.500441] [drm:intel_power_well_enable [i915]] enabling display
>[  774.500470] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.500518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.500548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.500577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.500605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.500632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.500660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.500691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.500721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.500751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.500778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.500804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.500835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.500864] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.502936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.502957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.502975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.502993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.504577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.504598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.504620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.506270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.506291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.508162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.511510] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.511596] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.511629] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.511670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.511776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.511822] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.511875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.528515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.528600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.545047] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.545125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.545196] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.562201] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.562239] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.562279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.562312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.562346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.562376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.562405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.562437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.562472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.562504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.562535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.562566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.562593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.562620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.562674] [drm:intel_power_well_disable [i915]] disabling display
>[  774.562714] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.562755] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.562786] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.562933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.562948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.563018] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.563051] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.563149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.563198] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.563239] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.563285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.563325] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.563367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.563405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.563445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.563479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.563491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.563527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.563538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.563579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.563614] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.563654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.563689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.563732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.563767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.563806] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.563840] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.563885] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.563920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.563958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.564056] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.564111] [drm:intel_power_well_enable [i915]] enabling display
>[  774.564144] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.564198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.564228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.564261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.564291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.564321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.564351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.564386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.564421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.564455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.564483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.564513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.564546] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.564578] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.566688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.566720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.566749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.566779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.568381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.568411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.568439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.570043] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.570101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.571995] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.575419] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.575476] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.575505] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.575546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.592263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.592315] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.592381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.592592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.592671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.608936] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.608983] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.609054] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.626149] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.626187] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.626227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.626261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.626297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.626328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.626357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.626389] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.626424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.626456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.626488] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.626519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.626547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.626575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.626629] [drm:intel_power_well_disable [i915]] disabling display
>[  774.626669] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.626711] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.626742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.626941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.626958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.627043] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.627144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.627198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.627260] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.627300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.627343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.627385] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.627426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.627465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.627504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.627541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.627553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.627588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.627598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.627635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.627673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.627710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.627747] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.627790] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.627827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.627865] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.628378] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.628410] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.628445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.628481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.628568] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.628605] [drm:intel_power_well_enable [i915]] enabling display
>[  774.628633] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.628681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.628712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.628740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.628769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.628796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.628825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.628856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.628887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.628917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.628944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.628971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.629002] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.629031] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.631135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.631156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.631177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.631201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.632772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.632793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.632811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.634363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.634384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.636257] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.639533] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.639572] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.639592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.639617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.656369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.656421] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.656494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.656696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.656779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.673046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.673128] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.673201] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.690203] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.690241] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.690280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.690314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.690348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.690378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.690407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.690438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.690474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.690506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.690537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.690568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.690596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.690634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.690666] [drm:intel_power_well_disable [i915]] disabling display
>[  774.690694] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.690724] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.690745] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.690879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.690890] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.690945] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.690969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.690993] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.691019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.691042] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.691128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.691168] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.691201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.691235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.691266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.691298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.691306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.691336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.691344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.691374] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.691406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.691437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.691467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.691501] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.691531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.691562] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.691592] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.691623] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.691658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.691693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.692203] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.692233] [drm:intel_power_well_enable [i915]] enabling display
>[  774.692261] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.692311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.692342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.692371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.692400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.692428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.692456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.692488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.692518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.692549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.692576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.692602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.692633] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.692663] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.694738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.694760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.694779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.694798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.696364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.696385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.696403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.697961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.697982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.699854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.703105] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.703172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.703191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.703217] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.719966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.720018] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.720302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.720490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.720569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.736643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.736691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.736760] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.753787] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.753825] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.753865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.753898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.753932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.753970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.754010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.754048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.754178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.754235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.754289] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.754340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.754387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.754434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.754519] [drm:intel_power_well_disable [i915]] disabling display
>[  774.754583] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.754647] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.754697] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.754979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.755021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.755149] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.755183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.755218] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.755255] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.755287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.755320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.755352] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.755384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.755415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.755445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.755474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.755482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.755511] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.755518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.755547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.755576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.755603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.755632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.755664] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.755693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.755720] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.755749] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.755778] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.755811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.755846] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.755934] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.755965] [drm:intel_power_well_enable [i915]] enabling display
>[  774.756003] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.756093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.756129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.756163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.756194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.756225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.756258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.756294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.756327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.756361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.756391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.756422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.756457] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.756489] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.758556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.758576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.758594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.758613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.760272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.760296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.760320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.761875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.761897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.763774] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.767104] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.767156] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.767196] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.767221] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.783944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.783995] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.784147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.784367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.784466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.800642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.800692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.800763] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.817810] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.817847] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.817886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.817919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.817953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.817983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.818011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.818042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.818159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.818212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.818261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.818313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.818359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.818407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.818462] [drm:intel_power_well_disable [i915]] disabling display
>[  774.818504] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.818533] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.818553] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.818690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.818701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.818758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.818779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.818802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.818827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.818847] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.818868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.818889] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.818909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.818928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.818947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.818965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.818970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.818988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.818992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.819011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.819029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.819082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.819108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.819139] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.819165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.819192] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.819218] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.819245] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.819275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.819307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.819396] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.819427] [drm:intel_power_well_enable [i915]] enabling display
>[  774.819457] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.819510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.819542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.819572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.819602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.819632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.819662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.819691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.819712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.819732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.819751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.819775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.819802] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.819829] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.821885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.821907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.821926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.821945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.823519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.823539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.823557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.825154] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.825175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.827037] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.830389] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.830491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.830531] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.830582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.847264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.847314] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.847380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.847583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.847662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.863940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.863988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.864137] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.881145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.881182] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.881222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.881255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.881290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.881320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.881349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.881380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.881422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.881465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.881507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.881549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.881587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.881626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.881684] [drm:intel_power_well_disable [i915]] disabling display
>[  774.881729] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.881775] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.881795] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.881904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.881915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.881967] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.881987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.882008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.882031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.882111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.882144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.882178] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.882207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.882238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.882265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.882294] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.882302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.882330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.882338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.882368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.882395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.882424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.882450] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.882481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.882507] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.882536] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.882563] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.882591] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.882626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.882661] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.883196] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.883228] [drm:intel_power_well_enable [i915]] enabling display
>[  774.883257] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.883310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.883341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.883369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.883398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.883424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.883454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.883487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.883518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.883549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.883575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.883603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.883635] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.883665] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.885738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.885760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.885779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.885799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.887385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.887407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.887427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.888986] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.889008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.890914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.894175] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.894231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.894250] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.894275] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.911028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.911113] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.911180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.911366] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.911445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.927703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.927755] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.927845] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  774.944851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  774.944889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  774.944928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.944962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.944996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.945027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.945133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.945183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.945240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.945295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.945579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.945608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.945633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.945657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.945700] [drm:intel_power_well_disable [i915]] disabling display
>[  774.945735] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  774.945771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.945797] [drm:intel_power_well_disable [i915]] disabling always-on
>[  774.945962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.945976] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  774.946103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  774.946148] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  774.946193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  774.946241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  774.946287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  774.946322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  774.946353] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  774.946384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  774.946414] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  774.946689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  774.946716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  774.946723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.946752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  774.946759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  774.946788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  774.946815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  774.946842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  774.946868] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  774.946899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  774.946925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  774.946954] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  774.946980] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  774.947008] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  774.947037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.947093] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  774.947363] [drm:intel_power_well_enable [i915]] enabling always-on
>[  774.947382] [drm:intel_power_well_enable [i915]] enabling display
>[  774.947399] [drm:hsw_set_power_well [i915]] Enabling power well
>[  774.947432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  774.947452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  774.947471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  774.947488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  774.947506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  774.947524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  774.947544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  774.947563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  774.947581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.947598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  774.947614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  774.947638] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  774.947662] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  774.949867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  774.949890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  774.949913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.949937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  774.951514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  774.951535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  774.951554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  774.953145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  774.953167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  774.955030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  774.958377] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  774.958474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  774.958498] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  774.958530] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  774.975252] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  774.975302] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  774.975368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  774.975566] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  774.975644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  774.991929] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  774.991975] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  774.992133] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  775.009139] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  775.009177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  775.009216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  775.009250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  775.009285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  775.009314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  775.009344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  775.009375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  775.009410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  775.009442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  775.009482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  775.009524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  775.009564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  775.009601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  775.009647] [drm:intel_power_well_disable [i915]] disabling display
>[  775.009681] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  775.009717] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  775.009743] [drm:intel_power_well_disable [i915]] disabling always-on
>[  775.013241] [IGT] kms_flip: exiting, ret=0
>[  775.035948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  775.035987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  775.036026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  775.036115] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  775.036148] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  775.036183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  775.036218] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  775.036251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  775.036282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  775.036313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  775.036342] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  775.036349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  775.036377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  775.036382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  775.036411] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  775.036439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  775.036467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  775.036495] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  775.036529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  775.036557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  775.036585] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  775.036612] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  775.036640] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  775.036674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  775.036711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  775.036813] [drm:intel_power_well_enable [i915]] enabling always-on
>[  775.036845] [drm:intel_power_well_enable [i915]] enabling display
>[  775.036877] [drm:hsw_set_power_well [i915]] Enabling power well
>[  775.036940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  775.036981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  775.037021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  775.037084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  775.037115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  775.037136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  775.037158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  775.037178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  775.037197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  775.037214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  775.037231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  775.037256] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  775.037280] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  775.039347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  775.039366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  775.039384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  775.039402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  775.041001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  775.041023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  775.041056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  775.042620] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  775.042640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  775.044553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  775.048090] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  775.048191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  775.048221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  775.048265] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  775.048345] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  775.048370] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  775.064986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  775.065034] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  775.065144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  775.065389] Console: switching to colour frame buffer device 240x75
>[  775.172681] Console: switching to colour dummy device 80x25
>[  775.172801] [IGT] kms_flip: executing
>[  775.183936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  775.183989] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  775.186151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  775.186192] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  775.188308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  775.188319] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  775.190437] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  775.190476] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  775.192591] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  775.192602] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  775.192610] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  775.192639] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  775.192681] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  775.193806] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  775.194752] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  775.194774] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  775.194792] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  775.194810] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  775.195821] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  775.195846] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  775.196961] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  775.196965] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  775.197175] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  775.197178] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  775.197184] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  775.197186] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  775.197191] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  775.197193] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  775.197203] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  775.197206] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  775.197209] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.197212] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.197215] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  775.197218] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  775.197221] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  775.197224] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  775.197227] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.197230] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.197233] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  775.197236] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  775.197239] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  775.197242] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  775.197245] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  775.197248] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  775.197250] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  775.197253] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  775.197256] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  775.197259] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  775.197262] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  775.197265] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  775.197268] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  775.197271] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  775.197274] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  775.197277] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  775.197280] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  775.197283] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  775.197286] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  775.197289] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  775.197291] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  775.197330] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  775.197353] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  775.199088] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  775.199123] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  775.201119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  775.201130] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  775.203110] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  775.203150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  775.205133] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  775.205144] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  775.205152] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  775.205549] [IGT] kms_flip: starting subtest 2x-flip-vs-modeset
>[  775.208884] [IGT] kms_flip: exiting, ret=77
>[  775.231928] Console: switching to colour frame buffer device 240x75
>[  775.336600] Console: switching to colour dummy device 80x25
>[  775.336717] [IGT] kms_flip: executing
>[  775.347922] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  775.347974] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  775.350118] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  775.350155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  775.352272] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  775.352285] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  775.354404] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  775.354443] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  775.356558] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  775.356570] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  775.356578] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  775.356609] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  775.356651] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  775.357925] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  775.358834] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  775.358857] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  775.358878] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  775.358897] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  775.359905] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  775.359927] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  775.361062] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  775.361066] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  775.361164] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  775.361167] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  775.361172] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  775.361174] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  775.361179] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  775.361181] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  775.361191] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  775.361194] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  775.361197] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.361200] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.361203] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  775.361206] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  775.361209] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  775.361212] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  775.361215] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.361218] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.361221] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  775.361224] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  775.361227] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  775.361230] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  775.361233] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  775.361235] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  775.361238] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  775.361241] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  775.361244] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  775.361247] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  775.361250] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  775.361253] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  775.361256] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  775.361259] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  775.361262] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  775.361265] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  775.361268] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  775.361271] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  775.361273] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  775.361276] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  775.361279] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  775.361318] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  775.361341] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  775.363098] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  775.363136] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  775.365120] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  775.365131] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  775.367251] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  775.367290] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  775.369404] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  775.369426] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  775.369433] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  775.371406] [IGT] kms_flip: starting subtest 2x-absolute-wf_vblank-interruptible
>[  775.373176] [IGT] kms_flip: exiting, ret=77
>[  775.415428] Console: switching to colour frame buffer device 240x75
>[  775.519432] Console: switching to colour dummy device 80x25
>[  775.519549] [IGT] kms_flip: executing
>[  775.530943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  775.530989] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  775.533124] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  775.533166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  775.535107] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  775.535120] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  775.537104] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  775.537146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  775.539262] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  775.539274] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  775.539282] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  775.539313] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  775.539355] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  775.540468] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  775.541394] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  775.541416] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  775.541434] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  775.541452] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  775.542470] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  775.542490] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  775.543605] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  775.543608] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  775.543716] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  775.543719] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  775.543724] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  775.543727] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  775.543731] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  775.543734] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  775.543743] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  775.543746] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  775.543749] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.543752] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.543755] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  775.543758] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  775.543761] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  775.543764] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  775.543767] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.543770] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  775.543773] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  775.543776] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  775.543779] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  775.543782] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  775.543785] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  775.543788] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  775.543791] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  775.543794] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  775.543797] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  775.543800] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  775.543803] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  775.543805] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  775.543808] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  775.543811] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  775.543814] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  775.543817] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  775.543820] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  775.543823] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  775.543826] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  775.543829] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  775.543832] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  775.543870] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  775.543892] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  775.545062] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  775.545088] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  775.547086] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  775.547097] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  775.549087] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  775.549123] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  775.551085] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  775.551095] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  775.551103] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  775.553176] [IGT] kms_flip: starting subtest absolute-wf_vblank-interruptible
>[  775.553781] [drm:drm_mode_addfb2] [FB:77]
>[  775.553809] [drm:drm_mode_addfb2] [FB:79]
>[  775.607522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  775.607587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  775.615398] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  775.615447] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  775.615536] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  775.632555] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  775.632599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  775.632632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  775.632671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  775.632703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  775.632738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  775.632769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  775.632798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  775.632829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  775.632864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  775.632897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  775.632928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  775.632958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  775.632998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  775.633102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  775.633187] [drm:intel_power_well_disable [i915]] disabling display
>[  775.633257] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  775.633325] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  775.633382] [drm:intel_power_well_disable [i915]] disabling always-on
>[  775.633511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  775.633622] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  775.633697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  775.633709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  775.633762] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  775.633784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  775.633808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  775.633833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  775.633853] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  775.633875] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  775.633900] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  775.633926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  775.633953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  775.633979] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  775.634006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  775.634036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  775.634069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  775.634077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  775.634107] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  775.634135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  775.634163] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  775.634190] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  775.634222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  775.634249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  775.634276] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  775.634303] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  775.634330] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  775.634362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  775.634394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  775.637804] [drm:intel_power_well_enable [i915]] enabling always-on
>[  775.637824] [drm:intel_power_well_enable [i915]] enabling display
>[  775.637840] [drm:hsw_set_power_well [i915]] Enabling power well
>[  775.637874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  775.637894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  775.637913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  775.637930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  775.637947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  775.637966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  775.637985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  775.638067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  775.638098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  775.638129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  775.638156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  775.638192] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  775.638226] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  775.640287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  775.640309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  775.640327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  775.640347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  775.641904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  775.641924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  775.641942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  775.643490] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  775.643511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  775.645406] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  775.648749] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  775.648842] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  775.648881] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  775.648907] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  775.648969] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  775.648990] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  775.665619] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  775.665667] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  775.665729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  785.690344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  785.707035] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  785.707085] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  785.707159] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  785.724165] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  785.724214] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  785.724254] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  785.724300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  785.724357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  785.724402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  785.724433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  785.724463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  785.724496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  785.724539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  785.724581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  785.724698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  785.724741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  785.724780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  785.724816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  785.724889] [drm:intel_power_well_disable [i915]] disabling display
>[  785.724951] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  785.725007] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  785.725055] [drm:intel_power_well_disable [i915]] disabling always-on
>[  785.725354] [drm:drm_mode_addfb2] [FB:77]
>[  785.725394] [drm:drm_mode_addfb2] [FB:78]
>[  785.755279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  785.755384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  785.755460] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  785.755531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  785.755543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  785.755662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  785.755698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  785.755735] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  785.755771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  785.755800] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  785.755834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  785.755867] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  785.755889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  785.755910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  785.755929] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  785.755948] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  785.755954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  785.755972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  785.755976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  785.755994] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  785.756013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  785.756031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  785.756049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  785.756070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  785.756089] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  785.756107] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  785.756125] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  785.756143] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  785.756165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  785.756188] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  785.759455] [drm:intel_power_well_enable [i915]] enabling always-on
>[  785.759476] [drm:intel_power_well_enable [i915]] enabling display
>[  785.759496] [drm:hsw_set_power_well [i915]] Enabling power well
>[  785.759536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  785.759561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  785.759586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  785.759676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  785.759709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  785.759741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  785.759777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  785.759811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  785.759844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  785.759874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  785.759904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  785.759935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  785.759956] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  785.762020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  785.762041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  785.762059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  785.762097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  785.763695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  785.763715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  785.763733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  785.765284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  785.765304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  785.767178] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  785.770448] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  785.770504] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  785.770524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  785.770550] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  785.787292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  785.787342] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  785.787408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.812014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.812109] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  795.812161] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  795.812344] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  795.829362] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  795.829410] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  795.829467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.829502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.829538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.829569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.829598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.829630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.829665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.829706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.829749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.829791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.829832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.829851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.829885] [drm:intel_power_well_disable [i915]] disabling display
>[  795.829910] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  795.829937] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  795.829956] [drm:intel_power_well_disable [i915]] disabling always-on
>[  795.830264] [drm:drm_mode_addfb2] [FB:77]
>[  795.830599] [drm:drm_mode_addfb2] [FB:78]
>[  795.859978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  795.860075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  795.860143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  795.860308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  795.860329] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  795.860419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  795.860442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  795.860467] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  795.860495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  795.860517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  795.860542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  795.860566] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  795.860590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  795.860614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  795.860637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  795.860660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  795.860665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.860687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  795.860692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  795.860716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  795.860739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  795.860762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  795.860786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  795.860809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  795.860832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  795.860866] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  795.860889] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  795.860923] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  795.860946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  795.860969] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  795.864389] [drm:intel_power_well_enable [i915]] enabling always-on
>[  795.864410] [drm:intel_power_well_enable [i915]] enabling display
>[  795.864429] [drm:hsw_set_power_well [i915]] Enabling power well
>[  795.864467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  795.864489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  795.864510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  795.864529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  795.864548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  795.864568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  795.864589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  795.864610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  795.864630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  795.864648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  795.864666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  795.864688] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  795.864709] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  795.866795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  795.866817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  795.866836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.866856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  795.868451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  795.868475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  795.868498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  795.870051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  795.870074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  795.871952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  795.875301] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  795.875387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  795.875420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  795.875462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  795.892165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  795.892252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  795.892324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  805.916910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  805.917003] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  805.917049] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  805.917122] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  805.934127] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  805.934164] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  805.934204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  805.934238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  805.934274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  805.934305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  805.934334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  805.934366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  805.934401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  805.934434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  805.934474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  805.934517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  805.934556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  805.934595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  805.934653] [drm:intel_power_well_disable [i915]] disabling display
>[  805.934699] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  805.934751] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  805.934865] [drm:intel_power_well_disable [i915]] disabling always-on
>[  805.936770] [IGT] kms_flip: exiting, ret=0
>[  805.957677] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  805.957715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  805.957753] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  805.957818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  805.957851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  805.957886] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  805.957920] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  805.957957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  805.957983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  805.958007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  805.958030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  805.958036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  805.958059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  805.958063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  805.958087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  805.958110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  805.958132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  805.958154] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  805.958181] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  805.958204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  805.958227] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  805.958249] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  805.958271] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  805.958298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  805.958332] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  805.958418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  805.958446] [drm:intel_power_well_enable [i915]] enabling display
>[  805.958473] [drm:hsw_set_power_well [i915]] Enabling power well
>[  805.958525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  805.958557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  805.958590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  805.958622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  805.958654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  805.958685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  805.958721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  805.958754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  805.958813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  805.958844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  805.958876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  805.958910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  805.958948] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  805.961014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  805.961034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  805.961052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  805.961071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  805.962645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  805.962663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  805.962680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  805.964241] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  805.964260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  805.966156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  805.969212] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  805.969269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  805.969287] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  805.969314] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  805.969379] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  805.969399] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  805.986074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  805.986122] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  805.986191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  805.986428] Console: switching to colour frame buffer device 240x75
>[  806.093377] Console: switching to colour dummy device 80x25
>[  806.093492] [IGT] kms_flip: executing
>[  806.104636] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  806.104689] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  806.106826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  806.106867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  806.108836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  806.108849] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  806.110838] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  806.110880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  806.112840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  806.112851] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  806.112859] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  806.112890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  806.112931] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  806.114053] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  806.114994] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  806.115023] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  806.115049] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  806.115073] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  806.116097] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  806.116119] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  806.117230] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  806.117234] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  806.117331] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  806.117334] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  806.117339] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  806.117341] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  806.117346] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  806.117348] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  806.117357] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  806.117361] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  806.117364] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  806.117367] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  806.117370] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  806.117373] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  806.117376] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  806.117379] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  806.117382] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  806.117385] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  806.117388] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  806.117391] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  806.117394] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  806.117397] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  806.117400] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  806.117403] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  806.117406] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  806.117409] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  806.117412] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  806.117414] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  806.117417] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  806.117420] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  806.117423] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  806.117426] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  806.117429] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  806.117432] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  806.117435] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  806.117438] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  806.117441] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  806.117444] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  806.117447] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  806.117485] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  806.117507] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  806.118806] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  806.118828] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  806.120842] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  806.120853] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  806.122860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  806.122897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  806.124844] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  806.124855] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  806.124863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  806.125250] [IGT] kms_flip: starting subtest blocking-absolute-wf_vblank
>[  806.126241] [drm:drm_mode_addfb2] [FB:58]
>[  806.126285] [drm:drm_mode_addfb2] [FB:79]
>[  806.179619] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  806.179682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  806.186217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  806.186266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  806.186341] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  806.203363] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  806.203407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  806.203440] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  806.203478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  806.203512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  806.203547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  806.203577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  806.203606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  806.203637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  806.203672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  806.203704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  806.203735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  806.203841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  806.203884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  806.203926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  806.204011] [drm:intel_power_well_disable [i915]] disabling display
>[  806.204066] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  806.204119] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  806.204163] [drm:intel_power_well_disable [i915]] disabling always-on
>[  806.204228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  806.204322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  806.204388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  806.204400] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  806.204456] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  806.204479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  806.204502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  806.204531] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  806.204556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  806.204583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  806.204609] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  806.204635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  806.204661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  806.204687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  806.204711] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  806.204717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  806.204744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  806.204785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  806.204819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  806.204849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  806.204877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  806.204906] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  806.204936] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  806.204964] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  806.204991] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  806.205018] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  806.205044] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  806.205075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  806.205107] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  806.208527] [drm:intel_power_well_enable [i915]] enabling always-on
>[  806.208548] [drm:intel_power_well_enable [i915]] enabling display
>[  806.208566] [drm:hsw_set_power_well [i915]] Enabling power well
>[  806.208602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  806.208624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  806.208644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  806.208663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  806.208682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  806.208702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  806.208724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  806.208813] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  806.208849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  806.208880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  806.208911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  806.208947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  806.208979] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  806.211049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  806.211069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  806.211087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  806.211106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  806.212671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  806.212692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  806.212714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  806.214320] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  806.214342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  806.216227] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  806.219542] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  806.219605] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  806.219638] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  806.219681] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  806.219751] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  806.219854] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  806.236375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  806.236421] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  806.236484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  816.261289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  816.277712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  816.277761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  816.277835] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  816.294857] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  816.294902] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  816.294935] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  816.294974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  816.295008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  816.295043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  816.295074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  816.295102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  816.295134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  816.295177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  816.295220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  816.295262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  816.295304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  816.295411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  816.295458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  816.295545] [drm:intel_power_well_disable [i915]] disabling display
>[  816.295616] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  816.295686] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  816.295744] [drm:intel_power_well_disable [i915]] disabling always-on
>[  816.296038] [drm:drm_mode_addfb2] [FB:58]
>[  816.296069] [drm:drm_mode_addfb2] [FB:78]
>[  816.325720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  816.325829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  816.325906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  816.325977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  816.325988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  816.326046] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  816.326069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  816.326092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  816.326116] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  816.326134] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  816.326155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  816.326175] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  816.326194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  816.326212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  816.326230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  816.326246] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  816.326251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  816.326268] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  816.326271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  816.326288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  816.326305] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  816.326376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  816.326403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  816.326435] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  816.326462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  816.326489] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  816.326518] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  816.326544] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  816.326576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  816.326609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  816.329867] [drm:intel_power_well_enable [i915]] enabling always-on
>[  816.329887] [drm:intel_power_well_enable [i915]] enabling display
>[  816.329904] [drm:hsw_set_power_well [i915]] Enabling power well
>[  816.329939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  816.329959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  816.329977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  816.329994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  816.330011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  816.330030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  816.330050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  816.330069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  816.330087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  816.330104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  816.330120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  816.330144] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  816.330168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  816.332232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  816.332255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  816.332273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  816.332293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  816.333909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  816.333929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  816.333947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  816.335535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  816.335558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  816.337424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  816.340732] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  816.340794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  816.340818] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  816.340849] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  816.357587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  816.357637] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  816.357703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  826.382299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  826.382393] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  826.382445] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  826.382523] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  826.399630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  826.399667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  826.399708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  826.399742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  826.399777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  826.399808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  826.399837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  826.399869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  826.399904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  826.400021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  826.400073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  826.400122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  826.400164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  826.400211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  826.400297] [drm:intel_power_well_disable [i915]] disabling display
>[  826.400365] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  826.400404] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  826.400426] [drm:intel_power_well_disable [i915]] disabling always-on
>[  826.400639] [drm:drm_mode_addfb2] [FB:58]
>[  826.400671] [drm:drm_mode_addfb2] [FB:78]
>[  826.429723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  826.429831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  826.429974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  826.430102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  826.430127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  826.430187] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  826.430209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  826.430234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  826.430261] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  826.430284] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  826.430309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  826.430332] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  826.430356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  826.430380] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  826.430403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  826.430425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  826.430430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  826.430455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  826.430462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  826.430493] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  826.430523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  826.430547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  826.430564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  826.430585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  826.430603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  826.430620] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  826.430636] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  826.430653] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  826.430673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  826.430695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  826.433997] [drm:intel_power_well_enable [i915]] enabling always-on
>[  826.434016] [drm:intel_power_well_enable [i915]] enabling display
>[  826.434033] [drm:hsw_set_power_well [i915]] Enabling power well
>[  826.434068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  826.434088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  826.434111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  826.434135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  826.434159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  826.434182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  826.434208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  826.434233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  826.434258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  826.434281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  826.434304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  826.434329] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  826.434352] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  826.436410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  826.436434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  826.436456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  826.436480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  826.438189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  826.438211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  826.438230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  826.439780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  826.439802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  826.441678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  826.445027] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  826.445113] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  826.445146] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  826.445188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  826.461895] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  826.461979] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  826.462048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  836.486820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  836.486999] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  836.487094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  836.487296] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  836.503903] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  836.503940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  836.503981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  836.504015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  836.504051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  836.504081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  836.504120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  836.504160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  836.504205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  836.504248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  836.504290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  836.504333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  836.504372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  836.504411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  836.504470] [drm:intel_power_well_disable [i915]] disabling display
>[  836.504599] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  836.504660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  836.504704] [drm:intel_power_well_disable [i915]] disabling always-on
>[  836.507953] [IGT] kms_flip: exiting, ret=0
>[  836.524312] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  836.524348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  836.524385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  836.524424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  836.524454] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  836.524487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  836.524544] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  836.524574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  836.524604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  836.524631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  836.524658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  836.524665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  836.524691] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  836.524697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  836.524724] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  836.524750] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  836.524776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  836.524801] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  836.524833] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  836.524860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  836.524886] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  836.524911] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  836.524937] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  836.524978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  836.525007] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  836.525092] [drm:intel_power_well_enable [i915]] enabling always-on
>[  836.525117] [drm:intel_power_well_enable [i915]] enabling display
>[  836.525139] [drm:hsw_set_power_well [i915]] Enabling power well
>[  836.525184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  836.525208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  836.525232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  836.525255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  836.525277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  836.525301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  836.525328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  836.525353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  836.525378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  836.525409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  836.525441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  836.525475] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  836.525524] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  836.527612] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  836.527632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  836.527650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  836.527669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  836.529251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  836.529269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  836.529290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  836.530850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  836.530878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  836.532761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  836.536278] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  836.536343] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  836.536376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  836.536420] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  836.536501] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  836.536550] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  836.553133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  836.553182] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  836.553251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  836.553531] Console: switching to colour frame buffer device 240x75
>[  836.658637] Console: switching to colour dummy device 80x25
>[  836.658751] [IGT] kms_flip: executing
>[  836.670373] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  836.670426] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  836.672560] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  836.672596] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  836.674556] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  836.674566] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  836.676561] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  836.676595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  836.678578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  836.678590] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  836.678598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  836.678627] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  836.678670] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  836.679786] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  836.680737] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  836.680760] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  836.680779] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  836.680798] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  836.681825] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  836.681847] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  836.682970] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  836.682974] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  836.683076] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  836.683078] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  836.683083] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  836.683086] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  836.683090] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  836.683093] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  836.683103] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  836.683106] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  836.683109] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  836.683112] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  836.683115] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  836.683118] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  836.683121] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  836.683124] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  836.683127] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  836.683130] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  836.683133] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  836.683136] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  836.683139] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  836.683142] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  836.683145] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  836.683148] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  836.683151] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  836.683154] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  836.683157] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  836.683160] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  836.683163] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  836.683166] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  836.683169] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  836.683172] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  836.683175] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  836.683178] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  836.683181] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  836.683184] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  836.683187] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  836.683190] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  836.683192] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  836.683231] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  836.683254] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  836.684537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  836.684560] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  836.686580] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  836.686591] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  836.688609] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  836.688650] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  836.690578] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  836.690589] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  836.690597] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  836.692712] [IGT] kms_flip: starting subtest dpms-off-confusion-interruptible
>[  836.693232] [drm:drm_mode_addfb2] [FB:77]
>[  836.693260] [drm:drm_mode_addfb2] [FB:79]
>[  836.747335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  836.747399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  836.753270] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  836.753324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  836.753402] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  836.770421] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  836.770465] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  836.770586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  836.770644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  836.770698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  836.770753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  836.770790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  836.770834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  836.770873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  836.770910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  836.770953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  836.770996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  836.771038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  836.771058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  836.771078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  836.771114] [drm:intel_power_well_disable [i915]] disabling display
>[  836.771141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  836.771174] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  836.771199] [drm:intel_power_well_disable [i915]] disabling always-on
>[  836.771272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  836.771365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  836.771446] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  836.771458] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  836.771576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  836.771608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  836.771644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  836.771680] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  836.771708] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  836.771743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  836.771777] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  836.771809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  836.771840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  836.771870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  836.771899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  836.771907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  836.771936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  836.771942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  836.771969] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  836.771994] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  836.772021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  836.772046] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  836.772073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  836.772098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  836.772124] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  836.772150] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  836.772175] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  836.772203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  836.772230] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  836.775581] [drm:intel_power_well_enable [i915]] enabling always-on
>[  836.775601] [drm:intel_power_well_enable [i915]] enabling display
>[  836.775618] [drm:hsw_set_power_well [i915]] Enabling power well
>[  836.775654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  836.775678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  836.775701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  836.775725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  836.775748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  836.775772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  836.775797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  836.775822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  836.775846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  836.775869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  836.775892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  836.775917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  836.775940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  836.777995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  836.778019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  836.778042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  836.778066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  836.779642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  836.779665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  836.779688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  836.781228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  836.781260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  836.783122] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  836.786405] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  836.786445] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  836.786471] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  836.786569] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  836.786661] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  836.786698] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  836.803232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  836.803282] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  836.803351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  846.827956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  846.844493] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  846.844539] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  846.844608] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  846.861628] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  846.861672] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  846.861705] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  846.861744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  846.861778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  846.861813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  846.861844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  846.861873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  846.861905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  846.861940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  846.861973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  846.862005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  846.862036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  846.862074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  846.862191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  846.862277] [drm:intel_power_well_disable [i915]] disabling display
>[  846.862348] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  846.862415] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  846.862472] [drm:intel_power_well_disable [i915]] disabling always-on
>[  846.862790] [drm:drm_mode_addfb2] [FB:77]
>[  846.862819] [drm:drm_mode_addfb2] [FB:78]
>[  846.892385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  846.892487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  846.892558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  846.892626] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  846.892637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  846.892695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  846.892717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  846.892739] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  846.892763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  846.892781] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  846.892801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  846.892821] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  846.892840] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  846.892859] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  846.892876] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  846.892893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  846.892897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  846.892914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  846.892917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  846.892942] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  846.892969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  846.892993] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  846.893016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  846.893041] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  846.893112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  846.893145] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  846.893176] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  846.893206] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  846.893240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  846.893276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  846.896553] [drm:intel_power_well_enable [i915]] enabling always-on
>[  846.896572] [drm:intel_power_well_enable [i915]] enabling display
>[  846.896589] [drm:hsw_set_power_well [i915]] Enabling power well
>[  846.896625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  846.896646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  846.896664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  846.896682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  846.896700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  846.896718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  846.896739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  846.896757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  846.896776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  846.896793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  846.896809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  846.896831] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  846.896849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  846.898910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  846.898931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  846.898953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  846.898977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  846.900546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  846.900569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  846.900592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  846.902166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  846.902187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  846.904058] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  846.907424] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  846.907517] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  846.907547] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  846.907572] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  846.924292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  846.924340] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  846.924404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  856.949038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  856.949123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  856.949166] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  856.949237] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  856.966249] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  856.966287] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  856.966328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  856.966369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  856.966414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  856.966454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  856.966494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  856.966534] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  856.966579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  856.966622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  856.966747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  856.966800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  856.966849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  856.966903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  856.966959] [drm:intel_power_well_disable [i915]] disabling display
>[  856.967004] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  856.967048] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  856.967081] [drm:intel_power_well_disable [i915]] disabling always-on
>[  856.967317] [drm:drm_mode_addfb2] [FB:77]
>[  856.967347] [drm:drm_mode_addfb2] [FB:78]
>[  856.996906] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  856.997013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  856.997087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  856.997158] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  856.997170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  856.997229] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  856.997254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  856.997280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  856.997307] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  856.997330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  856.997355] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  856.997379] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  856.997403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  856.997427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  856.997450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  856.997473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  856.997477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  856.997500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  856.997504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  856.997528] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  856.997551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  856.997575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  856.997598] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  856.997622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  856.997655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  856.997725] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  856.997760] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  856.997795] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  856.997831] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  856.997868] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  857.001207] [drm:intel_power_well_enable [i915]] enabling always-on
>[  857.001228] [drm:intel_power_well_enable [i915]] enabling display
>[  857.001246] [drm:hsw_set_power_well [i915]] Enabling power well
>[  857.001284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  857.001306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  857.001327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  857.001347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  857.001365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  857.001385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  857.001407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  857.001428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  857.001448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  857.001471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  857.001495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  857.001522] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  857.001546] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  857.003615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  857.003645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  857.003717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  857.003750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  857.005309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  857.005329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  857.005347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  857.006901] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  857.006922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  857.008793] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  857.012107] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  857.012173] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  857.012202] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  857.012240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  857.028929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  857.028975] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  857.029039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  867.053688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  867.053775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  867.053822] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  867.053913] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  867.070960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  867.070998] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  867.071039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  867.071080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  867.071124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  867.071165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  867.071205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  867.071244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  867.071369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  867.071427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  867.071472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  867.071517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  867.071554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  867.071593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  867.071665] [drm:intel_power_well_disable [i915]] disabling display
>[  867.071719] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  867.071772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  867.071814] [drm:intel_power_well_disable [i915]] disabling always-on
>[  867.073551] [IGT] kms_flip: exiting, ret=0
>[  867.094132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  867.094171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  867.094211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  867.094297] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  867.094330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  867.094365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  867.094401] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  867.094434] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  867.094466] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  867.094501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  867.094541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  867.094548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  867.094587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  867.094593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  867.094634] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  867.094674] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  867.094713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  867.094753] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  867.094793] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  867.094838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  867.094860] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  867.094879] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  867.094897] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  867.094920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  867.094943] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  867.095021] [drm:intel_power_well_enable [i915]] enabling always-on
>[  867.095040] [drm:intel_power_well_enable [i915]] enabling display
>[  867.095057] [drm:hsw_set_power_well [i915]] Enabling power well
>[  867.095093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  867.095116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  867.095140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  867.095164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  867.095187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  867.095211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  867.095271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  867.095294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  867.095317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  867.095340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  867.095364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  867.095389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  867.095413] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  867.097481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  867.097501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  867.097521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  867.097545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  867.099127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  867.099145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  867.099166] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  867.100752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  867.100771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  867.102653] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  867.106134] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  867.106183] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  867.106209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  867.106267] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  867.106353] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  867.106393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  867.122984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  867.123032] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  867.123101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  867.123388] Console: switching to colour frame buffer device 240x75
>[  867.229923] Console: switching to colour dummy device 80x25
>[  867.230038] [IGT] kms_flip: executing
>[  867.242087] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  867.242132] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  867.243676] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  867.243715] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  867.245322] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  867.245333] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  867.247312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  867.247351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  867.249324] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  867.249335] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  867.249343] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  867.249373] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  867.249416] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  867.250541] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  867.251492] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  867.251514] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  867.251536] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  867.251559] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  867.252577] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  867.252598] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  867.253719] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  867.253723] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  867.253823] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  867.253826] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  867.253831] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  867.253833] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  867.253838] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  867.253841] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  867.253850] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  867.253853] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  867.253856] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.253859] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.253862] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  867.253865] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  867.253868] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  867.253871] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  867.253874] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.253877] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.253880] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  867.253883] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  867.253886] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  867.253889] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  867.253892] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  867.253895] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  867.253898] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  867.253901] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  867.253904] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  867.253907] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  867.253910] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  867.253913] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  867.253916] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  867.253919] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  867.253922] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  867.253925] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  867.253928] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  867.253931] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  867.253933] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  867.253936] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  867.253939] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  867.253977] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  867.254000] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  867.255253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  867.255274] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  867.257325] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  867.257337] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  867.259302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  867.259338] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  867.261330] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  867.261341] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  867.261348] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  867.261766] [IGT] kms_flip: starting subtest 2x-single-buffer-flip-vs-dpms-off-vs-modeset
>[  867.264983] [IGT] kms_flip: exiting, ret=77
>[  867.289945] Console: switching to colour frame buffer device 240x75
>[  867.395643] Console: switching to colour dummy device 80x25
>[  867.395757] [IGT] kms_flip: executing
>[  867.411066] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  867.411112] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  867.412660] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  867.412699] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  867.414314] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  867.414325] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  867.416302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  867.416342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  867.418308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  867.418318] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  867.418327] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  867.418357] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  867.418400] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  867.419525] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  867.420450] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  867.420472] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  867.420490] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  867.420508] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  867.421526] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  867.421547] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  867.422666] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  867.422670] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  867.422773] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  867.422775] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  867.422780] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  867.422783] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  867.422788] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  867.422790] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  867.422799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  867.422803] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  867.422806] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.422809] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.422812] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  867.422815] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  867.422818] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  867.422821] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  867.422824] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.422827] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  867.422830] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  867.422833] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  867.422836] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  867.422838] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  867.422841] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  867.422844] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  867.422847] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  867.422850] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  867.422853] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  867.422856] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  867.422859] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  867.422862] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  867.422865] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  867.422868] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  867.422871] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  867.422874] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  867.422877] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  867.422880] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  867.422883] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  867.422886] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  867.422889] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  867.422926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  867.422949] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  867.424245] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  867.424268] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  867.426316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  867.426327] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  867.428305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  867.428344] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  867.430305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  867.430316] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  867.430323] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  867.432451] [IGT] kms_flip: starting subtest flip-vs-expired-vblank-interruptible
>[  867.433051] [drm:drm_mode_addfb2] [FB:77]
>[  867.433079] [drm:drm_mode_addfb2] [FB:79]
>[  867.487345] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  867.487407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  867.489914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  867.489963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  867.490036] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  867.507072] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  867.507116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  867.507148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  867.507186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  867.507219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  867.507339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  867.507384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  867.507433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  867.507479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  867.507538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  867.507581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  867.507622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  867.507663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  867.507700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  867.507736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  867.507807] [drm:intel_power_well_disable [i915]] disabling display
>[  867.507861] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  867.507915] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  867.507959] [drm:intel_power_well_disable [i915]] disabling always-on
>[  867.508107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  867.508295] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  867.508422] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  867.508448] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  867.508567] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  867.508604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  867.508632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  867.508659] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  867.508680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  867.508704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  867.508727] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  867.508750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  867.508771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  867.508792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  867.508811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  867.508817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  867.508836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  867.508841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  867.508861] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  867.508880] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  867.508899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  867.508918] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  867.508941] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  867.508961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  867.508980] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  867.508999] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  867.509017] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  867.509040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  867.509064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  867.512429] [drm:intel_power_well_enable [i915]] enabling always-on
>[  867.512450] [drm:intel_power_well_enable [i915]] enabling display
>[  867.512468] [drm:hsw_set_power_well [i915]] Enabling power well
>[  867.512505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  867.512527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  867.512548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  867.512568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  867.512587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  867.512607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  867.512638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  867.512660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  867.512681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  867.512700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  867.512719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  867.512743] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  867.512764] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  867.514818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  867.514840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  867.514859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  867.514879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  867.516468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  867.516490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  867.516509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  867.518069] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  867.518091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  867.519955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  867.523330] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  867.523393] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  867.523433] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  867.523484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  867.523568] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  867.523607] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  867.540170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  867.540219] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  867.540378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  877.564932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  877.581466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  877.581516] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  877.581609] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  877.598645] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  877.598690] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  877.598723] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  877.598761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  877.598795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  877.598921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  877.598970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  877.599019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  877.599070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  877.599127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  877.599182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  877.599220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  877.599251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  877.599279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  877.599306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  877.599362] [drm:intel_power_well_disable [i915]] disabling display
>[  877.599415] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  877.599470] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  877.599506] [drm:intel_power_well_disable [i915]] disabling always-on
>[  877.599773] [drm:drm_mode_addfb2] [FB:77]
>[  877.599857] [drm:drm_mode_addfb2] [FB:78]
>[  877.629310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  877.629420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  877.629485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  877.629545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  877.629558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  877.629617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  877.629639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  877.629663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  877.629690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  877.629713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  877.629737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  877.629761] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  877.629784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  877.629865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  877.629900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  877.629933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  877.629942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  877.629973] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  877.629981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  877.630013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  877.630044] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  877.630075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  877.630106] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  877.630142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  877.630172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  877.630203] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  877.630233] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  877.630263] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  877.630297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  877.630331] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  877.633792] [drm:intel_power_well_enable [i915]] enabling always-on
>[  877.633831] [drm:intel_power_well_enable [i915]] enabling display
>[  877.633852] [drm:hsw_set_power_well [i915]] Enabling power well
>[  877.633891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  877.633917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  877.633941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  877.633966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  877.633990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  877.634014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  877.634041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  877.634067] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  877.634092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  877.634116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  877.634140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  877.634166] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  877.634190] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  877.636292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  877.636319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  877.636342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  877.636366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  877.637965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  877.637985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  877.638004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  877.639555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  877.639576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  877.641452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  877.644670] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  877.644717] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  877.644736] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  877.644762] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  877.661508] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  877.661559] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  877.661629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  887.686210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  887.686295] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  887.686338] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  887.686499] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  887.703457] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  887.703489] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  887.703523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  887.703551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  887.703581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  887.703607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  887.703632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  887.703659] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  887.703695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  887.703731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  887.703767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  887.703803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  887.703836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  887.703869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  887.703917] [drm:intel_power_well_disable [i915]] disabling display
>[  887.703957] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  887.704000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  887.704030] [drm:intel_power_well_disable [i915]] disabling always-on
>[  887.704334] [drm:drm_mode_addfb2] [FB:77]
>[  887.704462] [drm:drm_mode_addfb2] [FB:78]
>[  887.737651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  887.737760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  887.737828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  887.737889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  887.737902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  887.737961] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  887.737986] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  887.738011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  887.738038] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  887.738061] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  887.738086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  887.738109] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  887.738133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  887.738157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  887.738180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  887.738203] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  887.738207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  887.738230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  887.738234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  887.738258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  887.738282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  887.738305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  887.738327] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  887.738351] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  887.738374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  887.738447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  887.738481] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  887.738513] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  887.738547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  887.738586] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  887.742027] [drm:intel_power_well_enable [i915]] enabling always-on
>[  887.742049] [drm:intel_power_well_enable [i915]] enabling display
>[  887.742070] [drm:hsw_set_power_well [i915]] Enabling power well
>[  887.742109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  887.742135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  887.742159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  887.742184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  887.742209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  887.742240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  887.742269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  887.742296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  887.742324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  887.742350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  887.742376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  887.742460] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  887.742491] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  887.744567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  887.744590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  887.744613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  887.744637] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  887.746216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  887.746237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  887.746256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  887.747817] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  887.747838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  887.749717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  887.753076] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  887.753151] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  887.753190] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  887.753241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  887.769934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  887.769986] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  887.770059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  897.794706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  897.794793] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  897.794845] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  897.794925] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  897.812040] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  897.812078] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  897.812118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  897.812152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  897.812187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  897.812218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  897.812247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  897.812279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  897.812313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  897.812346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  897.812386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  897.812429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  897.812468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  897.812507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  897.812572] [drm:intel_power_well_disable [i915]] disabling display
>[  897.812635] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  897.812684] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  897.812716] [drm:intel_power_well_disable [i915]] disabling always-on
>[  897.814930] [IGT] kms_flip: exiting, ret=0
>[  897.834824] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  897.834859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  897.834894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  897.834931] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  897.834972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  897.835031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  897.835063] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  897.835093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  897.835123] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  897.835151] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  897.835177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  897.835185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  897.835211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  897.835216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  897.835243] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  897.835280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  897.835318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  897.835356] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  897.835395] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  897.835433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  897.835471] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  897.835509] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  897.835542] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  897.835583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  897.835618] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  897.835679] [drm:intel_power_well_enable [i915]] enabling always-on
>[  897.835697] [drm:intel_power_well_enable [i915]] enabling display
>[  897.835713] [drm:hsw_set_power_well [i915]] Enabling power well
>[  897.835748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  897.835767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  897.835784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  897.835801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  897.835817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  897.835835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  897.835859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  897.835884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  897.835908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  897.835931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  897.835969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  897.836026] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  897.836046] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  897.838110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  897.838129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  897.838146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  897.838165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  897.839740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  897.839758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  897.839775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  897.841338] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  897.841357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  897.843233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  897.846389] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  897.846465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  897.846495] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  897.846546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  897.846648] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  897.846695] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  897.863251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  897.863302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  897.863378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  897.863673] Console: switching to colour frame buffer device 240x75
>[  897.969295] Console: switching to colour dummy device 80x25
>[  897.969411] [IGT] kms_flip: executing
>[  897.980845] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  897.980897] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  897.983021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  897.983057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  897.985149] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  897.985159] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  897.987255] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  897.987289] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  897.989401] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  897.989412] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  897.989420] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  897.989450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  897.989492] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  897.990646] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  897.991571] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  897.991592] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  897.991611] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  897.991629] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  897.992651] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  897.992672] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  897.993790] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  897.993793] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  897.993892] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  897.993895] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  897.993900] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  897.993902] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  897.993907] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  897.993909] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  897.993918] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  897.993922] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  897.993925] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  897.993928] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  897.993931] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  897.993980] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  897.993987] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  897.993993] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  897.994000] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  897.994006] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  897.994012] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  897.994019] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  897.994026] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  897.994032] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  897.994039] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  897.994044] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  897.994049] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  897.994055] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  897.994061] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  897.994066] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  897.994072] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  897.994078] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  897.994083] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  897.994089] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  897.994095] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  897.994103] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  897.994109] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  897.994116] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  897.994122] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  897.994128] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  897.994136] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  897.994202] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  897.994237] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  897.996043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  897.996082] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  897.998050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  897.998061] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  898.000053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  898.000091] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  898.002042] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  898.002053] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  898.002060] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  898.002428] [IGT] kms_flip: starting subtest 2x-wf_vblank
>[  898.006059] [IGT] kms_flip: exiting, ret=77
>[  898.030222] Console: switching to colour frame buffer device 240x75
>[  898.135804] Console: switching to colour dummy device 80x25
>[  898.135916] [IGT] kms_flip: executing
>[  898.147815] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  898.147868] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  898.149021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  898.149057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  898.151036] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  898.151047] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  898.153035] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  898.153078] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  898.155048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  898.155059] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  898.155066] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  898.155095] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  898.155137] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  898.156227] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  898.157147] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  898.157169] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  898.157188] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  898.157205] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  898.158224] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  898.158247] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  898.159360] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  898.159363] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  898.159470] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  898.159473] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  898.159478] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  898.159480] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  898.159485] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  898.159488] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  898.159497] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  898.159500] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.159503] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  898.159506] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  898.159509] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  898.159512] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  898.159515] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  898.159518] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  898.159521] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  898.159524] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  898.159527] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  898.159530] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  898.159533] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  898.159536] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  898.159539] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  898.159542] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  898.159545] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  898.159548] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  898.159551] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  898.159554] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  898.159557] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  898.159560] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  898.159563] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  898.159566] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  898.159568] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  898.159571] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  898.159574] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  898.159577] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  898.159580] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  898.159583] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  898.159586] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  898.159624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  898.159647] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  898.160979] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  898.161001] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  898.163019] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  898.163029] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  898.165045] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  898.165099] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  898.167024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  898.167034] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  898.167041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  898.169045] [IGT] kms_flip: starting subtest flip-vs-dpms-off-vs-modeset-interruptible
>[  898.169636] [drm:drm_mode_addfb2] [FB:77]
>[  898.169665] [drm:drm_mode_addfb2] [FB:79]
>[  898.223626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.223690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.230201] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.230251] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.230340] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.247359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.247404] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.247436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.247475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.247509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.247544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.247575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.247605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.247636] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.247672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.247705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.247737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.247768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.247796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.247823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.247877] [drm:intel_power_well_disable [i915]] disabling display
>[  898.247918] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.248047] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.248101] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.248269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  898.248437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  898.248517] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.248531] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.248585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.248607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.248631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.248656] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.248676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.248702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.248728] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.248754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.248778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.248808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.248841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.248847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.248868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.248872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.248894] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.248913] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.248931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.248987] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.249017] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.249044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.249071] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  898.249098] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.249124] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.249156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.249188] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.252576] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.252595] [drm:intel_power_well_enable [i915]] enabling display
>[  898.252617] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.252653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.252677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.252701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.252725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.252748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.252771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.252797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.252821] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.252846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.252869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.252892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.252917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  898.252941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.255054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.255075] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.255094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.255113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.256679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.256699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.256716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.258266] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.258287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.260146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.263483] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  898.263581] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.263614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  898.263664] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.263723] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  898.263752] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  898.280361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.280410] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.280481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.297195] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.297235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.297274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.297315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.297348] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.297395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.297447] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.297485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.297525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.297564] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.297603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.297610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.297649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.297656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.297696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.297735] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.297774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.297813] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.297853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.297891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.297932] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  898.298059] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.298106] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.298158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.298210] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.313708] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.313757] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.313844] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.330841] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.330889] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.330929] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.331059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.331100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.331133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.331164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.331193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.331231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.331279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.331335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.331370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.331401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.331431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.331484] [drm:intel_power_well_disable [i915]] disabling display
>[  898.331527] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.331558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.331593] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.331637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.331672] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.331778] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.331797] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.331892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.331933] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.332034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.332091] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.332131] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.332163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.332194] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.332224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.332252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.332280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.332307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.332315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.332341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.332349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.332376] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.332403] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.332430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.332456] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.332486] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.332512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.332540] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  898.332568] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.332597] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.332629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.332662] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.332737] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.332757] [drm:intel_power_well_enable [i915]] enabling display
>[  898.332775] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.332809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.332829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.332848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.332866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.332885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.332904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.332926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.332982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.333014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.333041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.333067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.333099] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  898.333128] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.335191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.335213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.335232] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.335251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.336823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.336844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.336862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.338424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.338446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.340341] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.343628] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  898.343720] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.343749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  898.343808] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.343892] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  898.343937] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  898.360508] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.360566] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.360652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.360872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.360947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.393851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.393899] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.394054] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.411232] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.411275] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.411307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.411345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.411377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.411410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.411455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.411495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.411527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.411562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.411603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.411645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.411687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.411712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.411735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.411780] [drm:intel_power_well_disable [i915]] disabling display
>[  898.411814] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.411849] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.411877] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.412527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.412551] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.412631] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.412661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.412697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.412720] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.412739] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.412759] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.412779] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.412797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.412815] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.412832] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.412861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.412865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.412883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.412887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.412914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.412978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.413011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.413037] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.413070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.413096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.413126] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  898.413153] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.413182] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.413217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.413252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.413581] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.413612] [drm:intel_power_well_enable [i915]] enabling display
>[  898.413642] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.413691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.413721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.413751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.413778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.413807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.413835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.413867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.413899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.413931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.413986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.414014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.414050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  898.414079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.416350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.416371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.416390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.416409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.418075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.418095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.418118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.419672] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.419695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.421561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.424878] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  898.424948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.425029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  898.425074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.425150] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  898.425179] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  898.441725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.441774] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.441838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.442158] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.442236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.475070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.475118] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.475188] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.492213] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.492257] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.492290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.492329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.492362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.492397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.492427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.492456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.492487] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.492530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.492561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.492591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.492620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.492645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.492671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.492722] [drm:intel_power_well_disable [i915]] disabling display
>[  898.492760] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.492807] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.492843] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.493199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.493227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.493356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.493401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.493451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.493503] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.493550] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.493583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.493614] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.493647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.493677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.493707] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.493734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.493743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.493770] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.493778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.493808] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.493835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.493863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.493890] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.493923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.493972] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.494001] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  898.494028] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.494057] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.494091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.494126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.494216] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.494247] [drm:intel_power_well_enable [i915]] enabling display
>[  898.494278] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.494327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.494356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.494383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.494411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.494438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.494468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.494500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.494532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.494564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.494590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.494618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.494648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  898.494678] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.496747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.496768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.496787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.496806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.498369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.498388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.498407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.499965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.499987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.501860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.505209] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  898.505297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.505330] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  898.505373] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.505452] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  898.505485] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  898.522079] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.522129] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.522194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.522407] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.522485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.555420] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.555469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.555540] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.572547] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.572594] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.572635] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.572679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.572720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.572763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.572803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.572842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.572883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.572944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.573062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.573098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.573140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.573159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.573179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.573220] [drm:intel_power_well_disable [i915]] disabling display
>[  898.573264] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.573307] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.573343] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.573512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.573525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.573581] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.573604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.573627] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.573651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.573672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.573693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.573714] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.573735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.573755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.573774] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.573792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.573797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.573814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.573818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.573837] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.573855] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.573872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.573890] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.573911] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.573951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.573969] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  898.573988] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.574005] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.574027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.574050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.574119] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.574151] [drm:intel_power_well_enable [i915]] enabling display
>[  898.574172] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.574205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.574230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.574257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.574283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.574309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.574335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.574363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.574390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.574417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.574442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.574469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.574496] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  898.574522] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.576572] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.576596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.576619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.576643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.578219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.578240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.578259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.579825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.579846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.581721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.585057] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  898.585155] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.585188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  898.585230] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.585305] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  898.585341] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  898.601935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.602020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.602091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.602294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.602377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.635282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.635334] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.635425] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.652467] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.652515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.652555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.652600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.652640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.652683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.652723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.652762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.652799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.652842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.652884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.652924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.653017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.653049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.653077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.653134] [drm:intel_power_well_disable [i915]] disabling display
>[  898.653178] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.653222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.653258] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.653396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.653408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.653464] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.653486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.653509] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.653534] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.653555] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.653577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.653598] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.653618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.653639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.653657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.653682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.653688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.653713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.653717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.653743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.653769] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.653795] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.653820] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.653847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.653872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.653898] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  898.653923] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.653978] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.654011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.654046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.654136] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.654166] [drm:intel_power_well_enable [i915]] enabling display
>[  898.654198] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.654251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.654284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.654315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.654346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.654376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.654407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.654441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.654469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.654490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.654509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.654527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.654550] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  898.654575] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.656620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.656644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.656667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.656691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.658269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.658290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.658308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.659866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.659887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.661800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.665107] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  898.665172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.665191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  898.665217] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.665276] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  898.665297] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  898.681998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.682049] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.682114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.682327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.682407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.715310] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.715359] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.715429] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.733866] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.733909] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.734028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.734087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.734139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.734195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.734229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.734259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.734292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.734328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.734360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.734392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.734423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.734453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.734480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.734535] [drm:intel_power_well_disable [i915]] disabling display
>[  898.734576] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.734622] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.734644] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.734786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.734798] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.734852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.734872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.734895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.734951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.734981] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.735014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.735046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  898.735075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  898.735104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.735130] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.735157] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.735166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.735192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.735200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.735227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.735253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.735280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.735308] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  898.735337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.735364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.735391] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  898.735417] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  898.735443] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  898.735473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.735505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  898.735595] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.735627] [drm:intel_power_well_enable [i915]] enabling display
>[  898.735658] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.735709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.735742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.735772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.735803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.735832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.735863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.735897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.735951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.735982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.736009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.736036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.736068] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  898.736097] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.738164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.738185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.738205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.738229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.739791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.739811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.739830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.741382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.741403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.743277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.746637] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  898.746711] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.746744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  898.746786] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.746867] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  898.746888] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  898.763494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.763544] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.763609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.763821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.763900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.796835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  898.796882] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.797031] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  898.814018] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  898.814062] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  898.814094] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.814132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.814165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.814199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.814229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.814258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.814289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.814323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.814355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.814395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.814437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.814476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.814506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.814539] [drm:intel_power_well_disable [i915]] disabling display
>[  898.814563] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.814589] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  898.814609] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.814800] [drm:drm_mode_addfb2] [FB:77]
>[  898.814827] [drm:drm_mode_addfb2] [FB:78]
>[  898.844469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  898.844574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  898.844674] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  898.844737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  898.844750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.844808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.844830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.844852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.844875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.844894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.844967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.845000] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  898.845029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  898.845058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.845085] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.845112] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.845119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.845145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.845153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.845179] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.845208] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.845236] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.845262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  898.845292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.845317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.845346] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  898.845369] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  898.845387] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  898.845409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.845433] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  898.848695] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.848716] [drm:intel_power_well_enable [i915]] enabling display
>[  898.848734] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.848785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.848808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.848838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.848857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.848875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.848895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.848984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.849019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.849053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.849080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.849110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.849145] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  898.849175] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.851255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.851276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.851295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.851314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.852908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.852950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.852979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.854537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.854558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.856465] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.859756] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  898.859846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.859875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  898.859912] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.876625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.876678] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  898.876749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.893448] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.893489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.893528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.893570] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.893603] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.893639] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.893675] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  898.893709] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  898.893741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.893773] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.893803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.893811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.893850] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.893857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.893899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.894017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.894061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.894103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  898.894150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.894193] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.894240] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  898.894280] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  898.894307] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  898.894340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.894373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  898.894458] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  898.894484] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.894540] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  898.910718] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  898.910755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.910799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.910839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.910879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.910919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.911040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.911092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.911141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.911177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.911209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.911240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.911268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.911324] [drm:intel_power_well_disable [i915]] disabling display
>[  898.911366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.911406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.911450] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  898.911494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.911528] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.911630] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  898.911643] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.911700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.911722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.911746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.911771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.911791] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.911813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.911835] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  898.911856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  898.911875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.911901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.911953] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.911962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.911990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.911997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.912025] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.912053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.912080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.912108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  898.912138] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.912165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.912195] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  898.912222] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  898.912248] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  898.912279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.912312] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  898.912403] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.912432] [drm:intel_power_well_enable [i915]] enabling display
>[  898.912452] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.912486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.912507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.912527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.912545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.912564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.912584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.912606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.912626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.912647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.912665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.912684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.912706] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  898.912727] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.914772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.914794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.914812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.914831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.916390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.916413] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.916435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.918032] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.918054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.919918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.923282] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  898.923368] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.923401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  898.923442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  898.940146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.940204] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  898.940270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.940483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  898.940560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.956827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  898.956875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  898.957161] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  898.974188] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  898.974226] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  898.974266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.974299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.974335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.974365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.974394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.974425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  898.974461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.974493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.974524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.974555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.974583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.974611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.974664] [drm:intel_power_well_disable [i915]] disabling display
>[  898.974704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  898.974745] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  898.974776] [drm:intel_power_well_disable [i915]] disabling always-on
>[  898.975102] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  898.975122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  898.975210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  898.975242] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  898.975277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  898.975314] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  898.975345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  898.975378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  898.975411] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  898.975442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  898.975473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  898.975503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  898.975533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  898.975540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.975568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  898.975575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  898.975604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  898.975633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  898.975663] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  898.975692] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  898.975721] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  898.975750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  898.975780] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  898.975809] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  898.975839] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  898.975872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  898.975906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  898.976022] [drm:intel_power_well_enable [i915]] enabling always-on
>[  898.976053] [drm:intel_power_well_enable [i915]] enabling display
>[  898.976084] [drm:hsw_set_power_well [i915]] Enabling power well
>[  898.976135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  898.976168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  898.976199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  898.976230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  898.976260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  898.976291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  898.976325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  898.976358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  898.976390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  898.976420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  898.976449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  898.976482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  898.976514] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  898.978585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  898.978607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  898.978626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.978645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  898.980223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  898.980243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  898.980265] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  898.981829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  898.981850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  898.983725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  898.987068] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  898.987161] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  898.987180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  898.987206] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.003973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.004024] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.004089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.004312] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.004391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.020638] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  899.020686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.020760] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  899.037851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  899.037889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.038014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.038061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.038116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.038159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.038204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.038255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.038304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.038351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.038397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.038443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.038481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.038521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.038600] [drm:intel_power_well_disable [i915]] disabling display
>[  899.038659] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.038716] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.038761] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.039027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.039055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.039185] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.039242] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.039277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.039315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.039340] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.039363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.039384] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  899.039405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  899.039424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.039443] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.039460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.039465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.039482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.039487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.039505] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.039522] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.039539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.039563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.039589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.039614] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.039639] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  899.039664] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  899.039689] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  899.039716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.039743] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  899.039807] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.039829] [drm:intel_power_well_enable [i915]] enabling display
>[  899.039850] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.039889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.039966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.040003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.040032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.040064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.040094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.040128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.040163] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.040197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.040224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.040255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.040290] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  899.040320] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.042412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.042435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.042458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.042482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.044075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.044098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.044116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.045676] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.045697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.047571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.050849] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  899.050902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.051011] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  899.051074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.067679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.067728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.067791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.068141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.068258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.084358] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  899.084409] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.084483] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  899.101512] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  899.101550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.101590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.101622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.101657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.101688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.101726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.101765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.101810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.101852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.101894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.102464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.102515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.102564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.102643] [drm:intel_power_well_disable [i915]] disabling display
>[  899.102682] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.102721] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.102751] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.102941] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.102956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.103031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.103065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.103100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.103138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.103162] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.103185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.103210] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  899.103235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  899.103261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.103286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.103311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.103316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.103340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.103345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.103370] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.103395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.103421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.103446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.103471] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.103496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.103521] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  899.103546] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  899.103571] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  899.103598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.103625] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  899.103688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.103710] [drm:intel_power_well_enable [i915]] enabling display
>[  899.103731] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.103771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.103797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.103822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.103848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.103873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.103898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.103962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.103997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.104032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.104064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.104096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.104132] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  899.104165] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.106241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.106262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.106281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.106300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.107902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.107938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.107957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.109527] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.109550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.111439] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.114753] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  899.114823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.114855] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  899.114902] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.131597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.131644] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.131707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.132014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.132131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.148288] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  899.148335] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.148427] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  899.167013] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  899.167051] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.167091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.167124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.167159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.167198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.167238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.167277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.167321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.167363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.167405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.167446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.167485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.167524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.167582] [drm:intel_power_well_disable [i915]] disabling display
>[  899.167628] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.167678] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.167714] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.168023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.168043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.168134] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.168168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.168203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.168241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.168272] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.168305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.168338] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  899.168370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  899.168402] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.168433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.168462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.168470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.168498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.168505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.168534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.168563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.168592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.168621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.168654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.168683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.168713] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  899.168743] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  899.168773] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  899.168806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.168841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  899.168958] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.168989] [drm:intel_power_well_enable [i915]] enabling display
>[  899.169020] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.169074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.169107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.169139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.169170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.169197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.169230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.169264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.169297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.169329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.169358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.169387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.169422] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  899.169454] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.171524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.171544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.171565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.171589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.173188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.173210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.173229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.174792] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.174814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.176691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.180036] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  899.180110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.180130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  899.180156] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.196906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.196988] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.197054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.197253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.197332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.213580] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  899.213628] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.213696] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  899.230724] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  899.230762] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.230802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.230835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.230869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.230898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.231005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.231051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.231107] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.231160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.231205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.231237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.231266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.231287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.231321] [drm:intel_power_well_disable [i915]] disabling display
>[  899.231348] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.231376] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.231396] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.231524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.231543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.231603] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.231629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.231655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.231684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.231709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.231736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.231761] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  899.231787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  899.231813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.231838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.231864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.231869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.231895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.231930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.231965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.231997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.232026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.232053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.232084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.232111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.232139] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  899.232165] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  899.232192] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  899.232222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.232255] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  899.232344] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.232375] [drm:intel_power_well_enable [i915]] enabling display
>[  899.232405] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.232457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.232490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.232520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.232551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.232581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.232612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.232641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.232664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.232684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.232704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.232722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.232745] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  899.232766] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.234808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.234829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.234848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.234867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.236481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.236501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.236519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.238094] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.238115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.239980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.243281] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  899.243365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.243405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  899.243440] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.260143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.260193] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.260258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.260470] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.260548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.276818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  899.276866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.277018] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  899.294023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  899.294061] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.294101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.294135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.294170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.294200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.294228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.294260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.294295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.294327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.294359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.294390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.294418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.294451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.294496] [drm:intel_power_well_disable [i915]] disabling display
>[  899.294530] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.294565] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.294591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.294787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.294813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.294888] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.294983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.295027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.295076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.295114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.295157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.295197] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  899.295237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  899.295275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.295315] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.295350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.295360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.295398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.295408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.295454] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.295481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.295510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.295536] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.295568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.295595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.295625] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  899.295651] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  899.296112] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  899.296146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.296182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  899.296268] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.296298] [drm:intel_power_well_enable [i915]] enabling display
>[  899.296327] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.296387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.296415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.296443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.296468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.296494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.296520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.296550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.296579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.296609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.296633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.296658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.296689] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  899.296716] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.298788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.298809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.298827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.298847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.300432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.300454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.300477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.302026] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.302049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.303908] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.307255] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  899.307358] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.307390] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  899.307431] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.324129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.324178] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.324241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.324460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.324536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.340810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  899.340856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.341010] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  899.358122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  899.358160] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.358204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.358244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.358288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.358328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.358368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.358405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.358449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.358492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.358533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.358575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.358614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.358652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.358709] [drm:intel_power_well_disable [i915]] disabling display
>[  899.358756] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.358785] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.358805] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.359023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.359044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.359132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.359165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.359198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.359234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.359262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.359294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.359323] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  899.359354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  899.359382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.359411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.359436] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.359444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.359470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.359476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.359505] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.359531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.359560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.359585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.359616] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.359642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.359669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  899.359695] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  899.359722] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  899.359752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.359785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  899.359872] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.359924] [drm:intel_power_well_enable [i915]] enabling display
>[  899.359954] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.360007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.360037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.360067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.360095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.360124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.360153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.360187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.360221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.360254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.360281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.360310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.360344] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  899.360376] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.362482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.362503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.362521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.362540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.364131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.364153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.364172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.365738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.365761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.367639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.370982] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  899.371058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.371077] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  899.371102] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.387864] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.387999] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.388069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.388305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.388409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.404556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  899.404607] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.404685] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  899.421759] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  899.421796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.421836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.421868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.421971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.422021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.422071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.422122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.422179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.422393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.422439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.422484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.422525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.422565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.422635] [drm:intel_power_well_disable [i915]] disabling display
>[  899.422672] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.422710] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  899.422738] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.423313] [drm:drm_mode_addfb2] [FB:77]
>[  899.423347] [drm:drm_mode_addfb2] [FB:78]
>[  899.453006] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  899.453108] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  899.453178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.453245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.453257] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.453315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.453337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.453361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.453388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.453410] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.453435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.453458] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.453482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.453505] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.453528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.453551] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.453556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.453587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.453595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.453623] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.453643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.453661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.453678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.453698] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.453720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.453744] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.453767] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.453791] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.453815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.453841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.457109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.457129] [drm:intel_power_well_enable [i915]] enabling display
>[  899.457146] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.457182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.457202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.457221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.457239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.457256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.457275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.457296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.457315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.457334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.457351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.457367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.457388] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.457408] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.459482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.459504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.459522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.459541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.461127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.461149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.461168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.462731] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.462753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.464626] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.467334] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.467386] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.467405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.467431] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.484162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.484211] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.484281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.501047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.501087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.501126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.501168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.501202] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.501238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.501274] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.501308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.501340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.501372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.501402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.501410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.501439] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.501446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.501490] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.501533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.501577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.501619] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.501667] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.501709] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.501754] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  899.501796] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.501838] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.501887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.501993] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.502100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.502151] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.502231] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.519280] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.519319] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.519359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.519391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.519422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.519451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.519479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.519525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.519572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.519604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.519645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.519684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.519723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.519781] [drm:intel_power_well_disable [i915]] disabling display
>[  899.519827] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.519868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.519991] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.520048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.520100] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.520256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.520276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.520365] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.520395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.520427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.520463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.520491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.520524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.520553] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.520583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.520611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.520640] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.520665] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.520673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.520699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.520706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.520736] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.520762] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.520789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.520814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.520845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.520870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.520928] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  899.520954] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.520983] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.521018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.521053] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.521127] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.521158] [drm:intel_power_well_enable [i915]] enabling display
>[  899.521187] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.521237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.521265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.521294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.521321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.521348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.521376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.521408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.521439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.521470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.521496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.521524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.521558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.521586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.523656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.523679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.523718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.523740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.525314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.525334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.525352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.526921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.526944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.528806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.532171] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.532239] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.532272] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.532314] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.549015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.549075] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.549139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.549365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.549464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.565709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.565759] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.565830] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.582858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.582895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.583025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.583063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.583100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.583131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.583162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.583193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.583230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.583265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.583305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.583349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.583389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.583429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.583487] [drm:intel_power_well_disable [i915]] disabling display
>[  899.583533] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.583587] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.583614] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.583760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.583775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.583844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.583871] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.583939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.583984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.584019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.584059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.584097] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.584134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.584169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.584204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.584237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.584247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.584280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.584289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.584323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.584356] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.584390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.584422] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.584460] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.584493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.584526] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.584568] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.584597] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.584629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.584664] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.584729] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.584749] [drm:intel_power_well_enable [i915]] enabling display
>[  899.584767] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.584803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.584824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.584849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.584876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.584934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.584966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.584999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.585031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.585064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.585094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.585125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.585160] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.585193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.587259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.587280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.587298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.587317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.588881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.588918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.588936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.590507] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.590528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.592442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.595796] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.595869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.595944] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.596001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.612633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.612681] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.612745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.613068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.613160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.629357] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.629406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.629473] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.646481] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.646519] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.646558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.646591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.646626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.646656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.646686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.646718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.646752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.646784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.646814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.646845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.646873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.646969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.647025] [drm:intel_power_well_disable [i915]] disabling display
>[  899.647144] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.647174] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.647194] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.647333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.647346] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.647400] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.647423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.647446] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.647473] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.647499] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.647525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.647551] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.647577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.647604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.647630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.647655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.647661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.647686] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.647690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.647717] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.647742] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.647775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.647807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.647841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.647863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.647916] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.647943] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.647970] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.648003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.648036] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.648301] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.648328] [drm:intel_power_well_enable [i915]] enabling display
>[  899.648359] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.648398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.648420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.648440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.648459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.648478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.648502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.648531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.648560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.648587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.648613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.648638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.648666] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.648692] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.650735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.650756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.650778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.650802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.652375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.652396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.652415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.654089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.654110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.655972] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.659288] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.659339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.659358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.659384] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.676136] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.676188] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.676253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.676501] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.676592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.692835] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.692881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.693145] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.710149] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.710186] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.710225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.710259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.710293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.710323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.710351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.710382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.710416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.710448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.710479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.710509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.710536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.710573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.710631] [drm:intel_power_well_disable [i915]] disabling display
>[  899.710676] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.710727] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.710762] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.711357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.711370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.711428] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.711452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.711479] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.711508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.711533] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.711561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.711587] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.711613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.711639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.711666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.711701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.711709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.711736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.711741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.711767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.711792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.711819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.711844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.711871] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.711931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.711962] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.711991] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.712018] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.712050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.712083] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.712329] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.712352] [drm:intel_power_well_enable [i915]] enabling display
>[  899.712374] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.712414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.712440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.712467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.712493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.712519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.712545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.712573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.712601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.712629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.712654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.712680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.712708] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.712734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.714773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.714794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.714813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.714833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.716409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.716429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.716447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.718101] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.718122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.720004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.723334] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.723390] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.723422] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.723463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.740168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.740220] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.740286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.740484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.740562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.756875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.756980] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.757072] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.774114] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.774150] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.774190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.774223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.774256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.774285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.774313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.774344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.774378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.774410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.774450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.774492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.774531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.774570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.774626] [drm:intel_power_well_disable [i915]] disabling display
>[  899.774673] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.774703] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.774724] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.774852] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.774918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.775025] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.775213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.775238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.775275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.775306] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.775338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.775362] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.775384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.775404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.775424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.775443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.775448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.775466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.775471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.775491] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.775509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.775527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.775545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.775567] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.775585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.775604] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.775622] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.775640] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.775661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.775685] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.775745] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.775764] [drm:intel_power_well_enable [i915]] enabling display
>[  899.775783] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.775817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.775838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.775858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.775906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.775935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.775964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.775996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.776026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.776057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.776083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.776109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.776141] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.776170] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.778485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.778506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.778524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.778543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.780123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.780142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.780160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.781718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.781738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.783612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.786917] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.786980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.786999] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.787025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.803753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.803802] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.803867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.804269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.804359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.820481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.820528] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.820618] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.837680] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.837717] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.837757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.837797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.837841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.837880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.837990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.838040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.838098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.838294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.838328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.838362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.838400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.838440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.838496] [drm:intel_power_well_disable [i915]] disabling display
>[  899.838543] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.838593] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.838630] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.838908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.838938] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.839037] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.839060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.839083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.839107] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.839135] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.839155] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.839179] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.839202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.839226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.839249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.839272] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.839276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.839299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.839304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.839327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.839351] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.839374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.839397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.839420] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.839443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.839467] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.839490] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.839513] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.839538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.839563] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.839621] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.839641] [drm:intel_power_well_enable [i915]] enabling display
>[  899.839660] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.839696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.839720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.839744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.839767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.839790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.839814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.839839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.839864] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.839937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.839970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.839998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.840031] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.840060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.842116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.842137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.842156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.842176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.843746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.843766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.843785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.845339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.845360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.847233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.850558] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.850616] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.850654] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.850702] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.867391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.867443] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.867529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.867753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.867829] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.884103] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.884151] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.884242] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.901303] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.901340] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.901398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.901438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.901481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.901521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.901561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.901598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.901642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.901683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.901724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.901765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.901805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.901843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.901965] [drm:intel_power_well_disable [i915]] disabling display
>[  899.902035] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.902297] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.902318] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.902437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.902450] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.902506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.902529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.902552] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.902577] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.902597] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.902619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.902640] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.902662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.902687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.902713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.902738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.902744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.902769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.902774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.902800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.902826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.902852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.902903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.902937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.902967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.902996] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.903024] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.903050] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.903085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.903117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.903389] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.903409] [drm:intel_power_well_enable [i915]] enabling display
>[  899.903428] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.903476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.903507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.903529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.903554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.903580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.903606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.903635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.903663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.903691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.903717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.903743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.903770] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.903796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.905838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.905859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.905933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.906019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.907573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.907593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.907617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.909186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.909207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.911081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.914425] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.914499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.914519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.914545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.931295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.931346] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.931414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.931629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.931711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.947994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  899.948042] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  899.948132] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  899.965198] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  899.965235] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  899.965279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.965319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.965363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.965403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.965442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.965479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.965522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.965565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.965606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.965648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.965687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.965733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.965777] [drm:intel_power_well_disable [i915]] disabling display
>[  899.965810] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  899.965847] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.965930] [drm:intel_power_well_disable [i915]] disabling always-on
>[  899.966316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.966331] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  899.966402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  899.966435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  899.966468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  899.966505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  899.966536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  899.966570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  899.966602] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  899.966635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  899.966668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  899.966700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  899.966740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  899.966746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.966769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  899.966775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  899.966803] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  899.966835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  899.966859] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  899.966914] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  899.966947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  899.966974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  899.967003] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  899.967030] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  899.967057] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  899.967087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  899.967120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  899.967378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  899.967401] [drm:intel_power_well_enable [i915]] enabling display
>[  899.967422] [drm:hsw_set_power_well [i915]] Enabling power well
>[  899.967462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  899.967488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  899.967515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  899.967541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  899.967568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  899.967593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  899.967621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  899.967647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  899.967675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.967700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  899.967726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  899.967753] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  899.967779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  899.969820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  899.969841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  899.969860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.969927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  899.971586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  899.971607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  899.971625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  899.973186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  899.973207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  899.975080] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  899.978374] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  899.978460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  899.978497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  899.978546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  899.995242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  899.995294] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  899.995365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  899.995585] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  899.995667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.011936] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  900.011981] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  900.012049] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  900.029070] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  900.029108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  900.029147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.029186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.029230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.029266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.029306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.029343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.029387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.029429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.029470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.029511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.029550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.029589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.029646] [drm:intel_power_well_disable [i915]] disabling display
>[  900.029691] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  900.029741] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  900.029777] [drm:intel_power_well_disable [i915]] disabling always-on
>[  900.031629] [IGT] kms_flip: exiting, ret=0
>[  900.052798] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  900.052836] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  900.052874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  900.052950] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  900.052982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  900.053018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  900.053053] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  900.053085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  900.053117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  900.053147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  900.053176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.053183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.053211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.053216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.053245] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  900.053285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  900.053325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.053364] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  900.053410] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.053430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.053449] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  900.053467] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  900.053484] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  900.053505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.053528] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  900.053602] [drm:intel_power_well_enable [i915]] enabling always-on
>[  900.053622] [drm:intel_power_well_enable [i915]] enabling display
>[  900.053640] [drm:hsw_set_power_well [i915]] Enabling power well
>[  900.053674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.053694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.053712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.053730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.053747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.053765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.053786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.053805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.053825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.053842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.053865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.053903] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  900.053926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  900.055996] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  900.056016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  900.056035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.056059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  900.057636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  900.057654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  900.057671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.059233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  900.059252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  900.061128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  900.064375] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  900.064461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  900.064493] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  900.064536] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  900.064618] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  900.064658] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  900.081248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.081297] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.081370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.081657] Console: switching to colour frame buffer device 240x75
>[  900.188683] Console: switching to colour dummy device 80x25
>[  900.188796] [IGT] kms_flip: executing
>[  900.199768] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  900.199821] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  900.201971] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  900.202009] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  900.204124] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  900.204135] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  900.206252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  900.206291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  900.208404] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  900.208415] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  900.208423] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  900.208453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  900.208495] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  900.209608] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  900.210531] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  900.210553] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  900.210572] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  900.210590] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  900.211607] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  900.211627] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  900.212744] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  900.212747] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  900.212895] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  900.212900] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  900.212911] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  900.212915] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  900.212924] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  900.212929] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  900.212945] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  900.212951] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.212957] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  900.212963] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  900.212968] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  900.212974] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  900.212979] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  900.212985] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  900.212990] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  900.212996] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  900.213002] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  900.213008] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  900.213013] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  900.213019] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  900.213024] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  900.213030] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  900.213036] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  900.213042] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  900.213047] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  900.213053] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  900.213058] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  900.213063] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  900.213070] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  900.213075] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  900.213081] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  900.213086] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  900.213091] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  900.213095] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  900.213099] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  900.213102] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  900.213106] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  900.213148] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  900.213172] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  900.214932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  900.214966] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  900.216949] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  900.216959] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  900.218939] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  900.218975] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  900.220955] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  900.220965] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  900.220972] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  900.222818] [IGT] kms_flip: starting subtest vblank-vs-dpms-suspend-interruptible
>[  900.223385] [drm:drm_mode_addfb2] [FB:58]
>[  900.223413] [drm:drm_mode_addfb2] [FB:79]
>[  900.277520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  900.277585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.281390] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  900.281439] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  900.281513] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  900.299791] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  900.299839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  900.299958] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  900.300019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.300072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.300128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.300161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.300201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.300241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.300287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.300330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.300374] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.300416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.300456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.300496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.300554] [drm:intel_power_well_disable [i915]] disabling display
>[  900.300601] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  900.300652] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.300691] [drm:intel_power_well_disable [i915]] disabling always-on
>[  900.300770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  900.300884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  900.301011] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  900.301028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  900.301132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  900.301160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  900.301183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  900.301206] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  900.301225] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  900.301245] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  900.301265] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  900.301284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  900.301302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  900.301319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  900.301336] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.301340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.301357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.301361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.301384] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  900.301408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  900.301439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.301458] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  900.301480] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.301499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.301517] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  900.301534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  900.301551] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  900.301573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.301596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  900.304991] [drm:intel_power_well_enable [i915]] enabling always-on
>[  900.305011] [drm:intel_power_well_enable [i915]] enabling display
>[  900.305028] [drm:hsw_set_power_well [i915]] Enabling power well
>[  900.305061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.305082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.305100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.305118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.305135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.305153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.305173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.305192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.305211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.305227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.305255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.305278] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  900.305307] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  900.307344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  900.307377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  900.307396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.307417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  900.308982] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  900.309005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  900.309028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.310575] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  900.310596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  900.312461] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  900.315778] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  900.315844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  900.315951] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  900.316018] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  900.316094] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  900.316126] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  900.332621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.332668] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.332731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.366168] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  900.366208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  900.366247] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  900.366289] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  900.366322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  900.366357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  900.366394] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  900.366427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  900.366461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  900.366493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  900.366523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.366530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.366559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.366566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.366596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  900.366626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  900.366655] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.366685] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  900.366720] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.366749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.366779] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  900.366808] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  900.366837] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  900.366959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.367012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  900.382660] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  900.382708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  900.382805] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  900.399853] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  900.399931] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  900.399964] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  900.400007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.400048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.400088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.400128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.400163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.400202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.400244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.400286] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.400327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.400366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.400405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.400462] [drm:intel_power_well_disable [i915]] disabling display
>[  900.400507] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  900.400548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.400590] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.400635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.400668] [drm:intel_power_well_disable [i915]] disabling always-on
>[  900.440385] PM: Syncing filesystems ... done.
>[  900.440632] PM: Preparing system for sleep (mem)
>[  900.441368] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  900.442976] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  900.443992] PM: Suspending system (mem)
>[  900.444100] Suspending console(s) (use no_console_suspend to debug)
>[  900.447074] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  900.447163] sd 0:0:0:0: [sda] Stopping disk
>[  900.447868] e1000e: EEE TX LPI TIMER: 00000011
>[  900.448504] [drm:intel_power_well_enable [i915]] enabling always-on
>[  900.448539] [drm:intel_power_well_enable [i915]] enabling display
>[  900.448574] [drm:hsw_set_power_well [i915]] Enabling power well
>[  900.450484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.450619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.450652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.450693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.450722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.450748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.450774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.450802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.450830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.450874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.450896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.450914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.450932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.450964] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.562116] PM: suspend of devices complete after 116.840 msecs
>[  900.563669] [drm:intel_power_well_disable [i915]] disabling display
>[  900.563739] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  900.563756] [drm:intel_power_well_disable [i915]] disabling always-on
>[  900.563782] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  900.576002] PM: late suspend of devices complete after 13.879 msecs
>[  900.578150] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  900.578471] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  900.590011] PM: noirq suspend of devices complete after 14.000 msecs
>[  900.590388] ACPI: Preparing to enter system sleep state S3
>[  900.614479] PM: Saving platform NVS memory
>[  900.614635] Disabling non-boot CPUs ...
>[  900.627776] smpboot: CPU 1 is now offline
>[  900.642897] Broke affinity for irq 23
>[  900.642904] Broke affinity for irq 42
>[  900.644220] smpboot: CPU 2 is now offline
>[  900.651953] Broke affinity for irq 8
>[  900.651958] Broke affinity for irq 9
>[  900.651964] Broke affinity for irq 23
>[  900.651969] Broke affinity for irq 42
>[  900.651974] Broke affinity for irq 43
>[  900.653018] smpboot: CPU 3 is now offline
>[  900.655874] ACPI: Low-level resume complete
>[  900.656021] PM: Restoring platform NVS memory
>[  900.656562] Suspended for 15.828 seconds
>[  900.656659] Enabling non-boot CPUs ...
>[  900.656795] x86: Booting SMP configuration:
>[  900.656801] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  900.658833]  cache: parent cpu1 should not be sleeping
>[  900.660377] CPU1 is up
>[  900.660491] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  900.661939]  cache: parent cpu2 should not be sleeping
>[  900.662859] CPU2 is up
>[  900.662925] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  900.664217]  cache: parent cpu3 should not be sleeping
>[  900.666126] CPU3 is up
>[  900.675122] ACPI: Waking up from system sleep state S3
>[  900.699421] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  900.699431] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  900.699531] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  900.699853] PM: noirq resume of devices complete after 12.249 msecs
>[  900.704299] hpet1: lost 6136 rtc interrupts
>[  900.705161] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  900.705303] [drm:intel_power_well_enable [i915]] enabling always-on
>[  900.705330] [drm:intel_power_well_enable [i915]] enabling display
>[  900.706897] PM: early resume of devices complete after 2.471 msecs
>[  900.707687] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  900.707732] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  900.707751] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  900.707838] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  900.710965] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  900.713378] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  900.713402] [drm:intel_opregion_setup [i915]] ASLE supported
>[  900.713423] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  900.713442] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  900.713680] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  900.713706] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  900.713737] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  900.713769] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  900.713800] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  900.713831] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  900.714316] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  900.714409] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  900.714434] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  900.714460] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  900.714482] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  900.714508] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  900.714529] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  900.714552] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  900.714574] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  900.714595] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  900.714614] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  900.714633] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  900.714655] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  900.714684] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  900.714713] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  900.714740] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  900.714766] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  900.714792] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  900.714835] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  900.714866] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  900.714896] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  900.714930] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  900.714956] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  900.714981] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  900.715018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.715024] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  900.715050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.715054] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  900.715080] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  900.715106] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  900.715132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.715157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  900.715184] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.715209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.715235] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  900.715261] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  900.715284] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  900.715312] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  900.715336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  900.715362] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  900.715387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.715391] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  900.715415] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.715418] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  900.715445] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  900.715470] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  900.715496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.715522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  900.715548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.715573] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.715599] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  900.715625] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  900.715651] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  900.715678] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  900.715704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  900.715729] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  900.715755] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.715759] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  900.715784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.715787] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  900.715814] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  900.715840] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  900.715865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.715891] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  900.715917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.715942] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.715968] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  900.715994] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  900.716033] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  900.716062] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  900.716088] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  900.716114] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  900.716191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  900.716218] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  900.716245] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  900.716274] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  900.716300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  900.716326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  900.716352] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  900.716378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  900.716404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  900.716430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  900.716455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.716460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.716485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.716489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.716516] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  900.716542] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  900.716567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.716593] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  900.716619] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.716645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.716671] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  900.716696] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  900.716722] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  900.716750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.716778] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  900.716939] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  900.716983] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  900.717023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.717050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.717076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.717102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.717129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.717155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  900.717185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  900.717214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.717242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.717270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.717298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.717323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.717348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.717387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.717418] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.717450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.717478] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  900.717509] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  900.717689] sd 0:0:0:0: [sda] Starting disk
>[  900.717771] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  900.717996] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  900.719839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  900.719861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  900.721945] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  900.721954] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  900.724048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  900.724077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  900.726159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  900.726167] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  900.726174] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  900.726206] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  900.727287] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  900.728200] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  900.728221] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  900.728241] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  900.728259] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  900.729280] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  900.729298] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  900.730318] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  900.730345] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  900.732483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  900.732524] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  900.734639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  900.734650] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  900.736767] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  900.736808] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  900.738921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  900.738931] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  900.738938] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  900.920437] PM: resume of devices complete after 213.544 msecs
>[  900.921520] PM: Finishing wakeup.
>[  900.921523] Restarting tasks ... 
>[  900.921806] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  900.921810] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  900.921923] [drm:intel_power_well_disable [i915]] disabling display
>[  900.922034] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  900.922059] [drm:intel_power_well_disable [i915]] disabling always-on
>[  900.923802] done.
>[  900.933777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  900.933815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  900.933852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  900.933890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  900.933921] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  900.933954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  900.933987] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  900.934072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  900.934103] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  900.934135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  900.934165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.934174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.934203] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.934210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.934239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  900.934269] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  900.934298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.934327] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  900.934360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.934389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.934420] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  900.934449] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  900.934477] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  900.934510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.934546] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  900.934633] [drm:intel_power_well_enable [i915]] enabling always-on
>[  900.934666] [drm:intel_power_well_enable [i915]] enabling display
>[  900.934697] [drm:hsw_set_power_well [i915]] Enabling power well
>[  900.934752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.934783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.934814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.934845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.934875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.934906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.934941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.934974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.935024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.935054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.935085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.935119] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  900.935150] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  900.937274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  900.937308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  900.937340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.937373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  900.938986] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  900.939328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  900.939360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  900.940938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  900.940974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  900.942913] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  900.945266] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  900.945343] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  900.945369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  900.945398] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  900.945462] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  900.945483] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  900.945540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.945567] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.945608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.962482] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  900.962520] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  900.962558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  900.962598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  900.962629] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  900.962663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  900.962702] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  900.962742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  900.962782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  900.962821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  900.962860] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  900.962869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.962908] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  900.962915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  900.962955] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  900.963001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  900.963099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  900.963147] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  900.963196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  900.963240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  900.963288] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  900.963330] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  900.963372] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  900.963421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  900.963473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  900.978778] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  900.978827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  900.978905] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  900.996865] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  900.996910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  900.996942] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  900.996982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  900.997085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  900.997131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  900.997179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  900.997226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  900.997272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  900.997329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  900.997384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  900.997427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.997506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  900.997531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  900.997577] [drm:intel_power_well_disable [i915]] disabling display
>[  900.997612] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  900.997639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  900.997668] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  900.997698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  900.997723] [drm:intel_power_well_disable [i915]] disabling always-on
>[  901.026828] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  901.115149] ata1.00: configured for UDMA/133
>[  901.218170] PM: Syncing filesystems ... done.
>[  901.218781] PM: Preparing system for sleep (mem)
>[  901.219375] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  901.221037] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  901.222170] PM: Suspending system (mem)
>[  901.222282] Suspending console(s) (use no_console_suspend to debug)
>[  901.224493] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  901.224579] sd 0:0:0:0: [sda] Stopping disk
>[  901.225693] e1000e: EEE TX LPI TIMER: 00000011
>[  901.226641] [drm:intel_power_well_enable [i915]] enabling always-on
>[  901.226667] [drm:intel_power_well_enable [i915]] enabling display
>[  901.226693] [drm:hsw_set_power_well [i915]] Enabling power well
>[  901.227752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  901.227837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  901.227856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  901.227878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  901.227901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  901.227924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  901.227947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  901.228005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  901.228039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  901.228058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  901.228076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  901.228092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  901.228108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  901.228130] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  901.340244] PM: suspend of devices complete after 116.752 msecs
>[  901.341713] [drm:intel_power_well_disable [i915]] disabling display
>[  901.341757] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  901.341783] [drm:intel_power_well_disable [i915]] disabling always-on
>[  901.341817] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  901.353097] PM: late suspend of devices complete after 12.838 msecs
>[  901.355328] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  901.355462] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  901.367133] PM: noirq suspend of devices complete after 14.029 msecs
>[  901.367510] ACPI: Preparing to enter system sleep state S3
>[  901.392821] PM: Saving platform NVS memory
>[  901.392984] Disabling non-boot CPUs ...
>[  901.406629] smpboot: CPU 1 is now offline
>[  901.418854] Broke affinity for irq 23
>[  901.418861] Broke affinity for irq 42
>[  901.420184] smpboot: CPU 2 is now offline
>[  901.426937] Broke affinity for irq 8
>[  901.426942] Broke affinity for irq 9
>[  901.426948] Broke affinity for irq 23
>[  901.426952] Broke affinity for irq 42
>[  901.426957] Broke affinity for irq 43
>[  901.428019] smpboot: CPU 3 is now offline
>[  901.429904] ACPI: Low-level resume complete
>[  901.430053] PM: Restoring platform NVS memory
>[  901.430595] Suspended for 16.228 seconds
>[  901.430697] Enabling non-boot CPUs ...
>[  901.430841] x86: Booting SMP configuration:
>[  901.430847] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  901.432964]  cache: parent cpu1 should not be sleeping
>[  901.434521] CPU1 is up
>[  901.434643] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  901.436133]  cache: parent cpu2 should not be sleeping
>[  901.436979] CPU2 is up
>[  901.437048] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  901.438354]  cache: parent cpu3 should not be sleeping
>[  901.440235] CPU3 is up
>[  901.449201] ACPI: Waking up from system sleep state S3
>[  901.477499] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  901.477508] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  901.477653] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  901.478073] PM: noirq resume of devices complete after 13.056 msecs
>[  901.478751] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  901.478859] [drm:intel_power_well_enable [i915]] enabling always-on
>[  901.478893] [drm:intel_power_well_enable [i915]] enabling display
>[  901.480893] PM: early resume of devices complete after 2.744 msecs
>[  901.481418] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  901.481446] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  901.481482] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  901.481512] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  901.482074] sd 0:0:0:0: [sda] Starting disk
>[  901.486256] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  901.487168] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  901.487194] [drm:intel_opregion_setup [i915]] ASLE supported
>[  901.487220] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  901.487244] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  901.487430] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  901.487455] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  901.487487] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  901.487514] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  901.487547] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  901.487574] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  901.487899] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  901.487987] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  901.488012] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  901.488040] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  901.488065] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  901.488090] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  901.488135] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  901.488160] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  901.488184] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  901.488210] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  901.488229] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  901.488253] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  901.488276] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  901.488300] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  901.488323] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  901.488341] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  901.488362] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  901.488383] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  901.488409] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  901.488433] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  901.488460] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  901.488489] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  901.488509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  901.488542] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  901.488559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  901.488564] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  901.488581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  901.488584] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  901.488601] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  901.488618] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  901.488634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  901.488650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  901.488669] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  901.488685] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  901.488702] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  901.488718] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  901.488734] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  901.488752] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  901.488767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  901.488783] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  901.488798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  901.488802] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  901.488817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  901.488820] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  901.488836] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  901.488851] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  901.488867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  901.488889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  901.488912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  901.488935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  901.488958] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  901.488981] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  901.489005] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  901.489029] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  901.489052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  901.489075] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  901.489097] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  901.489113] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  901.489136] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  901.489140] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  901.489163] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  901.489186] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  901.489209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  901.489232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  901.489254] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  901.489277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  901.489300] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  901.489323] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  901.489343] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  901.489369] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  901.489392] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  901.489415] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  901.489469] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  901.489493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  901.489517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  901.489543] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  901.489566] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  901.489590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  901.489613] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  901.489636] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  901.489660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  901.489683] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  901.489705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  901.489709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  901.489732] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  901.489736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  901.489759] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  901.489782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  901.489805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  901.489828] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  901.489850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  901.489872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  901.489895] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  901.489918] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  901.489941] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  901.489965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  901.489991] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  901.490070] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  901.490152] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  901.490177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  901.490196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  901.490213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  901.490230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  901.490247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  901.490266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  901.490287] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  901.490307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  901.490325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  901.490349] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  901.490374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  901.490397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  901.490420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  901.490446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  901.490473] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  901.490502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  901.490527] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  901.490555] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  901.490668] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  901.490727] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  901.492806] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  901.492826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  901.494906] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  901.494915] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  901.496998] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  901.497029] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  901.499138] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  901.499146] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  901.499154] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  901.499187] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  901.500300] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  901.501242] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  901.501269] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  901.501294] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  901.501317] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  901.502339] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  901.502361] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  901.503308] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  901.503341] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  901.505430] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  901.505461] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  901.507546] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  901.507553] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  901.509641] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  901.509670] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  901.511785] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  901.511795] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  901.511802] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  901.786873] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  901.829474] ata1.00: configured for UDMA/133
>[  902.733861] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  903.019152] PM: resume of devices complete after 1538.317 msecs
>[  903.020159] PM: Finishing wakeup.
>[  903.020162] Restarting tasks ... 
>[  903.020996] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  903.021003] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  903.021180] [drm:intel_power_well_disable [i915]] disabling display
>[  903.021223] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  903.021251] [drm:intel_power_well_disable [i915]] disabling always-on
>[  903.022643] done.
>[  903.028437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.028511] [drm:intel_power_well_enable [i915]] enabling always-on
>[  903.028550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.028584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.028619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.028651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.028682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.028714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.028746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.028781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.028815] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.028847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.028877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.028907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.028951] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  903.028988] [drm:intel_power_well_disable [i915]] disabling always-on
>[  903.029329] [drm:drm_mode_addfb2] [FB:58]
>[  903.029380] [drm:drm_mode_addfb2] [FB:78]
>[  903.078438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  903.078568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  903.078648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  903.078720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  903.078730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  903.078787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  903.078810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  903.078834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  903.078858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  903.078876] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  903.078896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  903.078917] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  903.078935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  903.078954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  903.078971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  903.078988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.078992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.079009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.079013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.079091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  903.079123] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  903.079151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.079178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.079212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.079239] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.079269] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  903.079295] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  903.079325] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  903.079359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.079394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  903.082754] [drm:intel_power_well_enable [i915]] enabling always-on
>[  903.082775] [drm:intel_power_well_enable [i915]] enabling display
>[  903.082794] [drm:hsw_set_power_well [i915]] Enabling power well
>[  903.082831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.082856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.082881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.082905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.082930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.082954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.082981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.083007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.083049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.083128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.083157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.083191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  903.083223] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  903.085288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  903.085308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  903.085326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  903.085345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  903.086893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  903.086918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  903.086943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  903.088504] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  903.088527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  903.090451] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  903.093769] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  903.093827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  903.093852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  903.093893] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  903.110614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.110664] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  903.110729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.144190] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  903.144231] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  903.144271] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  903.144318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  903.144359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  903.144401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  903.144443] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  903.144484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  903.144526] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  903.144567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  903.144607] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.144615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.144655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.144662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.144703] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  903.144743] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  903.144784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.144822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.144864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.144905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.144947] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  903.144988] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  903.145029] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  903.145137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.145194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  903.145329] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  903.145390] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  903.145498] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  903.162566] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  903.162602] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  903.162642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.162675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.162705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.162735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.162763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.162802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.162845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.162887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.162929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.162980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.163019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.163144] [drm:intel_power_well_disable [i915]] disabling display
>[  903.163316] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  903.163342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.163368] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  903.163392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.163413] [drm:intel_power_well_disable [i915]] disabling always-on
>[  903.204675] PM: Syncing filesystems ... done.
>[  903.204950] PM: Preparing system for sleep (mem)
>[  903.205759] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  903.207494] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  903.208992] PM: Suspending system (mem)
>[  903.209131] Suspending console(s) (use no_console_suspend to debug)
>[  903.210952] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  903.211050] sd 0:0:0:0: [sda] Stopping disk
>[  903.212003] e1000e: EEE TX LPI TIMER: 00000011
>[  903.212082] [drm:intel_power_well_enable [i915]] enabling always-on
>[  903.212102] [drm:intel_power_well_enable [i915]] enabling display
>[  903.212121] [drm:hsw_set_power_well [i915]] Enabling power well
>[  903.231275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.231368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.231397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.231423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.231448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.231472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.231499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.231530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.231559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.231586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.231613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.231637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.231661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.231693] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  903.296994] PM: suspend of devices complete after 86.759 msecs
>[  903.298577] [drm:intel_power_well_disable [i915]] disabling display
>[  903.298612] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  903.298628] [drm:intel_power_well_disable [i915]] disabling always-on
>[  903.298653] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  903.310198] PM: late suspend of devices complete after 13.196 msecs
>[  903.312867] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  903.312982] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  903.326091] PM: noirq suspend of devices complete after 15.883 msecs
>[  903.326467] ACPI: Preparing to enter system sleep state S3
>[  903.351472] PM: Saving platform NVS memory
>[  903.351628] Disabling non-boot CPUs ...
>[  903.364403] smpboot: CPU 1 is now offline
>[  903.380234] Broke affinity for irq 23
>[  903.380242] Broke affinity for irq 42
>[  903.381564] smpboot: CPU 2 is now offline
>[  903.394140] Broke affinity for irq 8
>[  903.394145] Broke affinity for irq 9
>[  903.394152] Broke affinity for irq 23
>[  903.394157] Broke affinity for irq 42
>[  903.394162] Broke affinity for irq 43
>[  903.395214] smpboot: CPU 3 is now offline
>[  903.397051] ACPI: Low-level resume complete
>[  903.397198] PM: Restoring platform NVS memory
>[  903.397738] Suspended for 16.034 seconds
>[  903.397835] Enabling non-boot CPUs ...
>[  903.397974] x86: Booting SMP configuration:
>[  903.397980] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  903.400069]  cache: parent cpu1 should not be sleeping
>[  903.401589] CPU1 is up
>[  903.401705] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  903.403170]  cache: parent cpu2 should not be sleeping
>[  903.404050] CPU2 is up
>[  903.404117] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  903.405437]  cache: parent cpu3 should not be sleeping
>[  903.407355] CPU3 is up
>[  903.416333] ACPI: Waking up from system sleep state S3
>[  903.442392] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  903.442398] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  903.442470] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  903.442732] PM: noirq resume of devices complete after 13.733 msecs
>[  903.442938] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  903.443010] [drm:intel_power_well_enable [i915]] enabling always-on
>[  903.443035] [drm:intel_power_well_enable [i915]] enabling display
>[  903.445506] PM: early resume of devices complete after 2.728 msecs
>[  903.445785] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  903.445846] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  903.445876] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  903.447218] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  903.450905] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  903.451226] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  903.451268] [drm:intel_opregion_setup [i915]] ASLE supported
>[  903.451305] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  903.451342] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  903.451591] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  903.451636] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  903.451665] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  903.451693] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  903.451720] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  903.451747] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  903.452119] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  903.452225] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  903.452251] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  903.452280] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  903.452306] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  903.452334] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  903.452357] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  903.452379] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  903.452408] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  903.452432] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  903.452454] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  903.452472] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  903.452494] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  903.452517] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  903.452540] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  903.452561] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  903.452581] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  903.452602] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  903.452628] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  903.452655] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  903.452681] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  903.452711] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  903.452735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  903.452757] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  903.452779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.452786] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  903.452808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.452812] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  903.452830] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  903.452851] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  903.452873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.452893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.452917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.452938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.452959] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  903.452983] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  903.453005] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  903.453028] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  903.453049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  903.453070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  903.453090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.453095] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  903.453115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.453119] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  903.453140] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  903.453171] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  903.453192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.453212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.453237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.453258] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.453278] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  903.453297] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  903.453314] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  903.453338] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  903.453358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  903.453377] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  903.453397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.453401] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  903.453417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.453422] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  903.453442] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  903.453462] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  903.453482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.453501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.453526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.453545] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.453573] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  903.453592] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  903.453615] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  903.453641] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  903.453664] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  903.453688] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  903.453742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  903.453766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  903.453790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  903.453816] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  903.453839] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  903.453863] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  903.453886] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  903.453909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  903.453933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  903.453955] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  903.453978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.453982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.454004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.454008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.454031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  903.454054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  903.454077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.454100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.454122] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.454145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.454179] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  903.454202] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  903.454224] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  903.454249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.454276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  903.454356] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  903.454390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  903.454414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.454437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.454461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.454484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.454508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.454531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  903.454557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  903.454583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.454608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.454633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.454658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.454681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.454704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.454731] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  903.454759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.454785] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  903.454814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.454838] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  903.454948] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  903.455009] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  903.456505] sd 0:0:0:0: [sda] Starting disk
>[  903.456966] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  903.456991] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  903.459073] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  903.459083] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  903.461205] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  903.461237] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  903.463323] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  903.463331] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  903.463338] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  903.463372] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  903.464481] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  903.465424] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  903.465451] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  903.465475] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  903.465498] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  903.466519] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  903.466540] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  903.467486] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  903.467512] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  903.469629] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  903.469667] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  903.471783] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  903.471793] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  903.473914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  903.473951] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  903.476067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  903.476077] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  903.476084] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  903.668717] PM: resume of devices complete after 223.215 msecs
>[  903.669758] PM: Finishing wakeup.
>[  903.669761] Restarting tasks ... 
>[  903.670045] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  903.670049] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  903.670136] [drm:intel_power_well_disable [i915]] disabling display
>[  903.670194] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  903.670219] [drm:intel_power_well_disable [i915]] disabling always-on
>[  903.671856] done.
>[  903.677035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  903.677072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  903.677109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  903.677147] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  903.679417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  903.679454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  903.679490] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  903.679523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  903.679554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  903.679584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  903.679614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.679623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.679652] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.679659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.679689] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  903.679718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  903.679747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.679776] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.679808] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.679837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.679867] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  903.679896] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  903.679925] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  903.679960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.679996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  903.680132] [drm:intel_power_well_enable [i915]] enabling always-on
>[  903.682438] [drm:intel_power_well_enable [i915]] enabling display
>[  903.682471] [drm:hsw_set_power_well [i915]] Enabling power well
>[  903.682531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.682565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.682598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.682629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.682658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.682690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.682726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.682759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.682792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.682821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.682850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.682884] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  903.682916] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  903.685049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  903.685085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  903.685116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  903.685149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  903.687531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  903.687566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  903.687597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  903.689197] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  903.689233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  903.691338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  903.694465] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  903.694510] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  903.694531] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  903.694558] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  903.694665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.694708] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  903.694772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.711507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  903.711547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  903.711587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  903.711627] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  903.711658] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  903.711693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  903.711728] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  903.711762] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  903.711793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  903.711822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  903.711851] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  903.711859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.711897] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  903.711904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  903.711945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  903.711982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  903.712022] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  903.712060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  903.712100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  903.712145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  903.712396] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  903.712448] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  903.712498] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  903.712551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.712609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  903.712706] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  903.712734] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  903.712798] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  903.728745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  903.728783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  903.728823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.728856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.728895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.728935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.728974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.729013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.729057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.729099] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.729141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.729248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.729296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.729382] [drm:intel_power_well_disable [i915]] disabling display
>[  903.729450] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  903.729504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.729560] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  903.729609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.729642] [drm:intel_power_well_disable [i915]] disabling always-on
>[  903.767708] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  903.785443] ata1.00: configured for UDMA/133
>[  903.820557] PM: Syncing filesystems ... done.
>[  903.820852] PM: Preparing system for sleep (mem)
>[  903.821485] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  903.823302] Freezing remaining freezable tasks ... (elapsed 0.000 seconds) done.
>[  903.824317] PM: Suspending system (mem)
>[  903.824424] Suspending console(s) (use no_console_suspend to debug)
>[  903.826534] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  903.826681] sd 0:0:0:0: [sda] Stopping disk
>[  903.827639] e1000e: EEE TX LPI TIMER: 00000011
>[  903.827719] [drm:intel_power_well_enable [i915]] enabling always-on
>[  903.827748] [drm:intel_power_well_enable [i915]] enabling display
>[  903.827779] [drm:hsw_set_power_well [i915]] Enabling power well
>[  903.839954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  903.840058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  903.840091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  903.840126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  903.840190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  903.840219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  903.840250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  903.840285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  903.840318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  903.840348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  903.840379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  903.840406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  903.840432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  903.840468] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  903.941375] PM: suspend of devices complete after 115.803 msecs
>[  903.942810] [drm:intel_power_well_disable [i915]] disabling display
>[  903.942854] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  903.942881] [drm:intel_power_well_disable [i915]] disabling always-on
>[  903.942915] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  903.954265] PM: late suspend of devices complete after 12.884 msecs
>[  903.956203] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  903.956549] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  903.968274] PM: noirq suspend of devices complete after 14.002 msecs
>[  903.968659] ACPI: Preparing to enter system sleep state S3
>[  903.993839] PM: Saving platform NVS memory
>[  903.993997] Disabling non-boot CPUs ...
>[  904.006709] smpboot: CPU 1 is now offline
>[  904.017265] Broke affinity for irq 23
>[  904.017272] Broke affinity for irq 42
>[  904.018595] smpboot: CPU 2 is now offline
>[  904.024266] Broke affinity for irq 8
>[  904.024270] Broke affinity for irq 9
>[  904.024277] Broke affinity for irq 23
>[  904.024282] Broke affinity for irq 42
>[  904.024287] Broke affinity for irq 43
>[  904.025341] smpboot: CPU 3 is now offline
>[  904.027876] ACPI: Low-level resume complete
>[  904.028020] PM: Restoring platform NVS memory
>[  904.028560] Suspended for 16.371 seconds
>[  904.028664] Enabling non-boot CPUs ...
>[  904.028811] x86: Booting SMP configuration:
>[  904.028817] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  904.031039]  cache: parent cpu1 should not be sleeping
>[  904.032590] CPU1 is up
>[  904.032711] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  904.034188]  cache: parent cpu2 should not be sleeping
>[  904.035105] CPU2 is up
>[  904.035175] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  904.036538]  cache: parent cpu3 should not be sleeping
>[  904.038499] CPU3 is up
>[  904.047299] ACPI: Waking up from system sleep state S3
>[  904.075694] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  904.075703] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  904.076155] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  904.076432] PM: noirq resume of devices complete after 12.700 msecs
>[  904.077071] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  904.077160] [drm:intel_power_well_enable [i915]] enabling always-on
>[  904.077198] [drm:intel_power_well_enable [i915]] enabling display
>[  904.078968] PM: early resume of devices complete after 2.492 msecs
>[  904.079248] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  904.079316] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  904.079336] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  904.080744] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  904.083243] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  904.085417] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  904.085443] [drm:intel_opregion_setup [i915]] ASLE supported
>[  904.085466] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  904.085489] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  904.085679] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  904.085705] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  904.085734] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  904.085763] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  904.085791] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  904.085820] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  904.086132] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  904.086209] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  904.086232] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  904.086263] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  904.086303] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  904.086328] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  904.086352] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  904.086377] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  904.086402] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  904.086428] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  904.086449] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  904.086474] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  904.086510] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  904.086529] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  904.086553] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  904.086577] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  904.086600] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  904.086623] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  904.086651] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  904.086679] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  904.086706] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  904.086736] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  904.086760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  904.086783] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  904.086805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.086810] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.086833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.086836] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.086859] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  904.086883] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  904.086906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.086928] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.086951] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.086974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.086997] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  904.087020] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  904.087043] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  904.087069] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  904.087091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  904.087114] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  904.087136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.087140] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.087162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.087165] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.087188] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  904.087211] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  904.087234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.087257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.087293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.087316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.087339] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  904.087362] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  904.087385] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  904.087411] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  904.087434] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  904.087456] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  904.087479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.087483] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.087505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.087509] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.087532] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  904.087555] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  904.087578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.087601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.087624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.087647] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.087670] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  904.087693] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  904.087713] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  904.087740] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  904.087763] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  904.087786] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  904.087839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  904.087863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  904.087887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  904.087914] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  904.087936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  904.087960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  904.087983] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  904.088006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  904.088030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  904.088053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  904.088075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.088079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.088101] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.088105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.088128] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  904.088152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  904.088175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.088197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.088219] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.088242] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.088265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  904.088304] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  904.088327] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  904.088352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.088378] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  904.088457] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  904.088487] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  904.088508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.088527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.088545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.088562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.088579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.088597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  904.088618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  904.088637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.088656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.088673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.088691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.088707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.088723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.088743] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  904.088770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.088797] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  904.088826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.088850] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  904.088961] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  904.089020] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  904.089965] sd 0:0:0:0: [sda] Starting disk
>[  904.090926] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  904.090954] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  904.093085] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  904.093096] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  904.095215] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  904.095253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  904.097391] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  904.097402] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  904.097409] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  904.097449] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  904.098567] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  904.099570] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  904.099603] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  904.099635] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  904.099667] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  904.100699] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  904.100723] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  904.101669] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  904.101704] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  904.103824] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  904.103865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  904.105979] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  904.105989] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  904.108110] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  904.108148] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  904.110262] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  904.110302] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  904.110309] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  904.272271] PM: resume of devices complete after 193.306 msecs
>[  904.273333] PM: Finishing wakeup.
>[  904.273337] Restarting tasks ... done.
>[  904.281740] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  904.281748] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  904.281898] [drm:intel_power_well_disable [i915]] disabling display
>[  904.281941] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  904.281969] [drm:intel_power_well_disable [i915]] disabling always-on
>[  904.285247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.285341] [drm:intel_power_well_enable [i915]] enabling always-on
>[  904.285380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.285414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.285449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.285480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.285511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.285544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.285577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.285612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.285645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.285678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.285707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.285735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.285778] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  904.285812] [drm:intel_power_well_disable [i915]] disabling always-on
>[  904.286145] [drm:drm_mode_addfb2] [FB:58]
>[  904.286194] [drm:drm_mode_addfb2] [FB:78]
>[  904.329642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  904.329744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  904.329815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  904.329883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  904.329894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  904.329954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  904.329976] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  904.329998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  904.330022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  904.330041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  904.330061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  904.330081] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  904.330100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  904.330118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  904.330136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  904.330153] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.330157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.330174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.330177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.330194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  904.330211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  904.330234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.330257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.330334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.330364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.330393] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  904.330420] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  904.330446] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  904.330478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.330511] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  904.333967] [drm:intel_power_well_enable [i915]] enabling always-on
>[  904.333989] [drm:intel_power_well_enable [i915]] enabling display
>[  904.334010] [drm:hsw_set_power_well [i915]] Enabling power well
>[  904.334049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.334074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.334099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.334123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.334148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.334172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.334199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.334225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.334251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.334341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.334376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.334414] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  904.334447] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  904.336526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  904.336547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  904.336565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  904.336584] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  904.338135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  904.338157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  904.338177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  904.339718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  904.339741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  904.341594] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  904.344883] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  904.344986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  904.345005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  904.345031] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  904.361765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.361817] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  904.361884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.395339] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  904.395380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  904.395419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  904.395461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  904.395494] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  904.395532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  904.395574] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  904.395616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  904.395657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  904.395698] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  904.395738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.395746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.395786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.395793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.395835] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  904.395876] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  904.395916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.395957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.396003] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.396035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.396067] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  904.396095] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  904.396121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  904.396152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.396185] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  904.396321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  904.396372] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  904.396464] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  904.399117] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  904.412979] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  904.413016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  904.413056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.413089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.413120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.413149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.413177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.413208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.413243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.413343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.413392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.413434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.413486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.413540] [drm:intel_power_well_disable [i915]] disabling display
>[  904.413581] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  904.413614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.413648] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  904.413671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.413691] [drm:intel_power_well_disable [i915]] disabling always-on
>[  904.418743] ata1.00: configured for UDMA/133
>[  904.448967] PM: Syncing filesystems ... done.
>[  904.449219] PM: Preparing system for sleep (mem)
>[  904.449807] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  904.451463] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  904.453127] PM: Suspending system (mem)
>[  904.453274] Suspending console(s) (use no_console_suspend to debug)
>[  904.453689] mei mei::bf3cb4da-4045-4f9b-838d-8cbcfb21a107:01: parent 0000:00:16.0 should not be sleeping
>[  904.453816] mei mei::55213584-9a29-4916-badf-0fb7ed682aeb:01: parent 0000:00:16.0 should not be sleeping
>[  904.454968] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  904.455458] sd 0:0:0:0: [sda] Stopping disk
>[  904.456286] e1000e: EEE TX LPI TIMER: 00000011
>[  904.456348] [drm:intel_power_well_enable [i915]] enabling always-on
>[  904.456376] [drm:intel_power_well_enable [i915]] enabling display
>[  904.456405] [drm:hsw_set_power_well [i915]] Enabling power well
>[  904.456752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.456851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.456881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.456914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.456942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.456969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.456998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.457032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.457063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.457093] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.457123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.457150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.457176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.457212] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  904.571495] PM: suspend of devices complete after 117.346 msecs
>[  904.572981] [drm:intel_power_well_disable [i915]] disabling display
>[  904.573010] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  904.573027] [drm:intel_power_well_disable [i915]] disabling always-on
>[  904.573052] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  904.584433] PM: late suspend of devices complete after 12.931 msecs
>[  904.586431] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  904.586705] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  904.598430] PM: noirq suspend of devices complete after 13.989 msecs
>[  904.598808] ACPI: Preparing to enter system sleep state S3
>[  904.623650] PM: Saving platform NVS memory
>[  904.623806] Disabling non-boot CPUs ...
>[  904.636599] smpboot: CPU 1 is now offline
>[  904.650410] Broke affinity for irq 23
>[  904.650418] Broke affinity for irq 42
>[  904.651752] smpboot: CPU 2 is now offline
>[  904.658348] Broke affinity for irq 8
>[  904.658353] Broke affinity for irq 9
>[  904.658359] Broke affinity for irq 23
>[  904.658364] Broke affinity for irq 42
>[  904.658369] Broke affinity for irq 43
>[  904.659417] smpboot: CPU 3 is now offline
>[  904.661312] ACPI: Low-level resume complete
>[  904.661455] PM: Restoring platform NVS memory
>[  904.661995] Suspended for 16.368 seconds
>[  904.662111] Enabling non-boot CPUs ...
>[  904.662256] x86: Booting SMP configuration:
>[  904.662263] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  904.664387]  cache: parent cpu1 should not be sleeping
>[  904.665918] CPU1 is up
>[  904.666032] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  904.667473]  cache: parent cpu2 should not be sleeping
>[  904.668337] CPU2 is up
>[  904.668439] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  904.669742]  cache: parent cpu3 should not be sleeping
>[  904.671684] CPU3 is up
>[  904.680679] ACPI: Waking up from system sleep state S3
>[  904.705809] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  904.705818] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  904.705915] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  904.706376] PM: noirq resume of devices complete after 13.082 msecs
>[  904.707045] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  904.707171] [drm:intel_power_well_enable [i915]] enabling always-on
>[  904.707212] [drm:intel_power_well_enable [i915]] enabling display
>[  904.709404] PM: early resume of devices complete after 2.961 msecs
>[  904.709998] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  904.710055] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  904.710118] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  904.710148] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  904.715695] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  904.716444] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  904.716471] [drm:intel_opregion_setup [i915]] ASLE supported
>[  904.716496] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  904.716521] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  904.716715] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  904.716740] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  904.716768] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  904.716798] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  904.716828] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  904.716857] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  904.716887] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  904.716963] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  904.716989] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  904.717021] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  904.717045] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  904.717073] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  904.717093] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  904.717121] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  904.717148] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  904.717172] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  904.717191] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  904.717213] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  904.717235] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  904.717260] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  904.717285] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  904.717307] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  904.717326] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  904.717356] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  904.717382] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  904.717419] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  904.717439] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  904.717464] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  904.717482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  904.717499] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  904.717516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.717521] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.717537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.717541] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.717557] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  904.717574] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  904.717590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.717605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.717624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.717640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.717656] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  904.717672] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  904.717687] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  904.717704] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  904.717720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  904.717735] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  904.717750] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.717753] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.717775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.717778] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.717802] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  904.717825] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  904.717848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.717871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.717894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.717917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.717940] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  904.717964] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  904.717987] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  904.718011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  904.718034] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  904.718057] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  904.718080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.718083] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.718106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.718109] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  904.718132] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  904.718155] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  904.718178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.718201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.718224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.718247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.718270] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  904.718293] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  904.718316] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  904.718341] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  904.718365] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  904.718388] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  904.718464] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  904.718487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  904.718511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  904.718538] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  904.718560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  904.718584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  904.718607] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  904.718630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  904.718653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  904.718676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  904.718699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.718703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.718725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.718729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.718753] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  904.718776] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  904.718799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.718821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.718845] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.718867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.718891] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  904.718914] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  904.718937] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  904.718961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.718989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  904.719070] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  904.719104] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  904.719128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.719151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.719175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.719198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.719221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.719244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  904.719270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  904.719296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.719321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.719346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.719370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.719393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.719439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.719465] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  904.719489] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  904.719513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.719533] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  904.719556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.719658] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  904.719714] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  904.720455] sd 0:0:0:0: [sda] Starting disk
>[  904.721713] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  904.721736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  904.723506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  904.723517] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  904.725603] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  904.725635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  904.727722] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  904.727730] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  904.727737] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  904.727770] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  904.728870] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  904.729811] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  904.729836] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  904.729858] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  904.729879] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  904.730909] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  904.730928] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  904.731922] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  904.731949] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  904.734058] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  904.734093] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  904.736209] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  904.736219] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  904.738340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  904.738378] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  904.740513] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  904.740523] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  904.740530] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  904.903272] PM: resume of devices complete after 193.870 msecs
>[  904.904201] PM: Finishing wakeup.
>[  904.904204] Restarting tasks ... done.
>[  904.910373] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  904.910403] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  904.910552] [drm:intel_power_well_disable [i915]] disabling display
>[  904.910597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  904.910621] [drm:intel_power_well_disable [i915]] disabling always-on
>[  904.911360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  904.911390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  904.911461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  904.911499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  904.911530] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  904.911566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  904.911600] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  904.911632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  904.911663] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  904.911694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  904.911723] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.911731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.911760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.911767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.911798] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  904.911826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  904.911854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.911894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.911927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.911956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.911987] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  904.912016] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  904.912048] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  904.912082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.912117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  904.912222] [drm:intel_power_well_enable [i915]] enabling always-on
>[  904.912254] [drm:intel_power_well_enable [i915]] enabling display
>[  904.912284] [drm:hsw_set_power_well [i915]] Enabling power well
>[  904.912339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.912371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.912402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.912479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.912508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.912539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.912573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.912603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.912635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.912661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.912690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.912724] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  904.912753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  904.924059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  904.924095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  904.924127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  904.924160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  904.925734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  904.925770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  904.925801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  904.927588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  904.927624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  904.929640] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  904.932805] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  904.932875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  904.932909] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  904.932954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  904.933070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.933114] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  904.933180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.949766] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  904.949791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  904.949816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  904.949845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  904.949870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  904.949896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  904.949921] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  904.949946] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  904.949972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  904.949994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  904.950019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  904.950025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.950049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  904.950054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  904.950079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  904.950102] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  904.950127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  904.950150] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  904.950176] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  904.950201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  904.950228] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  904.950261] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  904.950290] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  904.950318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  904.950349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  904.950645] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  904.950694] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  904.950779] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  904.967017] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  904.967054] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  904.967095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  904.967129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  904.967160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  904.967190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  904.967219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  904.967251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  904.967285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  904.967325] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  904.967367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.967407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  904.967513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  904.967593] [drm:intel_power_well_disable [i915]] disabling display
>[  904.967659] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  904.967707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  904.967741] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  904.967774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  904.967804] [drm:intel_power_well_disable [i915]] disabling always-on
>[  905.033016] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  905.053427] ata1.00: configured for UDMA/133
>[  905.089840] PM: Syncing filesystems ... done.
>[  905.090138] PM: Preparing system for sleep (mem)
>[  905.090704] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  905.092308] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  905.093826] PM: Suspending system (mem)
>[  905.093934] Suspending console(s) (use no_console_suspend to debug)
>[  905.095847] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  905.095938] sd 0:0:0:0: [sda] Stopping disk
>[  905.096943] e1000e: EEE TX LPI TIMER: 00000011
>[  905.097042] [drm:intel_power_well_enable [i915]] enabling always-on
>[  905.097071] [drm:intel_power_well_enable [i915]] enabling display
>[  905.097102] [drm:hsw_set_power_well [i915]] Enabling power well
>[  905.103773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.103881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.103917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.103955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.103987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.104017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.104050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.104087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.104123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.104156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.104189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.104219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.104248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.104288] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  905.135848] PM: suspend of devices complete after 40.727 msecs
>[  905.137482] [drm:intel_power_well_disable [i915]] disabling display
>[  905.137512] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  905.137528] [drm:intel_power_well_disable [i915]] disabling always-on
>[  905.137553] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[  905.149492] PM: late suspend of devices complete after 13.638 msecs
>[  905.151771] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[  905.152063] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[  905.163569] PM: noirq suspend of devices complete after 14.070 msecs
>[  905.163946] ACPI: Preparing to enter system sleep state S3
>[  905.189204] PM: Saving platform NVS memory
>[  905.189360] Disabling non-boot CPUs ...
>[  905.203115] smpboot: CPU 1 is now offline
>[  905.216263] Broke affinity for irq 23
>[  905.216269] Broke affinity for irq 42
>[  905.217618] smpboot: CPU 2 is now offline
>[  905.223337] Broke affinity for irq 8
>[  905.223341] Broke affinity for irq 9
>[  905.223347] Broke affinity for irq 23
>[  905.223352] Broke affinity for irq 42
>[  905.223356] Broke affinity for irq 43
>[  905.224410] smpboot: CPU 3 is now offline
>[  905.226775] ACPI: Low-level resume complete
>[  905.226922] PM: Restoring platform NVS memory
>[  905.227461] Suspended for 16.436 seconds
>[  905.227628] Enabling non-boot CPUs ...
>[  905.227772] x86: Booting SMP configuration:
>[  905.227779] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  905.229951]  cache: parent cpu1 should not be sleeping
>[  905.231457] CPU1 is up
>[  905.231611] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[  905.233064]  cache: parent cpu2 should not be sleeping
>[  905.233941] CPU2 is up
>[  905.234009] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[  905.235315]  cache: parent cpu3 should not be sleeping
>[  905.237165] CPU3 is up
>[  905.246046] ACPI: Waking up from system sleep state S3
>[  905.273861] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[  905.273868] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[  905.274085] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  905.274559] PM: noirq resume of devices complete after 12.669 msecs
>[  905.274845] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[  905.274933] [drm:intel_power_well_enable [i915]] enabling always-on
>[  905.274960] [drm:intel_power_well_enable [i915]] enabling display
>[  905.276942] PM: early resume of devices complete after 2.245 msecs
>[  905.277586] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[  905.277632] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  905.277652] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  905.278359] sd 0:0:0:0: [sda] Starting disk
>[  905.279118] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[  905.282019] rtc_cmos 00:03: System wakeup disabled by ACPI
>[  905.282585] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[  905.282608] [drm:intel_opregion_setup [i915]] ASLE supported
>[  905.282631] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  905.282654] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  905.282857] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  905.282883] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[  905.282912] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  905.282941] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  905.282969] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  905.282992] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  905.283018] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[  905.283097] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[  905.283122] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[  905.283152] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[  905.283177] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[  905.283206] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[  905.283230] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[  905.283258] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  905.283286] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  905.283313] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[  905.283339] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[  905.283364] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[  905.283389] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[  905.283417] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[  905.283445] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[  905.283471] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[  905.283496] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[  905.283522] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[  905.283569] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[  905.283599] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[  905.283629] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[  905.283661] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[  905.283686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  905.283711] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  905.283736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  905.283741] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  905.283766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  905.283770] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  905.283795] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  905.283820] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  905.283845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  905.283869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  905.283894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  905.283918] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  905.283943] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  905.283968] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  905.283993] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  905.284021] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[  905.284046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  905.284071] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  905.284095] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  905.284099] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  905.284123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  905.284127] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  905.284152] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  905.284177] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  905.284202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  905.284227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  905.284252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  905.284277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  905.284302] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  905.284327] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  905.284349] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  905.284376] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[  905.284401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  905.284425] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  905.284450] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  905.284454] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  905.284479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  905.284483] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  905.284508] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  905.284558] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  905.284581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  905.284602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  905.284624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  905.284644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  905.284663] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  905.284687] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  905.284712] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  905.284741] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[  905.284766] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[  905.284791] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[  905.284845] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  905.284866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  905.284889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  905.284913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  905.284932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  905.284953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  905.284974] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  905.284994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  905.285013] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  905.285031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  905.285048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  905.285052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.285069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  905.285073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.285091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  905.285108] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  905.285125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  905.285142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  905.285163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  905.285179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  905.285197] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  905.285213] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  905.285230] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  905.285255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.285285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  905.285384] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[  905.285420] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[  905.285446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.285471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.285496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.285521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.285559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.285584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[  905.285613] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[  905.285641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.285668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.285695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.285721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.285746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.285771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.285800] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  905.285831] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  905.285861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.285890] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  905.285920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.286045] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  905.286374] [drm:intel_opregion_register [i915]] 3 outputs detected
>[  905.288103] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  905.288126] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  905.290203] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  905.290211] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  905.292291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  905.292320] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  905.294395] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  905.294403] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  905.294410] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[  905.294442] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  905.295588] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  905.296564] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  905.296595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  905.296625] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  905.296655] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  905.297680] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  905.297703] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  905.298649] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[  905.298684] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  905.300802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  905.300841] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  905.302956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  905.302966] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  905.305085] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  905.305123] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  905.307241] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  905.307251] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  905.307258] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[  905.467294] PM: resume of devices complete after 190.354 msecs
>[  905.468249] PM: Finishing wakeup.
>[  905.468252] Restarting tasks ... 
>[  905.468473] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[  905.468477] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[  905.468620] [drm:intel_power_well_disable [i915]] disabling display
>[  905.468646] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  905.468661] [drm:intel_power_well_disable [i915]] disabling always-on
>[  905.469820] done.
>[  905.478370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.478443] [drm:intel_power_well_enable [i915]] enabling always-on
>[  905.478482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.478515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.478584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.478616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.478646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.478679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.478712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.478748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.478780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.478814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.478841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.478870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.478912] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  905.478944] [drm:intel_power_well_disable [i915]] disabling always-on
>[  905.481535] [IGT] kms_flip: exiting, ret=0
>[  905.482230] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[  905.494408] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  905.494442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  905.494477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  905.494514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  905.494562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  905.494594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  905.494626] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  905.494655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  905.494685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  905.494713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  905.494741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  905.494747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.494774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  905.494778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.494797] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  905.494814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  905.494831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  905.494848] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  905.494868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  905.494885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  905.494902] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  905.494919] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  905.494935] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  905.494956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.494979] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  905.495047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  905.495066] [drm:intel_power_well_enable [i915]] enabling display
>[  905.495084] [drm:hsw_set_power_well [i915]] Enabling power well
>[  905.495119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.495138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.495156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.495173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.495190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.495209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.495230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.495249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.495268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.495285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.495302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.495324] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  905.495348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  905.497468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  905.497500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  905.497584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  905.497616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  905.499207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  905.499239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  905.499267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  905.500841] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  905.500873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  905.502751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  905.505983] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  905.506069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  905.506088] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  905.506115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  905.506181] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  905.506201] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  905.522850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.522895] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  905.522962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.523212] Console: switching to colour frame buffer device 240x75
>[  905.587249] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  905.608605] ata1.00: configured for UDMA/133
>[  905.699726] Console: switching to colour dummy device 80x25
>[  905.699874] [IGT] kms_flip: executing
>[  905.713120] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  905.713173] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  905.714596] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  905.714631] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  905.716583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  905.716593] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  905.718599] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  905.718638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  905.720604] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  905.720616] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  905.720623] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  905.720652] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  905.720694] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  905.721826] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  905.722779] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  905.722813] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  905.722846] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  905.722879] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  905.723917] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  905.723938] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  905.725056] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  905.725059] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  905.725158] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  905.725160] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  905.725165] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  905.725168] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  905.725173] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  905.725175] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  905.725184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  905.725187] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.725190] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  905.725193] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  905.725196] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  905.725199] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  905.725202] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  905.725205] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  905.725208] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  905.725211] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  905.725214] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  905.725217] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  905.725220] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  905.725223] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  905.725226] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  905.725229] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  905.725232] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  905.725235] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  905.725238] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  905.725241] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  905.725244] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  905.725247] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  905.725250] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  905.725253] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  905.725256] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  905.725259] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  905.725262] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  905.725265] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  905.725268] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  905.725271] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  905.725274] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  905.725311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  905.725334] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  905.726564] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  905.726589] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  905.728623] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  905.728638] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  905.730605] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  905.730643] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  905.732586] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  905.732596] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  905.732603] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  905.734681] [IGT] kms_flip: starting subtest flip-vs-modeset-interruptible
>[  905.735277] [drm:drm_mode_addfb2] [FB:77]
>[  905.735307] [drm:drm_mode_addfb2] [FB:79]
>[  905.789106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  905.789173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.789697] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  905.789734] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  905.789803] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  905.807458] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  905.807502] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  905.807619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  905.807678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.807724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.807777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.807820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.807865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.807909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.807963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.808014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.808063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.808110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.808137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.808165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.808221] [drm:intel_power_well_disable [i915]] disabling display
>[  905.808270] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  905.808308] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  905.808339] [drm:intel_power_well_disable [i915]] disabling always-on
>[  905.808429] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  905.808583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  905.808720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  905.808738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  905.808821] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  905.808854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  905.808879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  905.808902] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  905.808921] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  905.808942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  905.808962] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  905.808981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  905.809004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  905.809026] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  905.809049] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  905.809054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.809077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  905.809081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.809104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  905.809125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  905.809149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  905.809169] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  905.809193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  905.809216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  905.809240] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  905.809263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  905.809287] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  905.809311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.809337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  905.812656] [drm:intel_power_well_enable [i915]] enabling always-on
>[  905.812677] [drm:intel_power_well_enable [i915]] enabling display
>[  905.812697] [drm:hsw_set_power_well [i915]] Enabling power well
>[  905.812735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.812761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.812786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.812810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.812835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.812859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.812885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.812911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.812937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.812961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.812984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.813010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  905.813034] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  905.815160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  905.815183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  905.815202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  905.815221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  905.816787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  905.816808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  905.816826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  905.818374] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  905.818397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  905.820259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  905.823552] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  905.823627] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  905.823647] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  905.823673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  905.823734] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  905.823759] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  905.840427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.840477] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  905.840628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.857120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  905.857139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  905.873933] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  905.874022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.907144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  905.907193] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  905.907281] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  905.924346] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  905.924389] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  905.924422] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  905.924460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.924492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.924616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.924658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.924691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.924723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.924760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.924793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.924825] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.924856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.924885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.924913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.924965] [drm:intel_power_well_disable [i915]] disabling display
>[  905.925006] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  905.925048] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  905.925082] [drm:intel_power_well_disable [i915]] disabling always-on
>[  905.925232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  905.925250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  905.925335] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  905.925369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  905.925404] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  905.925444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  905.925475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  905.925559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  905.925608] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  905.925659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  905.925687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  905.925715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  905.925742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  905.925751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.925777] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  905.925785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  905.925812] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  905.925838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  905.925866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  905.925892] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  905.925923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  905.925949] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  905.925975] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  905.926001] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  905.926028] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  905.926059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.926091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  905.926176] [drm:intel_power_well_enable [i915]] enabling always-on
>[  905.926197] [drm:intel_power_well_enable [i915]] enabling display
>[  905.926215] [drm:hsw_set_power_well [i915]] Enabling power well
>[  905.926248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  905.926268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  905.926288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  905.926306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  905.926325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  905.926344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  905.926366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  905.926386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  905.926409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.926437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  905.926462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  905.926486] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  905.926543] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  905.928627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  905.928651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  905.928674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  905.928698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  905.930273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  905.930295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  905.930313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  905.931881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  905.931905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  905.933776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  905.937042] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  905.937092] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  905.937112] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  905.937138] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  905.937199] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  905.937220] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  905.953881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  905.953932] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  905.954003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  905.954257] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  905.954350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  905.987236] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  905.987284] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  905.987354] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.004372] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.004416] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.004448] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.004486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.004601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.004653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.004703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.004745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.004778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.004813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.004846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.004877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.004908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.004937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.004965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.005020] [drm:intel_power_well_disable [i915]] disabling display
>[  906.005062] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.005103] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.005137] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.005275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.005292] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.005375] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.005410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.005432] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.005457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.005484] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.005619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.005653] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.005685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.005716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.005747] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.005776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.005784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.005813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.005820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.005849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.005868] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.005885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.005903] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.005924] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.005943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.005960] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.005978] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.005995] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.006017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.006040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.006100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.006123] [drm:intel_power_well_enable [i915]] enabling display
>[  906.006145] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.006183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.006209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.006236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.006262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.006288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.006313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.006342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.006370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.006398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.006424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.006449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.006476] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.006535] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.008604] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.008625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.008644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.008663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.010234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.010257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.010280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.011847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.011868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.013739] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.017041] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.017122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.017155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.017221] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.017298] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.017331] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.033907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.033956] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.034027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.034296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.034392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.067249] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.067301] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.067376] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.085349] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.085393] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.085426] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.085469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.085587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.085645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.085695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.085743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.085794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.085834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.085866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.085900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.085931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.085960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.085987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.086042] [drm:intel_power_well_disable [i915]] disabling display
>[  906.086070] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.086097] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.086119] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.086219] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.086231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.086285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.086306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.086331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.086361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.086386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.086413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.086439] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.086466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.086492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.086546] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.086576] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.086585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.086613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.086621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.086649] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.086677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.086704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.086730] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.086761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.086789] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.086816] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.086843] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.086868] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.086899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.086931] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.087020] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.087052] [drm:intel_power_well_enable [i915]] enabling display
>[  906.087082] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.087137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.087169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.087199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.087229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.087258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.087289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.087323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.087356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.087378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.087396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.087415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.087438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.087459] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.089536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.089557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.089576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.089595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.091169] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.091190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.091208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.092774] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.092796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.094659] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.097991] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.098095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.098128] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.098169] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.098251] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.098272] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.114867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.114914] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.114977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.115175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.115249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.148219] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.148264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.148332] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.165364] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.165408] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.165441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.165479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.165597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.165654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.165704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.165758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.165797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.165831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.165862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.165890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.165918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.165952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.165989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.166040] [drm:intel_power_well_disable [i915]] disabling display
>[  906.166082] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.166127] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.166162] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.166303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.166319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.166401] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.166438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.166474] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.166559] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.166602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.166646] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.166689] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.166730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.166770] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.166798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.166824] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.166833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.166860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.166867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.166895] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.166922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.166949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.166975] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.167005] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.167032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.167060] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.167086] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.167112] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.167145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.167179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.167266] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.167298] [drm:intel_power_well_enable [i915]] enabling display
>[  906.167329] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.167381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.167413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.167444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.167475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.167537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.167569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.167604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.167635] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.167669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.167699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.167727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.167761] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.167792] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.169842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.169863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.169881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.169900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.171485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.171517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.171536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.173106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.173129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.175032] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.178329] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.178416] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.178448] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.178490] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.178656] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.178701] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.195199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.195249] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.195314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.195636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.195752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.228544] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.228596] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.228671] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.245696] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.245740] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.245773] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.245811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.245844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.245879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.245909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.245939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.245977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.246022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.246064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.246106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.246148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.246188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.246227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.246283] [drm:intel_power_well_disable [i915]] disabling display
>[  906.246329] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.246379] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.246417] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.246611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.246630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.246721] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.246755] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.246784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.246813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.246839] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.246866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.246892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.246919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.246945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.246971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.246996] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.247002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.247027] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.247032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.247058] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.247084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.247110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.247135] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.247162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.247187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.247213] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.247238] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.247264] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.247291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.247319] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.247381] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.247403] [drm:intel_power_well_enable [i915]] enabling display
>[  906.247426] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.247464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.247519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.247551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.247580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.247608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.247636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.247669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.247700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.247731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.247761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.247787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.247820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.247849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.249913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.249935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.249953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.249972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.251539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.251560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.251578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.253148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.253171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.255043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.258029] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.258125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.258163] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.258211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.258289] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.258326] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.274907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.274957] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.275022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.275223] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.275303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.308249] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.308297] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.308368] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.325399] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.325442] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.325483] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.325630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.325683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.325740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.325786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.325833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.325883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.325940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.325992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.326043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.326089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.326118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.326148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.326203] [drm:intel_power_well_disable [i915]] disabling display
>[  906.326245] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.326285] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.326320] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.326450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.326502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.326590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.326613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.326642] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.326679] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.326700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.326722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.326744] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.326765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.326785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.326804] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.326822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.326827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.326845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.326849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.326868] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.326886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.326904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.326921] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.326943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.326960] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.326978] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.326996] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.327013] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.327035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.327057] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.327116] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.327136] [drm:intel_power_well_enable [i915]] enabling display
>[  906.327154] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.327187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.327207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.327226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.327245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.327263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.327282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.327303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.327323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.327342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.327360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.327377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.327399] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.327420] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.329470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.329509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.329528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.329548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.331121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.331141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.331159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.332715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.332737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.334620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.337948] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.338005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.338037] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.338079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.338157] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.338189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.354788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.354838] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.354903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.355117] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.355195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.388129] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.388181] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.388256] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.405262] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.405305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.405337] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.405375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.405409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.405444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.405475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.405599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.405652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.405711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.405765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.405817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.405877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.405908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.405937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.405988] [drm:intel_power_well_disable [i915]] disabling display
>[  906.406031] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.406071] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.406106] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.406268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.406285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.406368] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.406398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.406430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.406465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.406536] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.406570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.406604] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.406637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.406669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.406701] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.406731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.406739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.406769] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.406777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.406807] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.406837] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.406868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.406897] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.406927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.406958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.406988] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.407018] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.407047] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.407080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.407113] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.407202] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.407234] [drm:intel_power_well_enable [i915]] enabling display
>[  906.407264] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.407315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.407346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.407376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.407406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.407436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.407467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.407526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.407561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.407595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.407625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.407656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.407691] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.407723] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.409787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.409808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.409826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.409845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.411406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.411426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.411445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.413046] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.413068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.414956] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.418263] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.418335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.418369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.418413] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.418483] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.418588] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.435131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.435180] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.435245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.435452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.435630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.468482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.468566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.468639] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.485687] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.485730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.485762] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.485801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.485834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.485868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.485899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.485928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.485959] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.485994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.486027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.486059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.486090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.486118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.486145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.486198] [drm:intel_power_well_disable [i915]] disabling display
>[  906.486239] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.486280] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.486313] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.486450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.486544] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.486680] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.486720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.486757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.486794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.486813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.486836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.486857] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.486878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.486897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.486916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.486935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.486940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.486958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.486962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.486982] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.487006] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.487032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.487058] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.487084] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.487109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.487136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.487161] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.487188] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.487216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.487244] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.487306] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.487328] [drm:intel_power_well_enable [i915]] enabling display
>[  906.487349] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.487388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.487414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.487440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.487466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.487523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.487555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.487589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.487621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.487652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.487679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.487706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.487739] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.487768] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.489835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.489857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.489875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.489894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.491472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.491510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.491530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.493088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.493110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.495026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.498302] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.498354] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.498383] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.498421] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.498567] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.498614] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.515131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.515177] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.515240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.515531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.515649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.548486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.548567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.548655] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.565645] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.565689] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.565721] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.565760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.565793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.565827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.565857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.565886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.565916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.565951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.565984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.566015] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.566045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.566073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.566101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.566154] [drm:intel_power_well_disable [i915]] disabling display
>[  906.566195] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.566235] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.566269] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.566417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.566439] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.566562] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.566593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.566628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.566665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.566694] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.566727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.566989] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.567020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.567048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.567077] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.567103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.567111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.567138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.567145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.567174] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.567200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.567227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.567252] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.567284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.567310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.567338] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.567363] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.567391] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.567421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.567453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.567563] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.567808] [drm:intel_power_well_enable [i915]] enabling display
>[  906.567836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.567883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.567912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.567938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.567964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.567988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.568016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.568046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.568075] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.568104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.568128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.568153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.568186] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.568213] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.570294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.570316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.570335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.570358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.571929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.571949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.571967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.573527] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.573548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.575416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.577941] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.578038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.578067] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.578105] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.578175] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.578204] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.594819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.594866] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.594929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.595127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.595202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.628167] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.628215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.628285] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.645311] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.645355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.645388] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.645427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.645460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.645590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.645630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.645660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.645693] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.645736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.645779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.645822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.645863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.645902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.645942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.645999] [drm:intel_power_well_disable [i915]] disabling display
>[  906.646044] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.646095] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.646133] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.646246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.646258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.646316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.646339] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.646362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.646387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.646407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.646428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.646450] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.646511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.646542] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.646574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.646602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.646612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.646641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.646650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.646681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.646711] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.646742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.646772] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.646806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.646836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.646867] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.646897] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.646924] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.646959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.646994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.647085] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.647117] [drm:intel_power_well_enable [i915]] enabling display
>[  906.647148] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.647198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.647229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.647260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.647292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.647322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.647354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.647389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.647422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.647455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.647514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.647541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.647577] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.647609] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.649674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.649698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.649720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.649744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.651306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.651327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.651345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.652910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.652930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.654802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.658101] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.658186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.658224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.658276] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.658357] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.658397] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.674968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.675018] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.675083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.675296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.675375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.708313] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.708362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.708433] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.725550] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.725594] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.725626] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.725664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.725697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.725732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.725762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.725791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.725822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.725857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.725889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.725921] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.725952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.725979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.726015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.726058] [drm:intel_power_well_disable [i915]] disabling display
>[  906.726083] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.726108] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.726128] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.726227] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.726239] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.726290] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.726309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.726330] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.726356] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.726379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.726403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.726427] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.726450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.726528] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.726560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.726593] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.726602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.726633] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.726641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.726672] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.726702] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.726733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.726763] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.726797] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.726827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.726859] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.726889] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.726920] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.726954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.726989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.727079] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.727112] [drm:intel_power_well_enable [i915]] enabling display
>[  906.727142] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.727192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.727224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.727254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.727284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.727314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.727345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.727379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.727412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.727444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.727500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.727530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.727566] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.727598] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.729670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.729691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.729710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.729729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.731298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.731318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.731339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.732902] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.732932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.734811] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.738106] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.738193] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.738231] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.738257] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.738315] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.738336] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.754974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.755024] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.755089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.755288] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.755370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.788321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.788369] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.788439] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.807424] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.807468] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.807587] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.807648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.807840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.807875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.807904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.807931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.807961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.807994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.808025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.808055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.808084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.808110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.808145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.808198] [drm:intel_power_well_disable [i915]] disabling display
>[  906.808242] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.808288] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.808324] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.808526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.808554] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.808988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.809028] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.809069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.809115] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.809151] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.809190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.809229] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.809268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.809306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.809342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.809377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.809386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.809419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.809427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.809463] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.809538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.809579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.809615] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.809656] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.809691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.809728] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.809764] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.809800] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.809847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.809883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.810143] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.810164] [drm:intel_power_well_enable [i915]] enabling display
>[  906.810182] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.810217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.810243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.810269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.810295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.810320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.810344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.810372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.810399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.810426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.810451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.810512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.810552] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.810585] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.812887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.812908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.812927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.812950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.814597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.814620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.814643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.816202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.816224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.818097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.821383] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.821530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.821576] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.821643] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.821847] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.821882] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.838258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.838308] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.838372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.838805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.838885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.871605] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.871657] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.871733] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.888759] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.888803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.888835] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.888873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.888906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.888940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.888970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.888999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.889030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.889065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.889097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.889128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.889158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.889185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.889212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.889264] [drm:intel_power_well_disable [i915]] disabling display
>[  906.889305] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.889345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.889378] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.889590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.889609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.889696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.889726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.889759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.889796] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.889825] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.889856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.889885] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.889916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.889944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.889971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.889997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.890004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.890031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.890038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.890067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.890093] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.890121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.890146] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.890177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.890203] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.890231] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.890256] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.890285] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.890314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.890347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.890435] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.890488] [drm:intel_power_well_enable [i915]] enabling display
>[  906.890518] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.890569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.890598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.890629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.890657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.890687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.890716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.890750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.890782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.890815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.890842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.890872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.890906] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.890936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.893037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.893061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.893083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.893118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.894712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.894733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.894752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.896311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.896334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.898202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.901518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.901584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.901616] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.901660] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.901720] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.901741] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.918369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.918418] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.918565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.918821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.918899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.951713] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  906.951761] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  906.951832] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  906.968857] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  906.968901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  906.968933] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  906.968970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.969003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.969046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.969086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.969126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.969165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.969216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.969249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.969279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.969307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.969332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.969356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.969404] [drm:intel_power_well_disable [i915]] disabling display
>[  906.969440] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  906.969556] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.969605] [drm:intel_power_well_disable [i915]] disabling always-on
>[  906.970112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.970138] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  906.970255] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  906.970281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  906.970307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  906.970336] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  906.970359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  906.970384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  906.970408] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  906.970431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  906.970454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  906.970515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  906.970554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  906.970563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.970596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  906.970605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  906.970639] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  906.970671] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  906.970704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  906.970734] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  906.970771] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  906.970801] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  906.970835] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  906.971164] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  906.971196] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  906.971233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  906.971276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  906.971364] [drm:intel_power_well_enable [i915]] enabling always-on
>[  906.971402] [drm:intel_power_well_enable [i915]] enabling display
>[  906.971429] [drm:hsw_set_power_well [i915]] Enabling power well
>[  906.971516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  906.971546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  906.971578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  906.971606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  906.971636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  906.971665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  906.971699] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  906.971919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  906.971939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.971957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  906.971975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  906.971996] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  906.972015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  906.974175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  906.974199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  906.974222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.974246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  906.975811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  906.975832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  906.975850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  906.977434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  906.977472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  906.979334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  906.982572] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  906.982650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  906.982669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  906.982694] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  906.982753] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  906.982774] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  906.999448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  906.999533] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  906.999598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  906.999797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  906.999875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.032791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.032839] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.032910] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.049931] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.049975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.050007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.050046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.050079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.050114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.050145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.050174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.050206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.050241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.050274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.050305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.050335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.050363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.050390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.050442] [drm:intel_power_well_disable [i915]] disabling display
>[  907.050565] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.050629] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.050684] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.050898] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.050926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.051063] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.051113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.051156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.051200] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.051235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.051274] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.051311] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.051349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.051385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.051421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.051453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.051491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.051526] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.051535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.051575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.051608] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.051645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.051678] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.051718] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.051751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.051787] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.051821] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.051856] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.051895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.051938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.052047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.052085] [drm:intel_power_well_enable [i915]] enabling display
>[  907.052125] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.052175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.052205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.052235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.052262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.052293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.052322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.052354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.052387] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.052419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.052446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.052497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.052534] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.052564] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.054631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.054652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.054670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.054689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.056260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.056280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.056303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.057869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.057890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.059761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.063064] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.063148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.063187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.063239] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.063320] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.063369] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.079930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.079980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.080045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.080255] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.080333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.113273] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.113322] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.113392] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.130423] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.130556] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.130610] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.130668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.130720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.130757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.130788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.130818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.130850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.130887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.130922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.130953] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.130995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.131035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.131076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.131134] [drm:intel_power_well_disable [i915]] disabling display
>[  907.131180] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.131230] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.131269] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.131429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.131492] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.131633] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.131686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.131732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.131771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.131799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.131823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.131844] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.131866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.131886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.131906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.131924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.131929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.131947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.131951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.131978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.132004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.132030] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.132056] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.132082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.132108] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.132134] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.132160] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.132186] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.132213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.132241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.132319] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.132339] [drm:intel_power_well_enable [i915]] enabling display
>[  907.132357] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.132395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.132420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.132449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.132502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.132532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.132562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.132595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.132627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.132658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.132685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.132712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.132745] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.132773] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.134842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.134863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.134881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.134900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.136483] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.136512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.136531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.138093] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.138114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.139991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.143280] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.143375] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.143407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.143449] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.143622] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.143673] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.160149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.160199] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.160269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.160737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.160825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.193502] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.193548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.193636] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.210655] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.210703] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.210744] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.210787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.210828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.210871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.210911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.210950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.210989] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.211033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.211075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.211117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.211158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.211197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.211235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.211298] [drm:intel_power_well_disable [i915]] disabling display
>[  907.211334] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.211374] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.211403] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.211643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.211668] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.211783] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.211823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.211867] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.211914] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.211950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.211993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.212032] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.212072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.212108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.212146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.212180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.212190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.212225] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.212234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.212271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.212312] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.212340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.212366] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.212397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.212423] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.212477] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.212505] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.212534] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.212565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.212599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.212688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.212719] [drm:intel_power_well_enable [i915]] enabling display
>[  907.212748] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.212797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.212825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.212854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.212880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.212908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.212936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.212968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.212999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.213031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.213057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.213085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.213115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.213145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.215218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.215240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.215263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.215287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.216867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.216887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.216906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.218490] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.218511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.220388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.223637] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.223705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.223725] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.223750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.223810] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.223831] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.240510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.240562] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.240633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.240859] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.240941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.273895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.273943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.274015] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.292408] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.292452] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.292561] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.292619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.292665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.292717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.292759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.292804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.292848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.292900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.292950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.292992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.293024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.293050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.293077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.293133] [drm:intel_power_well_disable [i915]] disabling display
>[  907.293174] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.293213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.293247] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.293382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.293393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.293496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.293528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.293564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.293601] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.293630] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.293664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.293695] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.293728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.293757] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.293787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.293814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.293823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.293850] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.293858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.293888] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.293915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.293944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.293970] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.294002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.294028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.294057] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.294086] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.294115] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.294147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.294181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.294256] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.294287] [drm:intel_power_well_enable [i915]] enabling display
>[  907.294318] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.294368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.294396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.294425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.294475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.294505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.294534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.294567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.294600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.294633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.294659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.294689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.294723] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.294752] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.296808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.296831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.296850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.296870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.298437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.298475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.298497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.300073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.300094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.301991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.305268] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.305308] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.305337] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.305363] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.305423] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.305500] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.322108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.322158] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.322223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.322659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.322747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.355451] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.355531] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.355604] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.372609] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.372653] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.372692] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.372736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.372777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.372821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.372861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.372900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.372939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.372983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.373025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.373066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.373108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.373146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.373185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.373241] [drm:intel_power_well_disable [i915]] disabling display
>[  907.373287] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.373336] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.373374] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.373641] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.373670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.373811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.373858] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.373894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.373932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.373963] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.373994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.374027] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.374056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.374087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.374115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.374143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.374151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.374178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.374185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.374215] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.374241] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.374269] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.374294] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.374325] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.374350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.374378] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.374403] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.374431] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.374488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.374524] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.374617] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.374649] [drm:intel_power_well_enable [i915]] enabling display
>[  907.374680] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.374732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.374765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.374796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.374826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.374855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.374883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.374916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.374948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.374980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.375006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.375033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.375067] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.375099] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.377188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.377210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.377229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.377249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.378816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.378837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.378856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.380426] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.380459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.382329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.385708] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.385763] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.385796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.385838] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.385915] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.385948] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.404661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.404712] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.404778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.405001] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.405080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.435892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.435941] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.436012] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.453041] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.453085] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.453117] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.453155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.453195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.453239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.453279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.453318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.453358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.453402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.453444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.453567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.453611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.453653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.453690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.453754] [drm:intel_power_well_disable [i915]] disabling display
>[  907.453789] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.453827] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.453855] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.453989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.454005] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.454079] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.454106] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.454136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.454169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.454195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.454223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.454251] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.454278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.454304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.454328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.454351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.454358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.454382] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.454387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.454411] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.454436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.454504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.454544] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.454574] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.454603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.454630] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.454656] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.454681] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.454713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.454744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.454835] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.454857] [drm:intel_power_well_enable [i915]] enabling display
>[  907.454875] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.454908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.454928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.454948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.454966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.454984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.455004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.455026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.455046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.455066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.455085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.455103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.455125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.455145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.457203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.457224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.457243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.457262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.458836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.458857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.458875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.460425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.460457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.462323] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.464991] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.465045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.465074] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.465111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.465183] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.465212] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.481831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.481878] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.481941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.482163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.482240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.515200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.515249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.515337] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.533897] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.533941] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.533974] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.534012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.534052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.534096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.534136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.534176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.534215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.534259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.534301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.534343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.534385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.534424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.534523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.534611] [drm:intel_power_well_disable [i915]] disabling display
>[  907.534681] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.534751] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.534807] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.535008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.535027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.535102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.535128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.535155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.535184] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.535210] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.535237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.535263] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.535289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.535315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.535341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.535366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.535372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.535397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.535402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.535430] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.535487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.535519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.535548] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.535581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.535609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.535637] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.535664] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.535691] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.535723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.535756] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.535847] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.535880] [drm:intel_power_well_enable [i915]] enabling display
>[  907.535911] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.535963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.535996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.536027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.536050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.536068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.536089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.536112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.536132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.536158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.536184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.536210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.536237] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.536263] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.538318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.538345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.538369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.538396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.540127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.540149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.540171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.541737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.541758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.543627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.546957] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.547011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.547050] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.547102] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.547201] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.547260] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.565869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.565919] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.565984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.566205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.566307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.597138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.597186] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.597275] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.614287] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.614330] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.614363] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.614401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.614441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.614572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.614623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.614672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.614722] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.614774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.614807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.614839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.614869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.614898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.614923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.614976] [drm:intel_power_well_disable [i915]] disabling display
>[  907.615017] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.615056] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.615090] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.615248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.615266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.615346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.615373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.615403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.615477] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.615509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.615543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.615575] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.615607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.615636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.615666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.615693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.615702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.615730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.615738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.615767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.615794] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.615824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.615850] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.615883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.615912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.615942] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.615968] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.615996] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.616028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.616062] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.616155] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.616187] [drm:intel_power_well_enable [i915]] enabling display
>[  907.616218] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.616270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.616302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.616333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.616360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.616389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.616416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.616473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.616505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.616539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.616566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.616596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.616631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.616662] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.618724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.618746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.618766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.618787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.620349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.620369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.620387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.621985] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.622006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.623905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.627182] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.627222] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.627242] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.627268] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.627327] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.627348] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.644033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.644083] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.644148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.644352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.644431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.677364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.677413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.677794] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.696404] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.696479] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.696512] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.696550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.696583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.696618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.696648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.696676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.696707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.696742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.696774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.696805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.696836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.696863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.696891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.696969] [drm:intel_power_well_disable [i915]] disabling display
>[  907.697013] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.697055] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.697089] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.697241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.697258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.697330] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.697349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.697370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.697393] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.697410] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.697482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.697511] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.697541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.697569] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.697596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.697623] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.697631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.697657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.697664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.697691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.697718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.697744] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.697769] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.697800] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.697826] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.697853] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.697879] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.697905] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.697936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.697967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.698059] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.698092] [drm:intel_power_well_enable [i915]] enabling display
>[  907.698122] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.698174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.698207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.698238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.698268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.698298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.698330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.698363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.698385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.698405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.698453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.698479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.698511] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.698540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.700603] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.700626] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.700649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.700673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.702244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.702268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.702291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.703856] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.703878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.705750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.709067] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.709133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.709167] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.709209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.709286] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.709320] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.725918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.725968] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.726033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.726279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.726381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.759262] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.759313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.759387] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.776417] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.776495] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.776528] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.776571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.776612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.776656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.776695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.776735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.776774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.776818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.776861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.776902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.776944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.776983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.777015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.777048] [drm:intel_power_well_disable [i915]] disabling display
>[  907.777072] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.777099] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.777120] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.777215] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.777234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.777289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.777309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.777331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.777354] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.777376] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.777401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.777475] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.777506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.777535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.777563] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.777590] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.777599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.777625] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.777633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.777660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.777687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.777714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.777740] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.777771] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.777797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.777824] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.777850] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.777877] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.777908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.777939] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.778029] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.778062] [drm:intel_power_well_enable [i915]] enabling display
>[  907.778091] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.778143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.778176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.778207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.778236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.778267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.778299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.778331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.778353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.778374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.778393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.778411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.778465] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.778494] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.780555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.780576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.780594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.780613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.782184] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.782204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.782227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.783790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.783812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.785681] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.788983] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.789066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.789099] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.789142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.789218] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.789255] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.805848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.805897] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.805962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.806184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.806285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.839190] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.839238] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.839308] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.856344] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.856387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.856419] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.856544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.856598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.856654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.856703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.856738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.856770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.856808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.856842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.856873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.856905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.856934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.856962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.857014] [drm:intel_power_well_disable [i915]] disabling display
>[  907.857056] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.857105] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.857144] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.857302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.857321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.857413] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.857501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.857537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.857573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.857602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.857634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.857664] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.857693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.857722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.857750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.857776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.857786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.857812] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.857820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.857847] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.857873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.857900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.857925] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.857956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.857982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.858007] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.858036] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.858064] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.858094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.858126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.858217] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.858250] [drm:intel_power_well_enable [i915]] enabling display
>[  907.858280] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.858333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.858366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.858397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.858451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.858479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.858508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.858539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.858571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.858603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.858632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.858661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.858695] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.858728] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.860778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.860799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.860818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.860838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.862466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.862487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.862505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.864057] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.864079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.865955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.869218] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.869291] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.869331] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.869382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.869768] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.869801] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.886071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.886120] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.886186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.886484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.886572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.919413] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.919494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.919566] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  907.936572] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  907.936620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  907.936660] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  907.936704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.936744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.936787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.936827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.936866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.936905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.936949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.936991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.937033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.937075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.937114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.937162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.937195] [drm:intel_power_well_disable [i915]] disabling display
>[  907.937221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  907.937249] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.937269] [drm:intel_power_well_disable [i915]] disabling always-on
>[  907.937365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.937376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  907.937501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  907.937535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  907.937569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  907.937607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  907.937636] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  907.937669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  907.937700] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  907.937730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  907.937763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  907.937791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  907.937820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  907.937827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.937855] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  907.937862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  907.937892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  907.937918] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  907.937946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  907.937971] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  907.938003] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  907.938028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  907.938056] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  907.938082] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  907.938109] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  907.938142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.938175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  907.938263] [drm:intel_power_well_enable [i915]] enabling always-on
>[  907.938294] [drm:intel_power_well_enable [i915]] enabling display
>[  907.938323] [drm:hsw_set_power_well [i915]] Enabling power well
>[  907.938374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  907.938402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  907.938456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  907.938483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  907.938514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  907.938542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  907.938577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  907.938611] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  907.938645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.938672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  907.938701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  907.938736] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  907.938765] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  907.940850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  907.940874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  907.940894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.940915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  907.942552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  907.942573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  907.942592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  907.944139] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  907.944161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  907.946024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  907.949343] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  907.949410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  907.949476] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  907.949523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  907.949726] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  907.949747] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  907.966192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  907.966243] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  907.966308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  907.966793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  907.966885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  907.999535] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  907.999583] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  907.999653] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.016688] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.016731] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.016764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.016803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.016836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.016871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.016901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.016931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.016962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.016998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.017032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.017064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.017094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.017122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.017150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.017203] [drm:intel_power_well_disable [i915]] disabling display
>[  908.017243] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.017285] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.017318] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.017854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.017874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.017963] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.017993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.018027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.018064] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.018092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.018124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.018153] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.018183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.018212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.018240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.018265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.018273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.018299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.018306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.018335] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.018362] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.018390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.018441] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.018476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.018503] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.018534] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.018561] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.018589] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.018620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.018654] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.019006] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.019035] [drm:intel_power_well_enable [i915]] enabling display
>[  908.019064] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.019121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.019150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.019188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.019213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.019239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.019265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.019295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.019324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.019352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.019377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.019403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.019475] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.019505] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.021794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.021815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.021834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.021853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.023410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.023453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.023471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.025044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.025067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.026961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.030186] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.030226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.030245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.030271] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.030331] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.030355] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.047032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.047081] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.047147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.047336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.047415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.080389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.080479] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.080556] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.097592] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.097635] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.097668] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.097705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.097738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.097772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.097802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.097830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.097861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.097895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.097927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.097958] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.097989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.098017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.098044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.098097] [drm:intel_power_well_disable [i915]] disabling display
>[  908.098137] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.098185] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.098224] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.098378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.098469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.098598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.098628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.098662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.098698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.098726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.098758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.098787] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.098819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.098848] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.098877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.098903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.098910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.098936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.098943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.098973] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.098999] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.099028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.099054] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.099085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.099111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.099139] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.099164] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.099192] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.099221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.099254] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.099329] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.099360] [drm:intel_power_well_enable [i915]] enabling display
>[  908.099399] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.099479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.099509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.099540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.099568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.099601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.099630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.099664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.099697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.099729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.099758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.099788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.099823] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.099853] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.101921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.101942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.101960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.101979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.103547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.103569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.103588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.105147] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.105168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.107042] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.110354] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.110497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.110547] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.110615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.110729] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.110780] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.127204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.127254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.127319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.127656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.127751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.160553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.160601] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.160675] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.177705] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.177749] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.177781] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.177819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.177853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.177887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.177917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.177946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.177978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.178020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.178062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.178104] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.178146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.178185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.178224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.178289] [drm:intel_power_well_disable [i915]] disabling display
>[  908.178327] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.178369] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.178401] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.178652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.178677] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.178795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.178835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.178881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.178929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.178965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.179007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.179047] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.179087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.179124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.179161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.179195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.179204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.179239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.179248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.179286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.179323] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.179351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.179377] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.179408] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.179462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.179490] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.179519] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.179546] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.179579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.179616] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.179702] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.179733] [drm:intel_power_well_enable [i915]] enabling display
>[  908.179762] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.179811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.179840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.179869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.179896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.179924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.179952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.179984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.180016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.180047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.180073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.180101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.180131] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.180162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.182246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.182268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.182287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.182307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.183882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.183903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.183921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.185505] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.185526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.187387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.190661] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.190714] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.190738] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.190770] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.190832] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.190853] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.207513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.207562] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.207628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.207874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.207967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.240863] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.240928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.240998] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.259245] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.259288] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.259321] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.259359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.259393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.259505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.259552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.259602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.259648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.259704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.260097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.260135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.260159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.260183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.260206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.260241] [drm:intel_power_well_disable [i915]] disabling display
>[  908.260269] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.260299] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.260322] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.260639] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.260667] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.260738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.260758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.260782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.260809] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.260832] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.260856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.260880] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.260903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.260927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.260950] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.260973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.260978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.261001] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.261005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.261028] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.261052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.261075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.261097] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.261121] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.261144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.261167] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.261191] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.261214] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.261238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.261263] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.261320] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.261341] [drm:intel_power_well_enable [i915]] enabling display
>[  908.261361] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.261396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.261465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.261502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.261531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.261562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.261591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.261626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.261659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.261693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.261720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.261749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.261784] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.261814] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.264214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.264235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.264254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.264273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.265848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.265868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.265886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.267521] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.267543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.269489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.272823] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.272925] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.272958] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.273000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.273077] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.273111] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.289717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.289764] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.289827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.290046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.290147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.294413] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  908.323061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.323120] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.323537] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.342092] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.342136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.342168] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.342208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.342241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.342276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.342315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.342356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.342396] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.342510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.342570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.342625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.342680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.342726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.342775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.342852] [drm:intel_power_well_disable [i915]] disabling display
>[  908.342895] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.342938] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.342973] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.343127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.343146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.343239] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.343269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.343301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.343335] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.343364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.343405] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.343484] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.343517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.343551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.343582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.343613] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.343622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.343652] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.343660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.343689] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.343718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.343750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.343780] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.343814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.343844] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.343874] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.343901] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.343929] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.343962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.343997] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.344072] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.344104] [drm:intel_power_well_enable [i915]] enabling display
>[  908.344135] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.344185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.344216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.344247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.344276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.344306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.344337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.344370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.344403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.344462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.344492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.344523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.344559] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.344591] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.346671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.346694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.346713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.346733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.348304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.348325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.348347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.349916] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.349938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.351937] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.355211] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.355252] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.355271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.355297] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.355360] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.355381] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.372052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.372102] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.372168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.372380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.372565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.405390] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.405468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.405535] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.422551] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.422594] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.422627] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.422665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.422704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.422748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.422788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.422828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.422867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.422910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.422953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.422995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.423036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.423075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.423114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.423170] [drm:intel_power_well_disable [i915]] disabling display
>[  908.423216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.423265] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.423304] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.423557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.423585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.423687] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.423720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.423752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.423788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.423816] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.423848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.423878] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.423908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.423936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.423964] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.423990] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.423997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.424024] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.424031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.424060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.424086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.424114] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.424139] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.424170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.424197] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.424226] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.424256] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.424281] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.424312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.424346] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.424459] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.424489] [drm:intel_power_well_enable [i915]] enabling display
>[  908.424519] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.424570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.424598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.424630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.424659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.424687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.424716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.424747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.424780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.424811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.424838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.424866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.424899] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.424928] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.427001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.427025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.427048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.427071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.428660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.428682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.428702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.430255] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.430276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.432156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.435488] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.435540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.435573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.435614] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.435691] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.435724] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.452321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.452370] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.452524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.452780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.452856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.485666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.485714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.485786] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.504025] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.504055] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.504076] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.504101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.504122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.504150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.504176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.504201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.504227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.504260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.504282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.504301] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.504320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.504336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.504353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.504469] [drm:intel_power_well_disable [i915]] disabling display
>[  908.504513] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.504557] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.504592] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.504759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.504778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.504867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.504900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.504935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.504972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.505003] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.505036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.505069] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.505100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.505132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.505163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.505192] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.505201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.505230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.505237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.505267] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.505296] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.505326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.505355] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.505388] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.505443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.505476] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.505506] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.505537] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.505573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.505608] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.505685] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.505718] [drm:intel_power_well_enable [i915]] enabling display
>[  908.505750] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.505800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.505831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.505862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.505891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.505921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.505952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.505986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.506019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.506051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.506080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.506109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.506143] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.506174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.508233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.508255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.508274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.508292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.509848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.509869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.509887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.511447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.511468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.513324] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.515585] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.515629] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.515648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.515673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.515736] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.515756] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.532453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.532503] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.532568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.532789] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.532870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.565770] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.565821] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.565896] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.582937] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.582982] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.583013] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.583051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.583084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.583119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.583149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.583178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.583216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.583261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.583303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.583344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.583386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.583496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.583544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.583631] [drm:intel_power_well_disable [i915]] disabling display
>[  908.583695] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.583761] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.583813] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.583967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.583987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.584073] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.584102] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.584135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.584172] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.584200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.584232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.584261] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.584292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.584319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.584347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.584373] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.584405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.584432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.584441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.584470] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.584497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.584526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.584552] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.584586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.584613] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.584642] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.584669] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.584699] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.584732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.584767] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.584857] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.584888] [drm:intel_power_well_enable [i915]] enabling display
>[  908.584918] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.584966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.584994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.585023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.585049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.585078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.585105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.585136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.585168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.585200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.585225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.585252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.585282] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.585313] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.587397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.587443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.587466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.587490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.589090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.589112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.589131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.590690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.590711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.592579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.595897] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.595963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.595996] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.596039] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.596112] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.596134] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.612753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.612803] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.612868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.613090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.613196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.646128] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.646177] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.646250] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.663296] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.663340] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.663373] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.663504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.663557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.663612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.663660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.663706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.663756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.663812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.663866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.663919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.663969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.664015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.664060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.664145] [drm:intel_power_well_disable [i915]] disabling display
>[  908.664209] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.664270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.664323] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.664524] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.664537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.664594] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.664616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.664639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.664672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.664691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.664711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.664730] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.664748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.664766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.664783] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.664805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.664810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.664833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.664837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.664861] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.664882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.664906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.664929] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.664952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.664975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.664998] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.665022] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.665045] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.665069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.665095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.665153] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.665174] [drm:intel_power_well_enable [i915]] enabling display
>[  908.665193] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.665229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.665253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.665277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.665300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.665323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.665347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.665372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.665449] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.665488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.665521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.665553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.665590] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.665623] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.667707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.667730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.667749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.667769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.669370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.669418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.669439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.671000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.671023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.672904] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.676240] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.676340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.676373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.676486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.676605] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.676634] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.693122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.693172] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.693236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.693541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.693648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.726465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.726513] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.726584] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.743618] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.743662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.743694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.743731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.743764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.743799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.743830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.743860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.743891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.743926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.743958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.743990] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.744021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.744048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.744092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.744125] [drm:intel_power_well_disable [i915]] disabling display
>[  908.744150] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.744178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.744201] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.744300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.744313] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.744367] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.744451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.744484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.744523] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.744552] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.744586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.744617] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.744649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.744678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.744709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.744735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.744744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.744772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.744780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.744810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.744837] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.744866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.744892] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.744926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.744953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.744983] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.745011] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.745040] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.745070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.745105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.745194] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.745226] [drm:intel_power_well_enable [i915]] enabling display
>[  908.745255] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.745305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.745336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.745365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.745417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.745446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.745474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.745505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.745537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.745570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.745597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.745628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.745660] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.745691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.747759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.747780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.747799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.747818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.749382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.749420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.749438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.751001] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.751023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.752925] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.755312] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.755427] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.755457] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.755501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.755575] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.755605] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.772160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.772207] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.772271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.772726] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.772804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.805524] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.805575] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.805648] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.823940] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.823983] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.824016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.824054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.824087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.824122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.824153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.824182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.824213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.824248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.824289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.824331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.824372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.824489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.824534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.824624] [drm:intel_power_well_disable [i915]] disabling display
>[  908.824687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.824756] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.824790] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.824928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.824948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.825035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.825065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.825098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.825133] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.825161] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.825192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.825222] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.825252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.825280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.825308] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.825334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.825341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.825367] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.825400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.825431] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.825458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.825489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.825516] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.825548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.825575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.825605] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.825632] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.825660] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.825691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.825726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.825816] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.825847] [drm:intel_power_well_enable [i915]] enabling display
>[  908.825877] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.825926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.825954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.825984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.826011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.826039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.826071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.826103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.826135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.826166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.826191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.826219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.826252] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.826281] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.828343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.828364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.828425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.828460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.830026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.830045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.830067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.831632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.831654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.833530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.836848] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.836920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.836940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.836965] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.837024] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.837045] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.853696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.853746] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.853810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.854008] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.854086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.887039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.887088] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.887159] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.905328] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.905373] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.905491] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.905550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.905746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.905789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.905830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.905869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.905908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.905952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.905994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.906036] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.906078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.906116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.906155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.906211] [drm:intel_power_well_disable [i915]] disabling display
>[  908.906256] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.906312] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.906369] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.906828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.906841] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.906896] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.906918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.906939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.906962] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.906980] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.907000] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.907020] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.907039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.907057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.907074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.907091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.907095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.907117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.907122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.907146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.907167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.907191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.907214] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.907238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.907261] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.907285] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.907308] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.907332] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.907356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.907427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.907520] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.907816] [drm:intel_power_well_enable [i915]] enabling display
>[  908.907847] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.907899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.907929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.907959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.907987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.908016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.908044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.908076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.908108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.908141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.908167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.908195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.908225] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.908256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.910316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.910339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.910362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.910429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.912000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.912021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.912043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.913634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.913657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.915532] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  908.918766] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  908.918798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  908.918817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  908.918850] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  908.918916] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  908.918936] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  908.935596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.935645] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.935715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.935956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.936034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.968941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  908.968990] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  908.969063] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  908.987316] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  908.987359] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  908.987475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  908.987536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.987729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.987767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.987798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.987827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.987859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  908.987894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.987928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.987958] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.987989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.988017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.988044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.988095] [drm:intel_power_well_disable [i915]] disabling display
>[  908.988138] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  908.988163] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  908.988183] [drm:intel_power_well_disable [i915]] disabling always-on
>[  908.988277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  908.988288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  908.988339] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  908.988358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  908.988426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  908.988466] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  908.988495] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  908.988529] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  908.988559] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  908.988590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  908.988619] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  908.988648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  908.988674] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  908.988683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.988711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  908.988718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  908.988747] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  908.988776] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  908.988803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  908.988832] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  908.988862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  908.988891] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  908.988918] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  908.989253] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  908.989280] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  908.989313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  908.989348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  908.989558] [drm:intel_power_well_enable [i915]] enabling always-on
>[  908.989596] [drm:intel_power_well_enable [i915]] enabling display
>[  908.989624] [drm:hsw_set_power_well [i915]] Enabling power well
>[  908.989670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  908.989697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  908.989725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  908.989750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  908.989777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  908.989803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  908.989834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  908.989863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  908.989893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  908.989917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  908.989943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  908.989974] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  908.990001] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  908.992084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  908.992106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  908.992125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.992144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  908.993731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  908.993753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  908.993772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  908.995362] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  908.995396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  908.997264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.000550] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.000633] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.000653] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.000679] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.000739] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.000760] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.017432] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.017492] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.017573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.017787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.017866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.050774] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.050822] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.050893] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.067927] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.067971] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.068003] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.068041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.068073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.068108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.068139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.068168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.068200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.068234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.068267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.068298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.068329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.068367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.068480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.068566] [drm:intel_power_well_disable [i915]] disabling display
>[  909.068631] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.068694] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.068748] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.068951] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.068970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.069057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.069087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.069120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.069156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.069184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.069216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.069245] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.069275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.069303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.069331] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.069357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.069383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.069411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.069417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.069447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.069474] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.069502] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.069528] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.069560] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.069589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.069620] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.069650] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.069681] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.069715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.069750] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.069842] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.069875] [drm:intel_power_well_enable [i915]] enabling display
>[  909.069907] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.069960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.069991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.070024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.070051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.070080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.070108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.070140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.070172] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.070204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.070230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.070257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.070288] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.070318] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.072413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.072434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.072452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.072471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.074061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.074083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.074102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.075662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.075683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.077558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.080900] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.080995] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.081035] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.081087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.081163] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.081185] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.097782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.097833] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.097905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.098112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.098224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.131137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.131185] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.131257] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.148264] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.148312] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.148352] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.148477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.148525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.148580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.148629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.148672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.148713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.148764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.148811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.148858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.148904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.148942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.148983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.149064] [drm:intel_power_well_disable [i915]] disabling display
>[  909.149123] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.149181] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.149230] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.149494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.149513] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.149598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.149633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.149656] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.149690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.149709] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.149729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.149749] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.149767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.149785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.149802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.149818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.149822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.149845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.149849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.149873] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.149895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.149918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.149940] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.149970] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.149999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.150018] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.150036] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.150053] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.150073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.150095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.150141] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.150158] [drm:intel_power_well_enable [i915]] enabling display
>[  909.150174] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.150206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.150224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.150241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.150257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.150274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.150291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.150310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.150328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.150346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.150406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.150439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.150469] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.150502] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.152570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.152591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.152610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.152629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.154191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.154211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.154230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.155782] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.155803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.157662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.160950] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.161030] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.161049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.161075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.161133] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.161163] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.177828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.177877] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.177943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.178155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.178233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.211175] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.211243] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.211333] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.228359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.228437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.228470] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.228508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.228542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.228577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.228607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.228637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.228668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.228702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.228734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.228765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.228795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.228822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.228849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.228902] [drm:intel_power_well_disable [i915]] disabling display
>[  909.228943] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.228984] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.229018] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.229171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.229190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.229272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.229304] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.229342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.229414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.229448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.229480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.229513] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.229542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.229573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.229600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.229629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.229637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.229665] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.229673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.229703] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.229729] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.229758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.229784] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.229817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.229843] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.229873] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.229899] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.229928] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.229961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.229996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.230084] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.230116] [drm:intel_power_well_enable [i915]] enabling display
>[  909.230145] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.230195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.230225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.230252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.230280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.230307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.230336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.230393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.230426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.230457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.230488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.230515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.230549] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.230578] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.232648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.232669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.232687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.232705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.234267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.234290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.234309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.235875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.235896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.237784] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.241112] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.241221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.241254] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.241295] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.241372] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.241464] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.257998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.258051] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.258140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.258344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.258533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.291361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.291446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.291518] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.308581] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.308629] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.308670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.308714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.308755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.308798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.308839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.308894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.308936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.308974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.309006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.309044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.309070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.309093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.309116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.309161] [drm:intel_power_well_disable [i915]] disabling display
>[  909.309196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.309231] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.309260] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.309479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.309505] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.309623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.309667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.309712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.309761] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.309802] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.309846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.309889] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.309930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.309971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.310010] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.310056] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.310064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.310092] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.310099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.310129] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.310158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.310187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.310216] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.310248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.310278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.310307] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.310337] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.310389] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.310423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.310457] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.310550] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.310583] [drm:intel_power_well_enable [i915]] enabling display
>[  909.310614] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.310665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.310697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.310727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.310758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.310788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.310820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.310854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.310887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.310919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.310948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.310975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.311010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.311042] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.313117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.313139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.313158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.313178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.314767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.314791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.314814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.316368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.316416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.318289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.321584] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.321667] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.321695] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.321732] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.321818] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.321862] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.338463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.338513] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.338578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.338784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.338862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.371800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.371850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.371939] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.388954] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.388998] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.389030] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.389068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.389102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.389137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.389167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.389196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.389227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.389262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.389295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.389326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.389357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.389469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.389510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.389594] [drm:intel_power_well_disable [i915]] disabling display
>[  909.389651] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.389702] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.389741] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.389884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.389900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.389973] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.390006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.390042] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.390080] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.390113] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.390148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.390182] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.390217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.390251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.390285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.390317] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.390325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.390359] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.390400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.390445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.390484] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.390523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.390559] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.390600] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.390636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.390672] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.390708] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.390744] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.390793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.390825] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.390916] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.390949] [drm:intel_power_well_enable [i915]] enabling display
>[  909.390979] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.391031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.391064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.391094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.391127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.391156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.391187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.391221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.391252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.391283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.391309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.391335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.391389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.391417] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.393480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.393501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.393519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.393539] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.395108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.395131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.395155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.396722] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.396744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.398612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.401960] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.402031] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.402050] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.402076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.402135] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.402165] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.418827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.418877] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.418942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.419155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.419234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.452175] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.452224] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.452310] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.469314] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.469357] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.469482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.469691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.469727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.469764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.469795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.469833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.469873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.469917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.469959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.470001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.470043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.470082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.470120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.470176] [drm:intel_power_well_disable [i915]] disabling display
>[  909.470221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.470271] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.470309] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.470777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.470801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.470916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.470959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.471002] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.471048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.471088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.471130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.471171] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.471210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.471249] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.471286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.471323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.471332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.471405] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.471418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.471458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.471500] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.471531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.471561] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.471594] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.471625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.471657] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.471687] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.471716] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.471751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.471786] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.472118] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.472136] [drm:intel_power_well_enable [i915]] enabling display
>[  909.472153] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.472186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.472206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.472225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.472243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.472260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.472278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.472298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.472318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.472336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.472405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.472434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.472471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.472503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.474724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.474745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.474764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.474783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.476350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.476382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.476404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.477965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.477988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.479875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.483191] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.483256] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.483287] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.483326] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.483471] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.483517] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.500041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.500091] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.500156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.500451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.500568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.533400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.533446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.533515] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.550517] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.550565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.550605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.550649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.550689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.550733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.550772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.550812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.550851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.550895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.550937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.550978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.551020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.551059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.551098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.551155] [drm:intel_power_well_disable [i915]] disabling display
>[  909.551200] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.551243] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.551265] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.551441] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.551462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.551529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.551556] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.551582] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.551612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.551637] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.551663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.551689] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.551716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.551742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.551768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.551793] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.551799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.551824] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.551829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.551855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.551881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.551907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.551932] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.551959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.551984] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.552010] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.552036] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.552062] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.552089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.552117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.552179] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.552201] [drm:intel_power_well_enable [i915]] enabling display
>[  909.552223] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.552267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.552301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.552326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.552376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.552405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.552434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.552467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.552498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.552528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.552554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.552580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.552612] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.552640] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.554703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.554727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.554750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.554774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.556345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.556383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.556406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.557966] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.557988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.559910] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.563208] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.563295] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.563328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.563452] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.563529] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.563558] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.580081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.580131] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.580196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.580480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.580593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.613438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.613485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.613557] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.630598] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.630640] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.630672] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.630710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.630744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.630778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.630808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.630838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.630869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.630911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.630954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.630996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.631037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.631076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.631115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.631172] [drm:intel_power_well_disable [i915]] disabling display
>[  909.631218] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.631267] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.631305] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.631573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.631603] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.631740] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.631792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.631847] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.631906] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.631947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.631991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.632035] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.632077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.632118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.632157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.632195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.632205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.632241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.632251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.632289] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.632327] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.632398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.632436] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.632480] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.632520] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.632560] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.632600] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.632636] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.632682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.632729] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.632850] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.632896] [drm:intel_power_well_enable [i915]] enabling display
>[  909.632929] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.632983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.633017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.633051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.633083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.633112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.633146] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.633184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.633220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.633255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.633287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.633318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.633356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.633417] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.635498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.635519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.635537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.635556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.637127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.637147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.637165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.638719] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.638740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.640610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.643944] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.644045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.644078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.644119] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.644191] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.644212] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.660825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.660877] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.660947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.661167] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.661251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.694170] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.694223] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.694297] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.711375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.711450] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.711482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.711521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.711554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.711589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.711628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.711668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.711707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.711752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.711794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.711835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.711877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.711916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.711955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.712012] [drm:intel_power_well_disable [i915]] disabling display
>[  909.712058] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.712107] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.712146] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.712303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.712323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.712505] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.712553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.712589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.712930] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.712960] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.712993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.713023] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.713053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.713083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.713112] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.713138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.713146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.713172] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.713179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.713207] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.713233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.713263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.713288] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.713320] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.713373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.713401] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.713430] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.713459] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.713491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.713526] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.713810] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.713851] [drm:intel_power_well_enable [i915]] enabling display
>[  909.713878] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.713925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.713952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.713980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.714004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.714031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.714056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.714086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.714115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.714145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.714169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.714194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.714225] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.714251] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.716346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.716393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.716412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.716431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.718011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.718036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.718056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.719628] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.719667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.721555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.724680] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.724738] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.724771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.724817] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.724884] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.724911] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.741533] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.741584] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.741650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.741865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.741943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.774881] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.774930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.775004] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.793227] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.793276] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.793316] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.793455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.793512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.793568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.793617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.793664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.793714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.793771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.793823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.793874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.793924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.793970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.794015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.794100] [drm:intel_power_well_disable [i915]] disabling display
>[  909.794165] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.794227] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.794282] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.794516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.794535] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.794615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.794636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.794658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.794684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.794707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.794731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.794755] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.794778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.794802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.794823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.794846] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.794850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.794873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.794877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.794901] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.794924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.794948] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.794970] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.794994] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.795017] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.795040] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.795064] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.795087] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.795112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.795137] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.795197] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.795218] [drm:intel_power_well_enable [i915]] enabling display
>[  909.795237] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.795273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.795297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.795321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.795397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.795435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.795469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.795506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.795540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.795574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.795605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.795636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.795672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.795705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.797782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.797803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.797821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.797841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.799466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.799486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.799505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.801075] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.801098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.802975] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.806293] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.806434] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.806470] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.806515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.806614] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.806658] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.823142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.823192] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.823258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.823596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.823677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.856487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.856535] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.856623] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.873638] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.873682] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.873714] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.873753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.873786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.873822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.873861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.873901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.873941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.873985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.874027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.874074] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.874104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.874131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.874156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.874201] [drm:intel_power_well_disable [i915]] disabling display
>[  909.874236] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.874272] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.874300] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.874732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.874749] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.874825] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.874859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.874895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.874933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.874966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.875002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.875036] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.875081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.875105] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.875127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.875146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.875152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.875171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.875175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.875201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.875226] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.875252] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.875278] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.875303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.875329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.875388] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.875419] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.875448] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.875481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.875514] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.875769] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.875790] [drm:intel_power_well_enable [i915]] enabling display
>[  909.875807] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.875844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.875866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.875886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.875905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.875931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.875957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.875985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.876013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.876041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.876066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.876092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.876119] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.876145] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.878199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.878221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.878239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.878258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.879863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.879887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.879911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.881559] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.881582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.883457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.886796] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.886893] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.886926] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.886968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.887047] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.887079] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.903682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.903732] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.903797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.904000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.904077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.937017] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  909.937065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  909.937153] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  909.954171] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  909.954214] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  909.954247] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  909.954286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.954320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.954438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.954484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.954535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.954581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.954636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.954685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.954734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.954785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.954826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.954863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.954917] [drm:intel_power_well_disable [i915]] disabling display
>[  909.954959] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  909.954998] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.955032] [drm:intel_power_well_disable [i915]] disabling always-on
>[  909.955192] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.955210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  909.955292] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  909.955323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  909.955404] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  909.955441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  909.955472] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  909.955506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  909.955537] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  909.955569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  909.955600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  909.955630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  909.955657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  909.955667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.955694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  909.955702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  909.955731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  909.955757] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  909.955788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.955815] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  909.955847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  909.955873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  909.955902] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  909.955927] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  909.955955] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  909.955984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  909.956017] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  909.956106] [drm:intel_power_well_enable [i915]] enabling always-on
>[  909.956137] [drm:intel_power_well_enable [i915]] enabling display
>[  909.956166] [drm:hsw_set_power_well [i915]] Enabling power well
>[  909.956215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  909.956243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  909.956272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  909.956298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  909.956327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  909.956379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  909.956413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  909.956446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  909.956479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.956506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  909.956536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  909.956571] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  909.956600] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  909.958664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  909.958687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  909.958710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.958735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  909.960327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  909.960365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  909.960384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  909.961948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  909.961971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  909.963879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  909.967150] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  909.967207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  909.967227] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  909.967253] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  909.967314] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  909.967390] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  909.983995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  909.984044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  909.984119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  909.984419] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  909.984540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.017408] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.017457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.017530] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.036292] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.036336] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.036456] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.036507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.036548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.036594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.036634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.036676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.036715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.036762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.036805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.036844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.036888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.036928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.036968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.037027] [drm:intel_power_well_disable [i915]] disabling display
>[  910.037074] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.037136] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.037183] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.037401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.037431] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.037542] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.037564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.037588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.037613] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.037635] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.037662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.037688] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.037714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.037741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.037767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.037792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.037797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.037822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.037827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.037853] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.037879] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.037904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.037930] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.037956] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.037981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.038008] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.038033] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.038059] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.038086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.038115] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.038182] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.038205] [drm:intel_power_well_enable [i915]] enabling display
>[  910.038226] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.038266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.038292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.038318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.038379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.038412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.038442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.038475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.038509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.038540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.038567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.038594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.038627] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.038655] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.040717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.040738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.040756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.040778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.042339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.042384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.042402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.043950] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.043971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.045875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.049192] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.049259] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.049292] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.049402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.049512] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.049546] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.066035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.066082] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.066145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.066633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.066714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.099425] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.099472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.099561] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.116603] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.116646] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.116679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.116718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.116751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.116794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.116835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.116875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.116915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.116959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.117001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.117043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.117087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.117110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.117133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.117169] [drm:intel_power_well_disable [i915]] disabling display
>[  910.117196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.117226] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.117249] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.117416] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.117436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.117682] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.117706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.117731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.117757] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.117778] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.117800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.117822] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.117848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.117874] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.117900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.117926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.117932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.117957] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.117962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.117988] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.118014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.118040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.118065] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.118092] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.118118] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.118140] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.118166] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.118192] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.118219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.118247] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.118310] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.118366] [drm:intel_power_well_enable [i915]] enabling display
>[  910.118393] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.118446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.118477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.118507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.118535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.118563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.118592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.118624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.118655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.118688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.118915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.118935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.118960] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.118981] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.121041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.121064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.121083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.121102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.122682] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.122703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.122721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.124326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.124367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.126239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.129500] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.129556] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.129576] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.129601] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.129662] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.129683] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.146387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.146439] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.146511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.146739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.146844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.179699] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.179747] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.179818] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.198270] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.198314] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.198429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.198488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.198682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.198720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.198750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.198779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.198818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.198839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.198858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.198877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.198896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.198912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.198935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.198969] [drm:intel_power_well_disable [i915]] disabling display
>[  910.198998] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.199028] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.199051] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.199149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.199161] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.199216] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.199240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.199264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.199290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.199313] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.199384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.199422] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.199452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.199485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.199515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.199545] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.199554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.199583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.199590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.199620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.199647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.199677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.199702] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.199735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.199761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.199791] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.199818] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.199847] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.199882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.199917] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.200371] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.200404] [drm:intel_power_well_enable [i915]] enabling display
>[  910.200434] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.200487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.200518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.200549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.200577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.200606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.200634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.200667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.200699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.200730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.200757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.200785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.200815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.200846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.202932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.202955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.202978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.203003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.204592] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.204617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.204640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.206205] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.206227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.208096] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.210687] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.210776] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.210816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.210867] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.210965] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.211023] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.227561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.227611] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.227677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.227895] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.227973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.260960] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.261007] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.261096] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.279457] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.279501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.279533] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.279571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.279604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.279639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.279670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.279699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.279730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.279765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.279798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.279830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.279861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.279889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.279917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.279970] [drm:intel_power_well_disable [i915]] disabling display
>[  910.280016] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.280066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.280105] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.280263] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.280282] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.280451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.280501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.280557] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.280615] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.280662] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.280704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.280742] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.280782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.280817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.280855] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.280888] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.280898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.280931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.280940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.280975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.281007] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.281042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.281073] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.281112] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.281145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.281180] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.281212] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.281247] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.281284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.281327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.281448] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.281487] [drm:intel_power_well_enable [i915]] enabling display
>[  910.281524] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.281584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.281621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.281661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.281688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.281717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.281746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.281779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.281812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.281844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.281871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.281900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.281932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.281964] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.284051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.284078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.284110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.284133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.285713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.285734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.285752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.287368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.287391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.289264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.292600] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.292703] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.292743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.292794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.292885] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.292910] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.309481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.309532] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.309597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.309849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.309941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.342825] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.342877] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.342952] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.360302] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.360381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.360414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.360451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.360484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.360519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.360549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.360578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.360609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.360644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.360676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.360707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.360738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.360766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.360793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.360847] [drm:intel_power_well_disable [i915]] disabling display
>[  910.360887] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.360928] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.360961] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.361100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.361118] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.361201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.361232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.361273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.361296] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.361361] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.361398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.361429] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.361461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.361489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.361520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.361546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.361555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.361582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.361590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.361620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.361646] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.361675] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.361701] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.361734] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.361761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.361791] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.361817] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.361846] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.361880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.361914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.362427] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.362458] [drm:intel_power_well_enable [i915]] enabling display
>[  910.362488] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.362540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.362569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.362599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.362626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.362655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.362683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.362715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.362747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.362778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.362805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.362833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.362864] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.362894] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.364971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.364993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.365012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.365031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.366621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.366643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.366662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.368212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.368235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.370098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.373444] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.373516] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.373536] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.373561] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.373623] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.373644] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.390313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.390397] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.390468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.390693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.390799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.423655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.423704] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.423775] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.442260] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.442309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.442429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.442488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.442683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.442721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.442752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.442782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.442814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.442850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.442882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.442913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.442944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.442972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.442999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.443051] [drm:intel_power_well_disable [i915]] disabling display
>[  910.443098] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.443128] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.443151] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.443251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.443263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.443369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.443401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.443437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.443474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.443503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.443536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.443566] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.443598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.443627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.443657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.443683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.443693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.443720] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.443728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.443758] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.443785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.443814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.444137] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.444168] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.444198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.444226] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.444255] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.444281] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.444314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.444370] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.444608] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.444637] [drm:intel_power_well_enable [i915]] enabling display
>[  910.444665] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.444713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.444742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.444768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.444795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.444819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.444848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.444878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.444907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.444937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.444961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.444986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.445017] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.445043] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.447120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.447142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.447160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.447180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.448755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.448775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.448793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.450425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.450448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.452305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.455623] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.455696] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.455725] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.455763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.455832] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.455862] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.472483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.472533] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.472598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.472841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.472934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.505826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.505879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.505955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.524261] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.524309] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.524428] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.524629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.524664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.524707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.524733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.524758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.524785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.524815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.524843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.524870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.524896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.524920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.524943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.524987] [drm:intel_power_well_disable [i915]] disabling display
>[  910.525021] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.525056] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.525084] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.525217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.525233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.525308] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.525387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.525436] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.525485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.525524] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.525568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.525608] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.525651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.525691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.525732] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.525759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.525768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.525796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.525803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.525834] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.525861] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.525892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.525918] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.525951] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.525978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.526008] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.526354] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.526386] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.526422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.526456] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.526545] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.526576] [drm:intel_power_well_enable [i915]] enabling display
>[  910.526606] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.526656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.526689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.526717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.526746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.526772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.526803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.526838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.526869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.526901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.526927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.526954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.526985] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.527015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.529089] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.529111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.529130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.529150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.530724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.530750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.530772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.532360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.532381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.534259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.537576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.537642] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.537681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.537733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.537816] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.537856] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.554426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.554476] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.554541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.554790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.554881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.587770] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.587818] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.587892] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.604919] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.604967] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.605007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.605052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.605092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.605136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.605176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.605215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.605255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.605299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.605427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.605465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.605500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.605532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.605564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.605620] [drm:intel_power_well_disable [i915]] disabling display
>[  910.605662] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.605704] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.605739] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.605901] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.605921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.606016] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.606046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.606078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.606113] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.606143] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.606174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.606205] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.606234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.606263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.606290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.606359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.606370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.606400] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.606408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.606439] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.606470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.606501] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.606530] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.606565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.606595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.606626] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.606654] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.606684] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.606719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.606753] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.606845] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.606877] [drm:intel_power_well_enable [i915]] enabling display
>[  910.606907] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.606958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.606989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.607020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.607049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.607079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.607110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.607143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.607175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.607207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.607236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.607265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.607299] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.607357] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.609421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.609442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.609461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.609485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.611046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.611077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.611099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.612664] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.612685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.614556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.617790] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.617822] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.617842] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.617867] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.617926] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.617951] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.634621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.634671] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.634741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.634965] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.635071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.667966] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.668015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.668087] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.685121] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.685166] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.685205] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.685250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.685290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.685421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.685476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.685529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.685581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.685858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.685901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.685943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.685985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.686024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.686063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.686119] [drm:intel_power_well_disable [i915]] disabling display
>[  910.686165] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.686210] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.686231] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.686573] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.686593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.686675] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.686696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.686718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.686745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.686767] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.686792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.686815] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.686838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.686862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.686885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.686908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.686913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.686935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.686939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.686963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.686984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.687007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.687030] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.687054] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.687087] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.687111] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.687132] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.687160] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.687181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.687203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.687260] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.687278] [drm:intel_power_well_enable [i915]] enabling display
>[  910.687345] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.687399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.687433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.687466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.687497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.687525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.687557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.687593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.687626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.687661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.687692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.687723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.687758] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.687791] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.690159] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.690183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.690205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.690230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.691819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.691840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.691859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.693508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.693529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.695423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.698733] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.698801] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.698828] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.698864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.698929] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.698957] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.715591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.715640] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.715705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.715949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.716043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.748930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.748982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.749057] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.766087] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.766131] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.766164] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.766202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.766235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.766271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.766301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.766425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.766477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.766537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.766591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.766641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.766693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.766737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.766776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.766855] [drm:intel_power_well_disable [i915]] disabling display
>[  910.766914] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.766953] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.766988] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.767144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.767172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.767254] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.767284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.767357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.767398] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.767429] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.767463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.767498] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.767531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.767564] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.767594] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.767625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.767634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.767664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.767672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.767702] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.767732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.767764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.767795] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.767828] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.767857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.767889] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.767917] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.767946] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.767976] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.768010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.768100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.768132] [drm:intel_power_well_enable [i915]] enabling display
>[  910.768162] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.768212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.768244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.768275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.768329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.768360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.768392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.768426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.768460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.768493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.768522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.768552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.768585] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.768616] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.770678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.770699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.770718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.770741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.772301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.772347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.772370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.773944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.773967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.775848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.779077] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.779113] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.779133] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.779158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.779218] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.779239] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.795912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.795961] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.796025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.796270] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.796460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.829254] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.829303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.829694] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.847714] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.847757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.847789] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.847828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.847862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.847898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.847928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.847958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.847990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.848025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.848057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.848088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.848118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.848146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.848174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.848227] [drm:intel_power_well_disable [i915]] disabling display
>[  910.848267] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.848391] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.848460] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.848854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.848872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.848955] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.848986] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.849018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.849053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.849082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.849113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.849144] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.849173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.849202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.849231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.849259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.849265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.849292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.849347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.849379] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.849410] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.849441] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.849471] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.849502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.849532] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.849563] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.849593] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.849624] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.849658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.849693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.849957] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.849977] [drm:intel_power_well_enable [i915]] enabling display
>[  910.849995] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.850032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.850054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.850074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.850099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.850124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.850150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.850177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.850204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.850231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.850257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.850282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.850342] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.850376] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.852609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.852630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.852652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.852676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.854248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.854269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.854291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.855871] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.855895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.857773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.861096] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.861159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.861199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.861251] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.861419] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.861460] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.877946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.877996] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.878061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.878268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.878448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.911356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.911405] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.911479] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  910.928466] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  910.928510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  910.928542] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  910.928580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.928614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.928649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.928679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.928707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.928738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.928774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.928807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.928838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.928868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.928896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.928924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.928977] [drm:intel_power_well_disable [i915]] disabling display
>[  910.929018] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  910.929066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.929114] [drm:intel_power_well_disable [i915]] disabling always-on
>[  910.929200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.929212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  910.929264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  910.929284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  910.929371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  910.929408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  910.929437] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  910.929468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  910.929499] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  910.929528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  910.929558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  910.929586] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  910.929613] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  910.929621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.929647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  910.929655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  910.929682] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  910.929708] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  910.929738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  910.929766] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  910.929796] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  910.929822] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  910.929849] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  910.929878] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  910.929899] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  910.929926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.929955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  910.930034] [drm:intel_power_well_enable [i915]] enabling always-on
>[  910.930054] [drm:intel_power_well_enable [i915]] enabling display
>[  910.930072] [drm:hsw_set_power_well [i915]] Enabling power well
>[  910.930109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  910.930130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  910.930155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  910.930181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  910.930207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  910.930233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  910.930261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  910.930290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  910.930350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.930380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  910.930408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  910.930441] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  910.930471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  910.932548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  910.932569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  910.932588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.932607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  910.934174] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  910.934196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  910.934214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  910.935809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  910.935832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  910.937810] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  910.941123] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  910.941193] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  910.941226] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  910.941267] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  910.941406] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  910.941437] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  910.957981] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  910.958031] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  910.958095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  910.958400] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  910.958517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  910.991382] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  910.991428] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  910.991497] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.008530] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.008575] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.008607] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.008645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.008678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.008712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.008743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.008771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.008803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.008838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.008870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.008901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.008932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.008959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.008986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.009038] [drm:intel_power_well_disable [i915]] disabling display
>[  911.009078] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.009120] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.009154] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.009391] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.009705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.009796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.009837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.009860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.009885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.009905] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.009927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.009949] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.009969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.009989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.010007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.010025] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.010030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.010047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.010052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.010070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.010088] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.010106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.010123] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.010144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.010161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.010179] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.010196] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.010214] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.010234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.010258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.010372] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.010401] [drm:intel_power_well_enable [i915]] enabling display
>[  911.010428] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.010653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.010675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.010700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.010726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.010751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.010776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.010804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.010831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.010858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.010883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.010909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.010935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.010961] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.012991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.013014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.013035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.013055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.014601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.014623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.014645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.016211] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.016245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.018196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.021589] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.021679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.021709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.021750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.021835] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.021867] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.038468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.038519] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.038584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.038841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.038934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.071809] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.071858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.071931] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.090234] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.090281] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.090398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.090590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.090626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.090670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.090695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.090720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.090746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.090776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.090804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.090830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.090855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.090879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.090902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.090945] [drm:intel_power_well_disable [i915]] disabling display
>[  911.090980] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.091014] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.091042] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.091175] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.091191] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.091262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.091335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.091385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.091433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.091471] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.091516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.091555] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.091596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.091633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.091671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.091708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.091717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.091744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.091752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.091781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.091810] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.091840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.091867] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.091898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.091925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.092261] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.092315] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.092344] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.092377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.092514] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.092610] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.092650] [drm:intel_power_well_enable [i915]] enabling display
>[  911.092680] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.092736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.092762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.092789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.092813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.092839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.092865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.092894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.092923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.092951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.092975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.093001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.093031] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.093057] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.095138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.095160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.095179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.095198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.096763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.096788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.096813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.098408] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.098429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.100295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.103649] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.103740] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.103773] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.103815] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.103897] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.103919] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.120523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.120573] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.120638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.120891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.120982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.153867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.153915] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.153987] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.172233] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.172276] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.172390] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.172448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.172645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.172682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.172713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.172743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.172775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.172810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.172843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.172874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.172905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.172934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.172971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.173027] [drm:intel_power_well_disable [i915]] disabling display
>[  911.173073] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.173123] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.173162] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.173346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.173367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.173698] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.173722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.173747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.173774] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.173797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.173821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.173844] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.173868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.173892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.173915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.173938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.173942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.173965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.173969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.173993] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.174016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.174040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.174063] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.174086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.174109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.174132] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.174155] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.174178] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.174203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.174228] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.174331] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.174364] [drm:intel_power_well_enable [i915]] enabling display
>[  911.174395] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.174447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.174480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.174511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.174541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.174569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.174600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.174635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.174670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.174702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.175018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.175046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.175080] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.175109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.177164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.177195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.177213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.177232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.178820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.178840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.178858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.180535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.180559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.182436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.185702] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.185753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.185773] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.185798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.185858] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.185880] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.202536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.202583] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.202646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.202846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.202920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.235894] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.235943] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.236013] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.254700] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.254743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.254776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.254814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.254847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.254881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.254911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.254940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.254972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.255006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.255038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.255069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.255109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.255135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.255162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.255212] [drm:intel_power_well_disable [i915]] disabling display
>[  911.255250] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.255358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.255411] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.255939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.255965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.256048] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.256081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.256123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.256147] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.256165] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.256185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.256205] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.256224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.256241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.256258] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.256321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.256333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.256360] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.256368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.256398] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.256425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.256455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.256481] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.256512] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.256539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.256569] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.256596] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.256624] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.256948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.256982] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.257079] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.257108] [drm:intel_power_well_enable [i915]] enabling display
>[  911.257134] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.257181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.257209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.257235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.257261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.257325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.257358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.257391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.257424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.257456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.257482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.257510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.257544] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.257573] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.259809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.259830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.259849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.259867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.261460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.261483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.261502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.263071] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.263094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.264961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.268276] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.268395] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.268416] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.268441] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.268505] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.268537] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.285172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.285222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.285287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.285759] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.285852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.318522] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.318570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.318641] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.337096] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.337140] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.337172] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.337215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.337255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.337378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.337426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.337476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.337522] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.337858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.337901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.337951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.337984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.338011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.338037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.338081] [drm:intel_power_well_disable [i915]] disabling display
>[  911.338115] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.338152] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.338180] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.338651] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.338673] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.338750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.338780] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.338811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.338844] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.338870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.338899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.338927] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.338954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.338985] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.339002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.339018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.339023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.339039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.339043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.339060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.339076] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.339092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.339108] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.339128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.339144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.339161] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.339177] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.339193] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.339213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.339233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.339342] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.339374] [drm:intel_power_well_enable [i915]] enabling display
>[  911.339405] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.339456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.339491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.339519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.339549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.339575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.339606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.339932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.339965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.339996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.340023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.340051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.340085] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.340114] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.342178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.342199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.342217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.342241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.343842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.343863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.343883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.345461] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.345484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.347367] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.350703] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.350805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.350846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.350897] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.350979] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.351019] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.367585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.367635] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.367700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.367949] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.368039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.400929] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.400978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.401048] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.419113] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.419161] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.419202] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.419246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.419286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.419411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.419462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.419512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.419559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.419616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.419661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.419693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.419724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.419750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.419777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.419831] [drm:intel_power_well_disable [i915]] disabling display
>[  911.419871] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.419911] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.419945] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.420090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.420109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.420206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.420237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.420268] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.420350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.420381] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.420416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.420447] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.420479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.420510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.420540] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.420567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.420576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.420603] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.420611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.420642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.420671] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.420701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.420728] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.420761] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.420787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.420817] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.420843] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.420871] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.420903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.420936] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.421011] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.421043] [drm:intel_power_well_enable [i915]] enabling display
>[  911.421073] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.421122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.421152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.421179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.421208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.421236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.421266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.421323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.421355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.421389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.421416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.421445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.421479] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.421510] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.423581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.423602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.423620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.423639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.425202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.425222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.425240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.426834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.426854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.428738] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.431996] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.432056] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.432076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.432106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.432168] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.432193] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.448854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.448903] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.448968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.449187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.449378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.482196] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.482244] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.482408] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.499404] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.499448] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.499481] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.499519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.499559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.499603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.499643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.499682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.499722] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.499765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.499808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.499849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.499891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.499930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.499969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.500025] [drm:intel_power_well_disable [i915]] disabling display
>[  911.500070] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.500120] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.500159] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.500331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.500351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.500440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.500476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.500511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.500551] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.500584] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.500618] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.500651] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.500681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.500713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.500744] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.500774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.500782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.500810] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.500817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.500847] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.500876] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.500905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.500933] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.500965] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.500994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.501023] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.501052] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.501081] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.501114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.501148] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.501238] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.501269] [drm:intel_power_well_enable [i915]] enabling display
>[  911.501322] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.501374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.501408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.501439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.501471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.501504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.501536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.501571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.501605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.501638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.501666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.501694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.501730] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.501762] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.503878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.503900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.503919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.503938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.505513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.505536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.505557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.507123] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.507146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.509021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.512335] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.512412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.512432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.512459] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.512519] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.512540] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.529191] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.529241] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.529396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.529696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.529787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.562532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.562584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.562659] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.581187] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.581231] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.581264] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.581395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.581449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.581656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.581688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.581718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.581749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.581785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.581817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.581848] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.581878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.581895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.581917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.581951] [drm:intel_power_well_disable [i915]] disabling display
>[  911.581979] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.582009] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.582032] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.582132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.582144] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.582199] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.582223] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.582247] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.582328] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.582365] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.582400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.582435] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.582468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.582501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.582532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.582563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.582571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.582600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.582608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.582640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.582670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.582701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.582730] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.582764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.582794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.582825] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.582855] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.582886] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.582958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.582995] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.583378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.583411] [drm:intel_power_well_enable [i915]] enabling display
>[  911.583442] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.583502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.583533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.583562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.583590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.583618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.583647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.583678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.583709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.583739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.583766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.583792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.583824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.583853] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.585930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.585951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.585970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.585989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.587568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.587589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.587607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.589146] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.589168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.591030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.594305] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.594354] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.594381] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.594417] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.594482] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.594509] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.611144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.611194] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.611259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.611747] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.611837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.644488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.644536] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.644610] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.663341] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.663389] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.663429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.663474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.663514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.663558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.663598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.663638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.663677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.663721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.663763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.663805] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.663846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.663885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.663924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.663981] [drm:intel_power_well_disable [i915]] disabling display
>[  911.664026] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.664076] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.664115] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.664311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.664341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.664482] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.664527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.664553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.664582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.664607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.664634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.664660] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.664684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.664711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.664736] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.664762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.664768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.664793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.664798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.664823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.664848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.664875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.664901] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.664927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.664952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.664979] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.665005] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.665031] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.665058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.665086] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.665139] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.665161] [drm:intel_power_well_enable [i915]] enabling display
>[  911.665182] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.665221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.665247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.665300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.665332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.665361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.665390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.665423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.665454] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.665485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.665512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.665539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.665570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.665600] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.667676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.667700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.667721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.667742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.669310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.669341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.669368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.670942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.670965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.672841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.676151] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.676224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.676256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.676377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.676649] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.676684] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.693007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.693057] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.693123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.693584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.693664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.726351] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.726399] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.726470] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.745382] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.745426] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.745459] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.745497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.745531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.745566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.745596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.745625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.745656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.745691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.745723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.745754] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.745785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.745812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.745839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.745893] [drm:intel_power_well_disable [i915]] disabling display
>[  911.745933] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.745973] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.746007] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.746159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.746177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.746251] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.746337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.746375] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.746413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.746445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.746481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.746514] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.746547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.746580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.746612] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.746643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.746652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.746681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.746689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.746719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.746748] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.746780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.746809] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.746843] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.746873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.747247] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.747305] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.747338] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.747471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.747504] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.747587] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.747617] [drm:intel_power_well_enable [i915]] enabling display
>[  911.747645] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.747692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.747721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.747750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.747778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.747806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.747835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.747866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.747896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.747926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.747953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.747980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.748011] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.748040] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.750102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.750125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.750145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.750166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.751731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.751751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.751768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.753393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.753414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.755380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.758680] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.758759] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.758786] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.758822] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.758887] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.758915] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.775539] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.775589] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.775653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.775893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.775988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.808889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.808937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.809007] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.827206] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.827249] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.827375] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.827433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.827636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.827673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.827704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.827734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.827766] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.827800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.827833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.827864] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.827895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.827932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.827949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.827981] [drm:intel_power_well_disable [i915]] disabling display
>[  911.828006] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.828035] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.828058] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.828156] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.828168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.828223] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.828247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.828323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.828363] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.828395] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.828431] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.828465] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.828498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.828530] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.828561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.828591] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.828600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.828629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.828637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.828667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.828697] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.828728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.828758] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.828791] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.828821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.828852] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.828882] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.828913] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.828947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.829306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.829393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.829425] [drm:intel_power_well_enable [i915]] enabling display
>[  911.829456] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.829516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.829546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.829575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.829604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.829632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.829661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.829693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.829723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.829753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.829780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.829807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.829838] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.829868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.831946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.831970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.831993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.832017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.833586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.833607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.833626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.835174] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.835195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.837060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.840377] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.840435] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.840461] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.840496] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.840557] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.840588] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.857223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.857357] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.857459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.857688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.857764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.890570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.890620] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.890693] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.907730] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.907772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.907804] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.907842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.907875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.907910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.907941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.907970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.908001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.908036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.908069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.908100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.908130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.908157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.908184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.908237] [drm:intel_power_well_disable [i915]] disabling display
>[  911.908363] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.908430] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.908691] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.908795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.908808] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.908865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.908887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.908912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.908941] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.908966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.908994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.909020] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.909046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.909072] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.909098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.909123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.909129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.909154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.909158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.909186] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.909211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.909235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.909290] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.909323] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.909352] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.909381] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.909409] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.909436] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.909468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.909501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.909777] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.909797] [drm:intel_power_well_enable [i915]] enabling display
>[  911.909815] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.909852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.909874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.909894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.909914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.909933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.909959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.909987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.910015] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.910043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.910068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.910094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.910121] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.910147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.912194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.912216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.912234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.912300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.913959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.913979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.913998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.915562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.915583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.917456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  911.920792] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  911.920884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  911.920910] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  911.920944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  911.921006] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  911.921033] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  911.937671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.937720] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.937785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.938002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.938096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.971018] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  911.971069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  911.971144] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  911.988168] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  911.988211] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  911.988243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  911.988374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.988427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.988483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.988532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.988563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.988601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  911.988648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.988692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.988734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.988778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.988817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.988862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.988935] [drm:intel_power_well_disable [i915]] disabling display
>[  911.988977] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  911.989024] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  911.989058] [drm:intel_power_well_disable [i915]] disabling always-on
>[  911.989184] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  911.989196] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  911.989285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  911.989317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  911.989351] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  911.989387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  911.989416] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  911.989447] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  911.989477] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  911.989506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  911.989534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  911.989562] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  911.989588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  911.989597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.989623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  911.989630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  911.989660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  911.989690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  911.989717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  911.989747] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  911.989779] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  911.989809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  911.989840] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  911.989868] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  911.989897] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  911.989931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  911.989966] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  911.990042] [drm:intel_power_well_enable [i915]] enabling always-on
>[  911.990062] [drm:intel_power_well_enable [i915]] enabling display
>[  911.990080] [drm:hsw_set_power_well [i915]] Enabling power well
>[  911.990114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  911.990134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  911.990155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  911.990179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  911.990206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  911.990231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  911.990287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  911.990319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  911.990350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  911.990377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  911.990404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  911.990437] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  911.990466] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  911.992530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  911.992551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  911.992570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.992589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  911.994158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  911.994178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  911.994196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  911.995772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  911.995793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  911.997773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.001070] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  912.001158] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.001190] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  912.001232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.001406] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  912.001438] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  912.017946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.017996] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.018063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.018378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.018515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.051315] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  912.051366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.051442] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  912.068442] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  912.068505] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  912.068554] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.068609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.068659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.068711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.068756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.068807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.068849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.068897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.068941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.068983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.069026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.069064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.069101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.069173] [drm:intel_power_well_disable [i915]] disabling display
>[  912.069231] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.069721] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.069757] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.069881] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.069894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.069952] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.069982] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.070004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.070027] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.070045] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.070065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.070084] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  912.070103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  912.070121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.070139] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.070161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.070166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.070189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.070193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.070217] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.070239] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.070307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.070343] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  912.070374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.070406] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.070435] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  912.070467] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  912.070494] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  912.070527] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.070562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  912.070653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.070684] [drm:intel_power_well_enable [i915]] enabling display
>[  912.070713] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.070762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.070791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.070820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.070847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.070875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.070903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.070935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.070966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.070998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.071024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.071051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.071082] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  912.071112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.073195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.073217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.073235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.073307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.074875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.074895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.074917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.076479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.076502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.078370] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.081012] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  912.081080] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.081100] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  912.081126] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.081187] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  912.081208] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  912.097873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.097923] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.097993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.098329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.098628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.131221] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  912.131303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.131374] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  912.150104] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  912.150152] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  912.150193] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.150237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.150355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.150414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.150469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.150511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.150551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.150603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.150647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.150691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.150734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.150770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.150808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.150882] [drm:intel_power_well_disable [i915]] disabling display
>[  912.150938] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.150992] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.151038] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.151300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.151327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.151453] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.151503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.151533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.151566] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.151592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.151621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.151649] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  912.151677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  912.151702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.151740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.151766] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.151774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.151807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.151813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.151839] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.151863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.151889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.151912] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  912.151941] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.151965] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.151991] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  912.152015] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  912.152040] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  912.152071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.152102] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  912.152189] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.152218] [drm:intel_power_well_enable [i915]] enabling display
>[  912.152282] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.152335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.152368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.152397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.152427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.152454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.152486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.152520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.152555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.152588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.152615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.152644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.152679] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  912.152708] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.154762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.154783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.154801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.154821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.156426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.156449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.156468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.158010] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.158041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.159914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.163201] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  912.163367] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.163415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  912.163483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.163700] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  912.163737] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  912.180053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.180105] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.180174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.180464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.180542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.213398] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  912.213434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.213499] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  912.231987] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  912.232035] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  912.232076] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.232113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.232143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.232176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.232203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.232241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.232332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.232370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.232405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.232437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.232469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.232498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.232527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.232583] [drm:intel_power_well_disable [i915]] disabling display
>[  912.232617] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.232659] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.232686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.232795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.232808] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.232865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.232886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.232909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.232933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.232953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.232974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.232995] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  912.233014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  912.233033] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.233051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.233069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.233074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.233099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.233107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.233137] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.233165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.233194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.233221] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  912.233294] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.233324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.233354] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  912.233384] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  912.233414] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  912.233449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.233484] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  912.233574] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.233606] [drm:intel_power_well_enable [i915]] enabling display
>[  912.233636] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.233689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.233720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.233750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.233779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.233809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.233839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.233873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.233906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.233938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.233966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.233994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.234029] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  912.234060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.236142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.236177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.236207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.236248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.237919] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.237954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.237985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.239529] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.239554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.241400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.244804] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  912.244886] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.244917] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  912.244962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.245052] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  912.245086] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  912.261661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.261702] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.261754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.261942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.262006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.295031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  912.295083] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.295159] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  912.312960] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  912.313009] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  912.313050] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.313096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.313136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.313181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.313221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.313326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.313375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.313431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.313484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.313530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.313582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.313630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.313675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.313757] [drm:intel_power_well_disable [i915]] disabling display
>[  912.313802] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.313836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.313866] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.313989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.314003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.314062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.314083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.314106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.314131] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.314151] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.314173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.314194] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  912.314214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  912.314266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.314295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.314321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.314330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.314356] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.314363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.314391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.314418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.314445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.314470] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  912.314500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.314526] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.314552] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  912.314579] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  912.314605] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  912.314636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.314671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  912.314749] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.314781] [drm:intel_power_well_enable [i915]] enabling display
>[  912.314811] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.314864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.314895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.314925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.314955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.314984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.315010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.315033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.315054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.315081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.315106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.315133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.315160] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  912.315186] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.317274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.317296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.317315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.317334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.318913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.318935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.318954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.320520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.320542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.322414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.325717] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  912.325798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.325830] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  912.325871] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.325955] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  912.325980] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  912.342582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.342634] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.342705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.342916] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.343000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.375901] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  912.375939] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.376002] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  912.393766] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  912.393809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  912.393842] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.393881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.393914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.393949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.393979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.394008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.394040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.394077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.394111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.394144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.394176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.394206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.394234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.394460] [drm:intel_power_well_disable [i915]] disabling display
>[  912.394505] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.394548] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.394584] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.394748] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.394768] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.394857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.394891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.394924] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.394949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.394969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.394992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.395013] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  912.395034] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  912.395054] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.395073] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.395091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.395096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.395113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.395117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.395136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.395154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.395172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.395190] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  912.395211] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.395267] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.395296] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  912.395322] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  912.395349] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  912.395380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.395412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  912.395491] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.395531] [drm:intel_power_well_enable [i915]] enabling display
>[  912.395563] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.395616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.395648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.395678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.395708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.395739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.395770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.395804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.395836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.395869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.395898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.395926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.395961] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  912.395993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.398070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.398105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.398136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.398169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.399913] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.399947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.399978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.401623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.401659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.403560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.406243] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  912.406378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.406400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  912.406433] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.406492] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  912.406534] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  912.423191] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.423253] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.423479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.423698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.423775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.456514] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  912.456566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.456642] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  912.474792] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  912.474836] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  912.474868] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.474907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.474939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.474974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.475003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.475032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.475063] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.475097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.475138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.475168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.475197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.475223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.475325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.475409] [drm:intel_power_well_disable [i915]] disabling display
>[  912.475468] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.475525] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.475575] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.475777] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.475805] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.475931] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.475974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.476023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.476076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.476117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.476161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.476192] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  912.476223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  912.476278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.476306] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.476376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.476383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.476411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.476418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.476447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.476473] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.476500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.476525] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  912.476556] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.476582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.476610] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  912.476636] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  912.476663] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  912.476692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.476725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  912.476811] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.476842] [drm:intel_power_well_enable [i915]] enabling display
>[  912.476872] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.476921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.476951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.476978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.477007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.477033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.477062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.477094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.477126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.477157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.477182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.477211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.477267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  912.477296] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.479354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.479375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.479397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.479421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.480983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.481007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.481029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.482584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.482616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.484477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.487784] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  912.487860] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.487892] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  912.487934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.488010] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  912.488043] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  912.504642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.504692] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.504756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.504989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.505090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.537983] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  912.538031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.538101] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  912.555096] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  912.555141] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  912.555175] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.555214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.555335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.555505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.555538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.555569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.555602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.555638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.555671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.555704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.555744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.555786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.555826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.555885] [drm:intel_power_well_disable [i915]] disabling display
>[  912.555926] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.555956] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  912.555979] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.556260] [drm:drm_mode_addfb2] [FB:77]
>[  912.556331] [drm:drm_mode_addfb2] [FB:78]
>[  912.585704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  912.585812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.585889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  912.585992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.586004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.586067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.586091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.586115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.586141] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.586162] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.586184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.586209] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  912.586287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  912.586318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.586346] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.586373] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.586382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.586409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.586416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.586443] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.586470] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.586497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.586523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  912.586554] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.586582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.586611] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  912.586638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  912.586665] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  912.586699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.586735] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  912.590147] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.590167] [drm:intel_power_well_enable [i915]] enabling display
>[  912.590193] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.590293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.590325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.590354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.590384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.590410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.590441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.590475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.590507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.590539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.590565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.590594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.590628] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  912.590657] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.592733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.592753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.592772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.592791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.594376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.594396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.594419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.595972] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.595994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.597870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.601190] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  912.601328] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.601377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  912.601446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.618033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.618084] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.618152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.634707] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.634727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.651568] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.651645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.668070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  912.668118] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.668190] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  912.685300] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  912.685338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.685379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.685412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.685446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.685475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.685503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.685535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.685570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.685603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.685634] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.685665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.685693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.685721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.685774] [drm:intel_power_well_disable [i915]] disabling display
>[  912.685814] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.685855] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.685886] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.686021] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.686039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.686120] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.686151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.686186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.686223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.686314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.686371] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.686417] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  912.686467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  912.686512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.686559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.686601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.686623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.686659] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.686668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.686705] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.686739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.686775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.686807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  912.686847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.686880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.686916] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  912.686949] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  912.686985] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  912.687028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.687070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  912.687165] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.687202] [drm:intel_power_well_enable [i915]] enabling display
>[  912.687269] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.687333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.687368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.687406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.687444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.687476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.687513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.687553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.687597] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.687641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.687668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.687696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.687732] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  912.687761] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.689837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.689859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.689882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.689906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.691488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.691510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.691528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.693078] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.693099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.694963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.698313] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  912.698397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.698430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  912.698471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.715183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.715234] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.715524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.715735] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.715810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.731878] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  912.731927] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.732001] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  912.749050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  912.749087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.749127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.749160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.749196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.749320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.749370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.749423] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.749481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.749708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.749762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.749812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.749858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.749903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.749985] [drm:intel_power_well_disable [i915]] disabling display
>[  912.750037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.750072] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.750097] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.750270] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.750294] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.750554] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.750586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.750619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.750655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.750686] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.750718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.750750] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  912.750782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  912.750814] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.750841] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.750872] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.750878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.750909] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.750914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.750946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.750978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.751010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.751045] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  912.751079] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.751101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.751131] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  912.751148] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  912.751165] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  912.751186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.751208] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  912.751335] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.751368] [drm:intel_power_well_enable [i915]] enabling display
>[  912.751641] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.751694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.751727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.751760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.751791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.751821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.751852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.751887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.751920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.751953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.751983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.752013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.752047] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  912.752079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.754164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.754185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.754204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.754275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.755845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.755865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.755886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.757462] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.757485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.759346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.762663] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  912.762729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.762768] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  912.762820] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.779492] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.779540] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.779604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.779848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.779934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.796206] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  912.796286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.796374] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  912.814610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  912.814652] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.814697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.814738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.814782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.814822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.814861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.814900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.814944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.814987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.815029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.815071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.815110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.815148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.815205] [drm:intel_power_well_disable [i915]] disabling display
>[  912.815329] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.815374] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.815408] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.815792] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.815804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.815858] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.815879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.815901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.815924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.815943] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.815963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.815983] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  912.816006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  912.816030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.816053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.816076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.816081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.816104] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.816108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.816132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.816153] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.816176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.816199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  912.816270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.816307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.816337] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  912.816368] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  912.816396] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  912.816430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.816466] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  912.816860] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.816891] [drm:intel_power_well_enable [i915]] enabling display
>[  912.816920] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.816972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.817004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.817032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.817061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.817088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.817119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.817151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.817183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.817215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.817268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.817295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.817328] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  912.817358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.819625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.819647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.819669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.819693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.821327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.821348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.821366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.822913] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.822934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.824804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.828088] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  912.828187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.828220] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  912.828328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.844972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.845023] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.845088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.845419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.845539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.861669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  912.861719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.861807] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  912.880160] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  912.880196] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.880332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.880385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.880441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.880489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.880537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.880587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.880650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.880684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.880717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.880750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.880779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.880808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.880864] [drm:intel_power_well_disable [i915]] disabling display
>[  912.880906] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.880947] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.880987] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.881090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.881101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.881152] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.881171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.881194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.881272] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.881308] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.881342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.881377] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  912.881409] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  912.881442] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.881473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.881504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.881512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.881542] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.881550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.881581] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.881612] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.881642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.881669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  912.881703] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.881733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.881764] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  912.881794] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  912.881824] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  912.881859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.881894] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  912.881968] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.881998] [drm:intel_power_well_enable [i915]] enabling display
>[  912.882029] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.882081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.882113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.882145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.882175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.882204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.882256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.882292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.882326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.882359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.882389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.882419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.882453] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  912.882485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.884555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.884576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.884595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.884614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.886217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.886260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.886287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.887859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.887881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.889747] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.893009] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  912.893064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.893084] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  912.893109] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.909858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.909912] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.909983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.910276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.910396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.926543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  912.926589] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.926677] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  912.943682] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  912.943719] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  912.943763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.943803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.943847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.943887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.943926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.943965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.944009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.944051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.944093] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.944135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.944173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.944212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.944337] [drm:intel_power_well_disable [i915]] disabling display
>[  912.944405] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  912.944600] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.944633] [drm:intel_power_well_disable [i915]] disabling always-on
>[  912.944784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.944803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  912.944890] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  912.944924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  912.944963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  912.945007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  912.945027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  912.945049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  912.945075] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  912.945108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  912.945139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  912.945161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  912.945179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  912.945185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.945205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  912.945236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  912.945264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  912.945292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  912.945320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  912.945346] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  912.945377] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  912.945403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  912.945430] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  912.945457] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  912.945483] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  912.945514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.945546] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  912.945812] [drm:intel_power_well_enable [i915]] enabling always-on
>[  912.945832] [drm:intel_power_well_enable [i915]] enabling display
>[  912.945850] [drm:hsw_set_power_well [i915]] Enabling power well
>[  912.945886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  912.945908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  912.945928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  912.945948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  912.945966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  912.945987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  912.946009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  912.946029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  912.946055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.946081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  912.946107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  912.946134] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  912.946160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  912.948251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  912.948275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  912.948298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.948322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  912.949907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  912.949929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  912.949948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  912.951515] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  912.951536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  912.953409] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  912.956719] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  912.956791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  912.956824] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  912.956866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  912.973580] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  912.973631] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  912.973697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  912.973913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  912.973989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  912.990266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  912.990314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  912.990387] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.007388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.007425] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.007465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.007498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.007532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.007571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.007611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.007650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.007694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.007736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.007778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.007820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.007859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.007898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.007955] [drm:intel_power_well_disable [i915]] disabling display
>[  913.008001] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.008051] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.008086] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.008334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.008609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.008702] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.008734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.008767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.008801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.008829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.008860] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.008901] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.008932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.008972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.009000] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.009028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.009035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.009062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.009069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.009096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.009123] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.009150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.009177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.009204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.009274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.009304] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.009336] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.009366] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.009401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.009437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.009735] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.009766] [drm:intel_power_well_enable [i915]] enabling display
>[  913.009797] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.009849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.009882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.009913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.009944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.009974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.010006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.010040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.010073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.010106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.010137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.010166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.010200] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.010260] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.012484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.012504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.012522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.012540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.014104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.014124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.014142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.015721] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.015744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.017722] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.021010] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.021105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.021138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.021181] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.037894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.037944] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.038010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.038328] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.038422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.054588] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.054638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.054715] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.071748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.071785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.071825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.071858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.071893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.071923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.071952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.071983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.072018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.072050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.072081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.072112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.072153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.072198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.072341] [drm:intel_power_well_disable [i915]] disabling display
>[  913.072406] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.072468] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.072517] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.072719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.072738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.072824] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.072853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.072886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.072922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.072950] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.072982] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.073011] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.073041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.073069] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.073097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.073122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.073130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.073156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.073162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.073191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.073243] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.073275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.073301] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.073334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.073360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.073389] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.073416] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.073445] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.073479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.073514] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.073603] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.073632] [drm:intel_power_well_enable [i915]] enabling display
>[  913.073661] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.073711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.073741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.073768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.073798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.073824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.073854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.073886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.073918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.073949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.073974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.074001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.074032] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.074061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.076152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.076174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.076194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.076275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.077847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.077868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.077886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.079439] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.079460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.081326] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.084639] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.084710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.084743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.084786] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.101473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.101520] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.101583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.101789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.101862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.118163] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.118209] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.118505] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.135535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.135577] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.135622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.135662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.135706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.135746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.135785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.135824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.135868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.135910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.135952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.135994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.136033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.136070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.136103] [drm:intel_power_well_disable [i915]] disabling display
>[  913.136128] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.136156] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.136175] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.136607] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.136625] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.136709] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.136740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.136772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.136807] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.136835] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.136866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.136897] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.136928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.136957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.136986] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.137013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.137020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.137047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.137053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.137081] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.137109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.137136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.137163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.137190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.137257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.137287] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.137319] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.137351] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.137385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.137420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.137733] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.137752] [drm:intel_power_well_enable [i915]] enabling display
>[  913.137770] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.137807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.137829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.137849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.137869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.137888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.137908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.137930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.137951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.137977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.138002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.138028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.138055] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.138080] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.140143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.140166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.140189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.140261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.141842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.141865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.141888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.143452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.143473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.145349] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.148668] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.148730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.148761] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.148801] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.165512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.165563] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.165629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.165841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.165919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.182187] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.182267] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.182337] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.201284] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.201321] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.201361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.201394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.201428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.201457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.201485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.201516] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.201551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.201583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.201614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.201644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.201671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.201698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.201751] [drm:intel_power_well_disable [i915]] disabling display
>[  913.201791] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.201840] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.201875] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.202030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.202048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.202138] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.202179] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.202295] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.202357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.202404] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.202456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.202505] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.202555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.202607] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.202637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.202664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.202674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.202701] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.202709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.202740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.202766] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.202795] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.202822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.202854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.202880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.202910] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.202936] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.202965] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.202997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.203451] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.203538] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.203567] [drm:intel_power_well_enable [i915]] enabling display
>[  913.203596] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.203648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.203680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.203707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.203736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.203763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.203792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.203825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.203858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.203890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.203916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.203943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.203974] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.204004] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.206068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.206089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.206112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.206136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.207728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.207749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.207772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.209365] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.209388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.211309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.214642] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.214744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.214782] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.214808] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.231521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.231574] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.231645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.231882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.231974] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.248198] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.248280] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.248354] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.265361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.265398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.265438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.265471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.265506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.265535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.265564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.265596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.265631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.265663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.265694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.265725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.265763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.265803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.265860] [drm:intel_power_well_disable [i915]] disabling display
>[  913.265905] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.265962] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.265989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.266119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.266135] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.266273] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.266314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.266357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.266402] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.266442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.266482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.266521] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.266559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.266596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.266631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.266666] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.266676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.266714] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.266723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.266759] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.266793] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.266831] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.266865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.266906] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.266940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.266984] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.267012] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.267039] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.267068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.267101] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.267189] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.267236] [drm:intel_power_well_enable [i915]] enabling display
>[  913.267265] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.267316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.267347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.267374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.267402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.267429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.267458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.267491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.267522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.267553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.267579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.267607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.267637] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.267667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.269758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.269779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.269798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.269817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.271400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.271421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.271439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.273000] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.273021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.274897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.278178] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.278274] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.278303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.278339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.295061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.295112] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.295178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.295602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.295698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.311736] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.311783] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.311855] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.330118] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.330155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.330195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.330308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.330364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.330410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.330668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.330701] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.330745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.330787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.330830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.330872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.330911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.330950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.331006] [drm:intel_power_well_disable [i915]] disabling display
>[  913.331052] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.331102] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.331137] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.331575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.331587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.331641] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.331662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.331692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.331724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.331743] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.331764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.331784] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.331803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.331821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.331838] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.331855] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.331860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.331876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.331880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.331897] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.331913] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.331930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.331946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.331965] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.331982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.331998] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.332014] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.332030] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.332049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.332070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.332126] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.332143] [drm:intel_power_well_enable [i915]] enabling display
>[  913.332159] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.332236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.332272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.332300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.332331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.332358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.332389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.332423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.332457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.332491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.332518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.332547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.332583] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.332612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.335046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.335067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.335085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.335104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.336687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.336710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.336733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.338317] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.338339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.340297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.343628] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.343664] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.343684] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.343710] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.360461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.360512] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.360577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.360790] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.360867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.377135] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.377183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.377604] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.396037] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.396074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.396113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.396146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.396181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.396285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.396330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.396384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.396440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.396736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.396769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.396802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.396833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.396850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.396882] [drm:intel_power_well_disable [i915]] disabling display
>[  913.396907] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.396933] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.396951] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.397057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.397075] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.397130] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.397155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.397179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.397256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.397288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.397325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.397356] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.397388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.397416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.397448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.397474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.397483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.397510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.397518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.397549] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.397575] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.397604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.397631] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.397938] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.397969] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.397997] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.398026] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.398052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.398083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.398117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.398228] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.398259] [drm:intel_power_well_enable [i915]] enabling display
>[  913.398289] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.398340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.398370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.398406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.398432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.398456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.398484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.398514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.398544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.398574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.398598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.398623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.398654] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.398680] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.400789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.400810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.400829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.400848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.402421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.402445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.402468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.404018] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.404039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.405911] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.409184] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.409287] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.409313] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.409347] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.426075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.426126] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.426191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.426627] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.426704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.442751] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.442803] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.442876] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.459898] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.459941] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.459985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.460026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.460070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.460110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.460149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.460188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.460307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.460662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.460705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.460748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.460787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.460826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.460881] [drm:intel_power_well_disable [i915]] disabling display
>[  913.460927] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.460977] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.461012] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.461221] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.461241] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.461538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.461562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.461586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.461613] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.461636] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.461660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.461684] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.461708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.461731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.461751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.461774] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.461779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.461802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.461806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.461830] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.461850] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.461874] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.461895] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.461919] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.461942] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.461965] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.461988] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.462012] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.462036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.462062] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.462120] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.462139] [drm:intel_power_well_enable [i915]] enabling display
>[  913.462159] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.462246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.462278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.462311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.462340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.462371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.462400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.462473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.462507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.462540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.462853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.462883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.462915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.462946] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.465029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.465051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.465070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.465089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.466666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.466686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.466704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.468295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.468315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.470206] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.473504] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.473540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.473564] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.473595] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.490342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.490394] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.490460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.490687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.490789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.507021] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.507070] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.507140] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.524160] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.524233] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.524274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.524314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.524358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.524398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.524438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.524477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.524521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.524563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.524605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.524642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.524662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.524680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.524714] [drm:intel_power_well_disable [i915]] disabling display
>[  913.524739] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.524766] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.524784] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.524876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.524887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.524941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.524965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.524990] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.525016] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.525039] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.525063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.525086] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.525110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.525134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.525157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.525180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.525228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.525266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.525274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.525310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.525343] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.525375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.525406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.525441] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.525472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.525504] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.525533] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.525565] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.525600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.525635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.525727] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.525758] [drm:intel_power_well_enable [i915]] enabling display
>[  913.525790] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.525841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.525873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.525904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.525934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.525964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.525996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.526030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.526063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.526097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.526128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.526158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.526213] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.526245] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.528320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.528344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.528367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.528391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.529945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.529976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.529994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.531561] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.531581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.533452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.536763] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.536834] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.536864] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.536889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.553623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.553674] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.553739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.553990] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.554085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.570333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.570383] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.570453] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.587483] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.587526] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.587571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.587612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.587655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.587695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.587735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.587774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.587818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.587860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.587909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.587942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.587970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.587995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.588042] [drm:intel_power_well_disable [i915]] disabling display
>[  913.588078] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.588117] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.588145] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.588406] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.588433] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.588554] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.588595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.588641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.588691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.588730] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.588774] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.588815] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.588856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.588895] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.588934] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.588959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.588967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.588993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.589000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.589028] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.589054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.589082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.589107] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.589149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.589175] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.589228] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.589256] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.589285] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.589319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.589355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.589431] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.589461] [drm:intel_power_well_enable [i915]] enabling display
>[  913.589491] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.589541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.589571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.589599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.589627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.589653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.589683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.589715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.589746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.589777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.589803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.589830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.589861] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.589891] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.591964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.591986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.592005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.592024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.593590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.593611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.593629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.595185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.595223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.597082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.600358] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.600407] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.600435] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.600470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.617199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.617286] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.617353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.617605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.617697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.633895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.633945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.634017] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.652146] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.652184] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.652313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.652364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.652413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.652453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.652495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.652535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.652581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.652625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.652668] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.652707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.652748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.652788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.652847] [drm:intel_power_well_disable [i915]] disabling display
>[  913.652893] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.652944] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.652980] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.653131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.653144] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.653250] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.653282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.653315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.653351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.653379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.653412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.653443] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.653472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.653503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.653523] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.653541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.653546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.653563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.653567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.653585] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.653603] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.653621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.653638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.653659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.653676] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.653695] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.653712] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.653729] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.653750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.653773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.653822] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.653841] [drm:intel_power_well_enable [i915]] enabling display
>[  913.653861] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.653900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.653926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.653952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.653977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.654003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.654028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.654055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.654082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.654108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.654133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.654158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.654223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.654253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.656321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.656342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.656364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.656388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.657950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.657971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.657989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.659555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.659576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.661438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.664752] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.664824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.664875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.664933] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.681595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.681643] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.681706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.681959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.682035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.698273] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.698323] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.698397] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.716893] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.716931] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.716971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.717005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.717040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.717070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.717099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.717137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.717181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.717302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.717356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.717412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.717442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.717473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.717528] [drm:intel_power_well_disable [i915]] disabling display
>[  913.717557] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.717586] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.717607] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.717702] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.717714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.717768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.717799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.717831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.717861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.717887] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.717914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.717940] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.717966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.717992] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.718018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.718043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.718049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.718074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.718079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.718105] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.718131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.718157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.718215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.718249] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.718278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.718307] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.718335] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.718362] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.718394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.718427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.718517] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.718545] [drm:intel_power_well_enable [i915]] enabling display
>[  913.718576] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.718631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.718662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.718693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.718724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.718754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.718784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.718819] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.718852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.718885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.718910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.718929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.718952] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.718974] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.721020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.721041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.721059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.721079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.722652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.722672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.722690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.724300] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.724321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.726173] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.729501] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.729582] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.729602] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.729628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.746361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.746414] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.746485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.746744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.746823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.763035] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.763083] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.763153] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.780294] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.780332] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.780372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.780406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.780441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.780479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.780519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.780558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.780602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.780644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.780686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.780731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.780759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.780785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.780830] [drm:intel_power_well_disable [i915]] disabling display
>[  913.780864] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.780900] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.780926] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.781053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.781068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.781139] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.781167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.781276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.781327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.781368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.781414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.781458] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.781501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.781543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.781585] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.781626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.781638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.781675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.781686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.781732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.781765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.781796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.781830] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.781865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.781897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.781929] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.781960] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.781991] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.782026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.782064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.782163] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.782219] [drm:intel_power_well_enable [i915]] enabling display
>[  913.782253] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.782311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.782346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.782379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.782412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.782441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.782475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.782512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.782547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.782583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.782614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.782643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.782679] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.782714] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.784819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.784841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.784860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.784883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.786452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.786473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.786491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.788051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.788072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.789944] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.793242] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.793325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.793356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.793396] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.810106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.810157] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.810440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.810666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.810743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.826784] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.826833] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.826903] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.843939] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.843977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.844017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.844050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.844085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.844115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.844144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.844176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.844301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.844356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.844707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.844761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.844804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.844850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.844934] [drm:intel_power_well_disable [i915]] disabling display
>[  913.845000] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.845038] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.845068] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.845223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.845236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.845324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.845358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.845393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.845422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.845442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.845464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.845487] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.845507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.845526] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.845545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.845563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.845567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.845585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.845589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.845607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.845625] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.845643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.845667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.845693] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.845717] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.845743] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.845769] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.845794] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.845821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.845848] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.845910] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.845931] [drm:intel_power_well_enable [i915]] enabling display
>[  913.845953] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.845992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.846018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.846044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.846069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.846094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.846119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.846147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.846208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.846243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.846276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.846308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.846345] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.846379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.848458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.848479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.848497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.848516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.850088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.850108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.850126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.851703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.851723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.853660] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.856950] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.857044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.857077] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.857120] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.873816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.873867] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.873937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.874240] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.874566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.890498] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.890543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.890611] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.907660] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.907697] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.907736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.907770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.907812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.907852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.907892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.907931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.907976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.908018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.908060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.908101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.908140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.908179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.908318] [drm:intel_power_well_disable [i915]] disabling display
>[  913.908385] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.908656] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.908687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.908816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.908833] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.908909] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.908930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.908952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.908978] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.909001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.909025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.909049] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.909072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.909096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.909116] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.909140] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.909144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.909167] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.909213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.909250] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.909287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.909320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.909353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.909387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.909419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.909450] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.909482] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.909513] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.909549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.909585] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.909918] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.909949] [drm:intel_power_well_enable [i915]] enabling display
>[  913.909980] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.910032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.910064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.910096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.910126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.910156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.910209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.910244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.910279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.910312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.910342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.910372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.910407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.910555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.912655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.912677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.912695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.912714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.914284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.914304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.914322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.915879] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.915900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.917762] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.921081] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.921145] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.921259] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.921337] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  913.937922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.937975] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.938047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.938363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.938469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.954601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  913.954649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  913.954719] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  913.973124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  913.973161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  913.973294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.973481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.973520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.973551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.973581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.973612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  913.973647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.973689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.973731] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.973781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.973800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.973818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.973850] [drm:intel_power_well_disable [i915]] disabling display
>[  913.973875] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  913.973900] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  913.973919] [drm:intel_power_well_disable [i915]] disabling always-on
>[  913.974012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  913.974023] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  913.974073] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  913.974093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  913.974114] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  913.974136] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  913.974155] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  913.974227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  913.974259] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  913.974294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  913.974325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  913.974356] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  913.974386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  913.974395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.974424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  913.974432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  913.974462] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  913.974492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  913.974522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  913.974552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  913.974586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  913.974616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  913.974647] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  913.974677] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  913.974707] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  913.974742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  913.974776] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  913.975199] [drm:intel_power_well_enable [i915]] enabling always-on
>[  913.975230] [drm:intel_power_well_enable [i915]] enabling display
>[  913.975260] [drm:hsw_set_power_well [i915]] Enabling power well
>[  913.975313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  913.975346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  913.975378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  913.975408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  913.975438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  913.975471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  913.975506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  913.975540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  913.975572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  913.975603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  913.975632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  913.975666] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  913.975697] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  913.977771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  913.977792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  913.977810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.977829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  913.979428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  913.979450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  913.979468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  913.981028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  913.981050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  913.982927] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  913.986163] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  913.986245] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  913.986265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  913.986291] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.003040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.003091] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.003156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.003610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.003688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.019714] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.019776] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.019847] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.036865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.036903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.036942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.036976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.037011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.037041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.037071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.037102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.037137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.037258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.037315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.037369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.037418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.037466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.037855] [drm:intel_power_well_disable [i915]] disabling display
>[  914.037920] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.037984] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.038034] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.038274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.038299] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.038410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.038440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.038471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.038504] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.038531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.038561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.038589] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.038615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.038641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.038672] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.038705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.038712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.038745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.038750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.038784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.038814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.038848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.038877] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.038911] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.038940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.038973] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.039006] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.039039] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.039074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.039110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.039240] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.039275] [drm:intel_power_well_enable [i915]] enabling display
>[  914.039310] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.039368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.039406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.039442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.039477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.039512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.039548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.039585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.039623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.039658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.039690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.039723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.039762] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.039796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.041874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.041894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.041913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.041932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.043496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.043516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.043534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.045081] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.045102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.046965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.050283] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.050347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.050388] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.050424] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.067129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.067267] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.067372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.067587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.067663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.083805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.083853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.083923] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.100953] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.100991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.101031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.101065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.101100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.101130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.101169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.101291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.101353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.101408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.101667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.101690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.101709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.101734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.101776] [drm:intel_power_well_disable [i915]] disabling display
>[  914.101801] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.101828] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.101846] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.101932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.101943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.101995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.102014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.102036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.102063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.102086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.102110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.102133] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.102157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.102232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.102264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.102297] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.102306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.102336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.102344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.102375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.102406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.102437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.102467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.102501] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.102531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.102563] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.102593] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.102624] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.102659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.102694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.103058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.103090] [drm:intel_power_well_enable [i915]] enabling display
>[  914.103120] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.103198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.103232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.103262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.103294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.103425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.103455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.103487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.103517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.103546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.103573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.103600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.103631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.103661] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.105754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.105776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.105796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.105817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.107400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.107422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.107441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.108996] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.109018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.110887] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.114233] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.114333] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.114368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.114410] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.131106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.131169] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.131337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.131573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.131663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.147803] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.147852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.147942] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.165011] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.165048] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.165088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.165122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.165157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.165273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.165322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.165372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.165430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.165483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.165518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.165550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.165590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.165631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.165689] [drm:intel_power_well_disable [i915]] disabling display
>[  914.165735] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.165786] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.165822] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.165958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.165970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.166029] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.166055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.166082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.166111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.166136] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.166191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.166223] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.166253] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.166284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.166312] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.166338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.166347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.166373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.166380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.166408] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.166434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.166461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.166486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.166517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.166543] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.166569] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.166596] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.166622] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.166653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.166689] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.166780] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.166811] [drm:intel_power_well_enable [i915]] enabling display
>[  914.166842] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.166895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.166928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.166958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.166989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.167018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.167049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.167080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.167102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.167122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.167141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.167193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.167224] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.167253] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.169328] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.169350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.169370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.169389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.170961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.170982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.171001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.172564] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.172585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.174456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.177791] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.177892] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.177925] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.177967] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.194668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.194719] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.194784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.194999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.195079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.211346] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.211394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.211465] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.228492] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.228529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.228569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.228602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.228644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.228684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.228724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.228763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.228807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.228850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.228891] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.228933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.228972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.229011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.229067] [drm:intel_power_well_disable [i915]] disabling display
>[  914.229112] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.229162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.229296] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.229454] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.229474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.229563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.229597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.229632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.229669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.229700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.229734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.229767] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.229799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.229831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.229861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.229890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.229898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.229926] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.229933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.229963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.229992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.230022] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.230052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.230081] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.230111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.230141] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.230194] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.230225] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.230256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.230291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.230382] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.230414] [drm:intel_power_well_enable [i915]] enabling display
>[  914.230444] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.230496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.230528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.230560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.230591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.230621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.230652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.230685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.230718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.230750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.230780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.230809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.230843] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.230874] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.232937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.232958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.232976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.232995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.234563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.234593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.234611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.236163] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.236210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.238079] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.241392] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.241468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.241488] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.241514] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.258242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.258293] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.258358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.258574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.258652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.274917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.274964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.275033] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.293120] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.293158] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.293280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.293333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.293390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.293439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.293487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.293530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.293568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.293600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.293634] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.293666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.293688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.293706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.293742] [drm:intel_power_well_disable [i915]] disabling display
>[  914.293770] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.293798] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.293818] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.293924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.293936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.293989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.294010] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.294032] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.294057] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.294076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.294098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.294119] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.294139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.294190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.294218] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.294245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.294253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.294279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.294286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.294314] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.294341] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.294368] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.294394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.294425] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.294451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.294478] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.294505] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.294531] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.294561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.294593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.294668] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.294696] [drm:intel_power_well_enable [i915]] enabling display
>[  914.294728] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.294781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.294813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.294843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.294873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.294904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.294935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.294969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.295002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.295030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.295048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.295066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.295089] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.295109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.297207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.297228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.297246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.297265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.298846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.298870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.298893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.300451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.300473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.302343] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.305652] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.305726] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.305758] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.305800] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.322508] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.322558] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.322624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.322823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.322903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.339213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.339261] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.339333] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.356335] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.356373] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.356413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.356446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.356489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.356529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.356568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.356608] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.356652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.356694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.356735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.356777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.356816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.356854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.356911] [drm:intel_power_well_disable [i915]] disabling display
>[  914.356957] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.356998] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.357025] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.357218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.357243] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.357353] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.357383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.357414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.357448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.357474] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.357503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.357531] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.357558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.357585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.357610] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.357635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.357641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.357665] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.357671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.357696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.357720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.357745] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.357777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.357812] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.357845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.357880] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.357914] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.357957] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.357985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.358013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.358075] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.358096] [drm:intel_power_well_enable [i915]] enabling display
>[  914.358117] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.358185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.358217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.358246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.358277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.358304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.358333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.358365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.358396] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.358427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.358453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.358480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.358513] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.358543] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.360606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.360627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.360646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.360665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.362260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.362280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.362299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.363858] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.363881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.365756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.369045] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.369140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.369245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.369301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.385919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.385970] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.386035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.386521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.386602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.402596] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.402645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.402718] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.421497] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.421534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.421574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.421608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.421643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.421673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.421702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.421733] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.421768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.421800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.421831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.421861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.421889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.421916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.421969] [drm:intel_power_well_disable [i915]] disabling display
>[  914.422009] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.422050] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.422080] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.422308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.422328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.422418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.422452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.422487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.422521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.422546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.422573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.422600] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.422626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.422652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.422678] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.422703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.422709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.422734] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.422739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.422765] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.422790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.422817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.422842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.422868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.422893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.422920] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.422946] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.422972] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.422999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.423027] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.423080] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.423101] [drm:intel_power_well_enable [i915]] enabling display
>[  914.423123] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.423197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.423229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.423259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.423287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.423315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.423344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.423376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.423408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.423438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.423465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.423491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.423523] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.423553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.425646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.425667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.425685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.425704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.427278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.427299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.427318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.428869] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.428890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.430758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.434041] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.434140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.434250] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.434322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.450928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.450979] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.451045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.451383] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.451469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.467609] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.467657] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.467726] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.484984] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.485021] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.485061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.485094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.485136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.485252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.485298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.485350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.485406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.485457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.485506] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.485555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.485581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.485609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.485672] [drm:intel_power_well_disable [i915]] disabling display
>[  914.485713] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.485754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.485786] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.485948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.485960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.486012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.486032] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.486053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.486079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.486102] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.486127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.486195] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.486230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.486259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.486289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.486316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.486325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.486354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.486362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.486392] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.486419] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.486449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.486475] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.486509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.486535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.486565] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.486592] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.486620] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.486655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.486688] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.486778] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.486808] [drm:intel_power_well_enable [i915]] enabling display
>[  914.486837] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.486887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.486918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.486945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.486974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.487000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.487029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.487062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.487095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.487126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.487175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.487205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.487237] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.487268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.489334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.489355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.489374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.489392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.490963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.490983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.491002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.492564] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.492585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.494458] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.497762] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.497835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.497867] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.497908] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.514620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.514671] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.514736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.514936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.515015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.531298] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.531346] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.531417] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.548444] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.548482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.548521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.548554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.548589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.548619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.548648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.548679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.548714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.548746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.548777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.548807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.548835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.548868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.548913] [drm:intel_power_well_disable [i915]] disabling display
>[  914.548948] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.548982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.549008] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.549188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.549214] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.549327] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.549356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.549387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.549420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.549445] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.549475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.549503] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.549531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.549557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.549582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.549606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.549613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.549636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.549642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.549667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.549690] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.549715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.549748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.549783] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.549816] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.549851] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.549888] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.549910] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.549932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.549957] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.550017] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.550035] [drm:intel_power_well_enable [i915]] enabling display
>[  914.550053] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.550091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.550117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.550146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.550199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.550229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.550258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.550290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.550321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.550351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.550377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.550406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.550439] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.550468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.552534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.552556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.552574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.552594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.554227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.554247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.554266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.555827] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.555848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.557713] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.561001] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.561096] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.561128] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.561233] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.577873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.577923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.577989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.578306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.578447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.594552] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.594600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.594670] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.613090] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.613132] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.613253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.613302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.613513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.613546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.613577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.613609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.613645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.613686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.613728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.613770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.613809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.613848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.613904] [drm:intel_power_well_disable [i915]] disabling display
>[  914.613950] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.614000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.614035] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.614467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.614487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.614579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.614601] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.614623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.614646] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.614665] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.614688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.614712] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.614736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.614760] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.614780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.614803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.614808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.614831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.614835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.614859] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.614882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.614906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.614929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.614952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.614975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.614998] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.615022] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.615045] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.615070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.615095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.615202] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.615234] [drm:intel_power_well_enable [i915]] enabling display
>[  914.615265] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.615321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.615354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.615384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.615414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.615442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.615474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.615508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.615542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.615882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.615912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.615939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.615973] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.616001] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.618085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.618106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.618128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.618195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.619763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.619783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.619801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.621361] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.621382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.623260] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.626550] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.626629] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.626648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.626674] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.643418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.643466] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.643529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.643736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.643841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.660076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.660120] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.660290] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.677284] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.677326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.677383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.677423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.677466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.677506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.677546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.677585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.677629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.677671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.677713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.677754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.677793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.677832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.677889] [drm:intel_power_well_disable [i915]] disabling display
>[  914.677935] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.677985] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.678020] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.678269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.678297] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.678436] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.678491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.678551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.678588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.678620] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.678653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.678684] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.678714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.678742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.678772] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.678798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.678805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.678832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.678839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.678867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.678894] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.678921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.678947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.678978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.679004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.679032] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.679058] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.679085] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.679114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.679173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.679265] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.679296] [drm:intel_power_well_enable [i915]] enabling display
>[  914.679328] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.679381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.679413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.679445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.679475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.679506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.679534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.679568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.679600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.679631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.679658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.679685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.679716] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.679746] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.681833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.681856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.681878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.681903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.683477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.683498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.683517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.685065] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.685086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.686961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.690308] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.690397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.690429] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.690471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.707188] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.707236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.707301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.707515] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.707591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.723865] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.723911] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.724001] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.742261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.742299] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.742338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.742372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.742406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.742437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.742475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.742514] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.742559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.742601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.742643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.742685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.742723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.742762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.742820] [drm:intel_power_well_disable [i915]] disabling display
>[  914.742866] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.742915] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.742951] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.743051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.743062] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.743115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.743201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.743235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.743271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.743300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.743331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.743361] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.743390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.743419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.743446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.743472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.743481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.743507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.743514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.743545] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.743573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.743600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.743628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.743662] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.743691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.743720] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.743748] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.743776] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.743809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.743844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.743935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.743960] [drm:intel_power_well_enable [i915]] enabling display
>[  914.743979] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.744015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.744035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.744060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.744086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.744113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.744164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.744199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.744231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.744261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.744290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.744316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.744348] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.744378] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.746450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.746472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.746490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.746509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.748068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.748088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.748106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.749706] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.749727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.751618] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.754938] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.755001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.755034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.755076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.771780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.771831] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.771896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.772107] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.772458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.788459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.788507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.788578] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.807085] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.807122] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.807254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.807479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.807517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.807548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.807578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.807610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.807645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.807678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.807709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.807750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.807790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.807829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.807884] [drm:intel_power_well_disable [i915]] disabling display
>[  914.807930] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.807980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.808015] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.808209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.808229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.808510] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.808542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.808574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.808609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.808638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.808669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.808699] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.808729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.808758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.808787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.808815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.808822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.808848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.808854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.808881] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.808908] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.808936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.808960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.808989] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.809016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.809043] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.809067] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.809093] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.809123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.809204] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.809292] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.809583] [drm:intel_power_well_enable [i915]] enabling display
>[  914.809614] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.809668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.809702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.809733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.809764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.809794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.809825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.809859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.809892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.809925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.809954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.809982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.810017] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.810048] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.812107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.812131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.812208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.812319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.813884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.813905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.813928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.815492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.815513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.817383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.820664] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.820709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.820738] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.820775] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.837496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.837547] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.837612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.837824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.837902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.854207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.854255] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.854325] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.871336] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.871374] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.871414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.871447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.871481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.871511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.871540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.871572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.871606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.871638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.871669] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.871700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.871728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.871755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.871808] [drm:intel_power_well_disable [i915]] disabling display
>[  914.871848] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.871889] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.871920] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.872072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.872090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.872284] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.872337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.872395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.872450] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.872481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.872516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.872549] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.872581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.872612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.872641] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.872671] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.872679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.872706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.872713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.872744] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.872773] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.872802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.872831] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.872863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.872892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.872922] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.872951] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.872980] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.873013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.873048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.873162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.873193] [drm:intel_power_well_enable [i915]] enabling display
>[  914.873224] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.873277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.873310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.873343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.873373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.873404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.873436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.873471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.873505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.873537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.873566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.873595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.873629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.873660] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.875731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.875752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.875770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.875789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.877379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.877401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.877420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.878973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.878994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.880863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.884242] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.884295] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.884329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.884371] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.901081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.901131] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.901295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.901524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.901600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.917784] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.917848] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.917937] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.934984] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.935026] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.935071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.935111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.935290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.935343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.935394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.935444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.935501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.935554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.935605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.935656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.935702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.935747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.935816] [drm:intel_power_well_disable [i915]] disabling display
>[  914.935858] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.935899] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.935931] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.936057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.936068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.936120] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.936194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.936230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.936271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.936304] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.936339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.936373] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.936407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.936439] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.936471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.936501] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.936511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.936541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  914.936549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.936579] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  914.936611] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  914.936643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.936672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  914.936706] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  914.936735] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  914.936763] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  914.936791] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  914.936817] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  914.936849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.936883] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  914.936973] [drm:intel_power_well_enable [i915]] enabling always-on
>[  914.937005] [drm:intel_power_well_enable [i915]] enabling display
>[  914.937037] [drm:hsw_set_power_well [i915]] Enabling power well
>[  914.937088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.937120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.937176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.937204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.937234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.937266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.937301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.937334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.937366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.937395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.937424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.937457] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  914.937488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  914.939551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  914.939571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  914.939590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.939609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  914.941175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  914.941195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  914.941213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  914.942782] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  914.942805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  914.944676] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  914.948008] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  914.948045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  914.948069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  914.948100] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  914.964841] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.964892] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.964958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.965359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.965439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  914.981539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  914.981586] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  914.981653] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  914.998667] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  914.998704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  914.998744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  914.998778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  914.998813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  914.998843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  914.998872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  914.998903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  914.998938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  914.998970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  914.999001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  914.999033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  914.999068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  914.999092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  914.999216] [drm:intel_power_well_disable [i915]] disabling display
>[  914.999276] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  914.999327] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  914.999356] [drm:intel_power_well_disable [i915]] disabling always-on
>[  914.999495] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  914.999512] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  914.999587] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  914.999618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  914.999649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  914.999690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  914.999725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  914.999762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  914.999798] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  914.999835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  914.999872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  914.999908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  914.999943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  914.999952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  914.999995] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.000006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.000049] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.000079] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.000113] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.000164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.000195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.000222] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.000251] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.000279] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.000305] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.000337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.000369] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.000460] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.000480] [drm:intel_power_well_enable [i915]] enabling display
>[  915.000497] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.000532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.000552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.000572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.000596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.000622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.000648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.000676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.000701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.000729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.000755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.000781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.000808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.000833] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.002881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.002903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.002922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.002941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.004502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.004522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.004545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.006119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.006158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.008020] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.011300] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.011355] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.011403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.011444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.028121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.028205] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.028270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.028489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.028563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.044804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.044854] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.044926] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.061953] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.061995] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.062040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.062081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.062124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.062244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.062292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.062344] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.062401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.062679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.062699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.062719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.062736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.062753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.062784] [drm:intel_power_well_disable [i915]] disabling display
>[  915.062809] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.062835] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.062853] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.062946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.062957] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.063007] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.063026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.063047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.063070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.063088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.063108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.063174] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.063206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.063236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.063266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.063293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.063302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.063329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.063337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.063368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.063395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.063424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.063451] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.063483] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.063509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.063539] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.063565] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.063594] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.063627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.063662] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.064042] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.064072] [drm:intel_power_well_enable [i915]] enabling display
>[  915.064101] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.064177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.064309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.064335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.064362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.064389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.064417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.064448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.064477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.064507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.064531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.064557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.064588] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.064615] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.066698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.066719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.066737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.066756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.068337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.068379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.068400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.069945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.069967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.071846] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.075129] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.075226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.075257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.075296] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.092016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.092069] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.092213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.092471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.092549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.108706] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.108754] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.108828] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.127060] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.127097] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.127230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.127283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.127339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.127387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.127434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.127484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.127540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.127592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.127642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.127693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.127738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.127784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.127869] [drm:intel_power_well_disable [i915]] disabling display
>[  915.127933] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.128000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.128029] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.128173] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.128186] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.128257] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.128290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.128325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.128362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.128394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.128427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.128455] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.128476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.128496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.128514] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.128532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.128537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.128555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.128559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.128578] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.128597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.128614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.128632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.128653] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.128671] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.128688] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.128706] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.128724] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.128745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.128768] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.128828] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.128846] [drm:intel_power_well_enable [i915]] enabling display
>[  915.128864] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.128898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.128917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.128937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.128955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.128972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.128991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.129012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.129032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.129052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.129069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.129087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.129109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.129168] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.131241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.131264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.131283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.131302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.132862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.132883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.132902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.134457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.134478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.136348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.139664] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.139735] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.139775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.139826] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.156512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.156563] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.156629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.156830] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.156908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.173189] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.173240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.173313] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.190327] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.190369] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.190413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.190454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.190498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.190538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.190577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.190617] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.190660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.190702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.190744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.190786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.190825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.190864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.190920] [drm:intel_power_well_disable [i915]] disabling display
>[  915.190966] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.191016] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.191051] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.191319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.191350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.191441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.191475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.191507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.191533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.191553] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.191576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.191598] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.191618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.191638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.191657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.191675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.191680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.191698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.191702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.191721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.191739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.191757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.191774] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.191796] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.191821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.191849] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.191869] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.191886] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.191908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.191931] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.191992] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.192011] [drm:intel_power_well_enable [i915]] enabling display
>[  915.192029] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.192069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.192095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.192147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.192177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.192205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.192234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.192266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.192297] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.192326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.192352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.192378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.192411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.192440] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.194506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.194528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.194550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.194574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.196167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.196188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.196207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.197759] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.197780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.199646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.202941] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.203027] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.203057] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.203096] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.219807] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.219858] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.219923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.220225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.220342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.236486] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.236537] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.236611] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.253664] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.253702] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.253741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.253774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.253809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.253839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.253868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.253900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.253935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.253967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.253999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.254029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.254057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.254084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.254219] [drm:intel_power_well_disable [i915]] disabling display
>[  915.254287] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.254352] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.254403] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.254641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.254670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.254789] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.254821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.254854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.254891] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.254928] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.254959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.254989] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.255027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.255059] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.255098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.255162] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.255172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.255204] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.255212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.255243] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.255275] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.255306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.255336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.255370] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.255400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.255431] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.255458] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.255488] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.255521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.255556] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.255648] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.255680] [drm:intel_power_well_enable [i915]] enabling display
>[  915.255710] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.255761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.255794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.255824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.255854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.255884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.255915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.255949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.255981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.256014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.256043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.256072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.256106] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.256162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.258226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.258250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.258272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.258297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.259868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.259889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.259908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.261467] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.261488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.263340] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.266659] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.266724] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.266756] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.266798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.283504] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.283554] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.283624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.283845] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.283927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.300180] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.300228] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.300298] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.317326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.317364] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.317403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.317437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.317480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.317520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.317560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.317599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.317643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.317685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.317727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.317768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.317807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.317846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.317902] [drm:intel_power_well_disable [i915]] disabling display
>[  915.317947] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.317997] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.318032] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.318249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.318267] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.318359] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.318394] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.318429] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.318466] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.318498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.318531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.318564] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.318596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.318627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.318657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.318686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.318694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.318722] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.318729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.318758] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.318787] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.318818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.318847] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.318879] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.318909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.318939] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.318968] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.318997] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.319030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.319064] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.319179] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.319211] [drm:intel_power_well_enable [i915]] enabling display
>[  915.319242] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.319294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.319326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.319358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.319389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.319415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.319446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.319481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.319513] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.319546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.319576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.319605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.319638] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.319670] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.321859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.321882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.321905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.321929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.323497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.323518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.323537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.325100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.325132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.326991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.330306] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.330357] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.330376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.330402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.347186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.347236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.347302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.347499] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.347577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.363832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.363879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.363949] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.380979] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.381016] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.381056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.381090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.381214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.381264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.381313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.381363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.381419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.381471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.381504] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.381536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.381565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.381594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.381649] [drm:intel_power_well_disable [i915]] disabling display
>[  915.381691] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.381731] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.381763] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.381902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.381913] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.381964] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.381984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.382005] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.382028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.382047] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.382067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.382087] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.382157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.382188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.382220] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.382250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.382260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.382289] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.382298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.382328] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.382359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.382389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.382419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.382453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.382483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.382515] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.382545] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.382576] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.382611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.382645] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.382733] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.382764] [drm:intel_power_well_enable [i915]] enabling display
>[  915.382794] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.382845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.382877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.382907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.382938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.382967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.382994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.383028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.383060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.383093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.383143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.383174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.383207] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.383239] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.385304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.385328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.385350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.385374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.386947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.386968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.386987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.388540] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.388560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.390431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.393726] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.393807] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.393833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.393866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.410587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.410638] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.410704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.410914] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.410992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.427272] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.427321] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.427391] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.444417] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.444459] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.444504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.444545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.444589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.444629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.444669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.444708] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.444757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.444792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.444823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.444860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.444897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.444934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.444988] [drm:intel_power_well_disable [i915]] disabling display
>[  915.445031] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.445078] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.445193] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.445419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.445444] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.445578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.445628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.445679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.445734] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.445783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.445823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.445862] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.445900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.445939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.445975] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.446009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.446019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.446052] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.446060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.446096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.446163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.446196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.446232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.446272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.446308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.446345] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.446381] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.446417] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.446458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.446501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.446608] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.446644] [drm:intel_power_well_enable [i915]] enabling display
>[  915.446681] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.446741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.446784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.446814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.446844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.446874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.446905] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.446938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.446971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.447003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.447034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.447062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.447096] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.447152] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.449214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.449236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.449259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.449283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.450855] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.450876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.450894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.452458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.452479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.454351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.457653] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.457734] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.457766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.457807] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.474510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.474561] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.474626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.474842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.474920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.491192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.491241] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.491312] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.508335] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.508373] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.508413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.508446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.508480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.508519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.508559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.508598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.508642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.508684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.508726] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.508767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.508806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.508845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.508901] [drm:intel_power_well_disable [i915]] disabling display
>[  915.508947] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.508993] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.509012] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.509180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.509200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.509289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.509323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.509357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.509395] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.509426] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.509460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.509493] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.509524] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.509556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.509585] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.509615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.509622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.509651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.509658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.509687] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.509717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.509746] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.509774] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.509807] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.509836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.509866] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.509896] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.509922] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.509955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.509990] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.510080] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.510137] [drm:intel_power_well_enable [i915]] enabling display
>[  915.510167] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.510221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.510253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.510285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.510317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.510349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.510384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.510420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.510454] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.510488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.510518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.510548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.510583] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.510614] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.512702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.512725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.512748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.512772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.514360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.514383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.514411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.515969] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.515990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.517872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.521235] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.521290] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.521310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.521335] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.538076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.538207] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.538310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.538516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.538591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.554785] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.554833] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.554907] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.573073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.573110] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.573243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.573296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.573351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.573399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.573446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.573495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.573550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.573602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.573653] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.573703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.573748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.573792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.573877] [drm:intel_power_well_disable [i915]] disabling display
>[  915.573942] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.574004] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.574054] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.574308] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.574326] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.574408] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.574438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.574466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.574491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.574514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.574539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.574562] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.574586] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.574610] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.574631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.574653] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.574658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.574681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.574685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.574709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.574729] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.574753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.574776] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.574799] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.574822] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.574845] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.574869] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.574892] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.574916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.574942] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.575000] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.575020] [drm:intel_power_well_enable [i915]] enabling display
>[  915.575040] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.575076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.575100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.575174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.575206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.575240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.575274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.575310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.575345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.575378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.575409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.575440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.575476] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.575508] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.577593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.577616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.577635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.577669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.579335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.579356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.579375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.580933] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.580956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.582832] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.586175] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.586268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.586301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.586343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.603048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.603098] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.603385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.603623] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.603714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.619743] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.619790] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.619875] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.636902] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.636940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.636980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.637014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.637050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.637081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.637201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.637255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.637314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.637369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.637678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.637699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.637717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.637734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.637766] [drm:intel_power_well_disable [i915]] disabling display
>[  915.637791] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.637817] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.637836] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.637930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.637941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.637991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.638011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.638034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.638061] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.638084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.638159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.638191] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.638225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.638257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.638289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.638319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.638329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.638358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.638366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.638396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.638426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.638456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.638485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.638519] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.638549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.638579] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.638605] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.638912] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.638946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.638982] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.639071] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.639125] [drm:intel_power_well_enable [i915]] enabling display
>[  915.639155] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.639311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.639342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.639371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.639399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.639426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.639455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.639486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.639516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.639546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.639573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.639600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.639631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.639660] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.641734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.641756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.641774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.641793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.643365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.643388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.643411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.644961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.644983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.646848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.650046] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.650168] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.650214] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.650344] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.666908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.666959] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.667025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.667538] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.667628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.683608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.683654] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.683742] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.700748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.700785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.700825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.700858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.700893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.700923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.700952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.700986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.701030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.701073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.701194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.701254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.701306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.701356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.701442] [drm:intel_power_well_disable [i915]] disabling display
>[  915.701699] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.701763] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.701814] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.701999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.702010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.702062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.702082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.702156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.702197] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.702228] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.702263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.702297] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.702330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.702364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.702394] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.702425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.702434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.702464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.702695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.702716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.702735] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.702753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.702770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.702789] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.702807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.702824] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.702841] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.702857] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.702876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.702901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.702958] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.702978] [drm:intel_power_well_enable [i915]] enabling display
>[  915.702998] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.703034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.703058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.703081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.703155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.703188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.703224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.703260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.703294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.703327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.703358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.703388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.703424] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.703456] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.705730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.705750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.705773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.705797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.707363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.707383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.707402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.708950] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.708971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.710835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.714096] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.714203] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.714222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.714247] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.730998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.731051] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.731204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.731601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.731690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.747699] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.747745] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.747832] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.764887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.764924] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.764964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.764997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.765032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.765063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.765092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.765213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.765280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.765329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.765634] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.765671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.765706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.765741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.765791] [drm:intel_power_well_disable [i915]] disabling display
>[  915.765832] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.765876] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.765907] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.766035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.766051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.766200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.766249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.766307] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.766350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.766552] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.766592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.766630] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.766666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.766702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.766735] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.766768] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.766776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.766808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.766816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.766849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.766882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.766911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.766943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.766979] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.767012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.767042] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.767075] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.767139] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.767179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.767219] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.767525] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.767556] [drm:intel_power_well_enable [i915]] enabling display
>[  915.767586] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.767639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.767671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.767702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.767733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.767763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.767795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.767830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.767863] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.767896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.767926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.767956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.767989] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.768021] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.770132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.770153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.770171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.770190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.771764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.771791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.771816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.773371] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.773393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.775276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.778571] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.778645] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.778669] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.778701] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.795440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.795491] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.795556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.795793] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.795887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.812171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.812218] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.812305] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.829328] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.829365] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.829404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.829438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.829472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.829502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.829531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.829569] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.829614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.829664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.829697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.829727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.829753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.829779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.829829] [drm:intel_power_well_disable [i915]] disabling display
>[  915.829867] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.829906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.829935] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.830149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.830178] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.830309] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.830357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.830407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.830462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.830508] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.830557] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.830604] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.830651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.830702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.830739] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.830775] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.830784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.830817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.830825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.830860] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.830895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.830930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.830964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.831002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.831036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.831072] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.831134] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.831171] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.831210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.831253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.831360] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.831397] [drm:intel_power_well_enable [i915]] enabling display
>[  915.831433] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.831494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.831533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.831570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.831607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.831642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.831680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.831724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.831757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.831789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.831819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.831848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.831882] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.831913] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.834007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.834029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.834048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.834067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.835773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.835794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.835813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.837375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.837396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.839258] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.842590] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.842642] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.842675] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.842717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.859422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.859473] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.859539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.859786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.859880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.876165] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.876211] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.876299] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.893311] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.893349] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.893388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.893422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.893456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.893486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.893515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.893546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.893581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.893613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.893644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.893675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.893703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.893730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.893782] [drm:intel_power_well_disable [i915]] disabling display
>[  915.893822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.893863] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.893894] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.894045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.894060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.894222] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.894266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.894312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.894677] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.894719] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.894763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.894807] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.894849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.894891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.894931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.894969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.894979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.895024] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.895032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.895064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.895122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.895154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.895187] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.895223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.895255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.895290] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.895322] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.895355] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.895393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.895431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.895769] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.895803] [drm:intel_power_well_enable [i915]] enabling display
>[  915.895835] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.895893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.895928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.895961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.895994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.896033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.896062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.896134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.896171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.896205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.896236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.896266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.896301] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.896519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.898589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.898610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.898628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.898647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.900324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.900349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.900372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.901939] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.901961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.903843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.907205] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.907287] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.907309] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.907336] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.924055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.924184] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.924287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.924579] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.924669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.940758] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  915.940804] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  915.940890] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  915.957901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  915.957939] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  915.957978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.958012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.958047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.958078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.958198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.958245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.958282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.958323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.958363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.958397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.958430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.958465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.958514] [drm:intel_power_well_disable [i915]] disabling display
>[  915.958553] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  915.958596] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.958626] [drm:intel_power_well_disable [i915]] disabling always-on
>[  915.958750] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.958766] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  915.958844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  915.958880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  915.958915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  915.958954] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  915.958986] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  915.959022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  915.959056] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  915.959093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  915.959166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  915.959206] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  915.959243] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  915.959254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.959290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  915.959300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  915.959336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  915.959375] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  915.959402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  915.959429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  915.959459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  915.959485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  915.959512] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  915.959538] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  915.959564] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  915.959595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  915.959627] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  915.959717] [drm:intel_power_well_enable [i915]] enabling always-on
>[  915.959740] [drm:intel_power_well_enable [i915]] enabling display
>[  915.959762] [drm:hsw_set_power_well [i915]] Enabling power well
>[  915.959801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  915.959827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  915.959854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  915.959880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  915.959905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  915.959930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  915.959958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  915.959986] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  915.960013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.960038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  915.960064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  915.960119] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  915.960149] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  915.962210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  915.962231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  915.962249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.962268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  915.963838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  915.963858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  915.963877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  915.965440] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  915.965460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  915.967328] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  915.970600] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  915.970643] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  915.970662] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  915.970688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  915.987441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  915.987491] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  915.987557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  915.987776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  915.987878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.004174] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.004222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.004310] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.021325] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.021366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.021411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.021451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.021495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.021535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.021574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.021614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.021666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.021702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.021733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.021762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.021789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.021814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.021862] [drm:intel_power_well_disable [i915]] disabling display
>[  916.021899] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.021936] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.021964] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.022184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.022210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.022313] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.022344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.022376] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.022416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.022451] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.022489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.022525] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.022562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.022598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.022634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.022669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.022686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.022710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.022715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.022740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.022766] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.022792] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.022817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.022844] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.022869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.022896] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.022922] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.022948] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.022975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.023003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.023064] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.023115] [drm:intel_power_well_enable [i915]] enabling display
>[  916.023144] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.023198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.023228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.023258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.023286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.023314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.023342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.023374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.023405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.023437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.023466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.023493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.023527] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.023558] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.025652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.025674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.025692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.025711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.027281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.027302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.027320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.028873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.028897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.030772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.033499] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.033604] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.033643] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.033695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.050376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.050427] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.050493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.050739] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.050832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.067079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.067166] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.067254] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.084266] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.084303] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.084342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.084376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.084411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.084441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.084470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.084501] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.084536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.084568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.084599] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.084631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.084659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.084686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.084740] [drm:intel_power_well_disable [i915]] disabling display
>[  916.084780] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.084821] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.084852] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.084996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.085013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.085075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.085158] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.085192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.085230] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.085259] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.085291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.085321] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.085354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.085384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.085414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.085441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.085450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.085477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.085485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.085515] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.085541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.085570] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.085597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.085628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.085654] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.085682] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.085709] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.085738] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.085771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.085804] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.085892] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.085923] [drm:intel_power_well_enable [i915]] enabling display
>[  916.085952] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.086001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.086030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.086058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.086110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.086140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.086169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.086202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.086235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.086267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.086293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.086321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.086352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.086382] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.088462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.088484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.088507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.088531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.090128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.090149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.090167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.091738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.091760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.093635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.096730] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.096818] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.096851] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.096893] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.113595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.113646] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.113712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.113960] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.114052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.130293] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.130341] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.130427] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.148514] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.148551] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.148591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.148624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.148658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.148688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.148716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.148747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.148781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.148814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.148844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.148875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.148903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.148931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.148983] [drm:intel_power_well_disable [i915]] disabling display
>[  916.149024] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.149065] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.149188] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.149313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.149325] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.149381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.149402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.149424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.149453] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.149479] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.149506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.149532] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.149558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.149584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.149610] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.149635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.149641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.149666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.149671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.149697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.149722] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.149748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.149774] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.149799] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.149824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.149850] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.149875] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.149901] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.149928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.149956] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.150019] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.150042] [drm:intel_power_well_enable [i915]] enabling display
>[  916.150063] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.150144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.150175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.150205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.150234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.150261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.150290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.150323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.150355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.150385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.150412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.150439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.150470] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.150500] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.152583] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.152604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.152623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.152646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.154231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.154252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.154270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.155846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.155867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.157742] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.161031] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.161195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.161243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.161311] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.177914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.177964] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.178030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.178389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.178506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.194603] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.194651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.194724] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.211716] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.211753] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.211792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.211825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.211860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.211890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.211932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.211964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.211999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.212031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.212062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.212176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.212218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.212266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.212352] [drm:intel_power_well_disable [i915]] disabling display
>[  916.212424] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.212476] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.212517] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.212716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.212740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.212852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.212894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.212939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.212986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.213022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.213064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.213145] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.213186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.213228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.213264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.213302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.213314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.213352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.213362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.213402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.213446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.213476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.213502] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.213535] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.213561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.213590] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.213620] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.213647] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.213678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.213711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.213801] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.213831] [drm:intel_power_well_enable [i915]] enabling display
>[  916.213861] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.213911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.213943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.213970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.213999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.214025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.214054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.214111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.214144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.214178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.214205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.214234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.214270] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.214299] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.216370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.216390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.216408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.216427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.217993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.218015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.218039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.219635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.219656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.221535] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.224798] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.224850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.224869] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.224895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.241650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.241701] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.241767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.241982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.242059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.258328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.258382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.258457] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.275480] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.275517] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.275557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.275590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.275624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.275654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.275682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.275713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.275748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.275780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.275810] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.275841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.275869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.275896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.275949] [drm:intel_power_well_disable [i915]] disabling display
>[  916.275989] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.276030] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.276061] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.276365] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.276393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.276530] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.276578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.276617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.276657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.276689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.276722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.276764] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.276784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.276804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.276823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.276841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.276846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.276864] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.276868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.276887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.276905] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.276923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.276941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.276962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.276980] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.276999] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.277017] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.277035] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.277058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.277116] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.277189] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.277217] [drm:intel_power_well_enable [i915]] enabling display
>[  916.277245] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.277339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.277371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.277403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.277433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.277463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.277494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.277521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.277543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.277563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.277582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.277600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.277627] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.277653] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.279702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.279723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.279742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.279761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.281333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.281356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.281379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.282951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.282972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.284845] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.288090] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.288162] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.288181] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.288207] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.304955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.305006] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.305072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.305436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.305515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.321651] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.321701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.321789] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.338848] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.338885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.338925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.338958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.338993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.339024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.339053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.339183] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.339236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.339287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.339335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.339383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.339426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.339461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.339512] [drm:intel_power_well_disable [i915]] disabling display
>[  916.339551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.339598] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.339632] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.339785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.339803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.339889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.339925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.339965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.340007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.340044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.340130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.340183] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.340220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.340254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.340288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.340319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.340330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.340361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.340370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.340403] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.340434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.340466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.340497] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.340534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.340565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.340598] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.340629] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.340663] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.340703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.340745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.340852] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.340890] [drm:intel_power_well_enable [i915]] enabling display
>[  916.340928] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.340993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.341032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.341068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.341132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.341165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.341203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.341234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.341268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.341300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.341329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.341358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.341391] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.341412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.343449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.343470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.343489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.343508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.345070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.345106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.345125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.346669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.346692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.348559] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.351874] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.351940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.351972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.352013] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.368723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.368776] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.368848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.369276] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.369372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.385399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.385447] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.385534] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.402600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.402637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.402677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.402710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.402745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.402776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.402805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.402837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.402871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.402904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.402944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.402985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.403024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.403063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.403204] [drm:intel_power_well_disable [i915]] disabling display
>[  916.403271] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.403338] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.403388] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.403587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.403607] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.403694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.403728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.403762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.403800] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.403831] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.403864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.403897] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.403928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.403961] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.403991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.404021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.404029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.404058] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.404091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.404124] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.404153] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.404184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.404214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.404248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.404279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.404310] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.404340] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.404371] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.404405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.404440] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.404532] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.404560] [drm:intel_power_well_enable [i915]] enabling display
>[  916.404589] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.404642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.404672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.404702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.404732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.404762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.404793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.404826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.404859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.404891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.404920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.404949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.404982] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.405013] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.407121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.407142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.407165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.407189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.408762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.408782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.408801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.410359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.410380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.412241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.415559] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.415625] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.415658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.415699] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.432405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.432455] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.432520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.432734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.432812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.449079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.449172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.449260] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.466268] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.466305] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.466349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.466390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.466433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.466473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.466513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.466552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.466596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.466638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.466680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.466721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.466760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.466806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.466839] [drm:intel_power_well_disable [i915]] disabling display
>[  916.466865] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.466893] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.466911] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.467008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.467019] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.467140] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.467175] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.467213] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.467251] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.467283] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.467319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.467353] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.467386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.467418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.467450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.467480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.467489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.467517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.467801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.467831] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.467865] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.467896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.467926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.467959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.467990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.468020] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.468049] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.468100] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.468136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.468173] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.468406] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.468437] [drm:intel_power_well_enable [i915]] enabling display
>[  916.468467] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.468519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.468552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.468583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.468613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.468642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.468673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.468707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.468740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.468772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.468801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.468829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.468863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.468894] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.470963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.470985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.471008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.471032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.472646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.472667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.472686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.474256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.474277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.476178] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.479515] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.479613] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.479646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.479688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.496387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.496437] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.496503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.496716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.496795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.513062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.513155] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.513244] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.531386] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.531423] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.531463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.531496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.531530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.531559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.531588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.531619] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.531654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.531686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.531716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.531747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.531775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.531803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.531856] [drm:intel_power_well_disable [i915]] disabling display
>[  916.531896] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.531937] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.531967] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.532440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.532463] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.532574] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.532615] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.532658] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.532704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.532741] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.532782] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.532823] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.532864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.532903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.532939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.532990] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.533000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.533042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.533077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.533109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.533140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.533173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.533204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.533239] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.533271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.533304] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.533335] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.533367] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.533403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.533440] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.533783] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.533815] [drm:intel_power_well_enable [i915]] enabling display
>[  916.533846] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.533899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.533933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.533965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.533997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.534028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.534077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.534137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.534174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.534208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.534238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.534269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.534304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.534460] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.536501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.536524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.536547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.536571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.538171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.538192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.538211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.539769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.539790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.541663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.544975] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.545046] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.545147] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.545223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.561828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.561879] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.561945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.562264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.562385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.578503] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.578551] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.578637] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.595650] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.595687] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.595727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.595760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.595795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.595825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.595855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.595887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.595922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.595955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.595987] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.596018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.596047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.596155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.596237] [drm:intel_power_well_disable [i915]] disabling display
>[  916.596302] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.596563] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.596593] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.596723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.596740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.596794] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.596818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.596842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.596868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.596891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.596915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.596939] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.596962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.596986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.597009] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.597032] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.597037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.597111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.597121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.597155] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.597188] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.597221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.597252] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.597288] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.597319] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.597351] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.597381] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.597412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.597448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.597483] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.597846] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.597875] [drm:intel_power_well_enable [i915]] enabling display
>[  916.597903] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.597952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.597982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.598011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.598039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.598106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.598137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.598174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.598209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.598242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.598451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.598470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.598492] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.598515] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.600562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.600584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.600602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.600621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.602284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.602304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.602322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.603877] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.603898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.605768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.609050] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.609150] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.609182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.609224] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.625930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.625980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.626046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.626531] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.626609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.642619] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.642673] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.642759] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.659757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.659796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.659836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.659869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.659912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.659952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.659992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.660031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.660150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.660213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.660269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.660322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.660662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.660712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.660773] [drm:intel_power_well_disable [i915]] disabling display
>[  916.660812] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.660850] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.660880] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.661000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.661011] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.661120] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.661156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.661192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.661231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.661264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.661297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.661447] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.661472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.661498] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.661521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.661546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.661551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.661577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.661585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.661620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.661646] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.661667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.661685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.661707] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.661726] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.661745] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.661763] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.661781] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.661802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.661825] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.661884] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.661903] [drm:intel_power_well_enable [i915]] enabling display
>[  916.661921] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.661955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.661975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.661993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.662011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.662028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.662048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.662110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.662145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.662180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.662210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.662241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.662276] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.662308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.664662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.664685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.664708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.664732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.666322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.666345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.666364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.667912] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.667932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.669805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.673083] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.673122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.673141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.673167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.689926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.689976] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.690042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.690413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.690509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.706608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.706655] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.706723] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.723745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.723787] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.723832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.723873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.723916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.723956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.723996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.724035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.724169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.724227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.724282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.724336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.724383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.724429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.724508] [drm:intel_power_well_disable [i915]] disabling display
>[  916.724573] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.724636] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.724686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.724928] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.724957] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.725040] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.725110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.725145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.725186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.725218] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.725253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.725287] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.725321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.725353] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.725384] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.725413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.725423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.725452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.725459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.725488] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.725518] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.725548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.725573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.725606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.725634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.725661] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.725690] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.725716] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.725748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.725783] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.725874] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.725905] [drm:intel_power_well_enable [i915]] enabling display
>[  916.725935] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.725986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.726018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.726049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.726108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.726139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.726172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.726206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.726240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.726273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.726303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.726334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.726369] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.726400] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.728472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.728494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.728517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.728541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.730162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.730183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.730201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.731752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.731774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.733644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.736933] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.737028] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.737122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.737195] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.753814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.753865] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.753932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.754278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.754385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.770494] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.770543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.770612] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.787631] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.787668] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.787708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.787741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.787784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.787824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.787864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.787903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.787947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.787990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.788032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.788153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.788199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.788247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.788334] [drm:intel_power_well_disable [i915]] disabling display
>[  916.788374] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.788416] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.788447] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.788588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.788608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.788695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.788724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.788765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.788798] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.788824] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.788854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.788881] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.788909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.788934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.788960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.788984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.788991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.789015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.789021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.789059] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.789116] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.789148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.789175] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.789209] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.789236] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.789265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.789292] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.789321] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.789355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.789390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.789480] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.789510] [drm:intel_power_well_enable [i915]] enabling display
>[  916.789539] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.789589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.789621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.789648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.789676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.789702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.789731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.789763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.789795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.789826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.789852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.789880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.789910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.789940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.792006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.792028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.792096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.792129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.793797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.793818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.793837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.795391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.795412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.797283] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.800584] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.800651] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.800683] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.800712] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.817448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.817500] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.817565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.817777] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.817855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.834125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.834177] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.834251] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.851276] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.851313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.851352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.851386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.851429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.851469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.851509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.851548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.851593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.851638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.851671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.851700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.851727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.851752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.851800] [drm:intel_power_well_disable [i915]] disabling display
>[  916.851835] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.851873] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.851900] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.852088] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.852116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.852597] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.852648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.852680] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.852716] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.852744] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.852776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.852806] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.852837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.852865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.852894] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.852920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.852927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.852954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.852960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.852989] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.853015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.853044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.853094] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.853125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.853155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.853182] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.853211] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.853238] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.853271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.853305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.853679] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.853707] [drm:intel_power_well_enable [i915]] enabling display
>[  916.853735] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.853783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.853811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.853838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.853863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.853889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.853915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.853945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.853974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.854003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.854027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.854090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.854127] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.854156] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.856401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.856423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.856441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.856461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.858042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.858079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.858097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.859666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.859689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.861584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.864878] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.864951] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.864970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.864996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.881753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.881807] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.881878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.882176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.882297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.898432] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.898480] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.898549] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.915599] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.915636] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.915676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.915710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.915745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.915776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.915814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.915854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.915898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.915947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.915984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.916021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.916121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.916165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.916240] [drm:intel_power_well_disable [i915]] disabling display
>[  916.916298] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.916355] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.916399] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.916614] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.916639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.916760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.916805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.916853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.916903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.916948] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.916992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.917026] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.917083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.917115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.917146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.917174] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.917182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.917212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.917220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.917251] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.917281] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.917311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.917341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.917375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.917405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.917436] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.917462] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.917492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.917526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.917561] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.917635] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.917666] [drm:intel_power_well_enable [i915]] enabling display
>[  916.917697] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.917748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.917780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.917810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.917840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.917870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.917901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.917935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.917967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.918000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.918029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.918087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.918123] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.918155] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.920220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.920241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.920259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.920278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.921849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.921869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.921887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.923447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.923468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.925334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.928600] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.928666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.928699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.928741] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  916.945447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.945498] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.945564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.945776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.945854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.962120] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  916.962168] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  916.962240] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  916.979269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  916.979306] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  916.979346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.979380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.979414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.979445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.979474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.979506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  916.979541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.979572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.979603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.979633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.979661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.979689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.979742] [drm:intel_power_well_disable [i915]] disabling display
>[  916.979782] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  916.979823] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  916.979853] [drm:intel_power_well_disable [i915]] disabling always-on
>[  916.979993] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  916.980011] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  916.980192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  916.980226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  916.980261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  916.980299] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  916.980330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  916.980365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  916.980398] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  916.980430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  916.980461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  916.980490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  916.980521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  916.980529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.980557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  916.980564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  916.980593] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  916.980622] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  916.980651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  916.980680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  916.980712] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  916.980741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  916.980770] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  916.980799] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  916.980828] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  916.980861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  916.980896] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  916.980986] [drm:intel_power_well_enable [i915]] enabling always-on
>[  916.981017] [drm:intel_power_well_enable [i915]] enabling display
>[  916.981072] [drm:hsw_set_power_well [i915]] Enabling power well
>[  916.981127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  916.981160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  916.981192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  916.981224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  916.981255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  916.981288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  916.981323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  916.981356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  916.981389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  916.981418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  916.981447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  916.981481] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  916.981512] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  916.983577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  916.983598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  916.983617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.983636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  916.985225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  916.985248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  916.985267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  916.986818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  916.986839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  916.988717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  916.991850] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  916.991950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  916.991983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  916.992025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.008728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.008779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.008844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.009284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.009378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.025407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.025455] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.025541] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.042584] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.042621] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.042661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.042694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.042729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.042759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.042798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.042838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.042881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.042924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.042965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.043007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.043046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.043153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.043239] [drm:intel_power_well_disable [i915]] disabling display
>[  917.043304] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.043353] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.043385] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.043536] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.043548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.043605] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.043627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.043650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.043680] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.043705] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.043732] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.043758] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.043784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.043810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.043836] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.043861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.043867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.043892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.043896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.043923] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.043946] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.043972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.043997] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.044023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.044079] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.044112] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.044141] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.044169] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.044202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.044236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.044326] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.044350] [drm:intel_power_well_enable [i915]] enabling display
>[  917.044369] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.044404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.044425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.044449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.044480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.044503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.044523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.044546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.044566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.044587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.044605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.044624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.044650] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.044676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.046732] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.046753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.046773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.046792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.048363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.048383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.048401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.049960] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.049980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.051854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.055203] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.055288] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.055321] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.055372] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.072107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.072157] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.072223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.072438] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.072517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.088740] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.088789] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.088876] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.106998] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.107036] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.107159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.107218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.107275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.107323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.107359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.107391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.107429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.107463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.107494] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.107526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.107555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.107584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.107638] [drm:intel_power_well_disable [i915]] disabling display
>[  917.107678] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.107728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.107749] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.107852] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.107864] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.107919] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.107940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.107963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.107988] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.108008] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.108031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.108088] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.108119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.108147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.108174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.108200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.108209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.108235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.108243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.108270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.108296] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.108322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.108348] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.108378] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.108404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.108432] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.108458] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.108484] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.108515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.108548] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.108639] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.108670] [drm:intel_power_well_enable [i915]] enabling display
>[  917.108700] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.108753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.108786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.108817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.108889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.108919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.108951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.108975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.108996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.109016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.109063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.109090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.109123] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.109151] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.111215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.111235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.111254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.111273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.112844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.112864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.112882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.114445] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.114466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.116337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.119637] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.119720] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.119752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.119794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.136480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.136528] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.136591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.136806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.136881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.153169] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.153216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.153304] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.170326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.170364] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.170404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.170437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.170472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.170502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.170531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.170562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.170605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.170647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.170689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.170731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.170770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.170809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.170866] [drm:intel_power_well_disable [i915]] disabling display
>[  917.170911] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.170961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.170997] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.171334] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.171347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.171406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.171430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.171454] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.171479] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.171499] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.171522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.171544] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.171565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.171591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.171617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.171642] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.171648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.171673] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.171678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.171704] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.171729] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.171755] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.171780] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.171806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.171831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.171857] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.171882] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.171908] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.171935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.171963] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.172024] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.172075] [drm:intel_power_well_enable [i915]] enabling display
>[  917.172104] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.172158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.172189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.172218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.172247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.172274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.172304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.172336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.172366] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.172397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.172427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.172675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.172701] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.172722] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.174761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.174782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.174800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.174818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.176384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.176405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.176425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.177978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.177999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.180012] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.183346] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.183403] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.183422] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.183448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.200198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.200249] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.200315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.200520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.200599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.216872] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.216921] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.217010] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.234114] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.234152] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.234191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.234225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.234260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.234290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.234319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.234351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.234386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.234420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.234452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.234483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.234511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.234539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.234592] [drm:intel_power_well_disable [i915]] disabling display
>[  917.234632] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.234673] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.234704] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.234858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.234876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.234959] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.234991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.235025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.235125] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.235179] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.235237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.235280] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.235318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.235359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.235395] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.235434] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.235445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.235482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.235492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.235531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.235567] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.235608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.235645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.235687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.235722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.235761] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.235795] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.235833] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.235877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.235922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.236044] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.236118] [drm:intel_power_well_enable [i915]] enabling display
>[  917.236156] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.236223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.236266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.236294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.236323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.236349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.236379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.236414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.236447] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.236481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.236507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.236535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.236566] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.236597] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.238676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.238699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.238717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.238737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.240316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.240339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.240362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.241926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.241947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.243821] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.247198] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.247255] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.247287] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.247330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.264036] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.264119] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.264186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.264401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.264479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.280710] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.280758] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.280845] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.297861] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.297898] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.297938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.297972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.298007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.298131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.298181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.298233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.298293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.298345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.298395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.298445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.298490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.298536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.298604] [drm:intel_power_well_disable [i915]] disabling display
>[  917.298646] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.298686] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.298719] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.298878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.298889] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.298942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.298962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.298983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.299006] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.299075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.299107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.299142] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.299175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.299208] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.299239] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.299270] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.299279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.299308] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.299316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.299346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.299378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.299408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.299438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.299468] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.299498] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.299529] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.299558] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.299584] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.299616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.299652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.299746] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.299777] [drm:intel_power_well_enable [i915]] enabling display
>[  917.299807] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.299857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.299889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.299919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.299949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.299979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.300010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.300069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.300100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.300134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.300163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.300193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.300229] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.300261] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.302321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.302341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.302359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.302378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.303948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.303968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.303986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.305580] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.305600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.307570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.310833] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.310886] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.310905] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.310931] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.327671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.327720] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.327784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.327999] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.328186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.344362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.344410] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.344498] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.361512] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.361549] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.361588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.361621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.361656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.361695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.361735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.361774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.361827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.361862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.361892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.361922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.361948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.361974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.362024] [drm:intel_power_well_disable [i915]] disabling display
>[  917.362148] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.362211] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.362261] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.362491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.362516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.362645] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.362693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.362744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.362799] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.362847] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.362880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.362913] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.362944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.362975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.363005] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.363060] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.363069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.363100] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.363108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.363139] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.363169] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.363200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.363229] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.363263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.363293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.363323] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.363351] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.363381] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.363416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.363451] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.363543] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.363574] [drm:intel_power_well_enable [i915]] enabling display
>[  917.363603] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.363655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.363686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.363717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.363748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.363777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.363808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.363842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.363874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.363906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.363935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.363964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.363998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.364030] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.366118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.366139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.366157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.366177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.367748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.367768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.367786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.369339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.369362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.371225] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.374532] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.374609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.374641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.374683] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.391369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.391417] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.391480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.391678] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.391753] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.408107] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.408152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.408241] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.427166] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.427203] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.427248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.427289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.427332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.427372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.427412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.427451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.427495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.427537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.427579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.427620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.427659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.427698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.427755] [drm:intel_power_well_disable [i915]] disabling display
>[  917.427801] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.427851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.427887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.428133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.428163] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.428545] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.428577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.428609] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.428644] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.428672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.428703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.428733] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.428772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.428804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.428842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.428869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.428876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.428903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.428910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.428937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.428964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.428992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.429029] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.429098] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.429130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.429161] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.429192] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.429224] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.429259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.429294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.429636] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.429663] [drm:intel_power_well_enable [i915]] enabling display
>[  917.429680] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.429714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.429737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.429761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.429785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.429809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.429831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.429856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.429881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.429906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.429929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.429952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.429977] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.430000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.432101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.432124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.432147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.432171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.433744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.433766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.433784] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.435347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.435368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.437238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.440519] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.440554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.440573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.440599] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.457351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.457403] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.457469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.457683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.457763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.474021] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.474115] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.474204] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.491634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.491671] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.491711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.491747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.491784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.491819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.491852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.491886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.491924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.491959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.491995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.492037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.492683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.492706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.492744] [drm:intel_power_well_disable [i915]] disabling display
>[  917.492772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.492803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.492823] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.492940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.492953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.493330] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.493362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.493395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.493430] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.493459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.493490] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.493520] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.493549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.493589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.493619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.493648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.493656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.493685] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.493691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.493721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.493750] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.493779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.493808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.493841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.493869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.493898] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.493926] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.493954] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.493987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.494022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.494803] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.494833] [drm:intel_power_well_enable [i915]] enabling display
>[  917.494861] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.494914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.494945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.494974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.495002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.495275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.495309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.495345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.495380] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.495413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.495443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.495472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.495507] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.495540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.497976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.498001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.498173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.498207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.499770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.499804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.499835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.501377] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.501402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.503244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.506400] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.506473] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.506514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.506567] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.523207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.523257] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.523328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.523545] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.523624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.539927] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.539962] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.540024] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.558627] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.558663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.558702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.558734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.558769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.558800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.558830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.558861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.558897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.558929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.558961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.558993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.559022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.559100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.559155] [drm:intel_power_well_disable [i915]] disabling display
>[  917.559199] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.559241] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.559274] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.559442] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.559460] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.559548] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.559580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.559614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.559650] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.559679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.559711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.559742] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.559772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.559802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.559830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.559859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.559866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.559893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.559899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.559928] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.559955] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.559982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.560009] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.560080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.560109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.560140] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.560169] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.560199] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.560233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.560268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.560347] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.560378] [drm:intel_power_well_enable [i915]] enabling display
>[  917.560408] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.560462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.560494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.560524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.560553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.560583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.560614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.560648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.560681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.560714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.560742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.560770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.560804] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.560836] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.564393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.564430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.564462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.564495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.566070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.566106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.566137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.567763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.567800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.569911] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.573123] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.573186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.573207] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.573235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.589943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.589994] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.590315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.590525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.590605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.606656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.606692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.606761] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.624593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.624620] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.624649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.624671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.624695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.624715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.624734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.624755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.624779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.624800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.624820] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.624841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.624859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.624876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.624913] [drm:intel_power_well_disable [i915]] disabling display
>[  917.624941] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.624969] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.624989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.625180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.625203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.625294] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.625328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.625363] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.625401] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.625431] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.625464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.625497] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.625528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.625559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.625591] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.625620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.625628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.625655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.625662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.625691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.625720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.625749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.625779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.625809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.625838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.625868] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.625898] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.625928] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.625960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.625995] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.626097] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.626127] [drm:intel_power_well_enable [i915]] enabling display
>[  917.626158] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.626210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.626241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.626272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.626303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.626333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.626408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.626442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.626475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.626507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.626536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.626565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.626600] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.626632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.628717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.628754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.628787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.628821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.630405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.630440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.630472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.632080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.632117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.634068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.637065] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.637138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.637160] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.637188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.653919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.653980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.654155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.654436] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.654514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.670612] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.670662] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.670735] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.687752] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.687790] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.687831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.687864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.687899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.687929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.687958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.687990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.688118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.688174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.688228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.688281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.688326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.688369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.688428] [drm:intel_power_well_disable [i915]] disabling display
>[  917.688470] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.688511] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.688543] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.688712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.688730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.688811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.688841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.688873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.688907] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.688936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.688967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.688997] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.689069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.689103] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.689135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.689166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.689174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.689203] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.689211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.689242] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.689272] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.689304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.689336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.689369] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.689400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.689430] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.689460] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.689490] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.689524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.689558] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.689650] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.689680] [drm:intel_power_well_enable [i915]] enabling display
>[  917.689710] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.689760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.689791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.689822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.689852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.689882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.689913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.689946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.689978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.690011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.690064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.690095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.690128] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.690160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.692223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.692244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.692262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.692281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.693841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.693862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.693880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.695443] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.695464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.697334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.700629] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.700704] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.700735] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.700761] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.717478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.717535] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.717598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.717822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.717902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.734159] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.734231] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.734293] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.752564] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.752602] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.752642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.752677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.752713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.752734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.752753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.752773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.752797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.752818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.752838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.752858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.752876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.752893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.752931] [drm:intel_power_well_disable [i915]] disabling display
>[  917.752978] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.753016] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.753086] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.753245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.753258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.753317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.753338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.753362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.753387] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.753411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.753437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.753463] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.753488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.753514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.753539] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.753564] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.753569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.753594] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.753599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.753624] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.753647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.753673] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.753698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.753723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.753748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.753774] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.753799] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.753825] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.753853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.753881] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.753936] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.753957] [drm:intel_power_well_enable [i915]] enabling display
>[  917.753979] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.754054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.754086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.754116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.754144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.754172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.754200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.754232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.754264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.754295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.754322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.754348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.754381] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.754409] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.756487] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.756510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.756530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.756551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.758198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.758221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.758246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.759835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.759872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.761754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.764506] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.764582] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.764613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.764656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.781337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.781383] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.781451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.781662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.781739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.798015] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.798094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.798345] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.816536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.816562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.816593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.816619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.816648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.816673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.816699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.816724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.816752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.816779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.816806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.816833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.816858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.816883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.816920] [drm:intel_power_well_disable [i915]] disabling display
>[  917.816951] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.816984] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.817072] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.817225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.817244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.817337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.817371] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.817406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.817444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.817475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.817509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.817542] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.817574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.817605] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.817635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.817665] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.817672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.817700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.817707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.817737] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.817767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.817796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.817822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.817854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.817883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.817913] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.817942] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.817973] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.818006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.818068] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.818144] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.818176] [drm:intel_power_well_enable [i915]] enabling display
>[  917.818206] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.818259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.818291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.818322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.818352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.818379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.818410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.818444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.818477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.818509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.818540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.818569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.818603] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.818635] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.820711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.820747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.820780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.820813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.822402] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.822434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.822464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.824049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.824074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.825940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.828048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.828096] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.828118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.828145] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.844849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.844883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.844927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.845151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.845224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.861595] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.861645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.861718] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.879895] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.879933] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.879973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.880006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.880120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.880165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.880221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.880264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.880314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.880361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.880407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.880452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.880490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.880533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.880612] [drm:intel_power_well_disable [i915]] disabling display
>[  917.880672] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.880730] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.880776] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.881048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.881071] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.881155] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.881187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.881232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.881258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.881286] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.881306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.881326] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.881345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.881363] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.881380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.881397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.881401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.881417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.881421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.881438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.881454] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.881470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.881486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.881506] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.881522] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.881539] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.881555] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.881571] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.881591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.881616] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.881665] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.881685] [drm:intel_power_well_enable [i915]] enabling display
>[  917.881705] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.881741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.881765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.881789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.881813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.881836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.881859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.881885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.881909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.881934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.881957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.881980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.882005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.882072] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.884160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.884183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.884202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.884226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.885798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.885819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.885839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.887393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.887414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.889276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.892532] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.892593] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.892613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.892638] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.909389] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.909440] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.909505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.909717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.909795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.926064] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.926112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.926182] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  917.943211] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  917.943248] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  917.943287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.943321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.943356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.943385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.943414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.943445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.943480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.943521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.943550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.943579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.943605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.943631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.943680] [drm:intel_power_well_disable [i915]] disabling display
>[  917.943719] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  917.943757] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.943786] [drm:intel_power_well_disable [i915]] disabling always-on
>[  917.943929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.943946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  917.944106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  917.944157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  917.944210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  917.944265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  917.944312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  917.944362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  917.944410] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  917.944457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  917.944505] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  917.944549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  917.944578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  917.944587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.944616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  917.944624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  917.944654] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  917.944683] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  917.944714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  917.944743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  917.944777] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  917.944808] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  917.944837] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  917.944867] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  917.944896] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  917.944930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.944964] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  917.945076] [drm:intel_power_well_enable [i915]] enabling always-on
>[  917.945108] [drm:intel_power_well_enable [i915]] enabling display
>[  917.945138] [drm:hsw_set_power_well [i915]] Enabling power well
>[  917.945189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  917.945223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  917.945254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  917.945285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  917.945316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  917.945348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  917.945383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  917.945417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  917.945449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.945478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  917.945504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  917.945537] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  917.945569] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  917.947640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  917.947663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  917.947686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.947710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  917.949276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  917.949297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  917.949316] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  917.950865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  917.950885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  917.952749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  917.955977] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  917.956076] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  917.956103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  917.956139] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  917.972859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  917.972911] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  917.972977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  917.973322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  917.973400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  917.989535] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  917.989584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  917.989653] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.007954] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.007991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.008125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.008178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.008235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.008283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.008330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.008380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.008435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.008487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.008537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.008587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.008632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.008677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.008761] [drm:intel_power_well_disable [i915]] disabling display
>[  918.008826] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.008883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.008915] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.009069] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.009088] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.009182] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.009212] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.009245] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.009281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.009303] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.009327] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.009351] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.009374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.009398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.009421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.009444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.009448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.009471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.009475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.009499] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.009520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.009543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.009565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.009588] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.009611] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.009635] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.009658] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.009681] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.009705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.009730] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.009788] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.009807] [drm:intel_power_well_enable [i915]] enabling display
>[  918.009827] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.009863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.009887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.009910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.009934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.009957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.009980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.010056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.010096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.010131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.010164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.010195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.010230] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.010263] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.012336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.012357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.012376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.012399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.013997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.014033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.014052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.015612] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.015635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.017539] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.020861] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.020922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.020955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.020998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.037711] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.037764] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.037836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.038156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.038408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.054387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.054436] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.054526] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.072968] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.073005] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.073134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.073189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.073245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.073295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.073341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.073391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.073446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.073499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.073550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.073600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.073645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.073689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.073774] [drm:intel_power_well_disable [i915]] disabling display
>[  918.073838] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.073900] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.073951] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.074210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.074228] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.074307] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.074327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.074348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.074374] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.074397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.074421] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.074445] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.074468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.074492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.074512] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.074535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.074539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.074562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.074566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.074590] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.074611] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.074635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.074656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.074679] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.074702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.074725] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.074749] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.074772] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.074797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.074822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.074882] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.074902] [drm:intel_power_well_enable [i915]] enabling display
>[  918.074922] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.074958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.074982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.075056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.075088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.075121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.075154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.075190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.075224] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.075258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.075288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.075319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.075355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.075389] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.077485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.077506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.077525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.077544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.079209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.079229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.079248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.080805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.080826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.082697] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.085273] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.085373] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.085406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.085431] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.102150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.102200] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.102265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.102475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.102552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.118829] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.118881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.118954] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.137708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.137745] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.137784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.137818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.137853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.137882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.137910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.137942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.137977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.138082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.138135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.138188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.138236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.138284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.138370] [drm:intel_power_well_disable [i915]] disabling display
>[  918.138434] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.138505] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.138537] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.138693] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.138711] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.138800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.138841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.138874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.138908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.138937] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.138967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.139008] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.139084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.139116] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.139147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.139177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.139186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.139217] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.139225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.139255] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.139284] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.139315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.139344] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.139377] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.139408] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.139438] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.139468] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.139497] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.139530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.139564] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.139653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.139684] [drm:intel_power_well_enable [i915]] enabling display
>[  918.139715] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.139766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.139797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.139828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.139858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.139888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.139919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.139952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.139985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.140041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.140071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.140102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.140137] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.140169] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.142232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.142253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.142271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.142290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.143850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.143871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.143889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.145451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.145472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.147331] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.150663] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.150749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.150769] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.150794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.167555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.167608] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.167674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.167902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.167980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.184222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.184272] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.184344] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.201374] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.201411] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.201451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.201485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.201520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.201550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.201580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.201618] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.201663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.201705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.201747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.201796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.201825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.201851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.201896] [drm:intel_power_well_disable [i915]] disabling display
>[  918.201931] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.201967] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.202067] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.202534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.202559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.202674] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.202718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.202763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.202818] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.202848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.202879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.202910] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.202939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.202968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.203036] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.203066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.203076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.203106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.203114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.203145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.203176] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.203206] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.203236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.203270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.203300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.203331] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.203361] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.203615] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.203639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.203663] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.203722] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.203741] [drm:intel_power_well_enable [i915]] enabling display
>[  918.203759] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.203794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.203823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.203840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.203857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.203874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.203893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.203912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.203931] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.203949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.203966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.203982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.204053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.204084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.206331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.206354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.206373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.206394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.207987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.208024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.208042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.209613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.209633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.211525] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.214836] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.214911] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.214951] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.215002] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.231703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.231754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.231818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.232091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.232346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.248366] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.248414] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.248486] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.266940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.266977] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.267108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.267300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.267345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.267385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.267424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.267464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.267507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.267549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.267591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.267633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.267679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.267733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.267787] [drm:intel_power_well_disable [i915]] disabling display
>[  918.267828] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.267873] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.267904] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.268409] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.268429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.268519] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.268552] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.268587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.268625] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.268656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.268689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.268722] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.268754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.268785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.268815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.268845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.268853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.268882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.268889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.268918] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.268947] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.268976] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.269029] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.269062] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.269088] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.269118] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.269145] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.269174] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.269203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.269240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.269332] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.269577] [drm:intel_power_well_enable [i915]] enabling display
>[  918.269594] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.269629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.269649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.269667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.269685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.269702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.269721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.269745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.269775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.269806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.269825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.269842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.269863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.269882] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.271941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.271961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.271980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.272049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.273606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.273626] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.273644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.275221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.275244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.277108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.280475] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.280526] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.280545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.280571] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.297310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.297358] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.297421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.297667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.297756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.314000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.314088] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.314177] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.332857] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.332895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.332935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.332969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.333096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.333137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.333168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.333200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.333244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.333287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.333330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.333372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.333413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.333453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.333512] [drm:intel_power_well_disable [i915]] disabling display
>[  918.333557] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.333589] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.333610] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.333715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.333727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.333783] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.333805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.333828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.333857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.333882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.333909] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.333935] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.333961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.333990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.334046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.334076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.334085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.334114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.334121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.334150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.334177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.334205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.334233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.334263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.334290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.334317] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.334344] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.334371] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.334402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.334434] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.334510] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.334538] [drm:intel_power_well_enable [i915]] enabling display
>[  918.334569] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.334607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.334628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.334647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.334666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.334683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.334703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.334724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.334744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.334764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.334782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.334800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.334823] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.334843] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.336882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.336903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.336922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.336941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.338516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.338537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.338555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.340212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.340235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.342112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.345480] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.345546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.345580] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.345622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.362331] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.362381] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.362447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.362667] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.362745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.379076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.379136] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.379207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.396241] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.396277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.396317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.396350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.396384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.396413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.396441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.396473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.396508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.396540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.396570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.396601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.396628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.396655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.396707] [drm:intel_power_well_disable [i915]] disabling display
>[  918.396748] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.396788] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.396819] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.396923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.396934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.397053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.397083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.397117] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.397152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.397181] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.397210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.397240] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.397269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.397298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.397328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.397357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.397365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.397393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.397401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.397428] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.397455] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.397481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.397510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.397535] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.397554] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.397572] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.397590] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.397607] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.397629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.397652] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.397714] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.397733] [drm:intel_power_well_enable [i915]] enabling display
>[  918.397751] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.397784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.397804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.397823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.397842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.397860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.397880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.397902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.397922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.397948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.397974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.398027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.398060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.398089] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.400139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.400160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.400182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.400206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.401778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.401800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.401822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.403387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.403408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.405279] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.408603] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.408662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.408695] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.408738] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.425444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.425506] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.425586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.425786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.425862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.442118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.442167] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.442237] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.459265] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.459302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.459346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.459397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.459446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.459478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.459508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.459540] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.459582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.459625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.459667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.459709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.459748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.459787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.459844] [drm:intel_power_well_disable [i915]] disabling display
>[  918.459889] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.459939] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.459974] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.460285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.460304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.460395] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.460428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.460463] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.460500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.460531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.460565] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.460598] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.460630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.460662] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.460692] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.460722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.460729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.460757] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.460765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.460795] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.460824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.460854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.460883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.460913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.460942] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.460971] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.461022] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.461053] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.461086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.461122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.461213] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.461245] [drm:intel_power_well_enable [i915]] enabling display
>[  918.461275] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.461327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.461359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.461388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.461418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.461449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.461481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.461516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.461549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.461582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.461612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.461642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.461676] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.461708] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.463783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.463805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.463825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.463844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.465411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.465431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.465453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.467035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.467057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.468923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.471686] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.471735] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.471755] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.471781] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.488536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.488586] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.488652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.488909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.489089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.505239] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.505289] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.505378] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.522442] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.522479] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.522518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.522551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.522594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.522634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.522673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.522712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.522769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.522812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.522853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.522895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.522934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.522972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.523125] [drm:intel_power_well_disable [i915]] disabling display
>[  918.523192] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.523260] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.523310] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.523551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.523580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.523696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.523729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.523770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.523805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.523834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.523865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.523895] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.523923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.523952] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.523990] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.524046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.524058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.524088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.524096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.524127] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.524157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.524189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.524219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.524253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.524283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.524315] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.524345] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.524377] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.524412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.524446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.524521] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.524552] [drm:intel_power_well_enable [i915]] enabling display
>[  918.524582] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.524632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.524664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.524695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.524725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.524755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.524786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.524820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.524852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.524886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.524915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.524944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.524978] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.525034] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.527098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.527119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.527138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.527157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.528728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.528751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.528774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.530338] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.530360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.532231] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.535536] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.535615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.535647] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.535688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.552391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.552441] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.552507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.552717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.552795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.569079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.569139] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.569207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.587936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.587973] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.588107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.588159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.588217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.588266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.588313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.588363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.588419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.588470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.588523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.588573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.588619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.588664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.588748] [drm:intel_power_well_disable [i915]] disabling display
>[  918.588812] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.588863] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.588895] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.589092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.589110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.589189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.589210] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.589231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.589255] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.589277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.589302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.589326] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.589349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.589373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.589393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.589416] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.589420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.589443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.589447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.589471] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.589492] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.589515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.589537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.589561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.589583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.589607] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.589630] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.589653] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.589678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.589703] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.589763] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.589783] [drm:intel_power_well_enable [i915]] enabling display
>[  918.589802] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.589839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.589862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.589886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.589909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.589932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.589955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.590032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.590072] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.590108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.590139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.590171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.590208] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.590241] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.592321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.592343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.592361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.592381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.593971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.594007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.594026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.595596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.595619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.597513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.600832] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.600899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.600939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.601052] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.617675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.617724] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.617787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.618178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.618259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.634353] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.634400] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.634472] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.651509] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.651546] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.651586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.651619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.651654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.651684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.651713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.651744] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.651778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.651810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.651841] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.651871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.651899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.651926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.652058] [drm:intel_power_well_disable [i915]] disabling display
>[  918.652128] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.652193] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.652227] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.652322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.652334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.652389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.652410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.652433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.652458] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.652478] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.652499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.652521] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.652540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.652560] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.652578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.652596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.652601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.652618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.652623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.652641] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.652659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.652677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.652695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.652717] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.652734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.652752] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.652770] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.652787] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.652809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.652832] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.652891] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.652909] [drm:intel_power_well_enable [i915]] enabling display
>[  918.652927] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.652961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.653010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.653040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.653068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.653095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.653125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.653157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.653188] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.653217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.653244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.653271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.653303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.653331] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.655391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.655412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.655431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.655450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.657100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.657124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.657147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.658707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.658729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.660602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.663891] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.664053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.664191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.664235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.680764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.680815] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.680910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.681359] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.681439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.697440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.697488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.697558] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.715929] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.715966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.716093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.716153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.716210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.716260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.716294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.716326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.716363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.716397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.716428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.716470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.716511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.716551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.716614] [drm:intel_power_well_disable [i915]] disabling display
>[  918.716650] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.716681] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.716701] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.716803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.716815] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.716871] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.716901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.716934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.716960] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.717018] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.717051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.717081] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.717110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.717138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.717167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.717194] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.717202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.717228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.717236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.717263] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.717289] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.717317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.717342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.717373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.717399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.717426] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.717452] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.717478] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.717510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.717544] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.717634] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.717665] [drm:intel_power_well_enable [i915]] enabling display
>[  918.717695] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.717748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.717780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.717811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.717842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.717871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.717903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.717932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.717954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.718012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.718039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.718066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.718099] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.718127] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.720193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.720214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.720232] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.720251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.721825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.721846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.721868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.723432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.723453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.725325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.728618] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.728712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.728752] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.728803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.745482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.745534] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.745600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.745810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.745888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.762166] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.762219] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.762293] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.779316] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.779353] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.779393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.779426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.779461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.779491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.779520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.779552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.779586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.779626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.779669] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.779711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.779759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.779778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.779811] [drm:intel_power_well_disable [i915]] disabling display
>[  918.779836] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.779863] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.779881] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.780049] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.780069] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.780141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.780165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.780200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.780231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.780251] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.780273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.780295] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.780315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.780335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.780354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.780372] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.780377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.780395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.780400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.780418] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.780436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.780455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.780472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.780494] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.780519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.780545] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.780571] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.780598] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.780625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.780653] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.780715] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.780737] [drm:intel_power_well_enable [i915]] enabling display
>[  918.780759] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.780798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.780824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.780850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.780876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.780903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.780928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.780956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.781016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.781049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.781078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.781106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.781140] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.781169] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.783238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.783260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.783278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.783298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.784870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.784890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.784908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.786461] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.786481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.788365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.791681] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.791752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.791792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.791844] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.808526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.808577] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.808643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.808856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.808935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.825205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.825253] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.825322] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.843874] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.843911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.843955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.844073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.844139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.844190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.844239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.844290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.844343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.844378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.844409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.844442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.844470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.844499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.844551] [drm:intel_power_well_disable [i915]] disabling display
>[  918.844594] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.844642] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.844679] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.844823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.844842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.844928] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.844962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.845058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.845116] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.845154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.845195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.845235] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.845273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.845311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.845347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.845382] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.845394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.845428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.845438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.845474] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.845509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.845549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.845585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.845626] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.845662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.845696] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.845732] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.845769] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.845811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.845853] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.845972] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.846048] [drm:intel_power_well_enable [i915]] enabling display
>[  918.846095] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.846153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.846189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.846224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.846255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.846286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.846318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.846353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.846389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.846424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.846456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.846488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.846524] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.846548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.848593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.848614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.848632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.848650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.850226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.850246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.850264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.851813] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.851833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.853704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.857064] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.857137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.857170] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.857212] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.873920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.873970] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.874234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.874450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.874531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.890594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.890647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.890720] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.907738] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.907775] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.907814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.907848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.907883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.907913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.907943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.908054] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.908112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.908166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.908218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.908267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.908310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.908354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.908432] [drm:intel_power_well_disable [i915]] disabling display
>[  918.908474] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.908513] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.908545] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.908708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.908725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.908803] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.908824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.908845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.908867] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.908896] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.908924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.908944] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.909009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.909044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.909071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.909102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.909111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.909140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.909148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.909179] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.909206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.909236] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.909264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.909296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.909323] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.909353] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.909380] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.909409] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.909439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.909472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.909562] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.909592] [drm:intel_power_well_enable [i915]] enabling display
>[  918.909623] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.909673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.909701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.909731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.909757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.909786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.909814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.909847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.909879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.909910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.909936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.909965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.910019] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.910048] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.912113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.912133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.912152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.912170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.913742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.913763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.913782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.915344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.915366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.917230] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.920550] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.920618] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.920638] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.920664] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  918.937397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.937447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.937513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.937725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.937804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.954071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  918.954123] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  918.954198] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  918.971216] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  918.971254] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  918.971294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.971328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.971363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.971402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.971442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.971481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  918.971526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.971568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.971610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.971652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.971691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.971711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.971744] [drm:intel_power_well_disable [i915]] disabling display
>[  918.971769] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  918.971796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  918.971814] [drm:intel_power_well_disable [i915]] disabling always-on
>[  918.971909] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  918.971921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  918.972042] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  918.972073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  918.972109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  918.972148] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  918.972177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  918.972212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  918.972243] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  918.972275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  918.972303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  918.972335] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  918.972361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  918.972679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.972708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  918.972716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  918.972746] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  918.972773] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  918.972802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  918.972828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  918.972861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  918.972887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  918.972916] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  918.972942] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  918.972994] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  918.973026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  918.973061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  918.973352] [drm:intel_power_well_enable [i915]] enabling always-on
>[  918.973380] [drm:intel_power_well_enable [i915]] enabling display
>[  918.973407] [drm:hsw_set_power_well [i915]] Enabling power well
>[  918.973455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  918.973485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  918.973510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  918.973537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  918.973562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  918.973591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  918.973621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  918.973652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  918.973681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  918.973706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  918.973731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  918.973763] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  918.973789] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  918.975856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  918.975877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  918.975895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.975914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  918.977488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  918.977509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  918.977528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  918.979217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  918.979240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  918.981116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  918.984449] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  918.984551] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  918.984585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  918.984627] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.001330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.001381] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.001447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.001714] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.001799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.018032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  919.018089] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.018177] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  919.035189] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  919.035227] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.035267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.035301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.035335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.035374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.035414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.035453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.035497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.035539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.035581] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.035623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.035662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.035701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.035758] [drm:intel_power_well_disable [i915]] disabling display
>[  919.035803] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.035853] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.035888] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.036332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.036351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.036446] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.036475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.036506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.036540] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.036566] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.036595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.036623] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  919.036651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  919.036679] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.036705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.036729] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.036736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.036760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.036767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.036793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.036817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.036844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.036868] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.036897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.036921] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.036948] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  919.037020] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  919.037048] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  919.037082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.037117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  919.037206] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.037475] [drm:intel_power_well_enable [i915]] enabling display
>[  919.037505] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.037557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.037589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.037621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.037648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.037677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.037705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.037737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.037769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.037802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.037828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.037856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.037886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  919.037917] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.040008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.040029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.040047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.040066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.041643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.041667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.041687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.043244] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.043265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.045138] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.048391] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  919.048455] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.048475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  919.048501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.065251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.065302] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.065368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.065587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.065689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.081941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  919.082019] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.082107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  919.099100] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  919.099137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.099177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.099216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.099260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.099300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.099340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.099379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.099423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.099465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.099507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.099549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.099587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.099626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.099682] [drm:intel_power_well_disable [i915]] disabling display
>[  919.099728] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.099778] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.099813] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.100046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.100077] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.100503] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.100534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.100568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.100604] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.100634] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.100666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.100696] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  919.100726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  919.100755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.100785] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.100812] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.100820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.100848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.100854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.100883] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.100909] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.100937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.100987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.101021] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.101047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.101077] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  919.101104] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  919.101133] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  919.101164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.101198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  919.101538] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.101567] [drm:intel_power_well_enable [i915]] enabling display
>[  919.101595] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.101643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.101673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.101699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.101727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.101752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.101780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.101811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.101842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.101871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.101896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.101921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.101963] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  919.102021] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.104269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.104293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.104316] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.104340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.105933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.105974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.106005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.107611] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.107632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.109504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.112757] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  919.112831] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.112860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  919.112896] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.129616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.129669] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.129741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.130171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.130287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.146291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  919.146340] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.146427] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  919.163490] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  919.163527] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.163566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.163599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.163633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.163672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.163712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.163751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.163795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.163838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.163887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.163940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.164047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.164093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.164177] [drm:intel_power_well_disable [i915]] disabling display
>[  919.164230] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.164277] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.164309] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.164464] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.164482] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.164568] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.164589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.164615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.164644] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.164670] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.164697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.164723] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  919.164749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  919.164775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.164801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.164826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.164832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.164857] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.164862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.164888] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.164914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.164939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.164996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.165029] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.165058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.165087] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  919.165115] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  919.165143] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  919.165174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.165207] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  919.165297] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.165320] [drm:intel_power_well_enable [i915]] enabling display
>[  919.165338] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.165373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.165394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.165413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.165432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.165450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.165471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.165494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.165514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.165535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.165553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.165571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.165594] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  919.165615] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.167661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.167683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.167701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.167720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.169282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.169306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.169329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.170887] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.170909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.172817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.175636] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  919.175694] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.175727] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  919.175777] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.192481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.192531] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.192597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.192803] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.192880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.209177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  919.209224] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.209296] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  919.226342] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  919.226379] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.226419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.226452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.226487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.226517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.226546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.226584] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.226629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.226671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.226714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.226755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.226794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.226833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.226889] [drm:intel_power_well_disable [i915]] disabling display
>[  919.226934] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.227056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.227101] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.227281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.227305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.227419] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.227462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.227508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.227558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.227599] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.227643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.227686] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  919.227728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  919.227769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.227808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.227847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.227857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.227894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.227913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.227943] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.228002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.228031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.228061] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.228095] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.228126] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.228156] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  919.228187] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  919.228216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  919.228250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.228285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  919.228378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.228409] [drm:intel_power_well_enable [i915]] enabling display
>[  919.228439] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.228492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.228523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.228554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.228584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.228614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.228645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.228678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.228712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.228745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.228774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.228803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.228836] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  919.228867] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.230956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.231003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.231021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.231040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.232617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.232642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.232665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.234232] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.234254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.236128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.239453] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  919.239509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.239540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  919.239580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.256273] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.256321] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.256385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.256584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.256659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.273016] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  919.273061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.273149] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  919.291972] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  919.292042] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.292082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.292116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.292151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.292181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.292209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.292240] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.292275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.292307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.292338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.292369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.292397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.292425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.292478] [drm:intel_power_well_disable [i915]] disabling display
>[  919.292519] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.292561] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.292591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.292756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.292775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.292859] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.292891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.292926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.293029] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.293074] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.293121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.293168] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  919.293213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  919.293254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.293281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.293308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.293316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.293342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.293349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.293376] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.293402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.293429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.293455] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.293485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.293511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.293538] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  919.293564] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  919.293591] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  919.293624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.293868] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  919.293928] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.293978] [drm:intel_power_well_enable [i915]] enabling display
>[  919.294009] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.294113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.294135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.294155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.294175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.294194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.294218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.294247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.294274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.294301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.294327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.294352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.294380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  919.294403] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.296444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.296465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.296484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.296502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.298163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.298184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.298202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.299749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.299773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.301643] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.304371] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  919.304454] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.304473] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  919.304499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.321247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.321299] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.321365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.321578] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.321658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.337918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  919.338044] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.338155] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  919.355173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  919.355210] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.355250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.355283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.355319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.355349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.355378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.355410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.355452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.355495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.355537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.355578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.355605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.355631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.355678] [drm:intel_power_well_disable [i915]] disabling display
>[  919.355713] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.355756] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  919.355788] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.356452] [drm:drm_mode_addfb2] [FB:77]
>[  919.356495] [drm:drm_mode_addfb2] [FB:78]
>[  919.386069] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  919.386186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  919.386263] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.386335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.386346] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.386406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.386428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.386451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.386474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.386493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.386514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.386534] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.386553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.386571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.386589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.386605] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.386610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.386626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.386630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.386653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.386677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.386701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.386724] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.386748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.386771] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.386794] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.386817] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.386841] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.386866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.386891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.390391] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.390412] [drm:intel_power_well_enable [i915]] enabling display
>[  919.390431] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.390469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.390491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.390512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.390532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.390551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.390575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.390601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.390628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.390653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.390678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.390702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.390728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.390752] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.392825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.392848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.392866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.392885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.394491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.394514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.394536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.396111] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.396133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.398002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.400562] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.400610] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.400630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.400655] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.417409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.417461] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.417527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.434071] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.434091] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.450895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.451067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.467442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.467489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.467560] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.485895] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.485933] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.486059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.486112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.486169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.486217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.486271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.486306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.486339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.486369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.486397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.486426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.486451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.486476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.486524] [drm:intel_power_well_disable [i915]] disabling display
>[  919.486561] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.486598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.486626] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.486786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.486801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.486878] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.486906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.486938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.487027] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.487068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.487112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.487154] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.487195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.487233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.487278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.487308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.487318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.487348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.487356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.487387] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.487417] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.487447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.487477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.487510] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.487540] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.487570] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.487600] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.487630] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.487667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.487706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.487807] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.487842] [drm:intel_power_well_enable [i915]] enabling display
>[  919.487876] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.487936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.488001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.488036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.488071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.488102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.488136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.488171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.488207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.488244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.488283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.488312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.488346] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.488379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.490446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.490467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.490487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.490512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.492154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.492174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.492193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.493743] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.493764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.495627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.498917] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.499011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.499044] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.499087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.515789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.515841] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.515907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.516283] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.516375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.532469] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.532516] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.532586] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.550904] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.550941] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.551065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.551112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.551166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.551209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.551254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.551298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.551353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.551404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.551453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.551502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.551542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.551579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.551633] [drm:intel_power_well_disable [i915]] disabling display
>[  919.551683] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.551719] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.551748] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.551892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.551904] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.552017] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.552049] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.552084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.552121] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.552151] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.552185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.552215] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.552248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.552277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.552307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.552334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.552341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.552368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.552376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.552406] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.552433] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.552461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.552487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.552518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.552543] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.552571] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.552596] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.552625] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.552654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.552687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.552775] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.552805] [drm:intel_power_well_enable [i915]] enabling display
>[  919.552834] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.552884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.552913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.552966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.552994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.553024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.553052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.553086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.553118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.553151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.553178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.553208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.553241] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.553273] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.555336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.555357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.555375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.555399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.556987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.557010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.557033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.558594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.558617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.560489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.563783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.563865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.563891] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.563925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.580645] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.580693] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.580757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.581296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.581388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.597327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.597372] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.597439] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.615880] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.615917] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.616049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.616238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.616275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.616307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.616337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.616369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.616404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.616437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.616469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.616500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.616529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.616566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.616621] [drm:intel_power_well_disable [i915]] disabling display
>[  919.616666] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.616716] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.616751] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.616906] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.616980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.617073] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.617266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.617301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.617338] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.617369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.617403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.617436] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.617467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.617500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.617530] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.617560] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.617567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.617596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.617603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.617633] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.617662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.617692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.617721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.617754] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.617783] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.617813] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.617839] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.617868] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.617901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.617934] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.618046] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.618348] [drm:intel_power_well_enable [i915]] enabling display
>[  919.618380] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.618440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.618470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.618498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.618526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.618554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.618583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.618614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.618645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.618675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.618702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.618728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.618760] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.618789] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.620871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.620892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.620910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.620974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.622541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.622562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.622580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.624167] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.624190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.626070] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.629313] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.629388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.629407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.629433] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.646182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.646233] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.646300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.646500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.646580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.662861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.662909] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.663262] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.681897] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.681934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.682056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.682109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.682167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.682215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.682247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.682279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.682316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.682351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.682383] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.682425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.682465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.682506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.682564] [drm:intel_power_well_disable [i915]] disabling display
>[  919.682610] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.682657] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.682690] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.682842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.682860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.683036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.683084] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.683136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.683191] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.683232] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.683264] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.683294] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.683324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.683355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.683384] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.683411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.683419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.683445] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.683453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.683485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.683514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.683543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.683571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.683604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.683633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.683663] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.683692] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.683718] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.683740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.683764] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.683828] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.683847] [drm:intel_power_well_enable [i915]] enabling display
>[  919.683865] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.683899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.683919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.683974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.684003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.684030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.684059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.684091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.684121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.684151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.684178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.684204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.684236] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.684268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.686331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.686352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.686371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.686392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.687980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.688001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.688020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.689575] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.689596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.691465] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.694597] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.694689] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.694716] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.694750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.711474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.711525] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.711591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.711801] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.711880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.728150] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.728202] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.728277] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.745892] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.745930] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.746053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.746112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.746169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.746218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.746266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.746332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.746388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.746440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.746489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.746521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.746551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.746581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.746636] [drm:intel_power_well_disable [i915]] disabling display
>[  919.746678] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.746726] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.746756] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.746867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.746879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.746984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.747020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.747057] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.747096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.747128] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.747162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.747196] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.747229] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.747261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.747292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.747322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.747331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.747361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.747369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.747399] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.747428] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.747459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.747489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.747518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.747547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.747574] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.747603] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.747629] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.747661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.747696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.747786] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.747816] [drm:intel_power_well_enable [i915]] enabling display
>[  919.747847] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.747898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.747930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.747985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.748017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.748048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.748080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.748115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.748149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.748182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.748212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.748243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.748278] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.748310] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.750371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.750392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.750411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.750430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.752031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.752051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.752069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.753624] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.753645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.755509] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.758823] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.758877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.758898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.758976] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.775673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.775725] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.775792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.776242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.776323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.792349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.792397] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.792468] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.810883] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.810921] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.811051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.811239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.811277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.811309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.811348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.811388] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.811432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.811474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.811516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.811558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.811597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.811636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.811691] [drm:intel_power_well_disable [i915]] disabling display
>[  919.811736] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.811786] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.811822] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.812038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.812325] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.812444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.812489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.812534] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.812583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.812624] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.812667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.812710] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.812752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.812793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.812833] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.812872] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.812890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.812917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.812969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.813001] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.813032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.813064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.813094] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.813129] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.813159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.813189] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.813219] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.813249] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.813281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.813318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.813638] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.813655] [drm:intel_power_well_enable [i915]] enabling display
>[  919.813672] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.813706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.813726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.813749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.813773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.813796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.813830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.813854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.813876] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.813904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.813972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.814002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.814040] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.814072] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.816337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.816358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.816376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.816395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.818062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.818082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.818101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.819650] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.819671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.821534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.824824] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.824918] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.825010] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.825082] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.841694] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.841745] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.841811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.842286] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.842366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.858405] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.858453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.858520] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.876876] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.876912] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.877045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.877248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.877286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.877318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.877348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.877379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.877420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.877447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.877474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.877500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.877523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.877546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.877589] [drm:intel_power_well_disable [i915]] disabling display
>[  919.877624] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.877665] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.877695] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.877816] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.877831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.877909] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.877997] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.878046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.878099] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.878141] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.878187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.878231] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.878275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.878317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.878358] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.878398] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.878418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.878447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.878455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.878485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.878515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.878547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.878576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.878610] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.878908] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.878964] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.878995] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.879026] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.879148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.879183] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.879269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.879300] [drm:intel_power_well_enable [i915]] enabling display
>[  919.879330] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.879391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.879420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.879448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.879476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.879503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.879531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.879562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.879593] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.879622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.879650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.879677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.879707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.879736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.881804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.881825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.881843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.881862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.883450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.883471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.883489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.885126] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.885152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.887028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.890338] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.890409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.890441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.890491] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.907190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.907244] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.907316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.907534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.907616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.923867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.923915] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.924284] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  919.942887] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  919.942924] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  919.943047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.943106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.943165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.943351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.943383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.943415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.943451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.943484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.943515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.943546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.943573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.943601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.943652] [drm:intel_power_well_disable [i915]] disabling display
>[  919.943693] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  919.943741] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.943759] [drm:intel_power_well_disable [i915]] disabling always-on
>[  919.943851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.943862] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  919.943912] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  919.943983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  919.944017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  919.944056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  919.944088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  919.944122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  919.944155] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  919.944188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  919.944220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  919.944252] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  919.944283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  919.944292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.944321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  919.944329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  919.944359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  919.944391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  919.944421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  919.944713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  919.944747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  919.944779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  919.944811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  919.944841] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  919.944872] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  919.944905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.944961] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  919.945165] [drm:intel_power_well_enable [i915]] enabling always-on
>[  919.945194] [drm:intel_power_well_enable [i915]] enabling display
>[  919.945222] [drm:hsw_set_power_well [i915]] Enabling power well
>[  919.945270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  919.945300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  919.945328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  919.945356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  919.945384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  919.945412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  919.945444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  919.945474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  919.945503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.945530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  919.945557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  919.945588] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  919.945617] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  919.947697] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  919.947718] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  919.947737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.947755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  919.949318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  919.949338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  919.949361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  919.950915] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  919.950947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  919.952801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  919.956111] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  919.956178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  919.956205] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  919.956241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  919.972994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  919.973048] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  919.973121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  919.973339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  919.973423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  919.989640] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  919.989689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  919.989759] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.006784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.006821] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.006861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.006894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.007008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.007053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.007102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.007148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.007203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.007255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.007304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.007353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.007394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.007438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.007518] [drm:intel_power_well_disable [i915]] disabling display
>[  920.007581] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.007641] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.007690] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.007973] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.008003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.008125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.008154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.008187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.008225] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.008258] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.008292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.008326] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.008359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.008392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.008421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.008453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.008459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.008492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.008497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.008531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.008561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.008594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.008624] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.008657] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.008690] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.008723] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.008756] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.008789] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.008823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.008859] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.008963] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.009008] [drm:intel_power_well_enable [i915]] enabling display
>[  920.009045] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.009113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.009147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.009177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.009207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.009236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.009267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.009301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.009335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.009368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.009394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.009421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.009454] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.009485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.011562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.011583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.011602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.011620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.013186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.013206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.013229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.014788] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.014809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.016671] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.019986] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.020053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.020085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.020127] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.036835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.036886] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.037035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.037311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.037388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.053512] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.053560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.053630] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.071866] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.071903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.072027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.072074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.072128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.072172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.072217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.072262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.072318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.072369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.072418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.072449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.072475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.072502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.072557] [drm:intel_power_well_disable [i915]] disabling display
>[  920.072606] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.072643] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.072672] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.072803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.072819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.072871] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.072891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.072912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.072986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.073017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.073051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.073082] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.073114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.073142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.073174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.073203] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.073212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.073240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.073247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.073277] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.073304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.073334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.073360] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.073393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.073420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.073450] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.073477] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.073507] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.073540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.073575] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.073664] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.073694] [drm:intel_power_well_enable [i915]] enabling display
>[  920.073724] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.073774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.073805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.073833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.073861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.073888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.073918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.073976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.074010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.074044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.074070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.074101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.074131] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.074163] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.076223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.076243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.076261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.076280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.077849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.077869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.077887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.079482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.079503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.081402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.084702] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.084771] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.084790] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.084816] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.101565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.101619] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.101692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.102143] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.102258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.118243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.118291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.118362] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.135393] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.135430] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.135470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.135503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.135537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.135567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.135597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.135628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.135663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.135696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.135735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.135763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.135790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.135815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.135865] [drm:intel_power_well_disable [i915]] disabling display
>[  920.135903] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.136015] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.136058] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.136241] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.136260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.136342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.136373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.136407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.136449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.136486] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.136525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.136564] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.136602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.136641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.136679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.136717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.136735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.136758] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.136763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.136785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.136805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.136824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.136843] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.136864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.136883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.136901] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.136956] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.136983] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.137014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.137047] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.137137] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.137161] [drm:intel_power_well_enable [i915]] enabling display
>[  920.137179] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.137215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.137236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.137255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.137274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.137299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.137325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.137352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.137374] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.137396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.137414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.137433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.137456] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.137477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.139686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.139707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.139726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.139745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.141318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.141338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.141356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.143006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.143027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.144901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.148216] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.148290] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.148317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.148352] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.165046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.165095] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.165159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.165375] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.165451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.181750] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.181798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.181887] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.198993] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.199030] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.199069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.199103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.199137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.199167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.199195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.199226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.199260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.199293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.199324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.199355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.199383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.199422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.199479] [drm:intel_power_well_disable [i915]] disabling display
>[  920.199525] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.199574] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.199610] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.199766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.199784] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.199876] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.199917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.200005] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.200043] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.200072] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.200104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.200135] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.200164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.200193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.200221] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.200248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.200256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.200282] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.200290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.200317] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.200344] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.200371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.200397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.200430] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.200682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.200704] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.200723] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.200743] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.200765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.200789] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.200851] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.200883] [drm:intel_power_well_enable [i915]] enabling display
>[  920.200936] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.200991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.201036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.201191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.201211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.201232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.201252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.201275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.201295] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.201317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.201334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.201353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.201375] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.201395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.203435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.203456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.203474] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.203493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.205065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.205089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.205112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.206671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.206693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.208562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.211876] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.212012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.212144] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.212194] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.228723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.228776] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.228848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.229265] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.229345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.245398] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.245447] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.245517] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.263842] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.263880] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.263999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.264060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.264118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.264167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.264223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.264263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.264297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.264327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.264354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.264383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.264408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.264433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.264481] [drm:intel_power_well_disable [i915]] disabling display
>[  920.264518] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.264555] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.264583] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.264708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.264724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.264803] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.264840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.264877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.264922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.265000] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.265047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.265091] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.265132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.265173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.265211] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.265253] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.265265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.265295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.265303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.265334] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.265365] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.265394] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.265424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.265458] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.265489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.265519] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.265548] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.265582] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.265619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.265656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.265758] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.265793] [drm:intel_power_well_enable [i915]] enabling display
>[  920.265828] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.265889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.265954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.265991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.266026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.266060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.266095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.266131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.266169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.266205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.266245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.266274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.266310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.266341] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.268403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.268428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.268453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.268479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.270133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.270154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.270173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.271731] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.271753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.273626] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.276980] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.277059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.277092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.277142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.293837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.293889] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.294048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.294272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.294365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.310538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.310590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.310676] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.328864] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.328901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.329026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.329086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.329142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.329191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.329226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.329258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.329296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.329331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.329362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.329395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.329423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.329453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.329504] [drm:intel_power_well_disable [i915]] disabling display
>[  920.329532] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.329559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.329580] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.329705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.329717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.329773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.329795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.329818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.329843] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.329863] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.329884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.329937] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.329966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.329995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.330023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.330050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.330058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.330084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.330091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.330118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.330145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.330171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.330197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.330227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.330253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.330280] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.330306] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.330332] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.330363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.330395] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.330485] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.330516] [drm:intel_power_well_enable [i915]] enabling display
>[  920.330547] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.330600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.330631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.330662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.330692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.330722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.330753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.330788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.330816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.330837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.330856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.330875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.330897] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.330948] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.333013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.333035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.333053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.333075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.334645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.334666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.334684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.336246] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.336267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.338137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.341463] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.341523] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.341563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.341615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.358299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.358351] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.358418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.358660] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.358752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.374998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.375046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.375113] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.392749] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.392791] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.392836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.392877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.393011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.393104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.393155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.393207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.393247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.393281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.393312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.393345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.393372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.393401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.393454] [drm:intel_power_well_disable [i915]] disabling display
>[  920.393494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.393536] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.393568] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.393704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.393716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.393771] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.393792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.393814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.393839] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.393859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.393880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.393932] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.393961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.393990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.394018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.394044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.394052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.394078] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.394086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.394113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.394140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.394167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.394193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.394223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.394249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.394277] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.394303] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.394330] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.394362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.394394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.394485] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.394516] [drm:intel_power_well_enable [i915]] enabling display
>[  920.394546] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.394599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.394631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.394662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.394692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.394722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.394753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.394786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.394808] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.394829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.394848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.394865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.394889] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.394945] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.397008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.397029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.397047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.397066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.398637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.398657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.398675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.400227] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.400248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.402121] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.405439] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.405504] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.405537] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.405579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.422285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.422337] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.422404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.422652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.422743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.438982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.439029] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.439098] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.456113] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.456155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.456199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.456240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.456284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.456323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.456363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.456402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.456446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.456488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.456529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.456571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.456609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.456648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.456704] [drm:intel_power_well_disable [i915]] disabling display
>[  920.456750] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.456800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.456835] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.457292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.457308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.457385] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.457417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.457449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.457487] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.457520] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.457556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.457590] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.457625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.457659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.457688] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.457721] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.457728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.457761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.457768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.457802] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.457836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.457869] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.457903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.457975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.458027] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.458060] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.458091] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.458121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.458156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.458192] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.458465] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.458486] [drm:intel_power_well_enable [i915]] enabling display
>[  920.458506] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.458547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.458576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.458605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.458633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.458662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.458689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.458720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.458751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.458780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.458808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.458835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.458865] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.458894] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.461189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.461211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.461230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.461249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.462810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.462831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.462849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.464418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.464442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.466425] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.469668] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.469752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.469781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.469819] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.486538] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.486590] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.486656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.486878] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.487058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.503237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.503284] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.503352] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.520363] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.520405] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.520449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.520490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.520534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.520573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.520613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.520652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.520696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.520738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.520780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.520821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.520860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.520899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.521023] [drm:intel_power_well_disable [i915]] disabling display
>[  920.521089] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.521156] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.521207] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.521396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.521415] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.521510] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.521538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.521569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.521602] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.521629] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.521671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.521701] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.521739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.521765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.521791] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.521815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.521821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.521846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.521852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.521879] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.521945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.521975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.522004] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.522034] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.522064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.522091] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.522120] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.522147] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.522181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.522216] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.522304] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.522335] [drm:intel_power_well_enable [i915]] enabling display
>[  920.522364] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.522414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.522443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.522473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.522499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.522528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.522556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.522588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.522620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.522652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.522679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.522704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.522737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.522767] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.524863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.524885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.524964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.524999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.526679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.526700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.526718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.528280] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.528301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.530171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.533515] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.533589] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.533608] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.533634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.550385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.550436] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.550502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.550744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.550837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.567084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.567131] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.567199] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.584214] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.584251] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.584290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.584330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.584373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.584413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.584452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.584491] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.584535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.584577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.584622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.584654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.584687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.584719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.584768] [drm:intel_power_well_disable [i915]] disabling display
>[  920.584806] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.584848] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.584878] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.585140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.585164] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.585279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.585322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.585365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.585412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.585449] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.585491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.585530] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.585570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.585615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.585647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.585675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.585683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.585714] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.585721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.585752] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.585781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.585811] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.585839] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.585873] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.585923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.585954] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.585983] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.586014] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.586046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.586082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.586177] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.586210] [drm:intel_power_well_enable [i915]] enabling display
>[  920.586242] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.586296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.586329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.586359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.586390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.586418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.586450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.586485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.586520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.586554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.586582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.586612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.586653] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.586683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.588761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.588782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.588801] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.588820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.590417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.590438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.590461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.592057] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.592078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.593942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.596588] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.596669] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.596702] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.596744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.613445] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.613496] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.613563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.613811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.613903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.630144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.630192] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.630261] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.647851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.647888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.648012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.648071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.648127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.648175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.648278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.648327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.648384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.648436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.648487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.648537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.648583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.648629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.648708] [drm:intel_power_well_disable [i915]] disabling display
>[  920.648751] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.648793] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.648824] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.649059] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.649078] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.649166] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.649205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.649237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.649271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.649300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.649330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.649360] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.649389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.649417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.649445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.649469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.649476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.649502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.649508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.649535] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.649562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.649587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.649613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.649643] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.649671] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.649695] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.649722] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.649751] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.649781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.649813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.649935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.649968] [drm:intel_power_well_enable [i915]] enabling display
>[  920.650002] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.650053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.650086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.650117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.650149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.650179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.650211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.650245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.650279] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.650350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.650379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.650408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.650441] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.650472] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.652545] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.652569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.652592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.652616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.654191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.654212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.654231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.655779] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.655801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.657672] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.660997] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.661054] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.661087] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.661129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.677834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.677885] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.678171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.678392] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.678492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.694535] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.694582] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.694650] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.711676] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.711714] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.711754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.711788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.711824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.711854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.711884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.712003] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.712064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.712118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.712359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.712390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.712418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.712446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.712496] [drm:intel_power_well_disable [i915]] disabling display
>[  920.712534] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.712572] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.712602] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.712712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.712723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.712775] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.712795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.712816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.712839] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.712857] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.712880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.712954] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.712988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.713021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.713053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.713083] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.713092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.713122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.713130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.713161] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.713192] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.713222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.713251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.713285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.713314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.713342] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.713371] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.713402] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.713435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.713754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.713843] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.713875] [drm:intel_power_well_enable [i915]] enabling display
>[  920.713932] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.714055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.714076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.714095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.714114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.714136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.714160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.714186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.714211] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.714235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.714259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.714282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.714306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.714330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.716403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.716425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.716447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.716471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.718040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.718064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.718085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.719634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.719655] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.721523] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.724791] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.724851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.724879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.724987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.741634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.741686] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.741752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.742063] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.742180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.758331] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.758378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.758447] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.776862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.776941] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.776981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.777015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.777049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.777078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.777116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.777156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.777200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.777242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.777284] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.777325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.777364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.777403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.777460] [drm:intel_power_well_disable [i915]] disabling display
>[  920.777505] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.777559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.777578] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.777673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.777684] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.777737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.777757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.777779] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.777802] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.777820] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.777840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.777863] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.777934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.777968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.778003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.778035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.778045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.778074] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.778082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.778112] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.778142] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.778174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.778204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.778237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.778267] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.778299] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.778328] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.778359] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.778393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.778428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.778520] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.778551] [drm:intel_power_well_enable [i915]] enabling display
>[  920.778581] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.778631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.778663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.778693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.778720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.778749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.778777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.778810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.778843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.778875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.778927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.778955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.778991] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.779021] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.781079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.781102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.781130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.781149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.782710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.782730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.782748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.784310] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.784331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.786203] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.789512] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.789585] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.789624] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.789675] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.806363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.806414] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.806480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.806726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.806818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.823063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.823112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.823180] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.840193] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.840247] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.840294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.840328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.840363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.840394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.840423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.840454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.840489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.840521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.840553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.840583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.840610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.840637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.840690] [drm:intel_power_well_disable [i915]] disabling display
>[  920.840730] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.840771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.840802] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.841005] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.841024] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.841113] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.841145] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.841180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.841217] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.841248] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.841281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.841315] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.841347] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.841378] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.841408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.841438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.841446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.841474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.841481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.841511] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.841540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.841569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.841599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.841631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.841660] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.841691] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.841720] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.841750] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.841783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.841818] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.841930] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.841963] [drm:intel_power_well_enable [i915]] enabling display
>[  920.841994] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.842046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.842080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.842112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.842144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.842175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.842207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.842242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.842276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.842309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.842339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.842367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.842402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.842433] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.844525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.844547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.844566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.844586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.846151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.846172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.846190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.847748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.847769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.849643] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.853014] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.853074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.853098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.853129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.869856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.869989] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.870187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.870406] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.870506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.886556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.886615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.886694] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.904837] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.904874] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.905007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.905194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.905237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.905265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.905292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.905320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.905352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.905381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.905409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.905445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.905480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.905515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.905564] [drm:intel_power_well_disable [i915]] disabling display
>[  920.905606] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.905667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.905700] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.905823] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.905839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.905987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.906035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.906086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.906139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.906184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.906235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.906269] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.906301] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.906334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.906633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.906664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.906672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.906702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.906709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.906740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.906770] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.906800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.906829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.906860] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.906912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.906943] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.906973] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.907004] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.907039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.907074] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.907349] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.907379] [drm:intel_power_well_enable [i915]] enabling display
>[  920.907407] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.907455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.907485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.907514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.907542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.907570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.907598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.907629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.907659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.907689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.907727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.907754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.907796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.907825] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.909924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.909945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.909963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.909982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.911562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.911584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.911602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.913173] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.913194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.915073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.918396] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.918440] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.918464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.918495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.935236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.935287] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.935354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.935597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.935694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.951971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  920.952023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  920.952095] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  920.969097] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  920.969134] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  920.969173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.969213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.969257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.969297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.969337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.969376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.969420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.969462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.969504] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.969546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.969575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.969600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.969645] [drm:intel_power_well_disable [i915]] disabling display
>[  920.969679] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  920.969716] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.969742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  920.969941] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.969968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  920.970086] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  920.970129] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  920.970175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  920.970224] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  920.970265] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  920.970309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  920.970352] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  920.970393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  920.970434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  920.970473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  920.970513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  920.970531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.970559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  920.970566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  920.970596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  920.970625] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  920.970654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  920.970683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  920.970715] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  920.970744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  920.970774] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  920.970803] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  920.970833] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  920.970866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  920.970921] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  920.971013] [drm:intel_power_well_enable [i915]] enabling always-on
>[  920.971045] [drm:intel_power_well_enable [i915]] enabling display
>[  920.971077] [drm:hsw_set_power_well [i915]] Enabling power well
>[  920.971130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  920.971161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  920.971193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  920.971224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  920.971254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  920.971282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  920.971315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  920.971348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  920.971380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.971409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  920.971438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  920.971472] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  920.971503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  920.973578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  920.973602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  920.973625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.973649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  920.975226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  920.975247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  920.975270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  920.976864] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  920.976897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  920.978755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  920.982075] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  920.982134] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  920.982163] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  920.982201] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  920.998950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  920.999001] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  920.999068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  920.999313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  920.999412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.015615] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.015661] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.015729] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.033725] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.033763] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.033803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.033836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.033879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.033995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.034046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.034097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.034154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.034208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.034307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.034351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.034391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.034431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.034489] [drm:intel_power_well_disable [i915]] disabling display
>[  921.034536] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.034587] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.034623] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.034789] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.034809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.034948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.034980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.035014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.035049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.035077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.035109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.035139] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.035168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.035200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.035229] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.035257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.035265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.035291] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.035298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.035329] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.035359] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.035388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.035417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.035449] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.035479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.035508] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.035530] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.035548] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.035574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.035602] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.035666] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.035689] [drm:intel_power_well_enable [i915]] enabling display
>[  921.035711] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.035750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.035777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.035803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.035829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.035855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.035909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.035943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.035975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.036006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.036033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.036059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.036092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.036121] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.038189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.038210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.038228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.038247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.039811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.039831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.039849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.041449] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.041469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.043364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.046691] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.046754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.046804] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.046849] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.063529] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.063584] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.063656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.064006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.064088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.080227] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.080273] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.080340] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.097356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.097393] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.097433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.097467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.097502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.097532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.097561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.097593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.097649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.097696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.097739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.097781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.097820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.097859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.097998] [drm:intel_power_well_disable [i915]] disabling display
>[  921.098064] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.098130] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.098184] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.098324] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.098342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.098430] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.098461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.098493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.098528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.098556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.098588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.098618] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.098647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.098677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.098705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.098731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.098738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.098764] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.098771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.098800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.098826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.098854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.098907] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.098939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.098969] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.098996] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.099026] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.099053] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.099087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.099122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.099209] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.099240] [drm:intel_power_well_enable [i915]] enabling display
>[  921.099269] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.099321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.099350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.099379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.099406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.099435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.099463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.099496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.099528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.099559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.099585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.099613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.099643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.099673] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.101752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.101776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.101796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.101826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.103447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.103468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.103486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.105042] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.105064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.106935] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.110273] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.110374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.110393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.110419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.127148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.127200] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.127272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.127515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.127616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.143848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.143929] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.144006] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.161029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.161071] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.161116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.161156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.161200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.161240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.161280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.161319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.161363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.161405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.161451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.161486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.161519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.161552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.161600] [drm:intel_power_well_disable [i915]] disabling display
>[  921.161639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.161681] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.161711] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.161844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.161919] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.162036] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.162077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.162121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.162171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.162209] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.162251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.162290] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.162330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.162367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.162404] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.162450] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.162457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.162484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.162490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.162519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.162545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.162573] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.162598] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.162629] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.162654] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.162682] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.162707] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.162734] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.162763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.162797] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.162907] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.162938] [drm:intel_power_well_enable [i915]] enabling display
>[  921.162969] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.163021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.163051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.163083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.163111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.163141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.163169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.163203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.163236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.163268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.163295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.163323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.163357] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.163385] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.165567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.165589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.165607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.165626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.167190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.167210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.167228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.168786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.168806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.170678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.173965] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.174062] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.174099] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.174147] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.190839] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.190965] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.191171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.191412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.191504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.207537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.207584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.207651] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.225973] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.226011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.226050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.226084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.226118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.226148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.226177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.226209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.226243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.226276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.226307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.226338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.226366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.226393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.226446] [drm:intel_power_well_disable [i915]] disabling display
>[  921.226486] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.226526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.226557] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.226702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.226713] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.226763] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.226782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.226802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.226825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.226843] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.226862] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.226942] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.226971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.227000] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.227031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.227057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.227066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.227094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.227101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.227131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.227157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.227188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.227214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.227247] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.227273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.227303] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.227329] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.227359] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.227393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.227428] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.227895] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.227927] [drm:intel_power_well_enable [i915]] enabling display
>[  921.227957] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.228008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.228038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.228068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.228095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.228123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.228151] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.228183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.228214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.228246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.228272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.228299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.228330] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.228360] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.230461] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.230484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.230504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.230525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.232107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.232127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.232146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.233703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.233724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.235587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.238946] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.239005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.239025] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.239050] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.255803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.255855] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.256017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.256270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.256352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.272495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.272541] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.272623] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.290838] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.290914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.290955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.290990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.291026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.291057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.291087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.291119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.291162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.291204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.291246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.291288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.291327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.291366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.291425] [drm:intel_power_well_disable [i915]] disabling display
>[  921.291471] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.291522] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.291558] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.291717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.291736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.291832] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.291873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.291958] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.292001] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.292030] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.292066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.292098] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.292130] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.292160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.292190] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.292217] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.292227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.292255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.292263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.292293] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.292321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.292350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.292379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.292412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.292438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.292468] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.292494] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.292523] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.292555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.292590] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.292684] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.292714] [drm:intel_power_well_enable [i915]] enabling display
>[  921.292744] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.292795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.292826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.292853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.292913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.292940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.292971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.293005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.293039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.293074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.293101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.293129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.293164] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.293193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.295262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.295286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.295309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.295333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.296909] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.296930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.296949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.298537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.298560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.300438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.303787] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.303876] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.303966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.304039] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.320653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.320705] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.320771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.321085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.321164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.337330] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.337378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.337447] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.355804] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.355841] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.355966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.356173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.356207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.356235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.356262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.356291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.356322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.356352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.356380] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.356408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.356433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.356457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.356504] [drm:intel_power_well_disable [i915]] disabling display
>[  921.356540] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.356577] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.356604] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.356739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.356755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.356830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.356857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.356938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.356994] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.357034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.357084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.357126] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.357171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.357220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.357256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.357290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.357299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.357332] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.357341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.357376] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.357409] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.357442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.357472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.357508] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.357538] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.357975] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.358010] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.358041] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.358078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.358117] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.358224] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.358255] [drm:intel_power_well_enable [i915]] enabling display
>[  921.358282] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.358336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.358364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.358394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.358421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.358449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.358477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.358509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.358540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.358571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.358597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.358625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.358658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.358686] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.360773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.360796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.360815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.360838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.362435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.362457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.362475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.364053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.364076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.365958] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.369304] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.369393] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.369436] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.369470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.386172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.386223] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.386289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.386504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.386586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.402849] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.402930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.403001] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.420007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.420050] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.420094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.420135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.420179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.420219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.420258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.420297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.420341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.420383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.420425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.420479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.420510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.420530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.420563] [drm:intel_power_well_disable [i915]] disabling display
>[  921.420588] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.420615] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.420633] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.420730] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.420741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.420793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.420812] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.420833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.420920] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.420949] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.420981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.421011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.421040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.421069] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.421096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.421122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.421131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.421156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.421164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.421191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.421217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.421244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.421269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.421300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.421326] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.421353] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.421382] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.421410] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.421441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.421473] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.421547] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.421568] [drm:intel_power_well_enable [i915]] enabling display
>[  921.421590] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.421630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.421656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.421686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.421720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.421749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.421771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.421793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.421814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.421835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.421882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.421910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.421943] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.421972] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.424037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.424059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.424077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.424096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.425666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.425687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.425705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.427270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.427291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.429162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.432461] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.432546] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.432578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.432620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.449326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.449378] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.449443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.449659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.449739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.465998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.466047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.466117] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.484263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.484301] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.484340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.484374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.484417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.484457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.484497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.484536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.484580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.484622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.484664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.484706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.484749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.484778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.484827] [drm:intel_power_well_disable [i915]] disabling display
>[  921.484925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.484983] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.485025] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.485379] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.485396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.485476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.485506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.485540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.485575] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.485602] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.485634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.485664] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.485692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.485720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.485753] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.485773] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.485780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.485800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.485804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.485825] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.485845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.485912] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.485942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.485978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.486056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.486248] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.486270] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.486300] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.486330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.486363] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.486432] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.486457] [drm:intel_power_well_enable [i915]] enabling display
>[  921.486482] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.486526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.486556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.486586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.486615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.486645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.486673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.486702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.486734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.486769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.486790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.486811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.486833] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.486885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.489140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.489161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.489180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.489198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.490766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.490785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.490803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.492383] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.492406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.494390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.497716] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.497774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.497806] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.497848] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.514548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.514597] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.514661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.515102] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.515196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.531229] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.531274] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.531341] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.548401] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.548439] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.548479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.548512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.548556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.548595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.548635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.548674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.548717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.548760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.548801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.548843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.548958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.548989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.549043] [drm:intel_power_well_disable [i915]] disabling display
>[  921.549079] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.549110] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.549131] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.549231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.549243] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.549298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.549320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.549343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.549375] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.549407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.549431] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.549452] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.549473] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.549493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.549513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.549530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.549536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.549553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.549557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.549583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.549609] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.549636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.549661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.549687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.549713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.549738] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.549763] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.549788] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.549815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.549842] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.549957] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.549985] [drm:intel_power_well_enable [i915]] enabling display
>[  921.550012] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.550067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.550095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.550116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.550135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.550155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.550175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.550198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.550218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.550245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.550270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.550296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.550323] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.550349] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.552413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.552434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.552457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.552481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.554040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.554062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.554087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.555619] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.555642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.557495] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.560514] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.560560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.560580] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.560608] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.577359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.577411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.577480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.577708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.577789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.594033] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.594082] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.594154] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.612769] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.612807] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.612847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.612966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.613120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.613152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.613182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.613214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.613249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.613282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.613313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.613344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.613382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.613400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.613434] [drm:intel_power_well_disable [i915]] disabling display
>[  921.613461] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.613488] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.613508] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.613617] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.613628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.613679] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.613698] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.613719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.613742] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.613760] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.613779] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.613798] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.613816] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.613834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.613903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.613930] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.613939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.613965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.613973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.614000] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.614027] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.614054] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.614080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.614110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.614136] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.614163] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.614192] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.614218] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.614249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.614281] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.614613] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.614645] [drm:intel_power_well_enable [i915]] enabling display
>[  921.614666] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.614703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.614725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.614745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.614770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.614796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.614822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.614853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.614912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.614944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.614972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.615000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.615033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.615064] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.617239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.617260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.617278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.617296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.618931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.618951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.618970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.620534] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.620558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.622436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.625710] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.625752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.625771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.625797] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.642546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.642598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.642664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.643125] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.643247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.659222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.659270] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.659339] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.676396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.676433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.676472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.676505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.676541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.676571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.676600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.676631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.676666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.676698] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.676737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.676765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.676789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.676813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.676936] [drm:intel_power_well_disable [i915]] disabling display
>[  921.676996] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.677055] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.677100] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.677321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.677346] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.677467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.677514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.677562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.677614] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.677657] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.677703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.677754] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.677786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.677818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.677849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.677903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.677914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.677943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.677951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.677984] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.678014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.678046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.678076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.678110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.678140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.678172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.678202] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.678232] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.678265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.678300] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.678388] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.678419] [drm:intel_power_well_enable [i915]] enabling display
>[  921.678449] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.678501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.678533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.678564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.678595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.678625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.678656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.678690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.678722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.678755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.678784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.678813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.678847] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.678904] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.680968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.680989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.681008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.681027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.682597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.682617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.682639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.684195] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.684216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.686087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.689408] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.689471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.689504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.689546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.706251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.706304] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.706370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.706570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.706649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.722928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.722976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.723047] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.740076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.740114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.740154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.740188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.740223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.740253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.740283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.740314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.740348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.740390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.740432] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.740474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.740514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.740552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.740609] [drm:intel_power_well_disable [i915]] disabling display
>[  921.740654] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.740704] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.740740] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.740995] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.741033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.741125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.741159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.741193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.741230] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.741261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.741295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.741328] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.741360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.741391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.741421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.741451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.741458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.741488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.741495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.741525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.741555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.741584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.741613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.741646] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.741677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.741707] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.741737] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.741767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.741800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.741834] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.741955] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.741987] [drm:intel_power_well_enable [i915]] enabling display
>[  921.742018] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.742072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.742104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.742135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.742166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.742194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.742224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.742259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.742292] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.742325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.742355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.742385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.742419] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.742451] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.744517] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.744538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.744557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.744576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.746150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.746170] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.746188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.747748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.747769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.749641] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.752959] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.753027] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.753067] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.753118] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.769805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.769857] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.770146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.770359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.770436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.786482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.786530] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.786601] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.803630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.803667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.803706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.803739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.803775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.803806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.803835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.803960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.804020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.804075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.804125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.804177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.804222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.804267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.804351] [drm:intel_power_well_disable [i915]] disabling display
>[  921.804406] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.804447] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.804479] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.804642] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.804660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.804737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.804757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.804780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.804807] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.804830] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.804906] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.804943] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.804977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.805010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.805042] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.805073] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.805083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.805112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.805120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.805152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.805183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.805214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.805243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.805279] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.805309] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.805340] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.805371] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.805398] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.805432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.805467] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.805556] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.805587] [drm:intel_power_well_enable [i915]] enabling display
>[  921.805618] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.805668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.805701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.805732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.805763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.805793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.805824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.805881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.805916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.805947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.805977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.806008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.806043] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.806075] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.808142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.808163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.808182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.808201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.809761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.809783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.809802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.811360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.811381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.813273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.816606] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.816642] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.816666] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.816697] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.833443] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.833497] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.833569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.833780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.833915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.850114] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.850163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.850253] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.867312] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.867349] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.867390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.867423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.867457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.867487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.867515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.867546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.867580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.867612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.867643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.867682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.867708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.867734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.867784] [drm:intel_power_well_disable [i915]] disabling display
>[  921.867822] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.867954] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.868004] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.868237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.868263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.868394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.868442] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.868492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.868548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.868592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.868641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.868694] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.868725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.868756] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.868787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.868816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.868847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.868877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.868884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.868912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.868941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.868967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.868995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.869028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.869097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.869128] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.869159] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.869185] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.869219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.869254] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.869344] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.869375] [drm:intel_power_well_enable [i915]] enabling display
>[  921.869405] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.869456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.869488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.869518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.869548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.869577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.869608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.869642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.869675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.869708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.869738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.869766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.869800] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.869831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.871920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.871941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.871959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.871979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.873542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.873562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.873580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.875142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.875164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.877033] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.880370] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.880470] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.880502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.880545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.897244] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.897296] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.897362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.897561] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.897642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.913921] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.913969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.914039] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.931796] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.931834] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.931963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.932016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.932072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.932121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.932154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.932186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.932225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.932268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.932312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.932355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.932405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.932440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.932495] [drm:intel_power_well_disable [i915]] disabling display
>[  921.932537] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.932580] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.932611] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.932755] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.932773] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.932915] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.932961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.933013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.933072] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.933100] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.933130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.933162] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.933190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.933219] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.933246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.933273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.933281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.933309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.933316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.933344] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.933371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.933398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.933423] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.933457] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.933486] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.933515] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.933544] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.933574] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.933606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.933641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.933718] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.933747] [drm:intel_power_well_enable [i915]] enabling display
>[  921.933767] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.933802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.933823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.933883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.933912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.933939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.933968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.933999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.934029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.934059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.934089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.934116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.934151] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.934183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.936249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.936273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.936296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.936320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  921.937889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  921.937910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  921.937929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.939498] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  921.939519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  921.941385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  921.944118] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  921.944216] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  921.944265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  921.944303] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  921.960992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.961043] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.961109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.961322] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.961401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.977671] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  921.977720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  921.977791] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  921.994821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  921.994893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  921.994932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.994965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.995000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.995029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.995068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.995107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  921.995152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.995194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.995235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.995277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.995316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.995356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.995389] [drm:intel_power_well_disable [i915]] disabling display
>[  921.995414] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  921.995442] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  921.995460] [drm:intel_power_well_disable [i915]] disabling always-on
>[  921.995556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  921.995567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  921.995620] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  921.995640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  921.995662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  921.995685] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  921.995703] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  921.995723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  921.995742] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  921.995773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  921.995793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  921.995813] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  921.995892] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  921.995902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.995931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  921.995940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  921.995970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  921.996001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  921.996032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  921.996062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  921.996095] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  921.996125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  921.996156] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  921.996185] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  921.996216] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  921.996250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  921.996285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  921.996376] [drm:intel_power_well_enable [i915]] enabling always-on
>[  921.996407] [drm:intel_power_well_enable [i915]] enabling display
>[  921.996438] [drm:hsw_set_power_well [i915]] Enabling power well
>[  921.996488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  921.996520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  921.996551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  921.996581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  921.996610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  921.996642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  921.996676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  921.996709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  921.996741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  921.996772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  921.996801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  921.996835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  921.996893] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  921.998961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  921.998982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  921.999003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  921.999027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.000599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.000620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.000639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.002199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.002220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.004081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.007394] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.007464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.007496] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.007538] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.024246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.024297] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.024363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.024578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.024657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.040921] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.040969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.041040] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.058066] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.058104] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.058144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.058181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.058225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.058264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.058304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.058342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.058386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.058428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.058470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.058512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.058551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.058589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.058649] [drm:intel_power_well_disable [i915]] disabling display
>[  922.058675] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.058703] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.058722] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.058871] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.058891] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.058981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.059011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.059044] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.059080] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.059108] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.059140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.059170] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.059200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.059228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.059257] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.059283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.059290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.059316] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.059323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.059351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.059378] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.059405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.059430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.059462] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.059488] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.059516] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.059542] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.059569] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.059598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.059631] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.059718] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.059747] [drm:intel_power_well_enable [i915]] enabling display
>[  922.059776] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.059826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.059881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.059910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.059942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.059969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.059999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.060035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.060068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.060101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.060127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.060156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.060191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.060220] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.062332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.062354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.062373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.062392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.063973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.063995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.064014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.065578] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.065601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.067476] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.070767] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.070921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.070944] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.070972] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.087638] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.087690] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.087756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.088091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.088174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.104338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.104385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.104471] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.121476] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.121514] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.121552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.121585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.121620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.121650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.121679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.121711] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.121745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.121777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.121808] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.121917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.121960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.122003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.122240] [drm:intel_power_well_disable [i915]] disabling display
>[  922.122268] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.122297] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.122318] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.122422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.122442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.122506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.122526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.122548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.122571] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.122589] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.122609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.122629] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.122648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.122666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.122684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.122706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.122710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.122734] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.122738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.122762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.122785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.122809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.122882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.122914] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.122943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.122971] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.122999] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.123027] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.123060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.123092] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.123370] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.123389] [drm:intel_power_well_enable [i915]] enabling display
>[  922.123407] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.123444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.123465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.123487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.123506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.123532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.123558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.123587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.123615] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.123642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.123668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.123694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.123721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.123747] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.125786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.125808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.125872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.125907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.127541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.127562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.127580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.129143] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.129167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.131039] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.134293] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.134355] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.134373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.134399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.151150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.151202] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.151268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.151508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.151600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.167853] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.167942] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.168031] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.185047] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.185085] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.185124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.185158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.185193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.185224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.185254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.185286] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.185321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.185361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.185391] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.185420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.185446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.185471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.185521] [drm:intel_power_well_disable [i915]] disabling display
>[  922.185559] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.185602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.185651] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.185796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.185878] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.186006] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.186055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.186102] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.186154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.186197] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.186243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.186286] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.186330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.186370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.186416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.186446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.186455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.186486] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.186494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.186528] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.186558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.186592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.186622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.186658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.186688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.186721] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.186751] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.186783] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.186818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.186885] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.186989] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.187025] [drm:intel_power_well_enable [i915]] enabling display
>[  922.187061] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.187120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.187156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.187188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.187222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.187253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.187287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.187325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.187362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.187406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.187432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.187459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.187489] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.187519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.189595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.189619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.189639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.189660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.191216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.191236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.191255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.192880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.192902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.194765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.198071] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.198148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.198181] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.198222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.214937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.214989] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.215055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.215280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.215359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.231632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.231681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.231755] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.248766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.248803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.248938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.248990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.249047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.249095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.249142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.249192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.249248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.249301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.249352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.249403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.249449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.249494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.249579] [drm:intel_power_well_disable [i915]] disabling display
>[  922.249644] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.249705] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.249758] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.249933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.249952] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.250048] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.250079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.250111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.250139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.250158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.250178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.250197] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.250216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.250234] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.250251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.250268] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.250272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.250288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.250292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.250309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.250326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.250342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.250357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.250377] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.250399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.250423] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.250447] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.250470] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.250495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.250520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.250580] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.250600] [drm:intel_power_well_enable [i915]] enabling display
>[  922.250619] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.250656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.250680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.250704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.250727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.250750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.250773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.250799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.250823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.250899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.250936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.250969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.251006] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.251039] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.253123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.253145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.253165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.253184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.254744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.254765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.254784] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.256382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.256404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.258302] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.261408] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.261483] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.261515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.261558] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.278272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.278323] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.278390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.278615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.278694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.294965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.295014] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.295088] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.312260] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.312302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.312346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.312387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.312431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.312471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.312510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.312550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.312594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.312636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.312678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.312720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.312758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.312797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.312931] [drm:intel_power_well_disable [i915]] disabling display
>[  922.312997] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.313066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.313112] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.313254] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.313274] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.313362] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.313391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.313425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.313462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.313490] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.313521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.313551] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.313581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.313609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.313638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.313664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.313672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.313698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.313705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.313735] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.313761] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.313789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.313815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.313870] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.313898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.313928] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.313957] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.313986] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.314020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.314055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.314148] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.314178] [drm:intel_power_well_enable [i915]] enabling display
>[  922.314207] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.314258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.314287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.314316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.314343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.314371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.314399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.314431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.314462] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.314494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.314520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.314547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.314577] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.314607] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.316669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.316690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.316711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.316735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.318310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.318331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.318350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.319921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.319941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.321806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.325152] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.325253] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.325285] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.325327] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.342028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.342079] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.342145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.342368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.342469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.358761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.358809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.359037] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.376758] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.376794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.376915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.376967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.377024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.377072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.377120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.377169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.377225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.377276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.377326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.377376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.377420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.377464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.377519] [drm:intel_power_well_disable [i915]] disabling display
>[  922.377561] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.377602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.377642] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.377760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.377771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.377877] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.377913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.377950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.377990] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.378021] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.378056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.378090] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.378124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.378156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.378187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.378217] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.378225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.378255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.378263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.378292] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.378321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.378352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.378382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.378416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.378446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.378473] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.378502] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.378528] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.378560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.378595] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.378688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.378719] [drm:intel_power_well_enable [i915]] enabling display
>[  922.378750] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.378801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.378857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.378888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.378920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.378951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.378983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.379017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.379051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.379084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.379114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.379144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.379179] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.379210] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.381299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.381321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.381339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.381358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.382938] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.382958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.382977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.384524] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.384544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.386409] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.389697] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.389778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.389807] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.389899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.406566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.406616] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.406679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.407122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.407201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.423250] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.423298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.423367] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.440396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.440434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.440474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.440507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.440550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.440590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.440630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.440669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.440714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.440756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.440798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.440900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.440931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.440963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.441018] [drm:intel_power_well_disable [i915]] disabling display
>[  922.441059] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.441099] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.441130] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.441287] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.441305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.441394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.441422] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.441452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.441485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.441511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.441540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.441567] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.441596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.441622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.441649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.441672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.441679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.441704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.441710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.441736] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.441760] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.441786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.441809] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.441877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.441906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.441936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.441962] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.441992] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.442027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.442062] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.442151] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.442181] [drm:intel_power_well_enable [i915]] enabling display
>[  922.442210] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.442260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.442291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.442318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.442346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.442372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.442401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.442433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.442465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.442496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.442521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.442549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.442579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.442609] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.444676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.444707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.444726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.444745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.446308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.446329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.446347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.447923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.447944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.449806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.453133] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.453190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.453209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.453235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.469992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.470044] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.470112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.470331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.470411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.486663] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.486715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.486788] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.503901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.503938] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.503977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.504018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.504062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.504102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.504141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.504189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.504225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.504257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.504285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.504313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.504338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.504362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.504409] [drm:intel_power_well_disable [i915]] disabling display
>[  922.504445] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.504482] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.504509] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.504631] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.504647] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.504722] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.504751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.504782] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.504816] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.504900] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.504946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.504988] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.505027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.505067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.505104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.505140] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.505151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.505187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.505205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.505232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.505258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.505285] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.505311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.505341] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.505366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.505393] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.505419] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.505445] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.505476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.505510] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.505860] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.505880] [drm:intel_power_well_enable [i915]] enabling display
>[  922.505898] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.505945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.505976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.506004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.506033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.506054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.506075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.506098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.506120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.506140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.506165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.506191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.506219] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.506244] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.508308] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.508332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.508355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.508379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.510039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.510063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.510085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.511645] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.511667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.513541] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.516871] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.516926] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.516965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.517016] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.533703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.533757] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.533829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.534230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.534309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.550387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.550432] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.550500] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.568769] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.568807] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.568933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.568993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.569050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.569099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.569135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.569167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.569204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.569237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.569269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.569315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.569357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.569386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.569439] [drm:intel_power_well_disable [i915]] disabling display
>[  922.569481] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.569524] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.569557] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.569659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.569671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.569726] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.569747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.569769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.569794] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.569847] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.569878] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.569908] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.569936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.569965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.569991] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.570019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.570027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.570053] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.570060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.570087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.570114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.570141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.570167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.570197] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.570223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.570250] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.570276] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.570302] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.570333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.570368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.570457] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.570488] [drm:intel_power_well_enable [i915]] enabling display
>[  922.570518] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.570570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.570602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.570633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.570663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.570692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.570724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.570754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.570776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.570796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.570844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.570871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.570903] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.570931] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.572994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.573015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.573034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.573053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.574622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.574642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.574660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.576224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.576244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.578116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.581436] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.581499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.581532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.581574] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.598280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.598331] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.598398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.598609] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.598693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.614956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.615005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.615078] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.632108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.632146] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.632186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.632219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.632254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.632293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.632333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.632373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.632416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.632459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.632500] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.632542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.632592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.632636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.632690] [drm:intel_power_well_disable [i915]] disabling display
>[  922.632730] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.632774] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.632805] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.633058] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.633076] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.633163] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.633186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.633211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.633239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.633264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.633292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.633318] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.633344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.633370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.633396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.633422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.633428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.633453] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.633458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.633483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.633509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.633535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.633560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.633587] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.633611] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.633638] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.633663] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.633690] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.633716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.633744] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.633833] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.633863] [drm:intel_power_well_enable [i915]] enabling display
>[  922.633890] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.633943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.633974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.634004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.634033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.634061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.634091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.634123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.634154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.634188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.634217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.634244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.634277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.634310] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.636396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.636417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.636436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.636454] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.638026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.638047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.638064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.639614] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.639635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.641494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.644239] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.644306] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.644326] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.644351] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.661092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.661139] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.661203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.661427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.661523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.677805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.677897] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.677988] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.695045] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.695082] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.695122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.695155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.695190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.695220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.695248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.695286] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.695330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.695373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.695415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.695457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.695496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.695535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.695591] [drm:intel_power_well_disable [i915]] disabling display
>[  922.695637] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.695687] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.695722] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.696259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.696272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.696332] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.696355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.696379] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.696405] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.696425] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.696448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.696470] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.696490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.696510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.696529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.696548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.696553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.696570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.696575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.696594] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.696612] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.696630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.696648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.696670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.696687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.696705] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.696723] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.696740] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.696762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.696785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.696898] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.697081] [drm:intel_power_well_enable [i915]] enabling display
>[  922.697100] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.697136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.697159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.697179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.697199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.697218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.697238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.697260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.697281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.697302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.697321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.697339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.697365] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.697392] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.699435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.699458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.699481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.699505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.701081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.701102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.701121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.702669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.702691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.704563] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.707880] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.707945] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.707978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.708019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.724724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.724775] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.725046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.725245] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.725322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.741403] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.741453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.741524] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.759181] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.759223] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.759284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.759323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.759358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.759388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.759417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.759448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.759483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.759524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.759554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.759583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.759609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.759635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.759686] [drm:intel_power_well_disable [i915]] disabling display
>[  922.759723] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.759762] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.759790] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.760047] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.760064] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.760145] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.760177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.760211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.760248] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.760278] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.760310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.760341] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.760370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.760398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.760426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.760452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.760459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.760485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.760491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.760525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.760543] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.760561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.760579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.760601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.760618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.760644] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.760671] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.760697] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.760724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.760751] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.760828] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.760855] [drm:intel_power_well_enable [i915]] enabling display
>[  922.760883] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.760937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.760968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.760996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.761025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.761052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.761082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.761114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.761145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.761177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.761206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.761233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.761267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.761289] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.763338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.763359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.763382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.763406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.764982] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.765003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.765021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.766595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.766615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.768493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.771794] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.771861] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.771880] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.771906] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.788665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.788716] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.788782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.789152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.789240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.805364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.805414] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.805483] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.823771] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.823809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.823941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.823995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.824051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.824098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.824146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.824196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.824251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.824302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.824352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.824403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.824447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.824492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.824576] [drm:intel_power_well_disable [i915]] disabling display
>[  922.824641] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.824704] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.824755] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.825004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.825016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.825074] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.825104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.825125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.825150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.825173] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.825197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.825221] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.825244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.825268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.825289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.825312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.825316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.825339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.825343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.825367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.825390] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.825413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.825436] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.825459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.825481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.825505] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.825528] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.825551] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.825576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.825601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.825648] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.825668] [drm:intel_power_well_enable [i915]] enabling display
>[  922.825687] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.825724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.825748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.825771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.825794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.825869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.825902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.825940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.825975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.826009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.826040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.826071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.826107] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.826140] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.828210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.828231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.828250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.828269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.829857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.829877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.829900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.831472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.831494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.833360] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.836652] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.836743] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.836775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.836888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.853507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.853559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.853630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.853943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.854064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.870200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.870250] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.870324] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.888274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.888310] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.888349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.888383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.888418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.888457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.888497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.888536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.888581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.888623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.888665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.888706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.888745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.888784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.888926] [drm:intel_power_well_disable [i915]] disabling display
>[  922.888993] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.889063] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.889115] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.889343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.889362] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.889458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.889489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.889521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.889555] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.889583] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.889614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.889644] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.889674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.889702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.889730] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.889757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.889764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.889791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.889839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.889871] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.889904] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.889933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.889965] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.889998] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.890029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.890060] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.890091] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.890122] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.890157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.890192] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.890269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.890300] [drm:intel_power_well_enable [i915]] enabling display
>[  922.890331] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.890385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.890418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.890450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.890480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.890509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.890540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.890573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.890607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.890640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.890669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.890695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.890729] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.890760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.892857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.892878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.892896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.892914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.894497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.894520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.894539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.896090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.896112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.897980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.900657] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.900750] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.900777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.900886] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.917543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.917595] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.917660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.918051] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.918131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.934219] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.934264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.934332] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  922.951352] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  922.951394] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  922.951438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.951479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.951523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.951563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.951603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.951642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.951686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.951728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.951770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.951893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.951940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.951985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.952069] [drm:intel_power_well_disable [i915]] disabling display
>[  922.952119] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  922.952167] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.952199] [drm:intel_power_well_disable [i915]] disabling always-on
>[  922.952357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.952386] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  922.952480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  922.952514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  922.952559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  922.952588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  922.952613] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  922.952640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  922.952666] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  922.952692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  922.952718] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  922.952744] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  922.952769] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  922.952775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.952831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  922.952839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  922.952871] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  922.952900] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  922.952928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  922.952955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  922.952986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  922.953013] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  922.953041] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  922.953067] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  922.953096] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  922.953129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.953162] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  922.953246] [drm:intel_power_well_enable [i915]] enabling always-on
>[  922.953266] [drm:intel_power_well_enable [i915]] enabling display
>[  922.953284] [drm:hsw_set_power_well [i915]] Enabling power well
>[  922.953319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  922.953339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  922.953364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  922.953390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  922.953416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  922.953441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  922.953470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  922.953498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  922.953526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.953551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  922.953576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  922.953603] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  922.953629] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  922.955675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  922.955697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  922.955716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.955734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  922.957322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  922.957343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  922.957361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  922.958938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  922.958959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  922.960854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  922.964180] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  922.964235] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  922.964271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  922.964320] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  922.981014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  922.981066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  922.981133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  922.981352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  922.981432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  922.997690] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  922.997739] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  922.997895] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.016045] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.016082] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.016121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.016154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.016189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.016228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.016268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.016307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.016351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.016393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.016435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.016477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.016517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.016555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.016612] [drm:intel_power_well_disable [i915]] disabling display
>[  923.016658] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.016707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.016743] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.017026] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.017045] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.017136] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.017167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.017201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.017237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.017265] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.017297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.017327] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.017358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.017386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.017414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.017440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.017447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.017474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.017480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.017509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.017536] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.017564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.017589] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.017620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.017646] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.017674] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.017701] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.017728] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.017758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.017791] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.017936] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.017967] [drm:intel_power_well_enable [i915]] enabling display
>[  923.017997] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.018047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.018078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.018106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.018135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.018162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.018191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.018224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.018255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.018288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.018315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.018342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.018373] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.018403] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.020474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.020497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.020520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.020545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.022120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.022141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.022160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.023716] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.023737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.025601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.028920] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.028986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.029026] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.029078] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.045759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.045883] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.046090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.046300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.046378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.062438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.062490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.062580] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.079589] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.079626] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.079666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.079699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.079734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.079764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.079793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.079907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.079964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.080017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.080068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.080431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.080450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.080468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.080500] [drm:intel_power_well_disable [i915]] disabling display
>[  923.080525] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.080551] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.080570] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.080667] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.080678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.080730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.080749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.080770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.080847] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.080877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.080912] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.080942] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.080974] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.081002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.081032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.081059] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.081068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.081095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.081103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.081133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.081161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.081426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.081456] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.081488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.081516] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.081545] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.081571] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.081599] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.081633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.081666] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.081754] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.081785] [drm:intel_power_well_enable [i915]] enabling display
>[  923.081836] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.081888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.081920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.082137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.082163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.082189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.082216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.082245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.082275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.082304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.082328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.082354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.082384] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.082411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.084494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.084517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.084540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.084564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.086149] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.086170] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.086188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.087788] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.087827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.089691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.093037] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.093122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.093151] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.093189] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.109915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.109966] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.110033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.110257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.110336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.126608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.126656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.126728] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.143746] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.143784] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.143907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.143955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.144012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.144056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.144101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.144145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.144198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.144250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.144299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.144347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.144387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.144430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.144512] [drm:intel_power_well_disable [i915]] disabling display
>[  923.144574] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.144634] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.144683] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.144918] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.144933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.145008] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.145035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.145066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.145102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.145134] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.145167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.145199] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.145231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.145263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.145291] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.145322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.145329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.145360] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.145365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.145397] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.145429] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.145460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.145490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.145522] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.145551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.145584] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.145615] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.145646] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.145679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.145713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.145844] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.145872] [drm:intel_power_well_enable [i915]] enabling display
>[  923.145903] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.145957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.145990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.146020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.146050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.146078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.146110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.146144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.146177] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.146209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.146239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.146266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.146300] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.146329] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.148402] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.148425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.148448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.148472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.150058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.150080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.150099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.151648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.151670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.153535] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.156852] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.156933] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.156966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.157008] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.173692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.173740] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.173895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.174177] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.174255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.190371] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.190417] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.190485] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.207511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.207562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.207602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.207642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.207686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.207731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.207784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.207903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.207962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.208015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.208064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.208117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.208155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.208183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.208236] [drm:intel_power_well_disable [i915]] disabling display
>[  923.208277] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.208319] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.208350] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.208509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.208524] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.208576] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.208595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.208617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.208640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.208658] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.208677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.208697] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.208716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.208734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.208751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.208767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.208810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.208840] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.208849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.208879] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.208907] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.208936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.208962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.208996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.209023] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.209053] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.209079] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.209109] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.209143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.209178] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.209266] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.209296] [drm:intel_power_well_enable [i915]] enabling display
>[  923.209325] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.209374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.209404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.209434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.209461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.209489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.209520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.209553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.209585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.209616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.209643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.209670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.209701] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.209730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.211839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.211860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.211878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.211897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.213474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.213495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.213513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.215068] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.215089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.216961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.220281] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.220351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.220370] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.220396] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.237124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.237175] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.237244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.237462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.237545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.253802] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.253881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.253955] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.270953] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.270991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.271031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.271064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.271099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.271129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.271158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.271189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.271224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.271256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.271287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.271318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.271345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.271373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.271427] [drm:intel_power_well_disable [i915]] disabling display
>[  923.271452] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.271477] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.271496] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.271591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.271602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.271653] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.271672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.271693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.271715] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.271733] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.271752] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.271772] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.271852] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.271880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.271911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.271938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.271947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.271974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.271982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.272011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.272038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.272067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.272093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.272127] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.272154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.272184] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.272210] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.272239] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.272273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.272307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.272818] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.272849] [drm:intel_power_well_enable [i915]] enabling display
>[  923.272878] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.272930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.272962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.272990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.273019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.273046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.273076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.273108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.273141] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.273172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.273199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.273227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.273257] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.273287] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.275380] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.275400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.275419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.275438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.277008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.277028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.277051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.278610] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.278631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.280504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.283765] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.283821] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.283840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.283866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.300624] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.300676] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.300743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.301182] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.301261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.317293] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.317341] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.317414] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.335733] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.335771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.335893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.336096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.336133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.336165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.336194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.336225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.336260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.336292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.336324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.336354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.336382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.336409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.336460] [drm:intel_power_well_disable [i915]] disabling display
>[  923.336504] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.336555] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.336591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.336732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.336750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.336889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.336921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.336957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.336994] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.337023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.337323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.337355] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.337385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.337413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.337442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.337468] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.337476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.337502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.337509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.337538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.337564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.337592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.337617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.337648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.337674] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.337702] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.337728] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.337756] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.337809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.337844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.338135] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.338163] [drm:intel_power_well_enable [i915]] enabling display
>[  923.338190] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.338238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.338267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.338293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.338319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.338344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.338372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.338402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.338431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.338460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.338494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.338521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.338563] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.338589] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.340663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.340684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.340703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.340726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.342306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.342329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.342352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.344003] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.344026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.345896] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.349143] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.349213] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.349233] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.349259] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.366027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.366078] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.366145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.366348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.366459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.382696] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.382746] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.382941] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.399952] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.399994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.400039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.400080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.400123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.400163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.400203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.400242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.400286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.400329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.400370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.400412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.400451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.400490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.400546] [drm:intel_power_well_disable [i915]] disabling display
>[  923.400591] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.400641] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.400677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.400936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.400965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.401066] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.401100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.401135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.401173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.401204] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.401237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.401271] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.401303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.401334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.401366] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.401395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.401403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.401431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.401438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.401468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.401497] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.401526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.401556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.401589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.401619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.401649] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.401679] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.401709] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.401742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.401777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.401890] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.401920] [drm:intel_power_well_enable [i915]] enabling display
>[  923.401952] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.402004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.402037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.402068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.402100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.402130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.402162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.402196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.402229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.402262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.402292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.402321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.402355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.402387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.404463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.404485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.404504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.404523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.406090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.406109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.406127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.407679] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.407699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.409572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.412917] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.413007] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.413041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.413083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.429793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.429881] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.429949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.430199] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.430292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.446495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.446543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.446613] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.463652] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.463690] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.463729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.463763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.463887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.463928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.463960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.463992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.464029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.464069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.464113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.464157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.464197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.464232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.464267] [drm:intel_power_well_disable [i915]] disabling display
>[  923.464294] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.464323] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.464343] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.464447] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.464460] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.464515] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.464536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.464559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.464584] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.464603] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.464624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.464646] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.464671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.464697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.464723] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.464748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.464754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.464806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.464814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.464845] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.464873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.464901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.464927] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.464958] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.464985] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.465012] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.465038] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.465065] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.465097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.465129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.465219] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.465246] [drm:intel_power_well_enable [i915]] enabling display
>[  923.465264] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.465299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.465320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.465339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.465377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.465407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.465436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.465458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.465478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.465499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.465517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.465536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.465559] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.465580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.467630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.467652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.467671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.467690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.469267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.469292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.469315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.471048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.471071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.472945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.476281] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.476382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.476415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.476457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.493157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.493211] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.493284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.493507] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.493590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.509836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.509884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.509972] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.526987] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.527024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.527063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.527096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.527131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.527161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.527190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.527222] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.527256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.527289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.527319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.527359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.527398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.527438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.527494] [drm:intel_power_well_disable [i915]] disabling display
>[  923.527540] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.527590] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.527625] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.527726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.527737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.527864] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.527901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.527938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.527977] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.528294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.528326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.528358] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.528387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.528416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.528443] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.528471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.528478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.528504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.528510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.528538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.528565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.528593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.528620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.528647] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.528674] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.528701] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.528728] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.528754] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.528822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.528861] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.529143] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.529174] [drm:intel_power_well_enable [i915]] enabling display
>[  923.529204] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.529257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.529291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.529323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.529353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.529383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.529415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.529448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.529481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.529513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.529542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.529570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.529604] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.529635] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.531716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.531737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.531755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.531822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.533380] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.533402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.533422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.535002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.535025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.536895] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.540207] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.540273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.540302] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.540340] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.557064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.557116] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.557183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.557407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.557511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.573772] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.573862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.573932] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.590948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.590989] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.591034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.591074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.591118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.591158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.591197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.591236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.591281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.591323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.591365] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.591406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.591445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.591484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.591540] [drm:intel_power_well_disable [i915]] disabling display
>[  923.591586] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.591635] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.591671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.592111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.592125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.592184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.592208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.592232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.592259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.592284] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.592311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.592337] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.592364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.592390] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.592416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.592441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.592447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.592472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.592477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.592503] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.592530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.592566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.592595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.592618] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.592639] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.592658] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.592677] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.592695] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.592717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.592740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.592845] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.592873] [drm:intel_power_well_enable [i915]] enabling display
>[  923.592900] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.593131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.593158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.593185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.593211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.593238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.593263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.593292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.593320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.593348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.593373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.593399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.593426] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.593452] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.595507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.595529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.595548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.595568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.597133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.597154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.597172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.598752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.598795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.600658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.603968] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.604040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.604072] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.604114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.620848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.620898] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.620962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.621178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.621253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.637485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.637531] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.637599] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.654626] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.654663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.654703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.654736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.654771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.654888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.654933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.654984] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.655040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.655091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.655140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.655197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.655224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.655252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.655306] [drm:intel_power_well_disable [i915]] disabling display
>[  923.655346] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.655386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.655417] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.655572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.655583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.655635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.655655] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.655676] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.655700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.655729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.655750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.655809] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.655841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.655870] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.655902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.655928] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.655937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.655964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.655972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.656002] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.656029] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.656058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.656084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.656117] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.656144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.656173] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.656200] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.656228] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.656257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.656291] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.656379] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.656409] [drm:intel_power_well_enable [i915]] enabling display
>[  923.656438] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.656488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.656517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.656546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.656573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.656601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.656628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.656660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.656692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.656723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.656749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.656800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.656832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.656863] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.658934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.658955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.658973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.658991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.660562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.660583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.660601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.662153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.662174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.664035] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.667336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.667421] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.667454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.667481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.684200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.684252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.684325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.684545] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.684629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.700875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.700922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.700992] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.718021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.718058] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.718097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.718130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.718164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.718194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.718222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.718254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.718288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.718321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.718352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.718383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.718411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.718438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.718491] [drm:intel_power_well_disable [i915]] disabling display
>[  923.718535] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.718574] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.718593] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.718689] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.718700] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.718751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.718831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.718864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.718902] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.718932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.718966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.718996] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.719030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.719059] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.719088] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.719117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.719126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.719153] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.719161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.719191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.719219] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.719248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.719274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.719306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.719333] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.719695] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.719724] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.719755] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.719814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.719849] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.720052] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.720080] [drm:intel_power_well_enable [i915]] enabling display
>[  923.720108] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.720156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.720185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.720211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.720237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.720262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.720290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.720320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.720350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.720380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.720404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.720430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.720461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.720488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.722572] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.722594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.722613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.722632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.724211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.724231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.724249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.725808] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.725830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.727692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.730996] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.731086] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.731116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.731152] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.747861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.747912] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.747992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.748227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.748330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.764541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.764590] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.764661] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.781677] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.781714] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.781753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.781876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.781919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.781950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.781981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.782012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.782048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.782083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.782114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.782145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.782173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.782212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.782270] [drm:intel_power_well_disable [i915]] disabling display
>[  923.782316] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.782366] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.782402] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.782564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.782583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.782676] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.782717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.782758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.782866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.782917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.782978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.783025] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.783068] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.783112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.783155] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.783196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.783207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.783247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.783257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.783297] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.783337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.783377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.783412] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.783457] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.783496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.783537] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.783578] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.783617] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.783662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.783709] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.783860] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.783902] [drm:intel_power_well_enable [i915]] enabling display
>[  923.783942] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.784010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.784044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.784079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.784112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.784146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.784180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.784218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.784254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.784289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.784320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.784352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.784389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.784423] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.786507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.786529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.786547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.786567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.788132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.788154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.788173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.789751] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.789783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.791652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.794960] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.795033] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.795065] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.795106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.811837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.811888] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.811955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.812167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.812246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.828484] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.828530] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.828618] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.845607] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.845649] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.845694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.845734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.845854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.845903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.845954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.846001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.846058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.846109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.846159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.846208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.846249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.846296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.846379] [drm:intel_power_well_disable [i915]] disabling display
>[  923.846441] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.846481] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.846512] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.846672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.846683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.846736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.846805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.846842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.846879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.846908] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.846942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.846973] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.847005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.847035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.847066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.847092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.847102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.847129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.847137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.847165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.847192] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.847221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.847247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.847279] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.847305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.847333] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.847361] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.847390] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.847421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.847455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.847546] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.847576] [drm:intel_power_well_enable [i915]] enabling display
>[  923.847605] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.847654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.847684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.847711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.847740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.847794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.847825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.847859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.847893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.847927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.847954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.847983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.848018] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.848047] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.850112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.850132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.850151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.850170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.851768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.851812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.851831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.853397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.853418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.855308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.858625] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.858699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.858718] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.858744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.875474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.875526] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.875593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.876003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.876084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.892180] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.892228] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.892336] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.909379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.909416] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.909456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.909495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.909539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.909579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.909619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.909658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.909702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.909745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.909875] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.909912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.909940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.909969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.910018] [drm:intel_power_well_disable [i915]] disabling display
>[  923.910045] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.910075] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.910098] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.910209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.910222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.910282] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.910308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.910335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.910364] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.910389] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.910416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.910442] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.910469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.910495] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.910520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.910545] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.910550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.910575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.910580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.910606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.910631] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.910656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.910682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.910708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.910734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.910789] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.910820] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.910849] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.910880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.910914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.911007] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.911033] [drm:intel_power_well_enable [i915]] enabling display
>[  923.911052] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.911089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.911109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.911129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.911148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.911166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.911186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.911208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.911228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.911248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.911267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.911285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.911313] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.911344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.913541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.913562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.913581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.913600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.915167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.915190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.915213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.916788] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.916810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.918685] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.922071] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.922154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.922174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.922199] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  923.938956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.939008] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.939074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.939280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.939358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.955669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  923.955715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  923.955880] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  923.972885] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  923.972923] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  923.972963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.973003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.973047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.973087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.973127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.973166] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  923.973210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.973260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.973293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.973324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.973350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.973376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.973424] [drm:intel_power_well_disable [i915]] disabling display
>[  923.973460] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  923.973499] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  923.973526] [drm:intel_power_well_disable [i915]] disabling always-on
>[  923.973650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  923.973666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  923.973742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  923.973826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  923.973878] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  923.973929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  923.973969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  923.974015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  923.974057] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  923.974100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  923.974139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  923.974180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  923.974217] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  923.974229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.974272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  923.974280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  923.974309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  923.974336] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  923.974365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  923.974391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  923.974423] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  923.974450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  923.974479] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  923.974505] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  923.974914] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  923.974950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  923.974985] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  923.975074] [drm:intel_power_well_enable [i915]] enabling always-on
>[  923.975103] [drm:intel_power_well_enable [i915]] enabling display
>[  923.975132] [drm:hsw_set_power_well [i915]] Enabling power well
>[  923.975183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  923.975214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  923.975242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  923.975271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  923.975297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  923.975327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  923.975361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  923.975393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  923.975424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  923.975451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  923.975478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  923.975509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  923.975539] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  923.977611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  923.977634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  923.977653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.977676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  923.979240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  923.979260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  923.979282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  923.980867] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  923.980888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  923.982750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  923.986108] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  923.986200] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  923.986233] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  923.986276] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.002961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.003013] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.003080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.003303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.003382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.019655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.019703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.019847] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.037028] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.037065] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.037104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.037138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.037173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.037203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.037232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.037269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.037313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.037355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.037397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.037439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.037478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.037517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.037575] [drm:intel_power_well_disable [i915]] disabling display
>[  924.037601] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.037629] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.037648] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.037806] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.037825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.038127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.038159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.038191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.038226] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.038254] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.038285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.038315] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.038345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.038374] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.038401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.038429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.038436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.038462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.038468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.038496] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.038523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.038550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.038574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.038604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.038630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.038657] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.038684] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.038710] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.038738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.038810] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.038902] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.039194] [drm:intel_power_well_enable [i915]] enabling display
>[  924.039225] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.039278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.039310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.039342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.039372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.039403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.039435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.039469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.039502] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.039534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.039564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.039593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.039626] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.039658] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.041721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.041741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.041815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.041852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.043413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.043433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.043451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.045002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.045025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.046885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.050186] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.050274] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.050314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.050366] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.067050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.067102] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.067169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.067386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.067466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.083724] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.083806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.083878] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.100877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.100914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.100954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.100987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.101022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.101052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.101081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.101118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.101163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.101205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.101247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.101289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.101328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.101367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.101424] [drm:intel_power_well_disable [i915]] disabling display
>[  924.101469] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.101519] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.101554] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.101713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.101811] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.101904] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.101930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.101955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.101981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.102001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.102023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.102045] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.102066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.102087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.102106] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.102125] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.102130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.102147] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.102152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.102170] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.102188] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.102207] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.102224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.102251] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.102279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.102302] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.102320] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.102338] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.102359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.102383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.102443] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.102462] [drm:intel_power_well_enable [i915]] enabling display
>[  924.102480] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.102514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.102534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.102553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.102571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.102589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.102608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.102635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.102662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.102690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.102715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.102742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.102799] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.102829] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.104904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.104925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.104944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.104963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.106528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.106549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.106566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.108128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.108149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.110020] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.113271] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.113337] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.113357] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.113387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.130132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.130183] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.130250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.130469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.130548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.146808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.146856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.146925] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.165322] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.165359] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.165398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.165431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.165466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.165495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.165523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.165554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.165588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.165621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.165659] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.165711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.165741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.165855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.165938] [drm:intel_power_well_disable [i915]] disabling display
>[  924.166001] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.166064] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.166113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.166266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.166285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.166371] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.166400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.166433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.166476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.166503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.166532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.166560] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.166587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.166613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.166651] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.166678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.166685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.166712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.166718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.166765] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.166821] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.166851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.166879] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.166910] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.166939] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.166966] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.166995] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.167021] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.167054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.167090] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.167181] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.167211] [drm:intel_power_well_enable [i915]] enabling display
>[  924.167240] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.167291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.167321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.167348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.167376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.167402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.167431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.167463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.167496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.167528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.167554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.167582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.167612] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.167642] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.169694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.169715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.169734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.169796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.171367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.171388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.171405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.172967] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.172988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.174865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.178214] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.178301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.178333] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.178381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.195072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.195122] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.195186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.195402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.195477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.211753] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.211844] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.211913] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.228938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.228981] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.229039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.229082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.229118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.229149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.229187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.229226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.229270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.229313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.229354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.229401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.229422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.229440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.229473] [drm:intel_power_well_disable [i915]] disabling display
>[  924.229498] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.229525] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.229543] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.229638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.229649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.229700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.229719] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.229806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.229841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.229870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.229901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.229930] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.229959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.229988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.230015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.230042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.230051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.230076] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.230084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.230111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.230137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.230164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.230192] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.230224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.230250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.230278] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.230304] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.230333] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.230360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.230387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.230449] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.230472] [drm:intel_power_well_enable [i915]] enabling display
>[  924.230494] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.230533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.230560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.230586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.230612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.230639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.230665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.230692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.230720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.230775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.230806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.230835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.230869] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.230898] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.232963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.232984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.233002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.233021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.234580] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.234601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.234619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.236171] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.236191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.238053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.241381] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.241437] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.241470] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.241522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.258210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.258259] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.258323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.258574] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.258651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.274892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.274938] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.275008] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.292040] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.292078] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.292117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.292150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.292185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.292216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.292245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.292276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.292310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.292342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.292373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.292404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.292448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.292486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.292540] [drm:intel_power_well_disable [i915]] disabling display
>[  924.292580] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.292622] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.292661] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.292880] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.292902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.292975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.293003] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.293033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.293071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.293104] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.293140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.293174] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.293208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.293243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.293277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.293311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.293318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.293351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.293357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.293391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.293425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.293459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.293492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.293527] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.293560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.293595] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.293628] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.293671] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.293700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.293727] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.293844] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.293875] [drm:intel_power_well_enable [i915]] enabling display
>[  924.293904] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.293962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.293998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.294032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.294066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.294098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.294133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.294170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.294206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.294243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.294274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.294305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.294342] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.294367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.296413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.296434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.296452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.296471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.298043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.298063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.298081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.299642] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.299663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.301533] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.304873] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.304962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.304984] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.305023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.321747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.321833] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.321900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.322115] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.322194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.338423] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.338472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.338541] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.355572] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.355609] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.355648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.355682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.355716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.355834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.355879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.355912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.355947] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.355998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.356028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.356055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.356081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.356105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.356150] [drm:intel_power_well_disable [i915]] disabling display
>[  924.356185] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.356221] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.356248] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.356365] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.356381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.356452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.356486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.356521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.356560] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.356592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.356628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.356662] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.356696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.356731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.356819] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.356860] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.356872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.356909] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.356919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.356956] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.356992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.357034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.357060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.357091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.357118] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.357145] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.357171] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.357197] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.357227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.357260] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.357351] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.357382] [drm:intel_power_well_enable [i915]] enabling display
>[  924.357413] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.357466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.357498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.357529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.357559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.357588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.357620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.357654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.357686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.357708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.357726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.357778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.357811] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.357840] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.359902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.359926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.359948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.359989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.361561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.361584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.361606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.363170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.363191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.365062] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.368300] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.368382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.368412] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.368438] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.385176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.385228] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.385295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.385498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.385577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.401852] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.401903] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.401978] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.418999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.419036] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.419076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.419109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.419143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.419174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.419203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.419241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.419285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.419328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.419370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.419412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.419451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.419490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.419546] [drm:intel_power_well_disable [i915]] disabling display
>[  924.419592] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.419641] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.419677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.420197] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.420216] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.420305] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.420329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.420353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.420379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.420400] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.420422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.420444] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.420464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.420485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.420504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.420523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.420528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.420552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.420557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.420583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.420609] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.420635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.420660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.420687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.420712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.420766] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.420797] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.420826] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.420858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.420891] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.421148] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.421168] [drm:intel_power_well_enable [i915]] enabling display
>[  924.421186] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.421223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.421244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.421265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.421290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.421320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.421345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.421367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.421389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.421410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.421428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.421447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.421469] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.421490] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.423535] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.423556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.423574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.423593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.425162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.425183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.425206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.426775] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.426796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.428666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.432025] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.432100] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.432132] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.432174] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.448853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.448905] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.448976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.449192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.449272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.465556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.465606] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.465700] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.482797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.482834] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.482874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.482908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.482943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.482974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.483003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.483041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.483086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.483128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.483169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.483211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.483250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.483289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.483346] [drm:intel_power_well_disable [i915]] disabling display
>[  924.483391] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.483442] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.483477] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.483630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.483642] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.483695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.483716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.483792] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.483829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.483858] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.483889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.483920] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.483949] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.483978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.484006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.484032] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.484041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.484067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.484075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.484102] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.484129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.484156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.484182] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.484212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.484238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.484265] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.484295] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.484323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.484354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.484386] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.484477] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.484509] [drm:intel_power_well_enable [i915]] enabling display
>[  924.484540] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.484594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.484626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.484658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.484689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.484718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.484772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.484805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.484835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.484866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.484896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.484923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.484957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.484989] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.487052] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.487073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.487091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.487110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.488668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.488689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.488707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.490308] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.490329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.492219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.495539] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.495602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.495635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.495677] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.512372] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.512421] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.512486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.512704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.513054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.529054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.529098] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.529167] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.546202] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.546239] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.546278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.546312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.546347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.546377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.546407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.546438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.546472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.546505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.546536] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.546567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.546594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.546621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.546674] [drm:intel_power_well_disable [i915]] disabling display
>[  924.546714] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.546825] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.546872] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.547040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.547051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.547107] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.547128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.547151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.547180] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.547205] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.547232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.547258] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.547284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.547310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.547336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.547362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.547368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.547393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.547398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.547423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.547449] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.547475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.547500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.547527] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.547552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.547578] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.547604] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.547630] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.547657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.547685] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.547780] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.547807] [drm:intel_power_well_enable [i915]] enabling display
>[  924.547835] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.547889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.547921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.547949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.547981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.548011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.548040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.548074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.548107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.548140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.548168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.548197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.548231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.548263] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.550330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.550351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.550369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.550388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.551965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.551986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.552004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.553553] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.553575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.555448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.558795] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.558893] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.558927] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.558969] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.575662] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.575717] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.575898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.576151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.576229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.592338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.592390] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.592463] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.609492] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.609529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.609569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.609603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.609639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.609669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.609698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.609730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.609853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.609901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.609953] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.610004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.610050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.610097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.610181] [drm:intel_power_well_disable [i915]] disabling display
>[  924.610240] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.610269] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.610289] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.610390] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.610402] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.610457] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.610478] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.610500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.610533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.610561] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.610584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.610605] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.610631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.610657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.610683] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.610708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.610741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.610772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.610779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.610810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.610839] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.610867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.610893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.610924] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.610951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.610979] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.611005] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.611031] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.611062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.611094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.611185] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.611216] [drm:intel_power_well_enable [i915]] enabling display
>[  924.611246] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.611300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.611332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.611363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.611393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.611423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.611454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.611477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.611497] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.611519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.611537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.611563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.611591] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.611617] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.613670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.613691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.613710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.613780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.615349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.615370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.615388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.616954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.616975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.618835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.622130] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.622238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.622272] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.622315] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.638999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.639051] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.639123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.639360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.639437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.655674] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.655722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.655890] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.672882] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.672920] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.672960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.672993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.673027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.673057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.673086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.673117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.673152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.673184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.673215] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.673246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.673274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.673301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.673353] [drm:intel_power_well_disable [i915]] disabling display
>[  924.673393] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.673435] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.673465] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.673625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.673640] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.673708] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.673797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.673841] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.673885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.673920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.673958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.673995] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.674031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.674066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.674101] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.674133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.674144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.674176] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.674185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.674221] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.674257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.674293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.674326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.674362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.674395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.674428] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.674464] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.674491] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.674518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.674547] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.674627] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.674646] [drm:intel_power_well_enable [i915]] enabling display
>[  924.674664] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.674701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.674751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.674781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.674809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.674837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.674867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.674900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.674933] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.674964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.674992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.675021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.675053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.675085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.677117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.677149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.677170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.677189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.678771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.678791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.678814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.680382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.680406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.682273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.685566] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.685655] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.685687] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.685805] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.702428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.702477] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.702541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.702988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.703067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.719113] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.719161] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.719231] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.736253] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.736290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.736330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.736363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.736398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.736429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.736468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.736507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.736552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.736594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.736636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.736678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.736717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.736836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.736918] [drm:intel_power_well_disable [i915]] disabling display
>[  924.736991] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.737034] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.737065] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.737223] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.737242] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.737337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.737364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.737395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.737428] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.737454] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.737484] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.737511] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.737539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.737567] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.737593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.737617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.737623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.737648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.737654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.737680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.737704] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.737770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.737803] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.737832] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.737862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.737889] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.737918] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.737944] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.737975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.738011] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.738100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.738130] [drm:intel_power_well_enable [i915]] enabling display
>[  924.738160] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.738210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.738250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.738277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.738306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.738331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.738361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.738393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.738425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.738456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.738482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.738510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.738540] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.738570] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.740671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.740693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.740712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.740793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.742356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.742379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.742407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.743974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.743997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.745863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.749203] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.749282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.749301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.749327] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.766070] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.766120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.766184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.766386] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.766461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.782790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.782836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.782904] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.799924] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.799960] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.799999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.800040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.800083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.800123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.800162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.800201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.800246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.800288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.800329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.800371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.800392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.800410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.800442] [drm:intel_power_well_disable [i915]] disabling display
>[  924.800467] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.800494] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.800512] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.800604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.800615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.800666] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.800685] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.800706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.800797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.800826] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.800861] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.800892] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.800924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.800952] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.800983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.801009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.801018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.801045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.801053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.801083] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.801110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.801139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.801165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.801197] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.801224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.801253] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.801282] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.801309] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.801341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.801377] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.801466] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.801496] [drm:intel_power_well_enable [i915]] enabling display
>[  924.801525] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.801576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.801606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.801634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.801662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.801688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.801718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.801773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.801807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.801840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.801868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.801897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.801928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.801958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.804036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.804058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.804077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.804097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.805664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.805688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.805717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.807321] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.807345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.809237] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.812557] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.812623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.812642] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.812668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.829399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.829449] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.829516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.829967] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.830049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.846075] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.846123] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.846193] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.864669] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.864707] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.864837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.864897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.864954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.865002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.865049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.865098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.865156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.865208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.865259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.865310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.865355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.865400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.865483] [drm:intel_power_well_disable [i915]] disabling display
>[  924.865548] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.865610] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.865659] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.865879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.865905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.865989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.866020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.866047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.866070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.866089] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.866109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.866129] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.866148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.866166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.866183] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.866199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.866204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.866220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.866224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.866240] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.866257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.866273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.866289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.866308] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.866325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.866342] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.866358] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.866374] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.866393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.866414] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.866470] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.866487] [drm:intel_power_well_enable [i915]] enabling display
>[  924.866503] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.866535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.866553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.866570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.866587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.866603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.866621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.866640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.866658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.866676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.866693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.866709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.866780] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.866812] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.868875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.868898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.868927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.868946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.870514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.870534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.870552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.872103] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.872124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.873991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.877288] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.877372] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.877401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.877439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.894155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.894207] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.894273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.894487] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.894566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.910831] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.910880] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.910949] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.927982] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.928019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.928058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.928092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.928126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.928156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.928185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.928217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.928251] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.928283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.928323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.928365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.928404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.928443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.928501] [drm:intel_power_well_disable [i915]] disabling display
>[  924.928546] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.928597] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.928633] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.928930] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.928959] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.929079] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.929114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.929149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.929186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.929218] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.929252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.929286] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.929318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.929349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.929379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.929409] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.929416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.929444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.929451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.929480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.929510] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.929539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.929568] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.929601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.929630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.929658] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.929687] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.929717] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.929773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.929808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.929901] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.929932] [drm:intel_power_well_enable [i915]] enabling display
>[  924.929962] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.930014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.930045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.930076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.930107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.930134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.930165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.930199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.930231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.930263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.930293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.930322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.930355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.930387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.932461] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.932484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.932503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.932522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.934113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.934135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.934154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.935715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.935753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  924.937615] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  924.940965] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  924.941050] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  924.941083] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  924.941125] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  924.957824] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.957875] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.957942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.958141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.958248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.974507] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  924.974556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  924.974626] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  924.991651] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  924.991689] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  924.991825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.992012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.992058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.992107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.992138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.992176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  924.992222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.992243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.992262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.992281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.992298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.992314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.992346] [drm:intel_power_well_disable [i915]] disabling display
>[  924.992371] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  924.992396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  924.992414] [drm:intel_power_well_disable [i915]] disabling always-on
>[  924.992500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  924.992511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  924.992562] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  924.992581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  924.992602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  924.992624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  924.992642] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  924.992661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  924.992684] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  924.992708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  924.992781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  924.992812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  924.992844] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  924.992853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.992882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  924.992890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  924.992921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  924.992951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  924.992982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  924.993012] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  924.993046] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  924.993075] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  924.993106] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  924.993136] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  924.993167] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  924.993202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  924.993237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  924.993608] [drm:intel_power_well_enable [i915]] enabling always-on
>[  924.993639] [drm:intel_power_well_enable [i915]] enabling display
>[  924.993669] [drm:hsw_set_power_well [i915]] Enabling power well
>[  924.993746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  924.993781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  924.993812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  924.993845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  924.993876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  924.994044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  924.994077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  924.994107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  924.994138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  924.994175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  924.994213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  924.994245] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  924.994274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  924.996349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  924.996370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  924.996389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.996408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  924.997985] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  924.998006] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  924.998024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  924.999580] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  924.999602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.001464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.004788] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.004843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.004872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.004910] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.021637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.021688] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.021867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.022116] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.022193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.038282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.038327] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.038393] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.055439] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.055476] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.055516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.055550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.055584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.055614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.055643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.055681] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.055806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.055866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.055920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.055973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.056318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.056366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.056449] [drm:intel_power_well_disable [i915]] disabling display
>[  925.056513] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.056565] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.056595] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.056750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.056762] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.056843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.056877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.056912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.056945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.056966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.056989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.057011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.057031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.057051] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.057069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.057087] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.057092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.057109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.057113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.057131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.057149] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.057166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.057183] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.057204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.057222] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.057239] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.057257] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.057274] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.057296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.057318] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.057378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.057396] [drm:intel_power_well_enable [i915]] enabling display
>[  925.057415] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.057449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.057468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.057487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.057505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.057523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.057542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.057566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.057593] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.057621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.057646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.057671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.057698] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.057759] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.059831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.059853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.059872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.059891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.061450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.061475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.061503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.063051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.063073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.064942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.068262] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.068325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.068358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.068401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.085105] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.085157] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.085223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.085440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.085519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.101805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.101853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.101921] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.118935] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.118972] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.119012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.119046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.119080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.119110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.119139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.119170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.119204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.119236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.119267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.119298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.119335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.119374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.119431] [drm:intel_power_well_disable [i915]] disabling display
>[  925.119477] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.119527] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.119562] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.119807] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.119836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.119978] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.120012] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.120047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.120084] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.120115] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.120148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.120181] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.120213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.120244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.120274] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.120304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.120311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.120339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.120346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.120376] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.120405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.120435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.120464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.120496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.120525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.120554] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.120584] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.120614] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.120644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.120679] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.120792] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.120823] [drm:intel_power_well_enable [i915]] enabling display
>[  925.120854] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.120906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.120938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.120969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.120999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.121026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.121056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.121090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.121123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.121156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.121185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.121214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.121248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.121279] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.123344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.123365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.123383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.123401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.124965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.124988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.125011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.126563] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.126586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.128459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.131782] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.131841] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.131874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.131924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.148620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.148672] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.148832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.149133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.149222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.165320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.165367] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.165434] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.182459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.182496] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.182536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.182570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.182605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.182636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.182664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.182696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.182823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.182878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.182931] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.182982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.183271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.183318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.183401] [drm:intel_power_well_disable [i915]] disabling display
>[  925.183455] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.183492] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.183522] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.183634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.183646] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.183698] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.183773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.183811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.183851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.183883] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.183918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.183952] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.183985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.184185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.184206] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.184225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.184230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.184249] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.184253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.184272] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.184290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.184308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.184326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.184348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.184366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.184384] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.184402] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.184419] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.184440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.184463] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.184522] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.184541] [drm:intel_power_well_enable [i915]] enabling display
>[  925.184558] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.184592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.184613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.184632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.184650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.184668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.184688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.184752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.184784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.184818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.184848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.184878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.184915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.184947] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.187299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.187320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.187341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.187365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.188944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.188965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.188984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.190543] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.190564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.192437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.195724] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.195805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.195825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.195851] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.212598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.212652] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.212805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.213096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.213186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.229297] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.229344] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.229411] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.247575] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.247613] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.247656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.247696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.247830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.247882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.247937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.248157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.248214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.248266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.248316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.248366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.248411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.248457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.248539] [drm:intel_power_well_disable [i915]] disabling display
>[  925.248582] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.248625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.248656] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.248994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.249006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.249061] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.249086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.249110] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.249137] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.249160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.249184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.249211] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.249243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.249266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.249284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.249301] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.249305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.249322] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.249326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.249343] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.249360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.249376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.249392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.249411] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.249427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.249443] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.249459] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.249475] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.249495] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.249516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.249570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.249588] [drm:intel_power_well_enable [i915]] enabling display
>[  925.249604] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.249639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.249662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.249686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.249759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.249791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.249826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.249862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.249895] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.249929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.249959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.249991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.250027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.250060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.252443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.252464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.252483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.252501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.254065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.254086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.254104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.255690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.255722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.257592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.260897] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.260979] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.261006] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.261043] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.277756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.277811] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.277884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.278133] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.278232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.294456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.294502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.294572] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.311580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.311617] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.311657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.311690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.311812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.311863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.311910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.311960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.312018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.312061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.312095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.312136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.312155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.312172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.312208] [drm:intel_power_well_disable [i915]] disabling display
>[  925.312235] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.312263] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.312283] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.312384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.312397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.312451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.312471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.312493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.312518] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.312537] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.312563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.312590] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.312617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.312651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.312682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.312733] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.312743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.312770] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.312778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.312806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.312833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.312860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.312886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.312917] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.312943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.312970] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.312997] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.313023] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.313054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.313087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.313178] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.313209] [drm:intel_power_well_enable [i915]] enabling display
>[  925.313239] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.313292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.313324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.313354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.313384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.313414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.313446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.313473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.313495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.313515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.313533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.313551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.313573] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.313594] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.315640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.315661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.315679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.315745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.317400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.317420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.317442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.318993] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.319014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.320884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.324206] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.324267] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.324300] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.324350] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.341048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.341099] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.341165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.341414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.341504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.357790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.357836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.357905] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.374912] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.374949] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.374988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.375022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.375058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.375088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.375117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.375149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.375191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.375234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.375275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.375317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.375356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.375395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.375452] [drm:intel_power_well_disable [i915]] disabling display
>[  925.375494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.375523] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.375542] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.375628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.375639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.375691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.375776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.375809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.375845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.375873] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.375904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.375933] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.375965] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.375993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.376020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.376047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.376056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.376082] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.376089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.376118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.376147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.376174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.376200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.376233] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.376263] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.376283] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.376301] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.376319] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.376340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.376363] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.376425] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.376443] [drm:intel_power_well_enable [i915]] enabling display
>[  925.376461] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.376495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.376515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.376534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.376553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.376571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.376591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.376612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.376632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.376652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.376670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.376694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.376748] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.376777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.378845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.378866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.378885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.378904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.380473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.380493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.380511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.382072] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.382092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.383963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.387283] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.387345] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.387377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.387419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.404125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.404176] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.404243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.404464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.404564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.420826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.420873] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.420940] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.437945] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.437987] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.438032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.438072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.438117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.438156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.438196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.438235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.438279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.438321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.438363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.438404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.438443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.438481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.438538] [drm:intel_power_well_disable [i915]] disabling display
>[  925.438583] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.438633] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.438668] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.439114] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.439127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.439186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.439209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.439233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.439257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.439277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.439300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.439322] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.439347] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.439374] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.439400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.439426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.439431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.439456] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.439461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.439487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.439512] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.439538] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.439565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.439601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.439631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.439653] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.439673] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.439723] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.439754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.439787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.439878] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.440079] [drm:intel_power_well_enable [i915]] enabling display
>[  925.440098] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.440135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.440157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.440176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.440201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.440228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.440254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.440282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.440311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.440338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.440363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.440388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.440416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.440441] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.442482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.442504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.442523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.442542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.444115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.444135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.444153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.445765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.445786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.447677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.451008] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.451071] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.451103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.451144] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.467851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.467903] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.467970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.468213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.468305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.484553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.484600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.484668] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.501799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.501837] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.501876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.501909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.501944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.501974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.502013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.502052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.502096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.502139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.502181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.502223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.502262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.502300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.502333] [drm:intel_power_well_disable [i915]] disabling display
>[  925.502358] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.502386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.502405] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.502504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.502515] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.502571] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.502595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.502619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.502646] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.502669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.502744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.502779] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.502814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.502847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.502879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.502908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.502918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.502947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.502955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.502986] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.503016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.503047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.503076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.503110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.503140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.503171] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.503201] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.503231] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.503266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.503300] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.503392] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.503423] [drm:intel_power_well_enable [i915]] enabling display
>[  925.503453] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.503504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.503536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.503566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.503596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.503624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.503655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.503689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.503747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.503781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.503811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.503841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.503877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.503909] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.505976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.505997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.506019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.506044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.507615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.507639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.507662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.509261] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.509283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.511157] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.513796] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.513881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.513911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.513948] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.530663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.530796] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.530997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.531243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.531333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.547360] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.547407] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.547474] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.565645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.565688] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.565822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.566010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.566048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.566080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.566110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.566143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.566190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.566243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.566276] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.566307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.566336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.566363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.566414] [drm:intel_power_well_disable [i915]] disabling display
>[  925.566455] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.566496] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.566527] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.566664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.566722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.567023] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.567054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.567086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.567120] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.567149] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.567180] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.567210] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.567239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.567269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.567297] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.567324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.567331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.567357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.567364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.567392] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.567419] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.567446] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.567472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.567500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.567527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.567555] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.567582] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.567610] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.567640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.567672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.567796] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.567829] [drm:intel_power_well_enable [i915]] enabling display
>[  925.568095] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.568147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.568179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.568210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.568241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.568271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.568300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.568334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.568367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.568399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.568428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.568457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.568491] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.568522] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.570586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.570607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.570626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.570645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.572256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.572276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.572294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.573882] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.573905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.575821] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.579074] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.579139] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.579159] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.579184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.595935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.595986] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.596053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.596273] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.596375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.612633] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.612681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.612856] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.629863] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.629901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.629941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.629975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.630010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.630040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.630069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.630101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.630136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.630167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.630198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.630229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.630256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.630283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.630336] [drm:intel_power_well_disable [i915]] disabling display
>[  925.630376] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.630418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.630449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.630600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.630619] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.630785] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.630833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.630889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.630950] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.630999] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.631052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.631103] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.631150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.631181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.631212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.631242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.631251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.631280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.631288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.631318] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.631348] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.631380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.631408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.631442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.631472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.631502] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.631531] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.631560] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.631592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.631626] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.631739] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.631770] [drm:intel_power_well_enable [i915]] enabling display
>[  925.631801] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.631852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.631883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.631914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.631945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.631974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.632005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.632039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.632071] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.632104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.632134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.632164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.632198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.632229] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.634478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.634500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.634518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.634537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.636110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.636131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.636149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.637799] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.637822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.639675] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.642984] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.643069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.643101] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.643142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.659848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.659899] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.659966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.660208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.660301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.676546] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.676593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.676660] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.693782] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.693824] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.693869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.693909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.693953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.693992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.694032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.694071] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.694115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.694158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.694200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.694242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.694280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.694319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.694376] [drm:intel_power_well_disable [i915]] disabling display
>[  925.694421] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.694471] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.694508] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.694604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.694615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.694669] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.694743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.694778] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.694819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.694851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.694886] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.694920] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.694954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.694987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.695018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.695050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.695059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.695088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.695096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.695126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.695157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.695188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.695218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.695252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.695283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.695618] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.695649] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.695679] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.695734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.695771] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.695963] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.695992] [drm:intel_power_well_enable [i915]] enabling display
>[  925.696020] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.696069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.696099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.696128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.696156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.696184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.696213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.696245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.696275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.696305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.696332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.696358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.696389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.696419] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.698504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.698525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.698544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.698562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.700137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.700157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.700175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.701798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.701819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.703682] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.706906] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.706957] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.706977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.707003] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.723756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.723808] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.723874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.724123] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.724215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.740455] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.740502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.740571] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.757592] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.757635] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.757680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.757807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.757866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.757916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.757964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.758014] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.758072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.758125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.758176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.758229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.758275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.758320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.758404] [drm:intel_power_well_disable [i915]] disabling display
>[  925.758468] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.758530] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.758580] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.758786] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.758798] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.758856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.758878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.758901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.758926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.758953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.758973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.758993] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.759012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.759029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.759046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.759063] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.759067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.759084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.759087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.759104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.759120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.759136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.759152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.759172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.759189] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.759206] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.759222] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.759245] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.759270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.759295] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.759353] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.759373] [drm:intel_power_well_enable [i915]] enabling display
>[  925.759393] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.759429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.759452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.759476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.759500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.759523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.759546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.759571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.759596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.759621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.759644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.759667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.759741] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.759773] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.761848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.761869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.761888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.761907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.763477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.763498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.763516] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.765076] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.765097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.766971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.770264] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.770354] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.770386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.770428] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.787134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.787185] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.787252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.787473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.787575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.803833] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.803883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.803956] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.820964] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.821001] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.821041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.821074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.821117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.821157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.821197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.821235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.821280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.821322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.821364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.821405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.821444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.821483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.821538] [drm:intel_power_well_disable [i915]] disabling display
>[  925.821584] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.821633] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.821669] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.821939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.821958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.822045] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.822079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.822115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.822152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.822184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.822218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.822250] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.822282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.822314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.822344] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.822373] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.822381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.822408] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.822416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.822445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.822475] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.822504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.822534] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.822567] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.822597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.822626] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.822656] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.822710] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.822743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.822780] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.822872] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.822904] [drm:intel_power_well_enable [i915]] enabling display
>[  925.822934] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.822987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.823019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.823049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.823080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.823110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.823142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.823177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.823210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.823243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.823272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.823301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.823335] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.823367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.825431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.825454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.825475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.825496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.827064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.827084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.827102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.828658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.828690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.830558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.833890] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.833943] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.833977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.834019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.850753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.850807] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.850879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.851126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.851223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.867421] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.867468] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.867536] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.885656] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.885729] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.885769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.885809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.885853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.885893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.885933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.885972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.886016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.886058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.886100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.886142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.886181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.886219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.886271] [drm:intel_power_well_disable [i915]] disabling display
>[  925.886296] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.886325] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.886344] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.886439] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.886451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.886504] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.886523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.886544] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.886567] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.886585] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.886605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.886624] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.886643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.886661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.886733] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.886763] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.886774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.886804] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.886815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.886846] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.886877] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.886908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.886938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.886972] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.887002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.887033] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.887063] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.887094] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.887129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.887164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.887255] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.887286] [drm:intel_power_well_enable [i915]] enabling display
>[  925.887317] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.887368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.887400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.887431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.887460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.887490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.887520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.887554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.887587] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.887620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.887650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.887703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.887736] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.887769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.889840] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.889860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.889883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.889907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.891481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.891502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.891521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.893074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.893096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.894966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.898292] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.898349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.898381] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.898423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.915130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.915182] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.915248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.915495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.915586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.931829] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.931876] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.931946] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  925.948956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  925.948994] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  925.949034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.949074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.949118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.949157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.949197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.949236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.949280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.949322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.949364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.949406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.949445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.949484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.949539] [drm:intel_power_well_disable [i915]] disabling display
>[  925.949565] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  925.949593] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.949612] [drm:intel_power_well_disable [i915]] disabling always-on
>[  925.950016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.950043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  925.950141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  925.950173] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  925.950215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  925.950250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  925.950279] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  925.950310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  925.950341] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  925.950370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  925.950400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  925.950428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  925.950455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  925.950462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.950489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  925.950495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  925.950522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  925.950550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  925.950577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  925.950603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  925.950631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  925.950657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  925.950726] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  925.950755] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  925.950786] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  925.950821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.950857] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  925.951151] [drm:intel_power_well_enable [i915]] enabling always-on
>[  925.951181] [drm:intel_power_well_enable [i915]] enabling display
>[  925.951211] [drm:hsw_set_power_well [i915]] Enabling power well
>[  925.951264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  925.951296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  925.951327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  925.951358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  925.951387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  925.951418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  925.951452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  925.951485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  925.951517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.951547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  925.951576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  925.951610] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  925.951641] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  925.953899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  925.953920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  925.953938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.953958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  925.955528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  925.955549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  925.955567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  925.957128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  925.957149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  925.959018] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  925.961815] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  925.961880] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  925.961900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  925.961925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  925.978685] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  925.978773] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  925.978845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  925.979039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  925.979120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  925.995379] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  925.995427] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  925.995500] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  926.012513] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  926.012550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.012589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.012622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.012657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.012776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.012818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.012852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.012889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.012923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.012955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.012986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.013025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.013065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.013123] [drm:intel_power_well_disable [i915]] disabling display
>[  926.013169] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.013219] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  926.013255] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.013402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  926.013426] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  926.013568] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.013610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.013652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.013755] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.013785] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.013819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.013850] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  926.013881] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  926.013909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.013937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.013963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.013971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.013997] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.014005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.014032] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.014059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.014086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.014116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.014148] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.014175] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.014205] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  926.014225] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  926.014243] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  926.014265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.014290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  926.014352] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.014370] [drm:intel_power_well_enable [i915]] enabling display
>[  926.014389] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.014423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.014443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.014462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.014480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.014505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.014531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.014560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.014588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.014616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.014642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.014670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.014727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  926.014758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.016827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.016848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.016867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.016886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.018459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.018479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.018501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.020057] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.020078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.021954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.025233] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  926.025281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.025309] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  926.025346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.042074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.042126] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  926.042193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.042415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  926.042494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.058765] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  926.058814] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.058888] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  926.076502] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  926.076540] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.076579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.076612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.076646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.076763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.076810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.076858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.076895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.076928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.076959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.076990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.077018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.077046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.077101] [drm:intel_power_well_disable [i915]] disabling display
>[  926.077128] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.077156] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  926.077176] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.077281] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  926.077293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  926.077348] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.077374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.077401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.077430] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.077455] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.077482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.077508] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  926.077534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  926.077560] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.077587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.077611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.077618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.077642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.077673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.077708] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.077740] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.077769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.077799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  926.077830] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.077860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.077887] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  926.077914] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  926.077941] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  926.077974] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.078006] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  926.078082] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.078111] [drm:intel_power_well_enable [i915]] enabling display
>[  926.078142] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.078180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.078201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.078220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.078238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.078256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.078281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.078309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.078336] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.078363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.078389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.078415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.078443] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  926.078469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.080508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.080531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.080554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.080578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.082150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.082171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.082189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.083784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.083805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.085701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.088445] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  926.088513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.088532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  926.088558] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.105306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.105359] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  926.105425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.105890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  926.105993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.122004] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  926.122052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.122139] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  926.140286] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  926.140324] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.140363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.140397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.140431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.140470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.140510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.140549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.140593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.140635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.140677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.140802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.140850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.140900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.140981] [drm:intel_power_well_disable [i915]] disabling display
>[  926.141044] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.141107] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  926.141156] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.143702] [IGT] kms_flip: exiting, ret=0
>[  926.163647] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.163713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.163756] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.163795] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.163829] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.163855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.163880] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.163910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.163929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.163947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.163964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.163969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.163986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.163989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.164007] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.164028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.164051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.164074] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.164099] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.164122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.164146] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  926.164170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.164193] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.164219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.164246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.164313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.164334] [drm:intel_power_well_enable [i915]] enabling display
>[  926.164354] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.164393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.164417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.164441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.164465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.164489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.164512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.164538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.164563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.164588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.164611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.164634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.164659] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  926.164716] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.166788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.166808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.166826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.166844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.168417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.168434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.168451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.170011] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.170030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.171903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.175087] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  926.175168] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.175187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  926.175218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.175280] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  926.175307] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  926.191974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.192022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.192092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.192336] Console: switching to colour frame buffer device 240x75
>[  926.300584] Console: switching to colour dummy device 80x25
>[  926.300786] [IGT] kms_flip: executing
>[  926.312518] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  926.312570] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  926.314722] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  926.314759] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  926.316872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  926.316884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  926.318985] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  926.319025] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  926.321139] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  926.321150] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  926.321158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  926.321188] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  926.321231] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  926.322328] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  926.323253] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  926.323275] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  926.323294] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  926.323312] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  926.324334] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  926.324355] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  926.325486] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  926.325490] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  926.325591] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  926.325594] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  926.325599] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  926.325601] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  926.325606] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  926.325608] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  926.325617] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  926.325621] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.325624] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  926.325627] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  926.325630] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  926.325633] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  926.325636] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  926.325691] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  926.325698] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  926.325705] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  926.325712] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  926.325720] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  926.325727] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  926.325734] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  926.325741] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  926.325747] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  926.325753] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  926.325759] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  926.325765] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  926.325770] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  926.325776] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  926.325782] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  926.325788] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  926.325794] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  926.325800] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  926.325808] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  926.325815] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  926.325822] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  926.325829] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  926.325836] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  926.325842] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  926.325913] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  926.325948] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  926.327747] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  926.327786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  926.329748] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  926.329759] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  926.331733] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  926.331769] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  926.333884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  926.333895] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  926.333903] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  926.334317] [IGT] kms_flip: starting subtest dpms-vs-vblank-race
>[  926.335313] [drm:drm_mode_addfb2] [FB:58]
>[  926.335354] [drm:drm_mode_addfb2] [FB:79]
>[  926.400971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  926.401035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.408827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  926.408879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.408955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  926.427495] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  926.427539] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  926.427572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.427611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.427643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.427772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.427823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.427874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.427925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.427982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.428034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.428084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.428133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.428162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.428191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.428247] [drm:intel_power_well_disable [i915]] disabling display
>[  926.428289] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.428330] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.428365] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.428456] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  926.428558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  926.428631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  926.428690] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  926.428780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.428814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.428848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.428887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.428918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.428952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.428984] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.429016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.429047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.429079] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.429109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.429116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.429144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.429151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.429181] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.429210] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.429239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.429269] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.429299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.429328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.429358] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  926.429387] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.429416] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.429449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.429483] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.432956] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.432977] [drm:intel_power_well_enable [i915]] enabling display
>[  926.432996] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.433032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.433054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.433075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.433094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.433118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.433142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.433168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.433194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.433219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.433253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.433278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.433304] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  926.433328] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.435383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.435405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.435427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.435452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.437017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.437037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.437055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.438641] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.438681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.440551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.443899] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  926.443990] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.444030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  926.444081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.444166] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  926.444204] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  926.460752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.460799] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.460867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.477816] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.477855] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.477893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.477937] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.477976] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.478017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.478055] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.478095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.478135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.478174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.478212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.478221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.478259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.478266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.478306] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.478341] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.478381] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.478420] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.478459] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.478498] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.478539] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.478578] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.478617] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.478659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.478772] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.494133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  926.494180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.494284] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  926.511326] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  926.511370] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  926.511403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.511442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.511475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.511505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.511535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.511564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.511595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.511629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.511755] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.511810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.511858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.511907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.512196] [drm:intel_power_well_disable [i915]] disabling display
>[  926.512236] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.512268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.512301] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.512335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.512364] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.512517] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.512536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.512560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.512587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.512609] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.512633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.512708] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.512740] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.512774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.512805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.512835] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.512844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.512874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.512882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.512914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.512944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.512975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.513004] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.513039] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.513070] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.513357] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.513388] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.513418] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.513452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.513488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.513585] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.513606] [drm:intel_power_well_enable [i915]] enabling display
>[  926.513626] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.513716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.513749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.513883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.513902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.513925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.513949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.513974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.513999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.514024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.514047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.514070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.514095] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  926.514118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.516170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.516193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.516216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.516240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.517829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.517853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.517876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.519426] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.519448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.521310] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.524624] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  926.524746] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.524779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  926.524821] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.524899] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  926.524938] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  926.525026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.525074] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.525143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.575020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.575060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.575099] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.575140] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.575173] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.575210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.575251] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.575292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.575334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.575370] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.575411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.575418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.575459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.575466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.575507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.575549] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.575590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.575629] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.575730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.575790] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.575840] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.575890] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.575934] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.575987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.576043] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.591551] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  926.591600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.591757] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  926.608761] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  926.608809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  926.608850] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.608894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.608934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.608974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.609014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.609053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.609092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.609135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.609176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.609223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.609253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.609285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.609333] [drm:intel_power_well_disable [i915]] disabling display
>[  926.609372] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.609406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.609442] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.609480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.609508] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.610384] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.610406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.610428] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.610451] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.610474] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.610498] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.610522] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.610545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.610569] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.610592] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.610615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.610620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.610654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.610912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.610937] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.610960] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.610979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.610998] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.611020] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.611039] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.611059] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.611077] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.611095] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.611116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.611139] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.611199] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.611219] [drm:intel_power_well_enable [i915]] enabling display
>[  926.611236] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.611270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.611290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.611308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.611326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.611344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.611364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.611385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.611405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.611424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.611442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.611460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.611482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  926.611502] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.613546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.613568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.613587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.613606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.615216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.615238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.615257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.616822] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.616845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.618708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.622040] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  926.622093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.622132] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  926.622184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.622267] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  926.622306] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  926.622394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.622437] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.622491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.672348] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.672386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.672423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.672462] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.672493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.672526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.672560] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.672591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.672630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.672727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.672773] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.672787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.672829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.672841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.672885] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.672928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.672969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.673015] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.673347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.673381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.673413] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.673443] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.673472] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.673507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.673548] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.688934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  926.689002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.689107] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  926.707593] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  926.707638] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  926.707758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.707825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.707878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.707928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.707965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.707996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.708028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.708064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.708096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.708138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.708178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.708219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.708277] [drm:intel_power_well_disable [i915]] disabling display
>[  926.708323] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.708365] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.708409] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.708456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.708478] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.708870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.708894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.708919] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.708947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.708972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.708998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.709024] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.709050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.709075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.709097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.709122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.709127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.709152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.709156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.709182] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.709205] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.709230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.709255] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.709281] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.709305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.709331] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.709356] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.709381] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.709408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.709435] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.709495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.709518] [drm:intel_power_well_enable [i915]] enabling display
>[  926.709540] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.709578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.709604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.709630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.709688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.709719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.709749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.709782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.709813] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.709843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.709869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.709896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.709930] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  926.709958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.712010] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.712034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.712057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.712080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.713633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.713670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.713698] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.715254] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.715276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.717177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.720464] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  926.720561] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.720597] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  926.720623] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.720743] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  926.720773] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  926.720851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.720890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.720951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.770811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.770851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.770891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.770932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.770966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.771001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.771037] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.771070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.771104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.771135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.771166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.771173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.771203] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.771210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.771241] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.771270] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.771305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.771346] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.771387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.771428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.771470] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.771511] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.771552] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.771595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.771639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.787369] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  926.787422] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.787497] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  926.804522] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  926.804566] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  926.804606] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.804650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.804776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.804833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.804884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.804935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.804986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.805210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.805246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.805286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.805326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.805365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.805421] [drm:intel_power_well_disable [i915]] disabling display
>[  926.805467] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.805508] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.805550] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.805595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.805628] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.806241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.806263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.806285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.806308] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.806327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.806347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.806367] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.806386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.806404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.806421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.806437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.806442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.806458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.806461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.806478] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.806494] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.806511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.806526] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.806546] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.806562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.806580] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.806596] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.806612] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.806682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.806717] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.806807] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.807049] [drm:intel_power_well_enable [i915]] enabling display
>[  926.807080] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.807131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.807164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.807197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.807227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.807258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.807290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.807324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.807357] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.807389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.807418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.807444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.807478] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  926.807509] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.809573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.809599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.809623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.809704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.811271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.811292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.811311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.812870] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.812890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.814750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.818051] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  926.818115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.818134] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  926.818159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.818219] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  926.818240] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  926.818293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.818320] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.818368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.868392] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.868435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.868478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.868525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.868566] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.868608] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.868648] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.868768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.868818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.868867] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.868914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.868927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.868972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.868983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.869027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.869073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.869115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.869158] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.869204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.869247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.869290] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.869334] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.869373] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.869423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.869467] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.885025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  926.885101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.885217] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  926.902270] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  926.902314] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  926.902346] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.902385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.902418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.902449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.902478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.902507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.902538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.902572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.902604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.902644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.902758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.902813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.902901] [drm:intel_power_well_disable [i915]] disabling display
>[  926.903228] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  926.903261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.903295] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.903329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.903358] [drm:intel_power_well_disable [i915]] disabling always-on
>[  926.903785] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.903811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.903835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.903860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.903879] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.903901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.903924] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.903944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.903964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.903982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.904006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.904012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.904037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.904042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.904067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.904091] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.904116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.904140] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.904165] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.904190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.904217] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.904242] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.904267] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.904294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.904321] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.904383] [drm:intel_power_well_enable [i915]] enabling always-on
>[  926.904405] [drm:intel_power_well_enable [i915]] enabling display
>[  926.904427] [drm:hsw_set_power_well [i915]] Enabling power well
>[  926.904465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.904491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.904517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.904542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.904568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  926.904593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  926.904620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  926.904688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  926.904723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.904755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  926.904788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  926.904825] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  926.904858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  926.906931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  926.906952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  926.906974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.906998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  926.908550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  926.908573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  926.908593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  926.910164] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  926.910185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  926.912084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  926.915432] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  926.915504] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  926.915523] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  926.915549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  926.915607] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  926.915648] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  926.915783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  926.915823] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  926.915864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  926.965762] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  926.965802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  926.965842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  926.965885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  926.965926] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  926.965968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  926.966008] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  926.966049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  926.966090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  926.966126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  926.966165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  926.966173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.966213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  926.966220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  926.966262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  926.966302] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  926.966343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  926.966383] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  926.966424] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  926.966464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  926.966506] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  926.966547] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  926.966588] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  926.966631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  926.966729] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  926.982327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  926.982375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  926.982463] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  926.999476] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  926.999520] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  926.999552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  926.999590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  926.999623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  926.999737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  926.999941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  926.999972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.000006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.000043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.000076] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.000109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.000137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.000167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.000219] [drm:intel_power_well_disable [i915]] disabling display
>[  927.000260] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.000291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.000325] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.000359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.000388] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.000829] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.000864] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.000887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.000910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.000928] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.000948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.000968] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.000986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.001004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.001021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.001043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.001048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.001071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.001076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.001099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.001122] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.001146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.001168] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.001191] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.001214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.001239] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.001262] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.001285] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.001310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.001335] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.001392] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.001412] [drm:intel_power_well_enable [i915]] enabling display
>[  927.001432] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.001467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.001491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.001515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.001538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.001561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.001584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.001610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.001688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.001721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.001755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.001784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.001819] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.001849] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.003914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.003935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.003953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.003972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.005538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.005561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.005584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.007176] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.007198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.009182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.012474] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.012570] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.012609] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.012727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.012882] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.012904] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.012968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.012997] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.013039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.062831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.062871] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.062910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.062952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.062986] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.063022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.063058] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.063092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.063125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.063156] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.063187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.063195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.063224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.063230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.063261] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.063290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.063320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.063349] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.063384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.063413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.063444] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.063473] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.063502] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.063537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.063575] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.079374] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.079423] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.079494] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.096527] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.096572] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.096605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.096733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.096794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.096845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.096894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.096935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.096969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.097005] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.097037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.097069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.097097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.097126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.097179] [drm:intel_power_well_disable [i915]] disabling display
>[  927.097219] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.097250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.097283] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.097318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.097347] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.097855] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.097878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.097901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.097926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.097946] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.097967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.097988] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.098008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.098027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.098046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.098063] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.098068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.098085] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.098090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.098107] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.098125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.098143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.098167] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.098193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.098218] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.098244] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.098269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.098295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.098322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.098348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.098410] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.098432] [drm:intel_power_well_enable [i915]] enabling display
>[  927.098454] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.098492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.098518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.098543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.098569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.098594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.098621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.098691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.098724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.098756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.098783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.098811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.098845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.098874] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.100936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.100956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.100975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.100993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.102542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.102564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.102584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.104141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.104162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.106170] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.109460] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.109555] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.109587] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.109701] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.109995] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.110026] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.110080] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.110105] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.110144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.159799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.159839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.159879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.159926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.159967] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.160009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.160049] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.160090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.160131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.160172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.160212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.160220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.160260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.160267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.160308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.160344] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.160385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.160422] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.160463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.160503] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.160545] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.160586] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.160626] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.160733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.160785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.176362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.176410] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.176499] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.193486] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.193530] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.193563] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.193602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.193717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.193764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.193814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.193858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.193907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.193966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.194000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.194033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.194059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.194088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.194142] [drm:intel_power_well_disable [i915]] disabling display
>[  927.194183] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.194214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.194247] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.194281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.194312] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.194767] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.194791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.194822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.194845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.194863] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.194884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.194907] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.194931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.194955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.194976] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.194999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.195003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.195026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.195031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.195054] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.195075] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.195098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.195121] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.195145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.195168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.195192] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.195216] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.195239] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.195264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.195289] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.195346] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.195367] [drm:intel_power_well_enable [i915]] enabling display
>[  927.195386] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.195422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.195446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.195469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.195493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.195516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.195538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.195564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.195589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.195624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.195690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.195720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.195754] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.195784] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.197847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.197869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.197887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.197911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.199462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.199487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.199511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.201053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.201075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.202942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.206234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.206309] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.206329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.206355] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.206414] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.206444] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.206520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.206555] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.206594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.256590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.256631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.256732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.256793] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.256956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.256993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.257028] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.257061] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.257100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.257140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.257180] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.257190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.257229] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.257237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.257277] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.257319] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.257360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.257400] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.257439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.257479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.257523] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.257551] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.257580] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.257610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.257681] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.273131] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.273180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.273267] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.291563] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.291607] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.291725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.291793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.291844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.291895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.291932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.291973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.292013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.292058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.292102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.292146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.292186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.292225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.292262] [drm:intel_power_well_disable [i915]] disabling display
>[  927.292289] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.292313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.292337] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.292360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.292379] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.292818] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.292850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.292883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.292915] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.292934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.292954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.292975] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.292994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.293012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.293034] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.293057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.293063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.293086] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.293090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.293114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.293135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.293159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.293181] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.293204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.293227] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.293251] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.293274] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.293298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.293323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.293348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.293406] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.293427] [drm:intel_power_well_enable [i915]] enabling display
>[  927.293446] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.293482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.293505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.293529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.293552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.293576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.293600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.293678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.293716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.293751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.293780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.293810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.293846] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.293876] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.295940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.295961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.295983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.296008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.297608] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.297657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.297676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.299253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.299275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.301152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.304445] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.304521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.304544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.304575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.304683] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.304717] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.304921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.304960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.305018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.354806] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.354847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.354886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.354927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.354960] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.354996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.355032] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.355066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.355099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.355131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.355161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.355169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.355207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.355215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.355256] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.355297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.355338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.355377] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.355419] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.355459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.355502] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.355542] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.355583] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.355626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.355721] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.371343] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.371392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.371480] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.388478] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.388521] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.388553] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.388592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.388705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.388752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.388802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.388845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.388895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.388948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.388999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.389049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.389090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.389133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.389217] [drm:intel_power_well_disable [i915]] disabling display
>[  927.389279] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.389327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.389379] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.389433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.389480] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.390121] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.390152] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.390183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.390220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.390253] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.390288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.390321] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.390354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.390388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.390421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.390453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.390460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.390492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.390498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.390532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.390561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.390608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.390667] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.390705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.390736] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.390770] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.390799] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.390829] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.390864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.390901] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.390992] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.391022] [drm:intel_power_well_enable [i915]] enabling display
>[  927.391052] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.391101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.391129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.391158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.391185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.391213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.391240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.391272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.391303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.391335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.391360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.391388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.391418] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.391449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.393508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.393531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.393551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.393571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.395145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.395167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.395189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.396839] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.396862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.398758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.402043] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.402137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.402165] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.402201] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.402283] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.402325] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.402430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.402481] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.402534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.452397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.452438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.452478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.452519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.452553] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.452589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.452693] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.452743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.452797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.452846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.452893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.452908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.452955] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.452967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.453014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.453061] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.453117] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.453161] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.453205] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.453248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.453293] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.453336] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.453374] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.453422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.453472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.468952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.469001] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.469089] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.486132] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.486176] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.486209] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.486247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.486280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.486310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.486340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.486378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.486418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.486461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.486503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.486545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.486584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.486690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.486775] [drm:intel_power_well_disable [i915]] disabling display
>[  927.486841] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.487038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.487074] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.487112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.487144] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.487544] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.487570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.487596] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.487673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.487706] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.487743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.487776] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.487809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.487840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.487870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.487899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.487908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.487936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.487943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.487973] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.488003] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.488032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.488058] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.488091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.488121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.488152] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.488178] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.488207] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.488242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.488276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.488369] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.488401] [drm:intel_power_well_enable [i915]] enabling display
>[  927.488432] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.488482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.488514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.488545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.488574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.488604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.488654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.488688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.488721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.488753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.488782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.488811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.488844] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.488875] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.490936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.490957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.490979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.491004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.492587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.492634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.492653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.494221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.494244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.496141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.499440] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.499521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.499551] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.499590] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.499761] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.499808] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.499912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.499970] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.500035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.549802] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.549842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.549881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.549923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.549957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.549993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.550029] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.550063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.550095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.550126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.550156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.550164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.550199] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.550206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.550248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.550287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.550328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.550366] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.550407] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.550448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.550490] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.550531] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.550572] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.550615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.550725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.566346] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.566394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.566483] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.583471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.583515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.583547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.583586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.583700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.583747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.583797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.583841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.583891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.583943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.583995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.584047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.584088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.584131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.584215] [drm:intel_power_well_disable [i915]] disabling display
>[  927.584274] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.584304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.584337] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.584372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.584401] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.584848] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.584870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.584892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.584915] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.584933] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.584953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.584973] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.584992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.585011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.585028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.585044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.585049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.585065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.585069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.585086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.585103] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.585119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.585135] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.585154] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.585170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.585187] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.585204] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.585220] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.585239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.585260] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.585314] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.585331] [drm:intel_power_well_enable [i915]] enabling display
>[  927.585348] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.585379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.585397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.585415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.585431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.585447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.585465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.585490] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.585515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.585540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.585563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.585587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.585665] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.585696] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.587753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.587773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.587791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.587810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.589377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.589400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.589422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.590975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.590997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.592856] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.595922] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.595984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.596015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.596054] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.596126] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.596157] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.596235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.596274] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.596331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.646210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.646250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.646290] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.646331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.646364] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.646399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.646435] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.646469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.646501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.646532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.646562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.646571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.646600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.646661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.646710] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.646758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.646805] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.646852] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.646900] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.646949] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.647001] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.647048] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.647096] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.647150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.647206] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.662794] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.662842] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.662914] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.681509] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.681553] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.681585] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.681711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.681758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.681806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.681850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.681896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.681939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.681991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.682041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.682090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.682130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.682172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.682260] [drm:intel_power_well_disable [i915]] disabling display
>[  927.682322] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.682371] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.682422] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.682475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.682521] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.682921] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.682943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.682975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.682998] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.683017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.683037] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.683057] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.683076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.683094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.683111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.683127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.683132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.683148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.683152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.683169] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.683186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.683202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.683218] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.683237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.683260] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.683284] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.683308] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.683331] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.683356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.683381] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.683439] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.683459] [drm:intel_power_well_enable [i915]] enabling display
>[  927.683479] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.683515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.683539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.683562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.683597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.683657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.683693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.683730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.683764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.683798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.683826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.683856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.683892] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.683921] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.685991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.686015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.686038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.686062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.687653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.687674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.687693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.689245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.689266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.691138] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.693888] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.693950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.693969] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.693995] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.694056] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.694077] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.694132] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.694159] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.694207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.744230] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.744270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.744310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.744351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.744385] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.744421] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.744457] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.744491] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.744524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.744555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.744586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.744653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.744700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.744716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.744766] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.744815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.744864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.744911] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.744965] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.745012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.745064] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.745113] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.745140] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.745174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.745209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.760772] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.760824] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.760900] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.777925] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.777969] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.778002] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.778041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.778074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.778105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.778135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.778164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.778196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.778237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.778280] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.778322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.778361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.778400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.778457] [drm:intel_power_well_disable [i915]] disabling display
>[  927.778503] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.778544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.778586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.778723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.778775] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.779292] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.779323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.779356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.779391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.779419] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.779450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.779481] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.779512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.779541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.779569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.779608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.779643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.779676] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.779684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.779719] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.779751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.779782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.779813] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.779847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.779878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.779911] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.779942] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.779973] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.780006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.780041] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.780136] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.780169] [drm:intel_power_well_enable [i915]] enabling display
>[  927.780199] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.780250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.780281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.780312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.780342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.780371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.780403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.780437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.780469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.780502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.780531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.780560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.780593] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.780654] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.782719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.782741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.782763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.782787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.784361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.784383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.784401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.785961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.785982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.787851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.791162] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.791220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.791244] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.791275] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.791338] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.791359] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.791415] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.791443] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.791486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.841468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.841508] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.841548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.841589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.841691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.841745] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.841803] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.841857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.841909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.841956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.842004] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.842018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.842062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.842074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.842122] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.842168] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.842209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.842253] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.842303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.842349] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.842399] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.842445] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.842489] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.842522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.842557] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.858077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.858125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.858196] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.876707] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.876751] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.876791] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.876835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.876876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.876915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.876955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.876994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.877033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.877076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.877118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.877159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.877198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.877246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.877280] [drm:intel_power_well_disable [i915]] disabling display
>[  927.877305] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.877328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.877351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.877373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.877391] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.877819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.877853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.877889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.877926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.877958] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.877991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.878025] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.878057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.878089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.878121] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.878151] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.878159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.878187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.878195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.878224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.878253] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.878283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.878312] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.878345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.878374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.878405] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.878435] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.878465] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.878498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.878532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.878645] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.878679] [drm:intel_power_well_enable [i915]] enabling display
>[  927.878710] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.878762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.878796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.878829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.878860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.878891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.878925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.878960] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.878992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.879026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.879055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.879084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.879118] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.879150] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.881220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.881242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.881260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.881280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.882844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.882864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.882882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.884429] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.884449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.886312] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.888895] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.888984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.889013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.889058] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.889145] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.889190] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.889292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.889346] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.889402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.939269] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.939310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.939349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.939390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.939424] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.939460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.939496] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.939530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.939563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.939595] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.939684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.939703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.939749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.939761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.939810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.939854] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.939901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.939951] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.939999] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.940042] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.940087] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.940527] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.940568] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.940664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.940904] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.955809] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  927.955858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  927.955948] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  927.974512] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  927.974556] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  927.974588] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  927.974723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.974777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.974827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.974876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.974923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.974973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.975026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.975078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.975129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.975175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.975221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.975306] [drm:intel_power_well_disable [i915]] disabling display
>[  927.975371] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  927.975421] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.975473] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.975529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.975578] [drm:intel_power_well_disable [i915]] disabling always-on
>[  927.976051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  927.976081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  927.976111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  927.976144] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  927.976169] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  927.976197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  927.976225] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  927.976251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  927.976276] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  927.976300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  927.976323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  927.976330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.976353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  927.976358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  927.976382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  927.976405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  927.976428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  927.976459] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  927.976493] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  927.976526] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  927.976560] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  927.976594] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  927.976679] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  927.976727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  927.976777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  927.976897] [drm:intel_power_well_enable [i915]] enabling always-on
>[  927.976932] [drm:intel_power_well_enable [i915]] enabling display
>[  927.976965] [drm:hsw_set_power_well [i915]] Enabling power well
>[  927.977019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  927.977054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  927.977085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  927.977117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  927.977150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  927.977184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  927.977222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  927.977258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  927.977294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  927.977326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  927.977358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  927.977396] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  927.977430] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  927.979508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  927.979530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  927.979550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.979571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  927.981292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  927.981313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  927.981331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  927.982881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  927.982902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  927.984773] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  927.988075] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  927.988140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  927.988160] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  927.988186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  927.988246] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  927.988267] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  927.988320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  927.988347] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  927.988394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.038433] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.038478] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.038519] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.038562] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.038663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.038718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.038776] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.038828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.038880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.039219] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.039238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.039244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.039262] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.039266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.039284] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.039301] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.039318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.039335] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.039355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.039372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.039390] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.039407] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.039423] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.039444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.039470] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.054966] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.055016] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.055089] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.072555] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.072757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.072793] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.072833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.072867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.072898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.072934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.072959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.072987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.073018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.073046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.073082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.073117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.073152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.073202] [drm:intel_power_well_disable [i915]] disabling display
>[  928.073243] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.073279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.073317] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.073357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.073387] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.073965] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.073991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.074019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.074049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.074078] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.074109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.074139] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.074169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.074199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.074229] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.074258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.074265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.074293] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.074298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.074328] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.074357] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.074386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.074415] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.074444] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.074473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.074503] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.074532] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.074561] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.074625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.074666] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.074771] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.074808] [drm:intel_power_well_enable [i915]] enabling display
>[  928.074841] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.074899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.074941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.074969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.074997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.075024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.075056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.075090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.075120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.075150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.075180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.075208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.075242] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.075275] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.077359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.077381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.077400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.077420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.078994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.079014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.079032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.080578] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.080622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.082464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.085794] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.085848] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.085881] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.085924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.086002] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.086035] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.086124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.086150] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.086198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.136118] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.136159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.136199] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.136240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.136274] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.136310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.136346] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.136387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.136428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.136466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.136506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.136514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.136554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.136560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.136664] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.136716] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.136770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.136820] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.136875] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.136924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.136977] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.137025] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.137074] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.137129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.137184] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.152655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.152708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.152782] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.169808] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.169856] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.169896] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.169940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.169981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.170021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.170061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.170101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.170140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.170182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.170228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.170260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.170288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.170314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.170362] [drm:intel_power_well_disable [i915]] disabling display
>[  928.170398] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.170434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.170472] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.170512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.170542] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.171396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.171419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.171441] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.171464] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.171482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.171502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.171522] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.171541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.171559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.171629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.171657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.171667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.171697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.171706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.171736] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.171767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.171797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.171827] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.172067] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.172097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.172128] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.172157] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.172186] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.172217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.172248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.172334] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.172364] [drm:intel_power_well_enable [i915]] enabling display
>[  928.172392] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.172440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.172469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.172497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.172525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.172553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.172592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.172677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.172714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.172748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.172778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.172809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.172844] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.172876] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.175092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.175114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.175132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.175152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.176813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.176836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.176854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.178402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.178424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.180292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.183578] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.183671] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.183699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.183735] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.183816] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.183858] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.183954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.184006] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.184064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.233930] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.233971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.234011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.234058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.234098] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.234140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.234180] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.234221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.234263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.234304] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.234343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.234351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.234391] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.234398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.234439] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.234480] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.234521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.234561] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.234668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.234723] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.234786] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.234819] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.234852] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.234887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.234924] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.250483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.250535] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.250689] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.267887] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.267930] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.267962] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.268005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.268045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.268085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.268125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.268164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.268203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.268246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.268288] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.268329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.268368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.268407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.268479] [drm:intel_power_well_disable [i915]] disabling display
>[  928.268525] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.268558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.268657] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.268705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.268742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.269300] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.269331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.269362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.269395] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.269421] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.269450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.269482] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.269502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.269521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.269540] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.269565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.269602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.269629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.269637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.269666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.269694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.269721] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.269748] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.269778] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.269805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.269834] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.269860] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.269887] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.269921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.269954] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.270025] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.270044] [drm:intel_power_well_enable [i915]] enabling display
>[  928.270062] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.270095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.270115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.270134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.270152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.270170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.270189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.270211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.270231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.270252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.270270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.270288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.270310] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.270332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.272370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.272391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.272409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.272428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.273981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.274002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.274020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.275596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.275626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.277482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.280772] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.280850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.280870] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.280895] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.280957] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.280978] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.281033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.281059] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.281107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.331102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.331146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.331189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.331236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.331276] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.331318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.331358] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.331399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.331440] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.331476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.331516] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.331524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.331564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.331621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.331680] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.331730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.331783] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.331834] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.331882] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.331923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.331970] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.332010] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.332053] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.332104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.332156] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.347671] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.347719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.347792] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.364825] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.364869] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.364901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.364940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.364973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.365005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.365036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.365065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.365096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.365130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.365162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.365193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.365221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.365249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.365301] [drm:intel_power_well_disable [i915]] disabling display
>[  928.365342] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.365373] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.365406] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.365439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.365468] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.366192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.366214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.366236] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.366259] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.366277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.366297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.366317] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.366336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.366354] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.366371] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.366388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.366392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.366409] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.366412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.366429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.366446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.366462] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.366478] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.366498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.366514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.366532] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.366548] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.366575] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.366638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.366670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.366911] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.366931] [drm:intel_power_well_enable [i915]] enabling display
>[  928.366950] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.366986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.367008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.367028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.367047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.367066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.367086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.367108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.367129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.367150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.367169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.367188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.367210] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.367231] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.369277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.369298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.369317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.369336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.370911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.370931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.370949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.372496] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.372519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.374395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.377739] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.377814] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.377833] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.377859] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.377920] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.377941] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.377995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.378022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.378069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.428088] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.428132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.428175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.428222] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.428262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.428304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.428345] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.428386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.428428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.428464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.428503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.428511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.428551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.428611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.428666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.428714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.428759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.428803] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.428850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.428893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.428939] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.428983] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.429010] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.429044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.429079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.444663] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.444712] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.444783] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.461793] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.461837] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.461869] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.461908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.461942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.461974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.462005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.462035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.462066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.462100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.462132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.462164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.462192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.462219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.462272] [drm:intel_power_well_disable [i915]] disabling display
>[  928.462312] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.462352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.462394] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.462440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.462473] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.463123] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.463147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.463171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.463196] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.463216] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.463238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.463260] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.463281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.463301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.463319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.463337] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.463342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.463360] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.463364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.463382] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.463400] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.463418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.463435] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.463456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.463474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.463493] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.463511] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.463528] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.463550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.463621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.463714] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.463920] [drm:intel_power_well_enable [i915]] enabling display
>[  928.463939] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.463975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.463996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.464017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.464036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.464054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.464075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.464097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.464117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.464137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.464162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.464187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.464214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.464239] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.466275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.466297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.466315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.466334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.467897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.467918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.467937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.469478] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.469500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.471366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.474709] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.474801] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.474834] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.474874] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.474935] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.474958] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.475016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.475056] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.475095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.525021] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.525061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.525100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.525142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.525175] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.525210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.525246] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.525280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.525313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.525344] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.525383] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.525391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.525432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.525438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.525480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.525521] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.525562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.525668] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.525724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.525778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.525834] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.525884] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.525933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.525988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.526042] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.541634] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.541682] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.541753] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.558764] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.558809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.558842] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.558880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.558913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.558952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.558992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.559031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.559069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.559112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.559154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.559195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.559234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.559273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.559330] [drm:intel_power_well_disable [i915]] disabling display
>[  928.559375] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.559417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.559459] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.559504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.559537] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.560490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.560522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.560556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.560651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.560695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.560743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.560794] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.560836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.560882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.560913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.560943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.560952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.560980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.560988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.561017] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.561047] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.561076] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.561102] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.561135] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.561164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.561196] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.561222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.561251] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.561285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.561320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.561411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.561443] [drm:intel_power_well_enable [i915]] enabling display
>[  928.561474] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.561524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.561556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.561611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.561644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.561672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.561705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.561740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.561773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.561807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.561837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.561868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.561904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.561936] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.564000] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.564021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.564039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.564059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.565664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.565687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.565710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.567270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.567292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.569164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.572442] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.572494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.572524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.572564] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.572853] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.572885] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.572962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.573002] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.573060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.622761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.622802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.622842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.622883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.622924] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.622967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.623007] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.623048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.623089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.623126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.623166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.623174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.623213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.623220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.623262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.623303] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.623344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.623383] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.623424] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.623464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.623507] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.623548] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.623653] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.623708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.623769] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.639348] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.639397] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.639467] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.656480] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.656523] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.656555] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.656689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.656743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.656945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.656977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.657007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.657039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.657084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.657103] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.657121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.657138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.657155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.657187] [drm:intel_power_well_disable [i915]] disabling display
>[  928.657212] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.657231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.657255] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.657281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.657302] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.657866] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.657898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.657931] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.657965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.657994] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.658024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.658055] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.658085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.658115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.658143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.658171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.658178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.658205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.658211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.658238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.658267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.658295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.658321] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.658348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.658375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.658403] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.658430] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.658453] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.658483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.658515] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.658645] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.658680] [drm:intel_power_well_enable [i915]] enabling display
>[  928.658712] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.658762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.659061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.659093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.659125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.659155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.659187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.659221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.659254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.659287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.659316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.659346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.659380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.659411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.661459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.661481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.661501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.661521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.663088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.663108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.663126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.664771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.664792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.666670] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.669918] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.669999] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.670027] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.670064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.670134] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.670163] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.670234] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.670271] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.670328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.720246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.720287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.720327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.720368] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.720401] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.720437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.720474] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.720514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.720556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.720658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.720708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.720724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.720772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.720785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.720835] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.720883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.720933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.720979] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.721033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.721080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.721488] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.721541] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.721621] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.721655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.721788] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.736810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.736858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.736932] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.753964] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.754008] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.754040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.754080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.754114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.754145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.754176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.754205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.754236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.754285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.754316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.754354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.754391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.754428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.754482] [drm:intel_power_well_disable [i915]] disabling display
>[  928.754525] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.754564] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.754689] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.754749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.754796] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.755490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.755531] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.755608] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.755653] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.755693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.755734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.755774] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.755814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.755851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.755887] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.755922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.755931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.755965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.755974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.756009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.756044] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.756079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.756114] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.756149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.756183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.756221] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.756257] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.756291] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.756337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.756371] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.756464] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.756496] [drm:intel_power_well_enable [i915]] enabling display
>[  928.756527] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.756605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.756638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.756670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.756701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.756733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.756765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.756800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.756834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.756867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.756897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.756928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.756964] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.756996] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.759060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.759080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.759098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.759117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.760694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.760714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.760733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.762291] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.762311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.764171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.767458] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.767567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.767644] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.767689] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.767765] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.767797] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.767868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.767896] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.767935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.817819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.817863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.817906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.817953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.817993] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.818035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.818077] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.818118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.818159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.818200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.818240] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.818248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.818287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.818294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.818336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.818372] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.818413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.818449] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.818490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.818531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.818640] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.818693] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.818746] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.818803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.818862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.834361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.834412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.834487] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.851510] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.851554] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.851680] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.851741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.851792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.851842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.851889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.851936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.851985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.852039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.852090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.852140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.852185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.852230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.852314] [drm:intel_power_well_disable [i915]] disabling display
>[  928.852379] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.852429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.852481] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.852536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.852624] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.852975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.853006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.853027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.853050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.853069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.853088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.853108] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.853126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.853144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.853161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.853177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.853182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.853198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.853201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.853218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.853234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.853250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.853266] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.853285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.853301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.853325] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.853349] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.853373] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.853397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.853423] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.853478] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.853499] [drm:intel_power_well_enable [i915]] enabling display
>[  928.853519] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.853604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.853637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.853672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.853705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.853738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.853771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.853807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.853841] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.853875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.853905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.853932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.853968] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.854000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.856069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.856090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.856108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.856127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.857724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.857746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.857765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.859325] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.859347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.861221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.864538] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.864657] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.864691] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.864733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.864810] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.864843] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.864922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.864963] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.865023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.914910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.914951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.914990] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.915032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.915065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.915101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.915137] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.915172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.915213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.915251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.915292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.915300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.915340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.915347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.915388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.915425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.915466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.915506] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.915548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.915652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.915705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.915760] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.915809] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.915865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.915923] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.931463] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  928.931512] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  928.931663] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  928.948678] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  928.948722] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  928.948755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  928.948794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.948826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.948858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.948888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.948918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.948956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.948999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.949040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.949082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.949121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.949160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.949217] [drm:intel_power_well_disable [i915]] disabling display
>[  928.949262] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  928.949303] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.949345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.949390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.949424] [drm:intel_power_well_disable [i915]] disabling always-on
>[  928.950320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  928.950342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  928.950364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  928.950388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  928.950406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  928.950426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  928.950447] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  928.950466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  928.950484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  928.950501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  928.950518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  928.950523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.950549] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  928.950587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  928.950620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  928.950652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  928.950683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  928.950713] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  928.950747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  928.950778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  928.950810] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  928.950839] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  928.950870] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  928.950905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  928.950940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  928.951276] [drm:intel_power_well_enable [i915]] enabling always-on
>[  928.951306] [drm:intel_power_well_enable [i915]] enabling display
>[  928.951335] [drm:hsw_set_power_well [i915]] Enabling power well
>[  928.951383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  928.951413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  928.951441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  928.951469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  928.951497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  928.951525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  928.951601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  928.951635] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  928.951669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  928.951699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  928.951729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  928.951933] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  928.951953] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  928.954001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  928.954022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  928.954040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.954059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  928.955678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  928.955698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  928.955717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  928.957273] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  928.957295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  928.959165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  928.962413] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  928.962491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  928.962519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  928.962615] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  928.962844] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  928.962872] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  928.962941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  928.962977] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  928.963028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.012750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.012790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.012832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.012879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.012920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.012962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.013002] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.013043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.013085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.013126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.013166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.013174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.013213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.013220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.013262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.013303] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.013343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.013382] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.013433] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.013469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.013504] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.013535] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.013627] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.013677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.013733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.029305] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.029354] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.029426] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.046455] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.046498] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.046530] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.046662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.046713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.046763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.046811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.046859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.046908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.046962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.047014] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.047064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.047110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.047162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.047218] [drm:intel_power_well_disable [i915]] disabling display
>[  929.047260] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.047291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.047324] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.047360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.047391] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.047835] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.047865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.047888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.047911] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.047929] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.047949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.047969] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.047992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.048016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.048039] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.048062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.048067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.048090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.048095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.048118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.048141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.048165] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.048187] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.048210] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.048233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.048257] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.048281] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.048304] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.048329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.048354] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.048411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.048432] [drm:intel_power_well_enable [i915]] enabling display
>[  929.048452] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.048487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.048511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.048544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.048614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.048645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.048679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.048716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.048751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.048785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.048815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.048845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.048881] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.048914] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.050990] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.051011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.051030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.051049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.052653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.052676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.052699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.054259] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.054281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.056151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.059431] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.059467] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.059486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.059511] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.059783] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.059804] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.059856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.059882] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.059920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.109744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.109784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.109823] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.109865] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.109898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.109934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.109970] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.110004] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.110036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.110068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.110098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.110105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.110135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.110142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.110172] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.110202] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.110232] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.110261] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.110296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.110325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.110357] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.110386] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.110415] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.110450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.110488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.126291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.126340] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.126413] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.143443] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.143488] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.143520] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.143651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.143705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.143755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.143803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.143849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.143898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.143951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.144003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.144054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.144101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.144147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.144231] [drm:intel_power_well_disable [i915]] disabling display
>[  929.144296] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.144345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.144395] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.144431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.144462] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.144847] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.144870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.144896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.144925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.144957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.144979] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.144999] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.145018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.145036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.145053] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.145069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.145073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.145089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.145093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.145110] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.145126] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.145142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.145158] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.145177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.145193] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.145210] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.145232] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.145256] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.145281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.145306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.145362] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.145382] [drm:intel_power_well_enable [i915]] enabling display
>[  929.145402] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.145437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.145461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.145485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.145509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.145542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.145608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.145643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.145680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.145714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.145746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.145777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.145814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.145847] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.147916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.147937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.147956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.147975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.149635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.149655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.149673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.151234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.151255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.153117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.156405] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.156500] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.156532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.156626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.156701] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.156733] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.156812] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.156852] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.156919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.206721] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.206762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.206802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.206843] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.206877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.206913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.206949] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.206982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.207015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.207046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.207076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.207084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.207113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.207119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.207150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.207179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.207208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.207237] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.207272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.207301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.207332] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.207362] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.207390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.207425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.207463] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.223308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.223356] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.223427] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.240457] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.240501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.240534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.240668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.240722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.240962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.240994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.241024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.241057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.241092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.241125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.241156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.241184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.241212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.241264] [drm:intel_power_well_disable [i915]] disabling display
>[  929.241305] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.241335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.241369] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.241413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.241430] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.241896] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.241930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.241965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.242002] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.242034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.242076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.242107] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.242136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.242165] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.242193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.242221] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.242228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.242255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.242261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.242289] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.242316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.242340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.242366] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.242396] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.242422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.242451] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.242478] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.242502] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.242542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.242606] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.242699] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.242731] [drm:intel_power_well_enable [i915]] enabling display
>[  929.242762] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.242812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.242844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.242875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.242905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.242935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.242966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.242999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.243032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.243064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.243093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.243122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.243156] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.243188] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.245258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.245279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.245301] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.245326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.246899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.246920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.246938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.248515] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.248548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.250398] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.253695] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.253767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.253791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.253822] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.253886] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.253908] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.253962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.253990] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.254037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.304045] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.304085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.304125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.304167] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.304200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.304236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.304273] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.304313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.304355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.304392] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.304432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.304440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.304480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.304487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.304528] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.304636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.304688] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.304740] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.304795] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.304845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.304898] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.304929] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.304960] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.304995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.305031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.320591] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.320639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.320716] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.337754] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.337799] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.337839] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.337884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.337925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.337965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.338004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.338044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.338083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.338126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.338167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.338209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.338248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.338287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.338344] [drm:intel_power_well_disable [i915]] disabling display
>[  929.338390] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.338431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.338473] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.338522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.338611] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.339418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.339448] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.339480] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.339521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.339598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.339637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.339675] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.339710] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.339850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.339882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.339914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.339922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.339951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.339958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.339989] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.340020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.340050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.340077] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.340111] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.340143] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.340176] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.340206] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.340235] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.340269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.340304] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.340399] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.340432] [drm:intel_power_well_enable [i915]] enabling display
>[  929.340463] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.340515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.340594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.340628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.340659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.340690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.340722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.340757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.340791] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.340823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.340853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.340884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.340919] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.340952] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.343193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.343214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.343233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.343252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.344814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.344834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.344852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.346391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.346414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.348265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.351583] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.351647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.351686] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.351737] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.351819] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.351859] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.351913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.351940] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.351987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.401912] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.401957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.402002] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.402056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.402102] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.402151] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.402196] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.402243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.402290] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.402331] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.402377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.402386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.402432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.402440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.402487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.402534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.402657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.402716] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.402782] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.402840] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.402903] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.402959] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.403016] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.403079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.403142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.418457] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.418509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.418802] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.435813] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.435857] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.435889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.435928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.435960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.435991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.436021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.436049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.436081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.436115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.436147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.436179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.436207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.436235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.436289] [drm:intel_power_well_disable [i915]] disabling display
>[  929.436329] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.436360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.436393] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.436427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.436456] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.437128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.437163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.437197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.437234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.437265] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.437297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.437330] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.437363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.437395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.437433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.437461] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.437468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.437495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.437502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.437540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.437604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.437635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.437667] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.437700] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.437732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.437765] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.437795] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.437825] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.437859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.437895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.437987] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.438020] [drm:intel_power_well_enable [i915]] enabling display
>[  929.438050] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.438101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.438132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.438163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.438194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.438224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.438254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.438288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.438320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.438352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.438381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.438410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.438443] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.438475] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.440568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.440589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.440607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.440626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.442195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.442220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.442240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.443775] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.443799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.445659] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.449001] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.449095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.449130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.449155] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.449215] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.449245] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.449337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.449374] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.449413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.499362] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.499402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.499441] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.499482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.499515] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.499637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.499696] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.499750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.499802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.499850] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.500191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.500199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.500230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.500237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.500268] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.500297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.500326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.500354] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.500388] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.500416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.500451] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.500467] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.500484] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.500504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.500577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.515900] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.515952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.516027] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.534471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.534515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.534640] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.534700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.534890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.534931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.534971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.535010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.535049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.535092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.535142] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.535165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.535184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.535201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.535233] [drm:intel_power_well_disable [i915]] disabling display
>[  929.535258] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.535277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.535299] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.535320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.535337] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.535723] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.535756] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.535791] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.535829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.535860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.535893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.535926] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.535958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.535990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.536020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.536049] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.536057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.536086] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.536093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.536123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.536155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.536185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.536215] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.536248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.536278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.536310] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.536340] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.536369] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.536403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.536437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.536547] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.536578] [drm:intel_power_well_enable [i915]] enabling display
>[  929.536608] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.536660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.536692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.536722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.536752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.536781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.536812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.536846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.536879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.536911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.536940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.536969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.537003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.537034] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.539154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.539176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.539195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.539215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.540794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.540818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.540837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.542400] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.542423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.544290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.547509] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.547608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.547627] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.547653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.547712] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.547733] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.547787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.547814] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.547860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.597879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.597923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.597966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.598013] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.598053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.598095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.598135] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.598176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.598218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.598254] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.598293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.598301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.598341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.598348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.598390] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.598431] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.598472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.598512] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.598620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.598674] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.598723] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.598766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.598808] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.598855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.598903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.614431] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.614484] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.614638] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.631651] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.631696] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.631728] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.631767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.631800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.631831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.631870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.631910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.631949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.631992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.632033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.632075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.632114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.632153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.632210] [drm:intel_power_well_disable [i915]] disabling display
>[  929.632255] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.632297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.632340] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.632373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.632399] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.633354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.633376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.633398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.633422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.633440] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.633460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.633480] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.633499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.633570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.633598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.633627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.633636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.633662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.633670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.633697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.633728] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.633755] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.633782] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.633816] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.633845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.633876] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.633906] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.633935] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.633968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.634002] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.634066] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.634086] [drm:intel_power_well_enable [i915]] enabling display
>[  929.634107] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.634147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.634173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.634200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.634225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.634252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.634277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.634306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.634334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.634362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.634387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.634414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.634441] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.634467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.636554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.636578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.636601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.636625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.638188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.638210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.638228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.639780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.639801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.641662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.644968] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.645043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.645073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.645111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.645181] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.645211] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.645284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.645321] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.645375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.695315] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.695358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.695399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.695444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.695482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.695523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.695626] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.695677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.695724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.695767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.695810] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.695822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.695869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.695883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.695931] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.695977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.696023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.696067] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.696120] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.696166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.696215] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.696244] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.696272] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.696307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.696344] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.711848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.711894] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.711963] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.730465] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.730509] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.730630] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.730690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.730742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.730792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.730836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.730868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.730900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.730935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.730967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.731000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.731029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.731069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.731128] [drm:intel_power_well_disable [i915]] disabling display
>[  929.731174] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.731216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.731260] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.731306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.731340] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.731915] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.731957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.732001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.732050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.732088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.732127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.732170] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.732198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.732224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.732248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.732272] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.732279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.732302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.732307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.732331] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.732354] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.732378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.732400] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.732428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.732452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.732477] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.732503] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.732585] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.732626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.732669] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.732765] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.732816] [drm:intel_power_well_enable [i915]] enabling display
>[  929.732849] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.732905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.732940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.732972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.732994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.733015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.733036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.733061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.733083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.733105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.733125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.733151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.733181] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  929.733210] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.735279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.735301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.735320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.735339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.736904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.736925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.736943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.738491] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.738543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.740397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.742830] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  929.742922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.742956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  929.742999] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.743059] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  929.743080] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  929.743134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.743161] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.743208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.793179] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.793220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.793260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.793301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.793335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.793370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.793406] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  929.793440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  929.793482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.793523] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.793625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.793640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.793684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.793697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.793742] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.793785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.793826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.793868] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  929.793916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.793962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.794010] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.794052] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  929.794098] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  929.794150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.794204] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  929.809729] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  929.809781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.809857] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  929.826882] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  929.826926] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  929.826959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.826998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.827031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.827063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.827094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.827123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.827155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.827189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.827221] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.827254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.827291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.827330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.827387] [drm:intel_power_well_disable [i915]] disabling display
>[  929.827433] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.827474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.827517] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.827642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.827687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.827982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.828086] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.828119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.828150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.828184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.828216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.828249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.828281] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.828315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.828351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.828386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.828421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.828453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.828485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.828566] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  929.828609] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.828934] [drm:drm_mode_addfb2] [FB:58]
>[  929.828973] [drm:drm_mode_addfb2] [FB:78]
>[  929.861124] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  929.861227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  929.861300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  929.861369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  929.861381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  929.861441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.861463] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.861486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.861561] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.861592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.861627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.861660] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  929.861690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  929.861722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.861750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.861778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.861787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.861814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.861821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.861849] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.861877] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.861906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.861932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  929.861964] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.861990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.862019] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  929.862044] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  929.862071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  929.862101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.862134] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  929.865405] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.865424] [drm:intel_power_well_enable [i915]] enabling display
>[  929.865440] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.865475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.865495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.865557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.865588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.865618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.865648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.865683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.865715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.865748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.865774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.865801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.865836] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  929.865865] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.867931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.867953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.867973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.867994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.869549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.869570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.869588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.871146] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.871168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.873055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.876277] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  929.876319] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.876339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  929.876364] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.893113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.893162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  929.893226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.909941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.909979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.910017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.910056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.910088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.910121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.910155] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  929.910186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  929.910216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.910245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.910274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.910282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.910309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.910315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.910343] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.910371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.910398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.910424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  929.910457] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.910485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.910598] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.910645] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  929.910693] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  929.910747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.910804] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  929.910917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  929.910956] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.911031] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  929.928060] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  929.928102] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  929.928147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.928187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.928227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.928267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.928306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.928344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.928387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.928429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.928471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.928510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.928635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.928718] [drm:intel_power_well_disable [i915]] disabling display
>[  929.928783] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  929.928839] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.928894] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  929.928948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.928996] [drm:intel_power_well_disable [i915]] disabling always-on
>[  929.929346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.929376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.929408] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.929443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.929471] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.929501] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.929583] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  929.929618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  929.929650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.929682] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.929712] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.929722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.929751] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.929759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.929789] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.929819] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.929846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.929876] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  929.929908] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.929937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.929965] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.929993] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  929.930022] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  929.930055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.930089] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  929.930183] [drm:intel_power_well_enable [i915]] enabling always-on
>[  929.930214] [drm:intel_power_well_enable [i915]] enabling display
>[  929.930243] [drm:hsw_set_power_well [i915]] Enabling power well
>[  929.930295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  929.930327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  929.930357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  929.930387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  929.930417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  929.930445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  929.930479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  929.930512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  929.930568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.930599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  929.930629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  929.930665] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  929.930697] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  929.932763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  929.932787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  929.932810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.932833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  929.934396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  929.934417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  929.934436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  929.935985] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  929.936006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  929.937919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  929.941243] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  929.941302] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  929.941336] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  929.941378] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  929.941493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  929.941598] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  929.941661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  929.991583] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  929.991621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  929.991659] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  929.991697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  929.991735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  929.991776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  929.991814] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  929.991854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  929.991893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  929.991928] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  929.991966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  929.991974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.992013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  929.992019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  929.992060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  929.992099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  929.992138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  929.992177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  929.992217] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  929.992255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  929.992296] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  929.992335] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  929.992375] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  929.992416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  929.992458] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  929.992652] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  929.992720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  929.992986] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.009409] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.009447] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.009487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.009610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.009658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.009710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.009757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.009807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.009860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.009912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.009963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.010009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.010054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.010139] [drm:intel_power_well_disable [i915]] disabling display
>[  930.010206] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.010239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.010272] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.010305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.010337] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.010814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.010837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.010859] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.010882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.010901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.010921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.010941] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.010959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.010977] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.010995] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.011011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.011016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.011033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.011036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.011053] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.011076] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.011099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.011122] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.011146] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.011169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.011193] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.011217] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.011240] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.011265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.011290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.011346] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.011366] [drm:intel_power_well_enable [i915]] enabling display
>[  930.011386] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.011422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.011445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.011469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.011504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.011573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.011606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.011645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.011681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.011715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.011746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.011777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.011813] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.011846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.013920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.013942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.013960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.013979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.015547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.015568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.015587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.017139] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.017160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.019045] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.022342] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.022436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.022463] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.022499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.022700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.022756] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.022841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.072658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.072702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.072745] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.072791] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.072832] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.072873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.072913] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.072953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.072994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.073030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.073071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.073078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.073118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.073125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.073166] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.073207] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.073248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.073287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.073328] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.073368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.073410] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.073451] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.073491] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.073595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.073654] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.073812] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.073867] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.073954] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.090398] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.090436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.090476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.090593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.090650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.090699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.090749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.090799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.091023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.091048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.091073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.091096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.091119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.091154] [drm:intel_power_well_disable [i915]] disabling display
>[  930.091182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.091206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.091231] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.091256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.091276] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.091925] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.091948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.091970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.091994] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.092013] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.092033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.092053] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.092073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.092091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.092109] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.092125] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.092130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.092152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.092156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.092180] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.092202] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.092226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.092247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.092271] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.092294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.092318] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.092342] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.092365] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.092390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.092415] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.092474] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.092504] [drm:intel_power_well_enable [i915]] enabling display
>[  930.092570] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.092626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.092661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.092694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.092726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.092759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.092791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.092827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.092862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.092896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.092927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.092958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.092993] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.093024] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.095105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.095126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.095144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.095163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.096744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.096767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.096786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.098339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.098361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.100229] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.103553] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.103609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.103638] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.103676] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.103772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.103810] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.103865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.153893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.153934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.153973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.154019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.154060] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.154102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.154142] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.154183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.154225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.154265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.154305] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.154313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.154353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.154360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.154401] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.154442] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.154483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.154592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.154642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.154690] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.154739] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.154784] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.154827] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.154877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.154928] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.155089] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.155152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.155456] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.171401] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.171438] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.171478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.171595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.171647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.171696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.171744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.171794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.171853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.171874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.171901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.171927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.171953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.171990] [drm:intel_power_well_disable [i915]] disabling display
>[  930.172021] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.172048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.172076] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.172105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.172127] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.172425] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.172451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.172477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.172549] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.172580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.172613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.172644] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.172674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.172703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.172730] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.172757] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.172766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.172791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.172799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.172827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.172853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.172880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.172905] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.172935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.172961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.172991] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.173017] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.173043] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.173076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.173110] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.173203] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.173235] [drm:intel_power_well_enable [i915]] enabling display
>[  930.173266] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.173320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.173352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.173383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.173413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.173441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.173462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.173484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.173538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.173569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.173595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.173621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.173654] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.173682] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.175747] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.175770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.175793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.175817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.177389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.177414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.177437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.179040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.179063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.180985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.184217] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.184252] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.184276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.184307] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.184393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.184422] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.184463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.234500] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.234567] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.234611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.234657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.234697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.234740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.234779] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.234820] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.234862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.234898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.234938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.234946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.234986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.234993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.235034] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.235075] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.235116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.235156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.235198] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.235238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.235287] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.235320] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.235353] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.235389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.235427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.235573] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.235632] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.235960] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.252403] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.252441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.252481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.252604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.252656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.252857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.252889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.252922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.252957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.252988] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.253020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.253048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.253075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.253127] [drm:intel_power_well_disable [i915]] disabling display
>[  930.253168] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.253199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.253236] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.253279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.253313] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.253925] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.253960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.253997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.254035] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.254066] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.254101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.254136] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.254167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.254199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.254238] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.254265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.254272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.254299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.254306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.254333] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.254360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.254386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.254410] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.254440] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.254466] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.254506] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.254569] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.254599] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.254634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.254669] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.254761] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.254792] [drm:intel_power_well_enable [i915]] enabling display
>[  930.254823] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.254875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.254906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.254937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.254968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.254998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.255029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.255062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.255095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.255127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.255156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.255186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.255220] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.255251] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.257324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.257346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.257365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.257384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.258930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.258958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.258975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.260540] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.260561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.262419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.264818] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.264892] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.264930] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.264956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.265034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.265062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.265101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.315197] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.315237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.315277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.315319] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.315352] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.315389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.315426] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.315459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.315492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.315589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.315633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.315648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.315689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.315701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.315744] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.315786] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.315830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.315875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.315925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.315966] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.316015] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.316050] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.316078] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.316127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.316150] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.316222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.316249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.316305] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.333363] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.333400] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.333440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.333473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.333585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.333743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.333773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.333807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.333850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.333893] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.333937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.333976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.334017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.334073] [drm:intel_power_well_disable [i915]] disabling display
>[  930.334119] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.334161] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.334205] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.334249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.334283] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.334820] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.334842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.334865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.334888] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.334906] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.334927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.334947] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.334969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.334993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.335015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.335038] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.335043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.335066] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.335070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.335093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.335114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.335137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.335160] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.335184] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.335207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.335231] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.335254] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.335278] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.335302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.335328] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.335384] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.335404] [drm:intel_power_well_enable [i915]] enabling display
>[  930.335424] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.335460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.335494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.335560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.335590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.335620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.335649] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.335682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.335713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.335744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.335771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.335798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.335830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.335859] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.338150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.338171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.338189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.338208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.339771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.339791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.339809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.341370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.341393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.343257] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.346603] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.346700] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.346726] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.346759] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.346850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.346885] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.346934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.396948] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.396989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.397029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.397070] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.397104] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.397139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.397180] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.397221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.397262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.397303] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.397343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.397351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.397391] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.397398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.397440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.397477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.397592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.397641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.397696] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.397742] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.397797] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.397840] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.397887] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.397948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.397983] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.398090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.398128] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.398192] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.415232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.415269] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.415309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.415342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.415373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.415403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.415432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.415463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.415576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.415631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.415686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.415730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.415778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.416180] [drm:intel_power_well_disable [i915]] disabling display
>[  930.416221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.416257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.416294] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.416329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.416358] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.416864] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.416885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.416907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.416933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.416956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.416981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.417005] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.417029] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.417052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.417075] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.417098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.417103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.417126] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.417130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.417154] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.417174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.417198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.417221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.417244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.417267] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.417291] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.417314] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.417338] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.417362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.417388] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.417443] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.417463] [drm:intel_power_well_enable [i915]] enabling display
>[  930.417530] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.417584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.417615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.417645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.417673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.417701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.417729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.417762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.417794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.417825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.417852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.417881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.418152] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.418173] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.420210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.420231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.420249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.420268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.421833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.421853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.421871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.423417] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.423438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.425300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.428647] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.428729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.428757] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.428792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.428887] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.428923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.428974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.479193] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.479265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.479335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.479408] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.479467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.479653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.479739] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.479822] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.479911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.480307] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.480360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.480375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.480426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.480439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.480491] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.480598] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.480640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.480683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.480730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.480777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.480821] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.480863] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.480909] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.480962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.481016] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.481168] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.481212] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.481298] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.496263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.496300] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.496340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.496374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.496405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.496435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.496464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.496562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.496615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.496669] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.496716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.496761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.496796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.496849] [drm:intel_power_well_disable [i915]] disabling display
>[  930.496890] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.496921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.496956] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.496989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.497019] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.497440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.497462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.497543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.497579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.497608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.497640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.497671] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.497701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.497731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.497761] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.497787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.497796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.497825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.497830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.497850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.497869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.497886] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.497904] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.497925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.497944] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.497963] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.497980] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.497998] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.498019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.498046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.498109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.498131] [drm:intel_power_well_enable [i915]] enabling display
>[  930.498152] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.498191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.498217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.498243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.498269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.498295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.498321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.498349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.498377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.498405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.498431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.498457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.498490] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.498545] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.500604] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.500625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.500643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.500663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.502227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.502247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.502265] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.503805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.503835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.505701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.509008] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.509084] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.509123] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.509174] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.509326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.509394] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.509500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.559342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.559384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.559423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.559465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.559566] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.559614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.559664] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.559716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.559932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.559963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.559992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.560001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.560030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.560036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.560066] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.560095] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.560123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.560161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.560202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.560242] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.560284] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.560326] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.560365] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.560409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.560452] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.560850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.560896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.560983] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.578032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.578069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.578108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.578141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.578172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.578201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.578230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.578261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.578303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.578346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.578388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.578427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.578466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.578614] [drm:intel_power_well_disable [i915]] disabling display
>[  930.578798] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.578838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.578878] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.578915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.578945] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.579454] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.579484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.579561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.579597] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.579628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.579661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.579826] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.579846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.579865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.579882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.579899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.579903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.579920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.579924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.579941] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.579957] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.579980] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.580003] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.580026] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.580049] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.580074] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.580097] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.580121] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.580145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.580171] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.580228] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.580248] [drm:intel_power_well_enable [i915]] enabling display
>[  930.580268] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.580305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.580329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.580352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.580376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.580399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.580421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.580447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.580476] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.580550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.580580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.580608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.580641] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.580672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.582979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.583000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.583019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.583038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.584692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.584711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.584729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.586287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.586310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.588177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.591472] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.591553] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.591576] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.591607] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.591698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.591738] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.591799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.641798] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.641842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.641885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.641932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.641972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.642014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.642053] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.642094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.642136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.642171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.642211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.642219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.642260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.642267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.642308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.642349] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.642390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.642428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.642470] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.642569] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.642623] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.642668] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.642712] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.642762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.642816] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.643210] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.643247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.643320] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.660346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.660384] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.660428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.660468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.660586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.660753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.660787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.660821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.660859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.660892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.660924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.660954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.660993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.661049] [drm:intel_power_well_disable [i915]] disabling display
>[  930.661095] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.661137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.661184] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.661209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.661228] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.661652] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.661675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.661701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.661737] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.661757] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.661777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.661798] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.661817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.661835] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.661852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.661869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.661873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.661889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.661893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.661909] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.661925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.661942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.661958] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.661977] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.661993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.662010] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.662026] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.662042] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.662061] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.662082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.662137] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.662154] [drm:intel_power_well_enable [i915]] enabling display
>[  930.662171] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.662202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.662221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.662243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.662267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.662291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.662314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.662339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.662364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.662389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.662412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.662435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.662462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.662539] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.664601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.664622] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.664641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.664661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.666229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.666249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.666266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.667816] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.667838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.669700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.673009] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.673082] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.673115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.673156] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.673304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.673370] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.673467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.723342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.723383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.723423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.723463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.723559] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.723613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.723672] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.723723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.723773] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.724097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.724129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.724137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.724167] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.724173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.724204] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.724233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.724261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.724289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.724324] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.724352] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.724382] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.724409] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.724437] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.724470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.724571] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.724946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.724985] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.725060] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.742104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.742142] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.742182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.742216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.742247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.742276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.742305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.742337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.742379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.742422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.742464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.742583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.742630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.742713] [drm:intel_power_well_disable [i915]] disabling display
>[  930.743092] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.743146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.743198] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.743229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.743258] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.743710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.743732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.743754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.743778] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.743796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.743816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.743836] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.743855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.743873] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.743890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.743906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.743911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.743927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.743931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.743948] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.743965] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.743981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.743997] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.744016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.744038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.744063] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.744086] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.744110] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.744134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.744160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.744217] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.744236] [drm:intel_power_well_enable [i915]] enabling display
>[  930.744256] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.744292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.744316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.744340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.744364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.744387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.744410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.744435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.744471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.744541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.744574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.744608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.744645] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.744678] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.746751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.746772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.746791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.746810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.748359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.748381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.748400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.749951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.749972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.751873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.755189] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.755257] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.755289] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.755330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.755434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.755461] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.755579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.805528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.805570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.805611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.805660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.805701] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.805744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.805784] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.805825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.805867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.805903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.805943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.805953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.805993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.806000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.806042] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.806078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.806119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.806157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.806198] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.806238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.806281] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.806322] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.806362] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.806405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.806450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.806655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.806708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.807049] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.823379] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.823417] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.823458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.823581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.823629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.823681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.823728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.823777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.823831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.823881] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.823938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.823969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.823998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.824054] [drm:intel_power_well_disable [i915]] disabling display
>[  930.824096] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.824128] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.824162] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.824195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.824226] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.824710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.824734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.824758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.824785] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.824808] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.824851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.824874] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.824899] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.824933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.824952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.824969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.824974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.824990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.824994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.825017] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.825040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.825064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.825087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.825111] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.825133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.825158] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.825181] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.825205] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.825230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.825254] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.825313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.825333] [drm:intel_power_well_enable [i915]] enabling display
>[  930.825352] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.825389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.825412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.825436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.825470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.825541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.825574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.825610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.825645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.825680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.825711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.825742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.825779] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.825811] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.827887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.827911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.827934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.827958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.829526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.829549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.829572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.831137] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.831159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.833026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.836296] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.836343] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.836362] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.836388] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.836474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.836570] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.836635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.886643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.886681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.886718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.886756] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.886787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.886820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.886854] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.886886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.886917] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.886955] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.886994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.887002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.887041] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.887048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.887087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.887127] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.887166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.887204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.887243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.887282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.887322] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.887362] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.887401] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.887447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.887536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.887674] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.887729] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.887817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.904858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.904900] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.904946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.904987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.905027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.905067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.905106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.905143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.905187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.905228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.905270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.905309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.905348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.905405] [drm:intel_power_well_disable [i915]] disabling display
>[  930.905450] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.905571] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.905630] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.905687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.905738] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.906237] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.906269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.906301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.906324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.906347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.906372] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.906396] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.906419] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.906443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.906474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.906540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.906549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.906578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.906585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.906616] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.906644] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.906671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.906698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.906730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.906757] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.906786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.906815] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.906841] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.906873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.906907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.906998] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.907029] [drm:intel_power_well_enable [i915]] enabling display
>[  930.907058] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.907108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.907138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.907168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.907194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.907223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.907250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.907282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.907314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.907345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.907371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.907398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.907429] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.907460] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.909546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.909567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.909585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.909604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.911176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.911196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.911214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.912774] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.912795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.914663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.917979] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.918049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.918068] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.918094] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.918175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.918202] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.918242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.968291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.968332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.968371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.968413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.968446] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.968551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.968604] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.968658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.968709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.968760] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.968806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.968819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.968865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.968877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.968923] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.968970] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.969018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.969063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.969111] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.969155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.969204] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.969249] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.969290] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.969340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.969394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.969557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  930.969598] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  930.969665] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  930.986704] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  930.986741] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  930.986782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.986815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.986846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.986875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.986904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.986935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.986969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.987000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.987032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.987060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.987087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.987140] [drm:intel_power_well_disable [i915]] disabling display
>[  930.987181] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  930.987211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.987244] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.987275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.987304] [drm:intel_power_well_disable [i915]] disabling always-on
>[  930.987969] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  930.987992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  930.988016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  930.988044] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  930.988069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  930.988096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  930.988122] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  930.988148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  930.988175] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  930.988200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  930.988225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  930.988231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.988256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  930.988261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  930.988287] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  930.988313] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  930.988338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  930.988363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  930.988389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  930.988414] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  930.988441] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  930.988495] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  930.988527] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  930.988560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  930.988593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  930.988684] [drm:intel_power_well_enable [i915]] enabling always-on
>[  930.988715] [drm:intel_power_well_enable [i915]] enabling display
>[  930.988746] [drm:hsw_set_power_well [i915]] Enabling power well
>[  930.988801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  930.988835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  930.988866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  930.988898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  930.988918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  930.988939] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  930.988961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  930.988982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  930.989002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  930.989022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  930.989046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  930.989073] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  930.989100] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  930.991142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  930.991164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  930.991182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.991201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  930.992766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  930.992786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  930.992804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  930.994342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  930.994365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  930.996216] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  930.999533] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  930.999602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  930.999642] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  930.999693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  930.999809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  930.999859] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  930.999929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.049867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.049907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.049947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.049989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.050023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.050059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.050095] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.050129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.050162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.050193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.050223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.050231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.050260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.050266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.050297] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.050327] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.050357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.050386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.050421] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.050450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.050541] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.050594] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.050636] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.050689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.050745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.050901] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.050961] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.051326] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.067355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.067392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.067432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.067465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.067573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.067619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.067662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.067713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.067789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.067844] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.067886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.067921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.067958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.068030] [drm:intel_power_well_disable [i915]] disabling display
>[  931.068084] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.068125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.068168] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.068210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.068250] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.068913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.068935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.068958] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.068981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.069000] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.069020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.069040] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.069058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.069076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.069093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.069109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.069114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.069130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.069134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.069151] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.069167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.069183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.069199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.069218] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.069241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.069265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.069289] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.069312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.069337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.069362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.069418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.069438] [drm:intel_power_well_enable [i915]] enabling display
>[  931.069509] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.069565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.069597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.069626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.069654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.069682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.069711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.069743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.069774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.069807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.070051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.070071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.070096] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.070117] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.072164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.072188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.072211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.072235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.073812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.073835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.073858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.075438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.075482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.077343] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.080682] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.080778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.080811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.080852] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.080964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.081008] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.081075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.131032] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.131073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.131112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.131159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.131200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.131243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.131284] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.131325] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.131366] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.131402] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.131442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.131505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.131559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.131572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.131620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.131665] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.131711] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.131753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.131803] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.131845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.131896] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.131943] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.131986] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.132040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.132094] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.132255] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.132319] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.132410] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.149525] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.149568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.149613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.149653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.149693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.149733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.149772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.149811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.149854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.149896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.149938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.149977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.150016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.150072] [drm:intel_power_well_disable [i915]] disabling display
>[  931.150118] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.150159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.150201] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.150243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.150276] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.150863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.150887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.150912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.150941] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.150966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.150993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.151019] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.151045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.151072] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.151098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.151123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.151129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.151154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.151158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.151184] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.151210] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.151236] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.151261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.151287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.151312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.151339] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.151365] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.151391] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.151418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.151450] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.151559] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.151588] [drm:intel_power_well_enable [i915]] enabling display
>[  931.151615] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.151668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.151698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.151728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.151755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.151784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.151813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.151846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.151879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.151912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.151940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.151968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.152004] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.152036] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.154098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.154120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.154138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.154157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.155711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.155731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.155749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.157312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.157333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.159194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.162538] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.162628] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.162661] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.162703] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.162851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.162917] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.163016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.212879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.212920] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.212959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.213001] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.213035] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.213071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.213107] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.213141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.213174] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.213205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.213235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.213243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.213273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.213279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.213310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.213340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.213369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.213399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.213434] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.213527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.213573] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.213616] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.213657] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.213705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.213756] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.213915] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.213978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.214310] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.230347] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.230385] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.230425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.230457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.230567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.230734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.230763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.230796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.230831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.230862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.230893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.230920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.230949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.230997] [drm:intel_power_well_disable [i915]] disabling display
>[  931.231037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.231066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.231098] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.231128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.231159] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.231777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.231799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.231821] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.231844] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.231863] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.231883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.231903] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.231922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.231939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.231956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.231973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.231977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.231993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.231997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.232014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.232037] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.232060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.232083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.232107] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.232130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.232154] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.232178] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.232201] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.232226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.232251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.232307] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.232327] [drm:intel_power_well_enable [i915]] enabling display
>[  931.232346] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.232383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.232407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.232430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.232508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.232543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.232577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.232612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.232646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.232680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.232707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.232737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.232773] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.232803] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.234865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.234885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.234904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.234923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.236502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.236522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.236541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.238114] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.238136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.240004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.243302] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.243392] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.243432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.243567] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.243729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.243794] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.243890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.293693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.293737] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.293781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.293827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.293868] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.293910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.293952] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.293993] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.294035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.294071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.294111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.294119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.294159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.294165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.294207] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.294242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.294283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.294321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.294362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.294403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.294445] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.294552] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.294605] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.294664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.294722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.294887] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.294949] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.295051] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.312124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.312161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.312202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.312241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.312281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.312321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.312360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.312399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.312442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.312567] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.312622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.312666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.312696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.312733] [drm:intel_power_well_disable [i915]] disabling display
>[  931.312760] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.312781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.312804] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.312826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.312844] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.313237] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.313258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.313280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.313304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.313322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.313342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.313362] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.313393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.313412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.313432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.313496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.313504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.313533] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.313541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.313571] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.313597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.313618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.313636] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.313659] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.313678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.313707] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.313734] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.313762] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.313791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.313821] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.313903] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.313935] [drm:intel_power_well_enable [i915]] enabling display
>[  931.313966] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.314022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.314056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.314088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.314119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.314141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.314162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.314189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.314217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.314244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.314269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.314294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.314321] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.314347] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.316411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.316435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.316506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.316529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.318099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.318121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.318140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.319693] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.319714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.321595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.324916] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.324962] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.324981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.325007] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.325099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.325138] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.325197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.375200] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.375240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.375280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.375321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.375355] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.375390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.375426] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.375529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.375579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.375631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.375679] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.375692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.375740] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.375753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.375800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.375847] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.375893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.375939] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.375992] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.376038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.376079] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.376108] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.376134] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.376166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.376201] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.376306] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.376346] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.376412] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.393548] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.393585] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.393624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.393657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.393688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.393718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.393747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.393779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.393813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.393845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.393876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.393914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.393953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.394010] [drm:intel_power_well_disable [i915]] disabling display
>[  931.394056] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.394097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.394139] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.394181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.394214] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.394907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.394942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.394986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.395021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.395050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.395081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.395112] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.395141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.395170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.395197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.395225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.395232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.395259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.395265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.395292] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.395320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.395347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.395371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.395401] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.395428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.395501] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.395529] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.395561] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.395597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.395632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.395726] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.395757] [drm:intel_power_well_enable [i915]] enabling display
>[  931.395787] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.395839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.395871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.395901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.395931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.395961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.395992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.396025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.396057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.396089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.396118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.396148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.396181] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.396213] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.398278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.398300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.398319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.398338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.399912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.399932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.399950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.401567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.401589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.403443] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.406766] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.406822] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.406841] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.406868] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.406951] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.406978] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.407018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.457099] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.457139] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.457179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.457226] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.457266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.457308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.457350] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.457391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.457432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.457541] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.457592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.457608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.457658] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.457671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.457721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.457770] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.457820] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.457869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.457923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.457970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.458252] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.458284] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.458314] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.458348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.458383] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.458650] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.458741] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.458884] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.475305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.475342] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.475383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.475416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.475447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.475564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.475609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.475662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.475717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.476002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.476054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.476100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.476145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.476228] [drm:intel_power_well_disable [i915]] disabling display
>[  931.476270] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.476303] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.476337] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.476379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.476402] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.477031] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.477060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.477089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.477120] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.477145] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.477176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.477208] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.477240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.477272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.477300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.477331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.477337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.477368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.477374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.477409] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.477439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.477505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.477535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.477572] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.477605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.477640] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.477671] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.477703] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.477738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.477774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.478114] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.478143] [drm:intel_power_well_enable [i915]] enabling display
>[  931.478171] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.478221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.478251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.478280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.478309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.478336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.478365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.478397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.478427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.478506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.478537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.478568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.478603] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.478778] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.480858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.480879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.480897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.480916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.482484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.482504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.482522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.484081] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.484104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.485989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.489288] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.489373] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.489405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.489461] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.489891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.489919] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.489958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.539623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.539667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.539710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.539757] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.539798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.539840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.539881] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.539921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.539963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.540000] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.540040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.540048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.540088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.540095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.540136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.540177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.540218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.540257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.540299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.540339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.540381] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.540422] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.540521] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.540583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.540635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.541200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.541254] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.541320] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.558366] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.558403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.558444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.558561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.558609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.558661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.558881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.558914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.558957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.559000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.559042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.559081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.559120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.559175] [drm:intel_power_well_disable [i915]] disabling display
>[  931.559221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.559262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.559305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.559347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.559381] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.559997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.560020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.560042] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.560065] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.560084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.560105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.560125] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.560144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.560163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.560180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.560197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.560202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.560224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.560228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.560252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.560273] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.560297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.560320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.560343] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.560366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.560391] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.560414] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.560448] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.560511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.560548] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.560639] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.560909] [drm:intel_power_well_enable [i915]] enabling display
>[  931.560939] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.560993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.561023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.561053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.561081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.561110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.561139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.561171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.561203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.561235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.561261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.561289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.561319] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.561350] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.563418] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.563460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.563480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.563499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.565067] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.565091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.565114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.566667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.566689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.568544] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.571768] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.571821] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.571853] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.571894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.571992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.572032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.572088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.622089] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.622126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.622163] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.622202] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.622233] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.622266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.622299] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.622330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.622360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.622389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.622417] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.622484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.622530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.622547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.622597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.622645] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.622693] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.622741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.622794] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.622842] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.622894] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.622941] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.622989] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.623044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.623088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.623195] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.623235] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.623300] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.640397] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.640435] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.640560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.640607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.640659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.640702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.640748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.640793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.640844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.640894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.640943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.640984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.641028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.641112] [drm:intel_power_well_disable [i915]] disabling display
>[  931.641175] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.641223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.641274] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.641323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.641372] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.641750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.641773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.641797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.641822] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.641842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.641871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.641891] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.641910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.641928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.641945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.641962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.641966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.641983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.641987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.642004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.642026] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.642049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.642072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.642096] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.642119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.642143] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.642167] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.642190] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.642214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.642240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.642296] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.642316] [drm:intel_power_well_enable [i915]] enabling display
>[  931.642336] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.642372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.642396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.642419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.642490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.642526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.642557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.642592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.642625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.642660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.642687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.642716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.642752] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.642781] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.644848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.644869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.644887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.644906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.646489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.646509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.646531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.648099] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.648120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.649995] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.653314] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.653379] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.653418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.653534] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.653757] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.653797] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.653837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.703636] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.703676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.703716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.703756] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.703789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.703824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.703860] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.703893] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.703926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.703966] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.704006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.704014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.704054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.704061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.704103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.704144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.704185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.704225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.704266] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.704306] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.704349] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.704389] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.704430] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.704528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.704592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.705116] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.705157] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.705222] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.721324] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.721361] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.721402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.721436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.721547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.721592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.721643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.721689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.721743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.722031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.722066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.722095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.722123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.722175] [drm:intel_power_well_disable [i915]] disabling display
>[  931.722216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.722247] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.722281] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.722321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.722340] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.722837] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.722870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.722901] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.722925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.722944] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.722964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.722984] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.723006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.723030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.723051] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.723074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.723079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.723102] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.723106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.723130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.723154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.723177] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.723199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.723223] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.723246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.723270] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.723293] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.723316] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.723341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.723366] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.723433] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.723494] [drm:intel_power_well_enable [i915]] enabling display
>[  931.723526] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.723581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.723612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.723644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.723673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.723704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.723733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.723767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.723801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.723835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.723862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.723892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.723925] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.723957] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.726038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.726062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.726085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.726109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.727695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.727717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.727736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.729289] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.729310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.731178] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.734563] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.734655] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.734681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.734722] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.734837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.734890] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.734971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.784947] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.784991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.785034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.785081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.785121] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.785164] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.785206] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.785246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.785288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.785325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.785366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.785374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.785414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.785481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.785537] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.785586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.785631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.785677] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.785725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.785770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.785817] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.785859] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.785901] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.785953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.785988] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.786093] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.786134] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.786199] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.803215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.803253] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.803294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.803328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.803367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.803408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.803512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.803560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.803617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.803666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.803719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.803765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.803811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.803896] [drm:intel_power_well_disable [i915]] disabling display
>[  931.803941] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.803974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.804015] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.804058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.804093] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.804493] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.804528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.804564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.804602] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.804633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.804666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.804697] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.804718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.804738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.804757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.804776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.804781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.804799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.804803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.804822] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.804846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.804872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.804897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.804922] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.804947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.804974] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.804999] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.805025] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.805051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.805079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.805141] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.805163] [drm:intel_power_well_enable [i915]] enabling display
>[  931.805185] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.805224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.805250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.805275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.805301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.805326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.805351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.805379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.805406] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.805475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.805508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.805541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.805579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.805612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.807695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.807717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.807736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.807756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.809324] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.809344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.809362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.810944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.810966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.812841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.816182] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.816275] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.816308] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.816350] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.816552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.816595] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.816660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.866554] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.866593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.866632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.866674] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.866707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.866743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.866778] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.866811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.866844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.866875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.866905] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.866914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.866943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.866949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.866979] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.867009] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.867044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.867085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.867127] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.867167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.867210] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.867251] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.867292] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.867335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.867379] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.867575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.867644] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.867947] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.884335] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.884373] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.884413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.884534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.884588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.884640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.884840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.884873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.884909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.884942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.884973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.885001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.885039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.885095] [drm:intel_power_well_disable [i915]] disabling display
>[  931.885141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.885190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.885213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.885235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.885254] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.885869] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.885894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.885918] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.885945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.885968] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.885992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.886014] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.886038] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.886061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.886081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.886104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.886109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.886132] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.886136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.886160] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.886180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.886204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.886225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.886249] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.886271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.886296] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.886319] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.886343] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.886368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.886393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.886529] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.886802] [drm:intel_power_well_enable [i915]] enabling display
>[  931.886832] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.886886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.886919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.886951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.886983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.887013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.887046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.887080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.887113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.887146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.887175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.887205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.887240] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.887272] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.889330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.889353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.889373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.889393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.890995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.891015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.891033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.892612] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.892635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.894502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.897869] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.897936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.897968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.898011] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.898121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.898163] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.898223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.948174] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.948214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.948253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.948294] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.948328] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.948363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.948405] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.948509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.948561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.948615] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.948663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.948678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.948725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.948738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.948787] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.948834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.948881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.948929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.948980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.949025] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.949069] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.949114] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.949158] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.949210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.949263] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.949436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  931.949619] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  931.949779] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  931.966330] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  931.966368] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  931.966408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.966517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.966569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.966620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.966670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.966721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.966775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.966826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.966877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.966923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.966968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.967053] [drm:intel_power_well_disable [i915]] disabling display
>[  931.967117] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  931.967172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.967205] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.967239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.967269] [drm:intel_power_well_disable [i915]] disabling always-on
>[  931.967726] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  931.967747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  931.967770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  931.967793] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  931.967811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  931.967831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  931.967851] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  931.967870] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  931.967888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  931.967905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  931.967928] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  931.967933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.967956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  931.967960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  931.967984] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  931.968008] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  931.968031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  931.968054] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  931.968077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  931.968101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  931.968125] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  931.968148] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  931.968172] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  931.968196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  931.968221] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  931.968278] [drm:intel_power_well_enable [i915]] enabling always-on
>[  931.968298] [drm:intel_power_well_enable [i915]] enabling display
>[  931.968318] [drm:hsw_set_power_well [i915]] Enabling power well
>[  931.968354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  931.968378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  931.968401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  931.968476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  931.968508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  931.968543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  931.968580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  931.968615] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  931.968649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  931.968680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  931.968710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  931.968746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  931.968779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  931.970849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  931.970873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  931.970896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.970920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  931.972540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  931.972562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  931.972580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  931.974137] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  931.974158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  931.976020] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  931.979336] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  931.979412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  931.979492] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  931.979552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  931.979828] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  931.979864] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  931.979915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.029662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.029702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.029742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.029783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.029823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.029865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.029906] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.029947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.029988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.030024] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.030065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.030073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.030113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.030120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.030161] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.030198] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.030238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.030276] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.030317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.030358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.030400] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.030506] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.030558] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.030617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.030676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.031053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.031095] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.031164] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.047305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.047342] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.047382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.047414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.047533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.047579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.047630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.047680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.047954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.047990] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.048030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.048070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.048109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.048171] [drm:intel_power_well_disable [i915]] disabling display
>[  932.048197] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.048219] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.048241] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.048262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.048279] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.048746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.048781] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.048815] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.048860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.048889] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.048920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.048951] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.048980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.049010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.049038] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.049065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.049072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.049098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.049105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.049131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.049158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.049182] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.049209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.049238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.049265] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.049291] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.049318] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.049345] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.049375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.049417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.049539] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.049570] [drm:intel_power_well_enable [i915]] enabling display
>[  932.049600] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.049652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.049684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.049715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.049745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.049776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.049807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.049841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.049873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.049906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.049935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.049964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.049998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.050029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.052091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.052113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.052135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.052160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.053724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.053745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.053764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.055311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.055332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.057195] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.060501] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.060563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.060583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.060608] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.060692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.060719] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.060760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.110801] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.110841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.110881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.110923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.110955] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.110990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.111026] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.111060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.111093] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.111124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.111154] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.111162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.111192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.111198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.111228] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.111257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.111286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.111315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.111350] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.111380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.111411] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.111504] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.111549] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.111598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.111647] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.111777] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.111809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.111865] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.128953] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.128991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.129031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.129065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.129096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.129126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.129156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.129193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.129237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.129278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.129320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.129359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.129398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.129546] [drm:intel_power_well_disable [i915]] disabling display
>[  932.129732] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.129771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.129810] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.129848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.129877] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.130341] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.130362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.130384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.130413] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.130482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.130505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.130526] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.130548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.130568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.130587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.130605] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.130610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.130628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.130632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.130651] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.130669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.130687] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.130704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.130729] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.130754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.130781] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.130807] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.130833] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.130860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.130889] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.130951] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.130972] [drm:intel_power_well_enable [i915]] enabling display
>[  932.130994] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.131033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.131059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.131085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.131111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.131136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.131162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.131190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.131218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.131246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.131271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.131298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.131326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.131352] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.133395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.133437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.133456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.133476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.135036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.135057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.135075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.136637] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.136658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.138538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.141873] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.141974] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.142007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.142049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.142195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.142270] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.142330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.192235] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.192276] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.192316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.192359] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.192400] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.192498] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.192549] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.192594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.192639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.192688] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.193051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.193063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.193106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.193116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.193159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.193216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.193275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.193335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.193394] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.193508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.193556] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.193602] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.193644] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.193696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.193949] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.194055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.194097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.194186] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.211093] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.211130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.211170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.211203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.211234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.211264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.211293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.211331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.211375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.211417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.211528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.211580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.211632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.211720] [drm:intel_power_well_disable [i915]] disabling display
>[  932.211785] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.211836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.211890] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.211950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.211981] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.212354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.212377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.212400] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.212473] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.212504] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.212537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.212571] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.212603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.212634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.212665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.212694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.212703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.212731] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.212738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.212767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.212796] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.212825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.212851] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.212883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.212913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.212944] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.212970] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.213000] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.213033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.213068] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.213137] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.213168] [drm:intel_power_well_enable [i915]] enabling display
>[  932.213198] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.213251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.213282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.213313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.213343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.213373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.213404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.213465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.213501] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.213534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.213564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.213595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.213630] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.213662] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.215734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.215756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.215775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.215794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.217364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.217384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.217409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.219055] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.219076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.220943] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.224239] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.224311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.224331] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.224357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.224498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.224541] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.224606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.274588] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.274628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.274668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.274710] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.274744] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.274780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.274821] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.274862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.274904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.274940] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.274981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.274989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.275029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.275036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.275077] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.275114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.275155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.275191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.275233] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.275273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.275315] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.275355] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.275396] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.275489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.275524] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.276092] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.276162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.276301] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.293392] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.293470] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.293514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.293555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.293595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.293635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.293674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.293713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.293756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.293799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.293841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.293883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.293904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.293937] [drm:intel_power_well_disable [i915]] disabling display
>[  932.293962] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.293982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.294004] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.294024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.294041] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.294410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.294495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.294529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.294568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.294598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.294633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.294664] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.294696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.294725] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.294756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.294782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.294792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.294819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.294827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.294857] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.294884] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.294914] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.294940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.294974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.295001] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.295360] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.295388] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.295445] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.295476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.295649] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.295745] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.295774] [drm:intel_power_well_enable [i915]] enabling display
>[  932.295801] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.295849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.295878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.295904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.295931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.295956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.295984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.296014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.296044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.296073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.296097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.296123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.296154] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.296180] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.298253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.298275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.298294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.298313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.299887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.299907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.299924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.301526] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.301546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.303405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.306766] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.306860] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.306900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.306952] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.307064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.307121] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.307165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.357165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.357206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.357246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.357288] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.357321] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.357357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.357393] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.357494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.357545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.357595] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.357643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.357656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.357703] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.357719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.357766] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.357811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.357860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.357906] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.357957] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.358003] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.358052] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.358097] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.358138] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.358188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.358241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.358406] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.358495] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.358562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.375589] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.375628] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.375673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.375713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.375753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.375793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.375832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.375870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.375913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.375955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.375997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.376035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.376074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.376130] [drm:intel_power_well_disable [i915]] disabling display
>[  932.376176] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.376217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.376259] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.376301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.376334] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.376965] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.377000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.377036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.377074] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.377105] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.377138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.377172] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.377205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.377236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.377266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.377296] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.377305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.377334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.377341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.377370] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.377400] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.377454] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.377486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.377517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.377548] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.377581] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.377612] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.377642] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.377677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.377712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.377806] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.377837] [drm:intel_power_well_enable [i915]] enabling display
>[  932.377867] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.377919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.377951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.377981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.378009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.378038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.378069] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.378103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.378136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.378168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.378197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.378227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.378258] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.378290] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.380343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.380365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.380385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.380445] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.382025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.382049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.382073] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.383650] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.383672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.385561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.388907] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.388998] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.389031] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.389077] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.389197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.389250] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.389330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.439253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.439294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.439333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.439374] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.439407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.439506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.439556] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.439602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.439647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.439695] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.439738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.439752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.439797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.439808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.439840] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.439869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.439898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.439926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.439959] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.439988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.440018] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.440046] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.440074] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.440107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.440144] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.440251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.440292] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.440368] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.457384] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.457455] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.457496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.457529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.457560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.457590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.457619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.457650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.457684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.457716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.457756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.457781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.457806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.457853] [drm:intel_power_well_disable [i915]] disabling display
>[  932.457889] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.457917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.457953] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.457991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.458021] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.458663] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.458714] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.458772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.458811] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.458841] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.458865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.458889] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.458910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.458930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.458950] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.458974] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.458981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.459006] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.459011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.459037] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.459062] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.459089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.459114] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.459140] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.459166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.459192] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.459219] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.459244] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.459272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.459300] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.459363] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.459388] [drm:intel_power_well_enable [i915]] enabling display
>[  932.459445] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.459499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.459531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.459560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.459588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.459616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.459645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.459677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.459707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.459741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.459770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.459797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.459830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.459862] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.461907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.461930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.461950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.461975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.464590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.464612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.464636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.467234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.467257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.470164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.473219] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.473282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.473304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.473333] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.473608] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.473640] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.473683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.523568] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.523612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.523655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.523702] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.523743] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.523785] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.523825] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.523865] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.523907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.523943] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.523983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.523993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.524033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.524040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.524081] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.524117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.524158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.524196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.524237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.524282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.524317] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.524347] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.524376] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.524455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.524510] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.524654] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.524707] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.525031] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.541310] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.541347] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.541387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.541496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.541544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.541594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.541646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.541692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.541952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.541984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.542015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.542042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.542069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.542119] [drm:intel_power_well_disable [i915]] disabling display
>[  932.542157] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.542187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.542220] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.542249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.542276] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.542931] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.542953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.542975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.542998] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.543016] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.543036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.543059] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.543083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.543107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.543128] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.543151] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.543155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.543178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.543182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.543206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.543227] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.543250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.543273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.543297] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.543320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.543344] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.543367] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.543402] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.543468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.543503] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.543597] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.543629] [drm:intel_power_well_enable [i915]] enabling display
>[  932.543923] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.543978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.544008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.544038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.544066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.544094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.544122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.544154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.544186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.544217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.544243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.544272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.544302] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.544332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.547536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.547562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.547590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.547619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.551478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.551514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.551545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.554197] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.554229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.557202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.560510] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.560587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.560619] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.560661] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.560772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.560815] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.560876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.610846] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.610887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.610926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.610967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.611001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.611037] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.611073] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.611107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.611140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.611171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.611202] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.611209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.611239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.611246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.611276] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.611306] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.611336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.611365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.611400] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.611486] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.611540] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.611582] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.611629] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.611682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.611737] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.612352] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.612458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.612643] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.629684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.629722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.629762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.629796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.629835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.629875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.629915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.629954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.629997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.630039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.630081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.630120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.630159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.630216] [drm:intel_power_well_disable [i915]] disabling display
>[  932.630261] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.630303] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.630345] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.630388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.630495] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.631204] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.631226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.631248] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.631271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.631289] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.631310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.631330] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.631349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.631372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.631403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.631468] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.631475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.631504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.631511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.631541] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.631569] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.631597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.631623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.631654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.631680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.631709] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.631734] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.631762] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.631794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.631827] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.631918] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.631949] [drm:intel_power_well_enable [i915]] enabling display
>[  932.631978] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.632028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.632058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.632084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.632112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.632138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.632167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.632199] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.632230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.632261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.632287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.632314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.632344] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.632374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.635596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.635630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.635658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.635686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.639570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.639607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.639639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.642295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.642328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.645306] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.648629] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.648691] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.648723] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.648765] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.648876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.648919] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.648981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.698981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.699035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.699088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.699143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.699190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.699247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.699301] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.699356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.699411] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.699549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.699618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.699640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.699705] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.699723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.699790] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.699855] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.699921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.699984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.700056] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.700119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.700679] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.700716] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.700748] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.700785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.700823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.700918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.700959] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.701046] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.716033] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.716070] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.716111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.716143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.716173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.716202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.716230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.716261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.716295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.716335] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.716377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.716474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.716520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.716605] [drm:intel_power_well_disable [i915]] disabling display
>[  932.716660] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.716695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.716731] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.716764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.716794] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.717149] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.717172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.717195] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.717220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.717240] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.717265] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.717291] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.717316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.717342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.717365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.717395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.717434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.717458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.717462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.717485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.717504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.717524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.717542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.717564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.717583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.717604] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.717629] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.717656] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.717683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.717711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.717759] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.717781] [drm:intel_power_well_enable [i915]] enabling display
>[  932.717803] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.717842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.717869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.717895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.717921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.717947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.717973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.718000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.718028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.718056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.718081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.718107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.718133] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.718159] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.720206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.720229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.720252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.720276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.724157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.724193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.724224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.726966] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.726988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.730008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.733248] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.733325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.733345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.733371] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.733702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.733729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.733768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.783600] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.783640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.783682] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.783729] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.783770] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.783811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.783852] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.783893] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.783935] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.783975] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.784015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.784023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.784062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.784069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.784111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.784147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.784188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.784228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.784270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.784310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.784351] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.784392] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.784487] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.784523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.784562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.784669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.784710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.784777] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.801920] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.801958] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.801998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.802032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.802064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.802094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.802133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.802172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.802215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.802258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.802299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.802338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.802377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.802516] [drm:intel_power_well_disable [i915]] disabling display
>[  932.802583] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.802639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.802695] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.802749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.802799] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.803262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.803283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.803305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.803328] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.803346] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.803366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.803440] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.803470] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.803503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.803535] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.803568] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.803578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.803607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.803615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.803645] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.803675] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.803706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.803735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.803765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.803795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.803825] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.803854] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.803880] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.803911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.803945] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.804038] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.804069] [drm:intel_power_well_enable [i915]] enabling display
>[  932.804099] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.804150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.804182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.804213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.804244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.804274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.804304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.804338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.804370] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.804434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.804466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.804495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.804531] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.804563] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.806625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.806649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.806672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.806695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.810574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.810611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.810643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.813296] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.813328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.816300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.819642] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.819737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.819769] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.819810] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.819919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.819962] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.820024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.869970] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.870011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.870053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.870100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.870140] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.870183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.870223] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.870264] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.870306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.870342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.870382] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.870445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.870500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.870516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.870572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.870624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.870675] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.870723] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.870777] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.870826] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.870879] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.870927] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.870969] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.871025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.871079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.871240] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.871302] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.871402] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.888501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.888539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.888579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.888612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.888644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.888674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.888703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.888735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.888769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.888801] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.888832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.888870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.888909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.888965] [drm:intel_power_well_disable [i915]] disabling display
>[  932.889003] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.889037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.889073] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.889108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.889136] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.889714] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.889761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.889795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.889830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.889856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.889885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.889914] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.889948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.889968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.889986] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.890005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.890010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.890029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.890033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.890052] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.890071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.890089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.890107] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.890128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.890146] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.890166] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.890184] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.890202] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.890223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.890246] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.890307] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.890325] [drm:intel_power_well_enable [i915]] enabling display
>[  932.890343] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.890379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.890438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.890467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.890495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.890522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.890551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.890583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.890613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.890643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.890670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.890696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.890727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.890757] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.892820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.892841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.892859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.892879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.896780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.896818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.896849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.899511] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.899543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.902547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.905896] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.905985] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.906018] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.906059] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.906168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.906211] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.906262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.956249] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.956289] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.956329] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.956370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.956463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.956522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.956570] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.956619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.956664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.956711] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.956751] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.956766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.956808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.956818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.956862] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.956902] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.956946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.956985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.957034] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.957074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.957119] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.957159] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.957201] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.957247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.957298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.957489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  932.957560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  932.957639] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  932.974686] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  932.974728] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  932.974773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.974814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.974854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.974894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.974933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.974972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.975015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.975057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.975099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.975138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.975177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.975233] [drm:intel_power_well_disable [i915]] disabling display
>[  932.975279] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  932.975320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.975362] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.975484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.975535] [drm:intel_power_well_disable [i915]] disabling always-on
>[  932.976108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  932.976132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  932.976156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  932.976181] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  932.976201] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  932.976223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  932.976245] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  932.976265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  932.976285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  932.976304] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  932.976322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  932.976327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.976345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  932.976349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  932.976368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  932.976424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  932.976456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  932.976483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  932.976517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  932.976544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  932.976575] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  932.976602] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  932.976631] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  932.976661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  932.976695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  932.976789] [drm:intel_power_well_enable [i915]] enabling always-on
>[  932.976820] [drm:intel_power_well_enable [i915]] enabling display
>[  932.976849] [drm:hsw_set_power_well [i915]] Enabling power well
>[  932.976899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  932.976930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  932.976957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  932.976986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  932.977012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  932.977042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  932.977074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  932.977106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  932.977137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  932.977163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  932.977190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  932.977220] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  932.977250] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  932.979331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  932.979353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  932.979377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.979461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  932.983343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  932.983381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  932.983491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  932.986200] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  932.986231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  932.989239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  932.992550] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  932.992619] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  932.992646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  932.992681] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  932.992776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  932.992812] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  932.992869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.042878] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.042919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.042958] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.043000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.043033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.043069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.043106] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  933.043140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  933.043173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.043205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.043235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.043243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.043273] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.043280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.043310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.043340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.043370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.043457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.043515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.043557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.043611] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.043658] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  933.043696] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  933.043736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.043781] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  933.043915] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  933.043965] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.044280] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  933.060271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  933.060313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.060358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.060472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.060523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.060573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.060617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.060667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.060719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.060769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.060818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.060859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.060902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.060985] [drm:intel_power_well_disable [i915]] disabling display
>[  933.061027] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.061058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.061090] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.061123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.061153] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.061582] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.061613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.061635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.061658] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.061676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.061696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.061717] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  933.061735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  933.061753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.061776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.061799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.061804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.061827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.061831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.061855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.061878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.061901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.061924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.061947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.061970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.061995] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.062018] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  933.062041] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  933.062066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.062091] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  933.062147] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.062166] [drm:intel_power_well_enable [i915]] enabling display
>[  933.062186] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.062222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.062246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.062270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.062293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.062317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.062340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.062376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.062439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.062476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.062505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.062536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.062574] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  933.062604] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.065805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.065842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.065876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.065912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.069836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.069871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.069901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.072617] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.072651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.075649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.078988] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  933.079087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.079120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  933.079162] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.079274] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.079317] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.079369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.129353] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.129416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.129456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.129498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.129531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.129568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.129604] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  933.129639] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  933.129672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.129704] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.129735] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.129743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.129772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.129779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.129809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.129839] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.129880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.129920] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.129962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.130009] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.130057] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.130096] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  933.130136] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  933.130177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.130220] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  933.130333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  933.130382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.130747] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  933.147253] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  933.147290] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.147330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.147363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.147472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.147521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.147569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.147615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.147669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.147719] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.147770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.147811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.147854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.147936] [drm:intel_power_well_disable [i915]] disabling display
>[  933.148000] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.148032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.148065] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.148096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.148128] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.148529] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.148553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.148577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.148609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.148628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.148648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.148668] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  933.148687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  933.148710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.148731] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.148754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.148759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.148782] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.148786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.148810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.148830] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.148854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.148876] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.148899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.148922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.148946] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.148970] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  933.148993] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  933.149018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.149043] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  933.149101] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.149121] [drm:intel_power_well_enable [i915]] enabling display
>[  933.149140] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.149176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.149201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.149224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.149248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.149271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.149294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.149319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.149344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.149380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.149444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.149473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.149511] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  933.149541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.152756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.152791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.152820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.152850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.156737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.156774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.156806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.159494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.159528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.162585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.165933] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  933.166023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.166062] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  933.166113] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.166231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.166280] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.166347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.216279] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.216319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.216359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.216465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.216517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.216685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.216722] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  933.216754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  933.216785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.216823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.216862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.216872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.216911] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.216919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.216960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.217001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.217041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.217080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.217121] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.217161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.217203] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.217243] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  933.217284] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  933.217326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.217371] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  933.218007] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  933.218085] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.218229] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  933.233267] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  933.233305] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.233345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.233379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.233491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.233536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.233581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.233625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.233677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.233726] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.233776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.233817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.233860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.233939] [drm:intel_power_well_disable [i915]] disabling display
>[  933.233979] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.234010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.234043] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.234074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.234106] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.234551] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.234575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.234599] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.234634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.234656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.234681] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.234704] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  933.234727] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  933.234751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.234771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.234794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.234799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.234822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.234826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.234850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.234870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.234894] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.234915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.234938] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.234961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.234986] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.235009] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  933.235033] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  933.235057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.235082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  933.235139] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.235159] [drm:intel_power_well_enable [i915]] enabling display
>[  933.235179] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.235215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.235239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.235263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.235286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.235310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.235333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.235369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.235433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.235471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.235501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.235532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.235569] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  933.235599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.237664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.237685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.237703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.237721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.241583] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.241621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.241654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.244303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.244335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.247366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.250737] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  933.250832] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.250872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  933.250923] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.251075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.251145] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.251252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.301067] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.301110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.301154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.301200] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.301241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.301283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.301323] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  933.301364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  933.301471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.301518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.301564] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.301578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.301621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.301633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.301677] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.301724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.301768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.301810] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.301863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.301908] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.301957] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.302002] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  933.302048] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  933.302103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.302157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  933.302277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  933.302318] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.302554] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  933.319615] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  933.319652] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.319692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.319725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.319756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.319786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.319815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.319846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.319880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.319912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.319943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.319972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.320000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.320057] [drm:intel_power_well_disable [i915]] disabling display
>[  933.320092] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.320117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.320145] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.320172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.320196] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.320341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.320476] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.320525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.320567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.320611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.320651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.320690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.320732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.320775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.320818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.320860] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.320902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.320940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.320978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.321032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  933.321076] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.321411] [drm:drm_mode_addfb2] [FB:58]
>[  933.321466] [drm:drm_mode_addfb2] [FB:78]
>[  933.350640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  933.350744] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  933.350815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  933.350883] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  933.350895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  933.350953] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.350975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.350998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.351022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.351044] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.351069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.351092] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.351116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.351140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.351161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.351184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.351188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.351211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.351215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.351239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.351259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.351283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.351303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.351326] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.351350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.351429] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  933.351461] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.351491] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.351521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.351555] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.354842] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.354863] [drm:intel_power_well_enable [i915]] enabling display
>[  933.354882] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.354920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.354942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.354963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.354983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.355001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.355021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.355043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.355064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.355086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.355110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.355135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.355161] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.355185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.357240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.357265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.357288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.357312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.361214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.361252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.361283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.363982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.364017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.367019] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.370304] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.370467] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.370510] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.370573] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.387185] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.387236] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.387303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.404125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.404163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.404200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.404243] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.404282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.404323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.404362] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.404477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.404527] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.404578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.404621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.404636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.404682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.404695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.404746] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.404785] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.404824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.404861] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.404906] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.404943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.404984] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.405020] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.405059] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.405100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.405147] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.405285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  933.405337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.405470] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  933.422167] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  933.422204] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.422244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.422277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.422316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.422356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.422452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.422510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.422564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.422620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.422673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.422715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.422762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.422846] [drm:intel_power_well_disable [i915]] disabling display
>[  933.422909] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.422957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.423008] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.423057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.423104] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.423337] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.423361] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.423445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.423483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.423513] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.423548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.423579] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.423612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.423640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.423670] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.423697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.423705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.423732] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.423740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.423768] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.423794] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.423821] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.423846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.423878] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.423903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.423933] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.423959] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.423986] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.424015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.424048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.424142] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.424173] [drm:intel_power_well_enable [i915]] enabling display
>[  933.424203] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.424254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.424284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.424311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.424340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.424391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.424423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.424459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.424492] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.424527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.424554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.424582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.424617] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.424647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.426708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.426729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.426748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.426767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.430647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.430684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.430715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.433440] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.433475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.436485] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.439808] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.439866] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.439895] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.439932] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.440029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.440068] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.440123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.490296] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.490377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.490573] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.490707] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.490799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.490904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.490998] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.491097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.491185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.491279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.491361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.491450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.491497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.491510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.491557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.491600] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.491645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.491687] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.491735] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.491777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.491824] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.491864] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.491908] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.491958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.492012] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.492171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  933.492232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.492330] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  933.507445] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  933.507482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.507521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.507554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.507586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.507624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.507663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.507703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.507746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.507787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.507829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.507868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.507906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.507963] [drm:intel_power_well_disable [i915]] disabling display
>[  933.508009] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.508050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.508091] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.508134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.508176] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.508587] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.508620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.508655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.508691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.508719] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.508751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.508781] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.508811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.508839] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.508868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.508894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.508901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.508928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.508934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.508963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.508989] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.509017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.509042] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.509073] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.509099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.509128] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.509153] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.509180] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.509210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.509244] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.509332] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.509384] [drm:intel_power_well_enable [i915]] enabling display
>[  933.509414] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.509467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.509500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.509528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.509558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.509586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.509617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.509651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.509684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.509717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.509744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.509774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.509808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.509838] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.511950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.511970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.511989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.512008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.515945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.515983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.516015] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.518709] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.518744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.521725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.525044] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.525111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.525144] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.525186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.525295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.525338] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.525477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.575373] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.575440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.575484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.575530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.575571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.575613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.575653] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.575694] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.575736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.575772] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.575812] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.575820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.575860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.575867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.575908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.575945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.575985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.576022] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.576064] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.576104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.576147] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.576188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.576226] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.576269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.576313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.576501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  933.576566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.576880] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  933.593262] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  933.593299] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.593339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.593455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.593502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.593551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.593595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.593642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.593696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.593746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.593795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.593837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.593880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.593965] [drm:intel_power_well_disable [i915]] disabling display
>[  933.594027] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.594076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.594136] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.594168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.594199] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.594630] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.594652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.594674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.594696] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.594715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.594734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.594754] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.594777] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.594801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.594822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.594845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.594850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.594873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.594877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.594901] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.594922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.594945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.594968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.594992] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.595015] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.595039] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.595063] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.595086] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.595110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.595135] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.595191] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.595211] [drm:intel_power_well_enable [i915]] enabling display
>[  933.595231] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.595267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.595291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.595314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.595338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.595421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.595452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.595486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.595517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.595548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.595575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.595602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.595634] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.595663] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.597726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.597747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.597766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.597785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.600551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.600585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.600616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.603318] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.603349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.606422] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.609641] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.609688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.609708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.609733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.609818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.609846] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.609887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.659941] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.659982] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.660021] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.660063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.660097] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.660132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.660168] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.660203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.660236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.660268] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.660298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.660306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.660336] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.660398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.660446] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.660490] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.660532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.660574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.660621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.660663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.660711] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.660753] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.660792] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.660823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.660859] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.660962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  933.661003] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.661069] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  933.678108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  933.678145] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.678185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.678218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.678248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.678278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.678307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.678345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.678462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.678517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.678566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.678614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.678660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.678744] [drm:intel_power_well_disable [i915]] disabling display
>[  933.678812] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.678860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.678897] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.678932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.678962] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.679320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.679346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.679411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.679446] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.679475] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.679507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.679538] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.679571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.679600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.679628] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.679658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.679667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.679695] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.679703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.679732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.679761] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.679790] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.679819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.679844] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.679861] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.679882] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.679899] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.679917] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.679939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.679962] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.680022] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.680041] [drm:intel_power_well_enable [i915]] enabling display
>[  933.680058] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.680092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.680113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.680131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.680149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.680174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.680200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.680229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.680257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.680285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.680310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.680336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.680397] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.680427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.682491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.682513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.682531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.682550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.686420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.686455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.686491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.689206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.689243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.692264] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.695555] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.695635] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.695655] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.695680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.695763] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.695791] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.695832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.745930] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.745971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.746010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.746052] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.746086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.746122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.746158] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.746192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.746225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.746257] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.746287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.746295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.746325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.746387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.746436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.746479] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.746521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.746562] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.746611] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.746653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.746704] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.746730] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.746758] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.746792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.746826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.746932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  933.746973] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.747039] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  933.764086] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  933.764123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.764163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.764197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.764228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.764258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.764287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.764318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.764353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.764466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.764519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.764747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.764777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.764830] [drm:intel_power_well_disable [i915]] disabling display
>[  933.764871] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.764904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.764939] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.764971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.765002] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.765471] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.765498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.765524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.765560] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.765580] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.765602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.765623] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.765642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.765660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.765678] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.765694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.765699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.765715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.765719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.765736] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.765753] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.765769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.765791] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.765815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.765838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.765862] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.765886] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.765909] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.765933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.765958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.766014] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.766034] [drm:intel_power_well_enable [i915]] enabling display
>[  933.766054] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.766090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.766114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.766137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.766161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.766184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.766207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.766233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.766257] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.766282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.766305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.766328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.766412] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.766445] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.768511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.768535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.768558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.768582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.771264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.771301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.771335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.774102] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.774138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.777126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.780454] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.780496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.780515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.780541] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.780624] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.780655] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.780701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.830765] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.830806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.830845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.830886] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.830919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.830954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.830990] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.831024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.831057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.831088] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.831127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.831135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.831176] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.831183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.831224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.831263] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.831304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.831341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.831446] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.831495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.831546] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.831597] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.831641] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.831690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.831742] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.831859] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  933.831900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.831968] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  933.849087] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  933.849125] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.849165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.849204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.849245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.849284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.849324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.849440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.849499] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.849552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.849604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.849651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.849697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.849754] [drm:intel_power_well_disable [i915]] disabling display
>[  933.849795] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.849829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.849865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.849897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.849928] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.850345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.850473] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.850509] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.850547] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.850579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.850613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.850640] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.850661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.850681] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.850700] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.850718] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.850723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.850741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.850745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.850763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.850781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.850799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.850816] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.850837] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.850855] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.850874] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.850891] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.850916] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.850943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.850970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.851034] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.851056] [drm:intel_power_well_enable [i915]] enabling display
>[  933.851077] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.851116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.851143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.851169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.851194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.851219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.851243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.851271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.851298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.851325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.851388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.851422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.851458] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.851491] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.853558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.853579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.853597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.853616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.857500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.857522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.857541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.860231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.860268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.863266] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.866621] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.866687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.866707] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.866733] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.866814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.866842] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.866883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.916972] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.917012] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.917051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.917092] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.917126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.917161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.917198] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.917239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.917281] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.917321] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.917424] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.917440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.917488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.917502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.917553] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.917602] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.917652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.917701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.917753] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.917802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.917854] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.917899] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.917948] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.917982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.918017] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.918122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  933.918162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  933.918229] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  933.935432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  933.935469] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  933.935509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.935542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.935573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.935603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.935641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.935680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.935723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.935764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.935806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.935845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.935883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.935941] [drm:intel_power_well_disable [i915]] disabling display
>[  933.935986] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  933.936027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.936070] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.936112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.936145] [drm:intel_power_well_disable [i915]] disabling always-on
>[  933.936615] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  933.936651] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  933.936686] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  933.936724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  933.936755] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  933.936788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  933.936822] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  933.936854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  933.936886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  933.936916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  933.936945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  933.936953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.936981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  933.936988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  933.937019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  933.937049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  933.937078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  933.937107] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  933.937137] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  933.937165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  933.937197] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  933.937226] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  933.937255] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  933.937288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  933.937322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  933.937447] [drm:intel_power_well_enable [i915]] enabling always-on
>[  933.937479] [drm:intel_power_well_enable [i915]] enabling display
>[  933.937510] [drm:hsw_set_power_well [i915]] Enabling power well
>[  933.937563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  933.937595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  933.937626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  933.937653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  933.937682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  933.937713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  933.937748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  933.937781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  933.937814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  933.937844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  933.937873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  933.937907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  933.937939] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  933.941133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  933.941163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  933.941188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.941213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  933.945081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  933.945115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  933.945146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  933.947798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  933.947832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  933.950888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  933.954187] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  933.954273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  933.954306] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  933.954414] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  933.954655] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  933.954684] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  933.954735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.004532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.004573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.004613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.004655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.004689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.004724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.004762] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.004803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.004845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.004882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.004923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.004931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.004971] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.004978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.005019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.005056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.005097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.005133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.005175] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.005215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.005258] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.005299] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.005340] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.005448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.005505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.005965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.006006] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.006073] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.023144] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.023181] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.023221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.023254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.023285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.023315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.023434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.023489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.023544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.023597] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.023933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.023965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.023994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.024046] [drm:intel_power_well_disable [i915]] disabling display
>[  934.024087] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.024119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.024154] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.024187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.024216] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.024746] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.024768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.024790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.024814] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.024833] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.024853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.024873] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.024892] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.024910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.024927] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.024944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.024949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.024965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.024969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.024992] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.025016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.025039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.025062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.025086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.025109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.025133] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.025157] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.025180] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.025205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.025229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.025287] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.025306] [drm:intel_power_well_enable [i915]] enabling display
>[  934.025337] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.025426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.025462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.025496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.025529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.025560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.025594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.025629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.025664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.025698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.025729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.025760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.025796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.025829] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.027933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.027957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.027980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.028003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.031901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.031941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.031980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.034712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.034747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.037764] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.041118] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.041202] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.041235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.041276] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.041456] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.041695] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.041735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.091461] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.091501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.091540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.091582] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.091615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.091651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.091687] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.091721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.091754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.091786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.091816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.091824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.091854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.091860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.091890] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.091924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.091965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.092006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.092047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.092086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.092129] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.092170] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.092209] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.092252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.092296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.092498] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.092566] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.092942] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.109247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.109284] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.109324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.109437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.109493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.109543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.109592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.109642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.109851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.109885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.109917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.109945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.109973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.110024] [drm:intel_power_well_disable [i915]] disabling display
>[  934.110065] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.110096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.110130] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.110162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.110190] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.110652] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.110686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.110722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.110760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.110790] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.110832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.110862] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.110891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.110920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.110947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.110971] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.110978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.111004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.111010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.111038] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.111065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.111092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.111116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.111145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.111172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.111201] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.111225] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.111251] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.111281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.111313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.111441] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.111472] [drm:intel_power_well_enable [i915]] enabling display
>[  934.111498] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.111549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.111580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.111611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.111641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.111671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.111702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.111735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.111768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.111800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.111829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.111858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.111892] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.111923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.113999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.114020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.114038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.114057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.116753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.116791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.116823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.119642] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.119679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.122685] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.126029] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.126124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.126157] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.126199] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.126309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.126427] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.126632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.176405] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.176446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.176486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.176527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.176560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.176595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.176631] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.176665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.176698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.176729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.176759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.176767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.176796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.176803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.176833] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.176863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.176902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.176944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.176986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.177026] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.177068] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.177109] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.177149] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.177192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.177236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.177412] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.177480] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.177581] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.194118] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.194155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.194195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.194235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.194275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.194315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.194428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.194481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.194539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.194592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.194644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.194691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.194740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.194827] [drm:intel_power_well_disable [i915]] disabling display
>[  934.194891] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.194941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.194994] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.195044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.195075] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.195587] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.195609] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.195631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.195657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.195680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.195704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.195727] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.195751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.195775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.195795] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.195818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.195823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.195845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.195850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.195873] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.195894] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.195917] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.195938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.195962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.195985] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.196009] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.196033] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.196056] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.196080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.196105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.196162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.196182] [drm:intel_power_well_enable [i915]] enabling display
>[  934.196201] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.196237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.196261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.196285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.196308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.196382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.196419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.196454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.196490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.196524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.196555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.196585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.196621] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.196655] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.198722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.198743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.198762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.198781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.202637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.202674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.202706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.205406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.205439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.208428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.211767] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.211866] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.211898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.211940] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.212051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.212095] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.212157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.262086] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.262126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.262166] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.262208] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.262241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.262277] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.262319] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.262421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.262473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.262526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.262575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.262589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.262636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.262649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.262697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.262745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.263155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.263204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.263257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.263305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.263413] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.263468] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.263515] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.263569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.263625] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.263831] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.263857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.263910] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.280942] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.280979] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.281019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.281053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.281092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.281132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.281171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.281211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.281253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.281296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.281338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.281453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.281512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.281599] [drm:intel_power_well_disable [i915]] disabling display
>[  934.281965] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.282020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.282075] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.282129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.282169] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.282590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.282625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.282665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.282689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.282708] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.282728] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.282748] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.282767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.282785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.282801] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.282818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.282822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.282838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.282842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.282858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.282875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.282891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.282906] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.282926] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.282942] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.282959] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.282975] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.282991] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.283010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.283035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.283093] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.283113] [drm:intel_power_well_enable [i915]] enabling display
>[  934.283132] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.283169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.283192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.283216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.283240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.283263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.283286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.283321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.283390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.283429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.283462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.283494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.283531] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.283564] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.286790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.286827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.286859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.286890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.290739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.290778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.290810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.293498] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.293536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.296530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.299845] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.299918] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.299957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.300009] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.300127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.300177] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.300247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.350180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.350220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.350260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.350301] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.350399] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.350453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.350512] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.350563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.350618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.350902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.350934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.350942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.350972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.350978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.351009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.351038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.351067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.351095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.351129] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.351157] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.351187] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.351215] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.351253] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.351295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.351337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.351822] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.351861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.351936] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.369007] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.369044] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.369084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.369117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.369148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.369178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.369207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.369238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.369273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.369304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.369423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.369467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.369516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.369602] [drm:intel_power_well_disable [i915]] disabling display
>[  934.369855] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.369908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.369962] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.370015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.370071] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.370441] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.370464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.370488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.370517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.370542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.370568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.370595] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.370620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.370646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.370668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.370693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.370698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.370723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.370727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.370753] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.370778] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.370804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.370828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.370853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.370878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.370904] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.370930] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.370955] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.370982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.371009] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.371069] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.371091] [drm:intel_power_well_enable [i915]] enabling display
>[  934.371112] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.371151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.371178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.371203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.371229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.371254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.371279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.371306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.371368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.371402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.371433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.371464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.371499] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.371531] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.374752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.374793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.374832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.374873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.378806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.378844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.378875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.381567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.381602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.384610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.387965] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.388049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.388082] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.388123] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.388233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.388276] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.388412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.438291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.438332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.438435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.438495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.438545] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.438599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.438651] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.438702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.438752] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.438799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.438844] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.438857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.438901] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.438912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.438959] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.439005] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.439050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.439094] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.439141] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.439185] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.439233] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.439279] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.439320] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.439407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.439461] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.439666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.439763] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.440339] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.457273] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.457312] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.457439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.457493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.457544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.457595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.457643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.457692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.457746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.457799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.457853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.457899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.457944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.458028] [drm:intel_power_well_disable [i915]] disabling display
>[  934.458093] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.458146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.458180] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.458213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.458244] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.458644] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.458671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.458697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.458726] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.458758] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.458782] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.458805] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.458829] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.458852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.458872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.458895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.458900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.458923] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.458927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.458951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.458972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.458995] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.459015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.459039] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.459062] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.459086] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.459110] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.459133] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.459157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.459182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.459238] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.459258] [drm:intel_power_well_enable [i915]] enabling display
>[  934.459277] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.459324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.459395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.459426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.459460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.459492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.459525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.459561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.459594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.459628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.459659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.459689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.459725] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.459758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.461829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.461850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.461869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.461888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.464686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.464723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.464755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.467462] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.467493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.470564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.473887] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.473944] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.473974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.474012] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.474112] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.474151] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.474205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.524215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.524255] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.524294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.524404] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.524453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.524511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.524565] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.524616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.524666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.524714] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.524760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.524772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.524816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.524828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.524874] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.524920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.524967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.525012] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.525058] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.525103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.525152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.525199] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.525240] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.525292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.525381] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.525544] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.525607] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.525708] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.542862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.542899] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.542944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.542984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.543024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.543063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.543103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.543141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.543184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.543226] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.543267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.543306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.543422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.543506] [drm:intel_power_well_disable [i915]] disabling display
>[  934.543570] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.543625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.543681] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.543734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.543782] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.544305] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.544376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.544413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.544451] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.544484] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.544518] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.544551] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.544583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.544615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.544645] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.544672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.544680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.544708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.544715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.544744] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.544775] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.544804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.544833] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.544863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.544892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.544924] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.544955] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.544985] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.545018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.545052] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.545153] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.545182] [drm:intel_power_well_enable [i915]] enabling display
>[  934.545210] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.545257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.545286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.545326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.545385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.545417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.545449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.545484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.545517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.545550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.545580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.545611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.545647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.545679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.547742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.547763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.547782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.547801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.550460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.550495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.550525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.553221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.553258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.556258] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.559535] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.559578] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.559602] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.559633] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.559719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.559748] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.559790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.609851] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.609892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.609934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.609981] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.610022] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.610064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.610104] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.610145] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.610186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.610222] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.610262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.610269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.610309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.610373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.610430] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.610491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.610543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.610593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.610654] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.610687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.610721] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.610752] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.610784] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.610819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.610855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.610959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.611000] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.611064] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.628109] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.628146] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.628186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.628220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.628250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.628280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.628308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.628426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.628486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.628541] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.628592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.628943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.628992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.629072] [drm:intel_power_well_disable [i915]] disabling display
>[  934.629098] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.629119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.629140] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.629160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.629177] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.629685] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.629706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.629728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.629751] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.629769] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.629789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.629809] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.629828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.629846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.629863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.629879] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.629884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.629900] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.629904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.629921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.629938] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.629954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.629970] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.629989] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.630005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.630029] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.630052] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.630076] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.630101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.630126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.630180] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.630201] [drm:intel_power_well_enable [i915]] enabling display
>[  934.630220] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.630257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.630281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.630314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.630379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.630409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.630442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.630478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.630511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.630543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.630573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.630602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.630636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.630668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.632738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.632759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.632778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.632797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.635499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.635536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.635567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.638276] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.638307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.641380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.644706] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.644761] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.644790] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.644827] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.644926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.644965] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.645020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.695021] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.695065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.695108] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.695154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.695195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.695237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.695277] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.695318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.695427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.695479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.695532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.695547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.695595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.695608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.695666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.695713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.695759] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.695804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.695853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.695897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.695944] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.695987] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.696030] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.696080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.696132] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.696283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.696455] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.696591] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.713646] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.713683] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.713723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.713756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.713787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.713817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.713845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.713877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.713910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.713942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.713973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.714001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.714029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.714085] [drm:intel_power_well_disable [i915]] disabling display
>[  934.714122] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.714157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.714193] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.714229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.714257] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.714878] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.714925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.714971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.715020] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.715069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.715105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.715140] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.715175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.715208] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.715240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.715272] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.715280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.715312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.715357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.715391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.715426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.715459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.715493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.715529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.715563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.715599] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.715631] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.715664] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.715702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.715740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.715840] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.715873] [drm:intel_power_well_enable [i915]] enabling display
>[  934.715906] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.715961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.715996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.716031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.716072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.716103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.716135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.716170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.716203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.716235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.716264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.716294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.716355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.716388] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.719596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.719633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.719665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.719697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.723577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.723614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.723646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.726347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.726380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.729387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.732704] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.732769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.732797] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.732834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.732931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.732969] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.733024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.783030] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.783070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.783110] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.783151] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.783184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.783220] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.783256] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.783290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.783389] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.783438] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.783489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.783503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.783551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.783563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.783612] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.783659] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.783706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.783753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.783806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.783853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.783903] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.784279] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.784357] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.784552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.784980] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.785246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.785320] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.785575] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.800077] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.800114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.800154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.800187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.800218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.800248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.800277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.800308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.800432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.800488] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.800541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.800588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.800883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.800970] [drm:intel_power_well_disable [i915]] disabling display
>[  934.801010] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.801041] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.801074] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.801105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.801133] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.801667] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.801689] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.801711] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.801734] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.801753] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.801772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.801792] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.801811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.801829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.801846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.801863] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.801867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.801884] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.801888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.801904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.801921] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.801937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.801953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.801972] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.801989] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.802006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.802022] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.802038] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.802058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.802078] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.802131] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.802148] [drm:intel_power_well_enable [i915]] enabling display
>[  934.802164] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.802196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.802215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.802232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.802255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.802279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.802310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.802383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.802415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.802450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.802477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.802506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.802538] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.802570] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.804989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.805010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.805028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.805051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.808918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.808955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.808988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.811672] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.811707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.814699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.818045] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.818137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.818169] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.818211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.818369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.818413] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.818599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.868388] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.868426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.868464] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.868508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.868547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.868587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.868633] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.868664] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.868692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.868719] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.868745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.868752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.868777] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.868782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.868807] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.868832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.868866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.868900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.868936] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.868970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.869006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.869041] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.869076] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.869112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.869150] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.869251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.869294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.869424] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.886076] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.886113] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.886153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.886187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.886218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.886248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.886278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.886309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.886425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.886479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.886734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.886766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.886795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.886848] [drm:intel_power_well_disable [i915]] disabling display
>[  934.886889] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.886921] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.886964] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.886985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.887004] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.887420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.887443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.887467] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.887501] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.887524] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.887548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.887571] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.887595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.887619] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.887639] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.887662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.887667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.887689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.887694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.887717] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.887738] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.887761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.887783] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.887806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.887829] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.887854] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.887877] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.887901] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.887935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.887961] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.888030] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.888047] [drm:intel_power_well_enable [i915]] enabling display
>[  934.888067] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.888103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.888127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.888151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.888174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.888198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.888221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.888246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.888271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.888301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.888369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.888406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.888440] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.888473] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.890538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.890559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.890578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.890597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.894463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.894504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.894543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.897235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.897271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.900386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.903711] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.903770] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.903800] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.903840] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.903944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.903986] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.904045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.954035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.954079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.954122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.954168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.954208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.954251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.954291] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.954398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.954448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.954493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.954538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.954550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.954594] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.954604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.954653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.954695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.954738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.954779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.954832] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.954878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.954928] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.954975] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.955020] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.955071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.955126] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.955236] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  934.955278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  934.955429] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  934.972209] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  934.972247] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  934.972287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.972410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.972463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.972514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.972562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.972613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.972666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.972718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.972769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.972814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.972861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.972946] [drm:intel_power_well_disable [i915]] disabling display
>[  934.972999] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  934.973030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.973064] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.973097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.973128] [drm:intel_power_well_disable [i915]] disabling always-on
>[  934.973588] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  934.973610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  934.973632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  934.973655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  934.973674] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  934.973694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  934.973714] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  934.973733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  934.973751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  934.973768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  934.973784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  934.973789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.973805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  934.973809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  934.973826] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  934.973842] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  934.973865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  934.973888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  934.973912] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  934.973935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  934.973959] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  934.973983] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  934.974006] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  934.974031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  934.974056] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  934.974113] [drm:intel_power_well_enable [i915]] enabling always-on
>[  934.974133] [drm:intel_power_well_enable [i915]] enabling display
>[  934.974153] [drm:hsw_set_power_well [i915]] Enabling power well
>[  934.974189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  934.974213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  934.974236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  934.974260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  934.974294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  934.974368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  934.974405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  934.974442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  934.974478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  934.974509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  934.974540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  934.974577] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  934.974610] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  934.976682] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  934.976704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  934.976722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.976741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  934.980602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  934.980643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  934.980681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  934.983358] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  934.983393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  934.986437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  934.989778] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  934.989874] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  934.989907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  934.989949] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  934.990059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  934.990103] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  934.990165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.040106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.040147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.040187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.040229] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.040263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.040299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.040404] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.040455] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.040509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.040559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.040606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.040621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.040667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.040679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.040726] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.040771] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.040820] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.040866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.040913] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.040958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.041006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.041050] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.041092] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.041142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.041196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.041521] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.041647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.041845] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.058970] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.059007] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.059047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.059080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.059110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.059140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.059168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.059200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.059233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.059265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.059295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.059402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.059451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.059532] [drm:intel_power_well_disable [i915]] disabling display
>[  935.059597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.059648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.059701] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.059753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.059801] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.060518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.060565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.060611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.060659] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.060700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.060743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.060786] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.060828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.060869] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.060908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.060946] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.060956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.060994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.061003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.061042] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.061079] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.061106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.061133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.061160] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.061186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.061214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.061243] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.061267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.061308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.061375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.061467] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.061497] [drm:intel_power_well_enable [i915]] enabling display
>[  935.061528] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.061580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.061613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.061644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.061675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.061705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.061737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.061770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.061803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.061835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.061865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.061894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.061928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.061959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.065140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.065184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.065215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.065247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.069121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.069152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.069179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.071901] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.071938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.074990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.078291] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.078375] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.078413] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.078439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.078518] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.078546] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.078587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.128683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.128723] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.128763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.128809] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.128850] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.128892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.128932] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.128973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.129015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.129055] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.129095] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.129103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.129144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.129151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.129192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.129233] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.129273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.129374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.129436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.129482] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.129536] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.129580] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.129629] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.129684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.129739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.129861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.129899] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.130139] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.146193] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.146230] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.146270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.146387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.146434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.146484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.146527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.146577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.146630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.146682] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.146733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.146774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.146818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.146904] [drm:intel_power_well_disable [i915]] disabling display
>[  935.146967] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.147016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.147067] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.147119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.147168] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.147575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.147607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.147640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.147669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.147689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.147709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.147729] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.147747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.147765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.147782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.147798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.147803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.147819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.147823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.147846] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.147869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.147892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.147915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.147939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.147962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.147986] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.148009] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.148032] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.148057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.148082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.148140] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.148159] [drm:intel_power_well_enable [i915]] enabling display
>[  935.148179] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.148215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.148239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.148263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.148297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.148425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.148461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.148497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.148529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.148562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.148589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.148616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.148648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.148678] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.151868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.151905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.151937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.151970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.155887] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.155923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.155953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.158613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.158648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.161644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.164987] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.165081] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.165120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.165171] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.165291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.165423] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.165629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.215358] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.215398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.215437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.215478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.215511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.215547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.215582] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.215616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.215648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.215679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.215709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.215716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.215746] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.215752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.215783] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.215812] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.215842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.215870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.215905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.215935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.215966] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.215995] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.216023] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.216057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.216095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.216205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.216247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.217134] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.234267] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.234339] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.234379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.234411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.234443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.234472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.234502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.234533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.234574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.234617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.234659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.234698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.234737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.234794] [drm:intel_power_well_disable [i915]] disabling display
>[  935.234839] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.234880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.234922] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.234965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.234999] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.235563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.235608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.235655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.235705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.235746] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.235791] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.235835] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.235876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.235918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.235957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.235998] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.236008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.236045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.236055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.236093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.236140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.236172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.236204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.236240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.236272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.236324] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.236356] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.236386] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.236422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.236459] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.236559] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.236593] [drm:intel_power_well_enable [i915]] enabling display
>[  935.236625] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.236681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.236715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.236749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.236782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.236811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.236845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.236881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.236917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.236952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.236983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.237014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.237052] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.237086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.240315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.240380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.240412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.240444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.244332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.244363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.244391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.247106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.247147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.250159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.253449] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.253531] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.253554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.253586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.253668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.253698] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.253740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.303857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.303898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.303938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.303980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.304013] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.304050] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.304086] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.304120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.304153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.304185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.304215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.304223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.304252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.304259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.304289] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.304391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.304433] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.304477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.304524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.304567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.304613] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.304655] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.304698] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.304749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.304803] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.304944] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.304985] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.305068] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.322086] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.322124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.322165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.322197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.322236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.322277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.322388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.322442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.322660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.322694] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.322728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.322757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.322787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.322847] [drm:intel_power_well_disable [i915]] disabling display
>[  935.322874] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.322894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.322917] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.322937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.322956] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.323217] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.323238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.323261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.323327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.323356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.323387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.323417] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.323445] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.323473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.323501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.323527] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.323536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.323562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.323569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.323598] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.323624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.323651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.323676] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.323709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.323925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.323947] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.323966] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.323985] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.324007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.324030] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.324093] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.324112] [drm:intel_power_well_enable [i915]] enabling display
>[  935.324130] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.324164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.324184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.324203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.324222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.324240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.324265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.324321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.324353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.324384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.324411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.324438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.324471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.324499] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.327790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.327814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.327835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.327856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.331750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.331788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.331820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.334536] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.334571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.337577] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.340926] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.341016] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.341049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.341091] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.341230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.341270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.341394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.391298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.391363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.391403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.391445] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.391478] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.391514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.391551] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.391585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.391617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.391649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.391678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.391686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.391716] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.391723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.391753] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.391783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.391812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.391841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.391876] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.391906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.391937] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.391966] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.391995] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.392029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.392067] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.392179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.392222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.392359] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.409407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.409444] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.409485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.409526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.409566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.409605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.409645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.409683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.409726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.409768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.409809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.409848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.409881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.409914] [drm:intel_power_well_disable [i915]] disabling display
>[  935.409939] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.409961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.409982] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.410006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.410026] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.410467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.410491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.410516] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.410541] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.410562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.410584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.410606] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.410627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.410646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.410665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.410684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.410689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.410707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.410711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.410731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.410749] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.410768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.410785] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.410807] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.410825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.410845] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.410863] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.410881] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.410902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.410926] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.410983] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.411002] [drm:intel_power_well_enable [i915]] enabling display
>[  935.411020] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.411054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.411074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.411099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.411125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.411151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.411176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.411203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.411231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.411259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.411308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.411331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.411354] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.411376] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.413425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.413447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.413465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.413484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.417305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.417358] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.417389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.420120] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.420152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.423186] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.426465] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.426504] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.426524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.426549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.426633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.426661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.426702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.476760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.476801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.476840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.476881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.476914] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.476949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.476986] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.477020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.477052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.477083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.477117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.477125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.477165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.477173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.477214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.477252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.477293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.477400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.477451] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.477507] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.477550] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.477589] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.477628] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.477673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.477718] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.477862] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.477918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.478217] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.494174] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.494211] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.494252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.494286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.494405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.494455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.494504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.494555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.494606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.494641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.494673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.494704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.494732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.494788] [drm:intel_power_well_disable [i915]] disabling display
>[  935.494830] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.494861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.494895] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.494931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.494953] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.495258] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.495331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.495367] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.495406] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.495439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.495474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.495507] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.495539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.495570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.495600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.495629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.495638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.495666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.495673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.495702] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.495731] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.495760] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.495785] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.495817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.495846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.495877] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.495904] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.495932] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.495966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.496000] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.496093] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.496124] [drm:intel_power_well_enable [i915]] enabling display
>[  935.496154] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.496205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.496236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.496267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.496319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.496350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.496382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.496418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.496451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.496484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.496514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.496544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.496580] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.496612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.498676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.498697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.498715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.498734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.502619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.502656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.502688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.505404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.505439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.508435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.511778] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.511873] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.511906] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.511948] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.512058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.512102] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.512164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.562137] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.562177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.562216] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.562257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.562359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.562412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.562469] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.562521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.562571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.562619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.562668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.562682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.562725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.562739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.562786] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.562831] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.562872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.562916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.562968] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.563013] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.563057] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.563102] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.563147] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.563199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.563253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.563445] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.563507] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.563613] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.580656] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.580698] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.580743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.580783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.580823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.580862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.580902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.580941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.580991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.581027] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.581059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.581087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.581113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.581163] [drm:intel_power_well_disable [i915]] disabling display
>[  935.581201] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.581230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.581263] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.581379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.581427] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.582101] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.582131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.582163] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.582197] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.582226] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.582257] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.582330] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.582364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.582398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.582430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.582461] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.582470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.582500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.582508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.582539] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.582568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.582600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.582630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.582663] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.582692] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.582723] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.582749] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.582778] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.582811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.582846] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.582938] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.582969] [drm:intel_power_well_enable [i915]] enabling display
>[  935.583000] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.583051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.583082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.583114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.583144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.583174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.583207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.583241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.583274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.583334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.583364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.583395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.583430] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.583462] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.585522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.585543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.585562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.585581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.589452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.589489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.589520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.592231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.592261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.595357] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.598682] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.598737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.598765] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.598803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.598903] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.598942] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.599003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.648963] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.649004] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.649044] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.649085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.649118] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.649153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.649190] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.649223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.649270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.649373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.649406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.649415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.649443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.649453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.649483] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.649511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.649542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.649569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.649605] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.649634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.649676] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.649703] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.649731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.649764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.649801] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.649934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.649993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.650086] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.667223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.667260] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.667388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.667440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.667491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.667540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.667587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.667625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.667663] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.667695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.667727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.667756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.667785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.667838] [drm:intel_power_well_disable [i915]] disabling display
>[  935.667879] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.667911] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.667944] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.667976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.668011] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.668553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.668575] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.668597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.668621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.668639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.668660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.668680] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.668699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.668717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.668734] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.668751] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.668756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.668772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.668776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.668793] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.668809] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.668826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.668842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.668864] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.668887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.668912] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.668936] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.668959] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.668983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.669008] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.669065] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.669085] [drm:intel_power_well_enable [i915]] enabling display
>[  935.669105] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.669141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.669165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.669188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.669212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.669235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.669262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.669347] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.669384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.669421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.669453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.669485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.669522] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.669555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.672743] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.672779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.672811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.672843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.676764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.676802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.676835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.679510] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.679544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.682540] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.685885] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.685977] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.686010] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.686052] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.686157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.686202] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.686264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.736280] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.736344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.736384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.736425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.736459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.736495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.736531] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.736565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.736598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.736629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.736659] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.736667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.736697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.736703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.736734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.736763] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.736792] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.736822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.736857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.736886] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.736917] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.736946] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.736975] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.737009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.737047] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.737157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.737200] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.737268] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.755221] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.755258] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.755377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.755425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.755475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.755518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.755562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.755606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.755657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.755707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.755756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.755797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.755840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.755925] [drm:intel_power_well_disable [i915]] disabling display
>[  935.755989] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.756038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.756087] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.756117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.756145] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.756599] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.756621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.756643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.756670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.756692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.756716] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.756740] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.756763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.756787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.756807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.756830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.756835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.756858] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.756863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.756886] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.756910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.756933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.756956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.756980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.757002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.757027] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.757050] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.757074] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.757098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.757124] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.757180] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.757200] [drm:intel_power_well_enable [i915]] enabling display
>[  935.757219] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.757266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.757330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.757366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.757396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.757428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.757457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.757492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.757527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.757562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.757590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.757620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.757651] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.757683] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.759778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.759801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.759824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.759848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.763712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.763750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.763782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.766523] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.766558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.769600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.772941] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.773039] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.773072] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.773114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.773262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.773402] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.773550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.823280] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.823344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.823383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.823429] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.823469] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.823511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.823551] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.823592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.823634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.823674] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.823714] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.823722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.823762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.823768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.823810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.823851] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.823891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.823930] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.823971] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.824011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.824053] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.824094] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.824135] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.824178] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.824222] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.824408] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.824472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.824784] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.841173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.841211] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.841251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.841362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.841411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.841461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.841504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.841554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.841607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.841657] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.841707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.841748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.841791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.841876] [drm:intel_power_well_disable [i915]] disabling display
>[  935.841940] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.841997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.842030] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.842062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.842092] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.842579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.842600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.842622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.842645] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.842663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.842683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.842707] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.842731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.842755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.842776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.842799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.842804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.842827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.842831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.842855] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.842876] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.842900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.842923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.842947] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.842969] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.842993] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.843016] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.843039] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.843063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.843088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.843144] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.843164] [drm:intel_power_well_enable [i915]] enabling display
>[  935.843184] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.843220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.843244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.843316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.843353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.843382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.843416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.843453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.843486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.843519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.843547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.843576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.843611] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.843640] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.845712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.845736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.845759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.845783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.848523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.848563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.848603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.851316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.851350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.854381] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.857733] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.857819] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.857852] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.857901] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.858022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.858072] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.858141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.908085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.908126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.908165] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.908208] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.908250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.908344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.908403] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.908451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.908502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.908546] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.908593] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.908605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.908649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.909002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.909046] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.909078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.909109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.909138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.909172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.909201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.909232] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.909260] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.909360] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.909409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.909465] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.909804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.909831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.909885] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  935.926151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  935.926188] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  935.926228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.926262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.926374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.926419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.926468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.926514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.926567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.926907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.926941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.926971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.927009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.927040] [drm:intel_power_well_disable [i915]] disabling display
>[  935.927066] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  935.927089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.927115] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.927140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.927160] [drm:intel_power_well_disable [i915]] disabling always-on
>[  935.927592] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.927618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.927642] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.927667] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.927697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.927717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.927737] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.927755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.927773] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.927790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.927807] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.927811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.927834] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.927838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.927862] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.927886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.927909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.927932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.927955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.927978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.928002] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.928026] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.928049] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.928073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.928098] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.928155] [drm:intel_power_well_enable [i915]] enabling always-on
>[  935.928175] [drm:intel_power_well_enable [i915]] enabling display
>[  935.928195] [drm:hsw_set_power_well [i915]] Enabling power well
>[  935.928231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  935.928265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  935.928334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  935.928363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  935.928391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  935.928420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  935.928452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  935.928483] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  935.928514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.928541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  935.928567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  935.928598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  935.928627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  935.930693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  935.930714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  935.930732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.930751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  935.933450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  935.933484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  935.933515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  935.936206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  935.936243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  935.939314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  935.942563] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  935.942632] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  935.942652] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  935.942678] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  935.942761] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  935.942789] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  935.942830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  935.992904] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  935.992945] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  935.992984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  935.993026] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  935.993059] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  935.993095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  935.993131] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  935.993165] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  935.993198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  935.993229] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  935.993258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  935.993320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.993366] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  935.993379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  935.993422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  935.993464] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  935.993505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  935.993547] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  935.993593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  935.993635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  935.993680] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  935.993721] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  935.993749] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  935.993784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.993818] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  935.993922] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  935.993963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  935.994021] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.011088] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.011125] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.011166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.011199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.011229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.011259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.011371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.011421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.011477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.011530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.011582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.011628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.011674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.011736] [drm:intel_power_well_disable [i915]] disabling display
>[  936.011779] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.011810] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.011845] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.011877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.011906] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.012340] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.012369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.012393] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.012418] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.012438] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.012460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.012481] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.012501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.012521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.012545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.012570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.012576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.012600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.012605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.012630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.012656] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.012681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.012705] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.012731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.012756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.012782] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.012807] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.012832] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.012859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.012886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.012948] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.012970] [drm:intel_power_well_enable [i915]] enabling display
>[  936.012991] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.013030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.013056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.013081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.013107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.013132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.013157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.013185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.013212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.013239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.013301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.013331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.013366] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.013395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.015458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.015479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.015497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.015517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.019379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.019414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.019443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.022135] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.022172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.025165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.028479] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.028536] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.028555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.028581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.028670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.028710] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.028770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.078805] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.078846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.078885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.078927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.078960] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.078996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.079032] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.079065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.079098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.079138] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.079178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.079186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.079227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.079234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.079333] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.079382] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.079426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.079468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.079517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.079559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.079605] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.079642] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.079669] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.079702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.079734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.079837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.079877] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.080087] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.096147] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.096185] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.096225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.096265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.096383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.096435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.096484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.096534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.096584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.096620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.096652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.096682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.096710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.096766] [drm:intel_power_well_disable [i915]] disabling display
>[  936.096808] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.096840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.096881] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.096925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.096960] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.097293] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.097325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.097359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.097393] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.097422] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.097453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.097483] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.097512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.097541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.097568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.097594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.097602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.097630] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.097637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.097667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.097695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.097724] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.097750] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.097779] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.097807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.097830] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.097848] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.097866] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.097887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.097910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.097971] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.097989] [drm:intel_power_well_enable [i915]] enabling display
>[  936.098007] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.098041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.098061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.098080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.098099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.098124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.098149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.098177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.098204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.098231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.098289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.098318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.098352] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.098381] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.100442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.100465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.100488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.100512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.104357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.104393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.104424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.107152] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.107190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.110202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.113469] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.113521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.113540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.113566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.113648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.113676] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.113717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.163797] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.163837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.163877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.163924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.163965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.164007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.164047] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.164088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.164129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.164170] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.164210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.164218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.164258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.164320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.164376] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.164424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.164470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.164522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.164565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.164603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.164644] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.164682] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.164719] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.164765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.164814] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.164957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.165013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.165372] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.182208] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.182246] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.182377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.182429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.182480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.182528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.182576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.182626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.182680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.182731] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.182782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.182828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.182873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.182953] [drm:intel_power_well_disable [i915]] disabling display
>[  936.182995] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.183028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.183061] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.183094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.183125] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.183537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.183569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.183603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.183638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.183668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.183694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.183715] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.183734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.183752] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.183769] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.183786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.183790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.183807] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.183811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.183828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.183844] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.183861] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.183877] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.183896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.183913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.183936] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.183960] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.183984] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.184008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.184034] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.184091] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.184111] [drm:intel_power_well_enable [i915]] enabling display
>[  936.184131] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.184166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.184190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.184214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.184248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.184315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.184349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.184387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.184421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.184455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.184486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.184517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.184553] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.184586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.187781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.187809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.187833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.187857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.191742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.191780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.191812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.194490] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.194525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.197509] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.200854] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.200947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.200986] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.201038] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.201157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.201207] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.201325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.251167] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.251207] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.251246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.251359] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.251554] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.251590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.251625] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.251658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.251688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.251717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.251745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.251753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.251781] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.251787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.251816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.251843] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.251871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.251898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.251931] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.251960] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.251990] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.252017] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.252044] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.252076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.252112] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.252217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.252313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.252410] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.269149] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.269186] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.269226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.269338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.269381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.269412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.269442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.269475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.269510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.269543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.269577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.269606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.269646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.269704] [drm:intel_power_well_disable [i915]] disabling display
>[  936.269750] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.269792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.269836] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.269879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.269913] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.270412] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.270436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.270460] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.270485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.270516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.270538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.270562] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.270586] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.270609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.270632] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.270655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.270660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.270683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.270687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.270711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.270731] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.270754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.270778] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.270801] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.270824] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.270848] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.270872] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.270895] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.270920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.270945] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.271003] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.271023] [drm:intel_power_well_enable [i915]] enabling display
>[  936.271043] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.271079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.271103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.271126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.271150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.271173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.271196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.271221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.271298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.271333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.271363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.271391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.271424] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.271454] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.273502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.273522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.273541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.273560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.276234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.276304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.276342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.279066] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.279105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.282093] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.285345] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.285412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.285431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.285457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.285536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.285564] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.285605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.335734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.335774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.335813] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.335854] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.335887] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.335922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.335958] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.335992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.336025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.336056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.336087] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.336095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.336125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.336132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.336163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.336193] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.336222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.336323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.336373] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.336415] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.336459] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.336502] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.336548] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.336604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.336660] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.336797] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.336851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.337171] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.353161] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.353199] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.353238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.353336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.353383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.353433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.353478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.353512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.353547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.353588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.353633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.353673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.353714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.353772] [drm:intel_power_well_disable [i915]] disabling display
>[  936.353819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.353860] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.353903] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.353947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.353985] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.354418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.354448] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.354471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.354494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.354512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.354532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.354552] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.354576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.354599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.354623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.354646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.354651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.354674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.354678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.354702] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.354725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.354748] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.354770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.354794] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.354817] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.354841] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.354864] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.354888] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.354912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.354937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.354995] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.355015] [drm:intel_power_well_enable [i915]] enabling display
>[  936.355034] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.355070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.355094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.355118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.355142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.355165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.355187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.355212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.355243] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.355325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.355356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.355388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.355426] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.355459] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.357525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.357546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.357568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.357592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.361497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.361534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.361565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.364282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.364318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.367360] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.370675] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.370741] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.370771] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.370809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.370909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.370949] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.371004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.420981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.421021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.421062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.421109] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.421150] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.421192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.421233] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.421338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.421391] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.421444] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.421493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.421509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.421557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.421569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.421618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.421667] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.422024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.422071] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.422123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.422171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.422224] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.422327] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.422377] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.422431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.422488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.422803] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.422833] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.422889] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.439135] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.439171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.439211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.439244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.439357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.439414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.439463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.439514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.439569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.439832] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.439866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.439896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.439924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.439975] [drm:intel_power_well_disable [i915]] disabling display
>[  936.440012] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.440031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.440051] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.440070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.440087] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.440657] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.440678] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.440700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.440726] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.440749] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.440773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.440797] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.440820] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.440844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.440864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.440888] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.440892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.440915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.440920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.440943] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.440967] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.440990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.441013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.441036] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.441059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.441083] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.441106] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.441130] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.441154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.441179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.441285] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.441315] [drm:intel_power_well_enable [i915]] enabling display
>[  936.441348] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.441402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.441437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.441471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.441503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.441534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.441567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.441603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.441637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.441670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.441965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.441997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.442032] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.442064] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.445298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.445336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.445367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.445400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.449251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.449300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.449329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.452045] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.452084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.455093] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.458380] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.458412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.458432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.458457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.458537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.458566] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.458606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.508737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.508778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.508817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.508858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.508891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.508927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.508962] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.508996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.509029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.509060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.509098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.509106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.509147] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.509154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.509196] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.509237] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.509345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.509392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.509442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.509487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.509534] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.509577] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.509620] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.509652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.509684] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.509789] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.509831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.509898] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.526145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.526183] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.526223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.526345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.526402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.526453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.526501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.526550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.526604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.526655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.526706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.526752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.526798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.526883] [drm:intel_power_well_disable [i915]] disabling display
>[  936.526939] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.526971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.527005] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.527038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.527069] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.527511] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.527536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.527558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.527583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.527606] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.527630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.527653] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.527676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.527700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.527723] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.527746] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.527750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.527773] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.527777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.527801] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.527824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.527848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.527871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.527894] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.527917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.527941] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.527965] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.527988] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.528012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.528037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.528095] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.528114] [drm:intel_power_well_enable [i915]] enabling display
>[  936.528134] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.528170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.528194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.528218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.528296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.528332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.528365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.528402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.528437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.528471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.528503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.528534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.528570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.528603] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.531750] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.531776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.531800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.531824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.535717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.535754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.535786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.538459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.538491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.541500] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.544837] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.544939] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.544972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.545014] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.545162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.545236] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.545373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.595195] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.595235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.595331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.595396] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.595439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.595491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.595538] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.595585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.595629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.595673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.595713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.595726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.595767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.595778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.595822] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.595862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.595906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.595945] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.595993] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.596033] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.596079] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.596119] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.596162] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.596208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.596297] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.596487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.596605] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.596796] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.613934] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.613971] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.614011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.614045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.614076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.614105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.614134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.614165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.614207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.614316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.614368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.614416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.614459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.614543] [drm:intel_power_well_disable [i915]] disabling display
>[  936.614607] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.614656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.614709] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.614759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.614806] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.615290] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.615331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.615364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.615398] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.615418] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.615438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.615458] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.615477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.615496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.615513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.615529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.615534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.615550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.615554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.615571] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.615587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.615604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.615620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.615639] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.615656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.615673] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.615689] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.615705] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.615724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.615745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.615800] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.615820] [drm:intel_power_well_enable [i915]] enabling display
>[  936.615840] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.615876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.615900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.615923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.615947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.615970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.615992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.616018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.616043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.616068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.616090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.616113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.616138] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.616161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.619429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.619466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.619497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.619529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.623384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.623420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.623452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.626157] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.626189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.629305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.632675] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.632742] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.632782] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.632833] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.632950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.633001] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.633070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.683010] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.683051] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.683091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.683132] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.683168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.683210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.683313] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.683359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.683406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.683449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.683491] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.683504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.683548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.683560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.683604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.683651] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.683687] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.683715] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.683750] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.683778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.683810] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.683838] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.683867] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.683900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.683938] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.684046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.684087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.684170] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.701191] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.701229] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.701352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.701412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.701463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.701512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.701551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.701585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.701623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.701656] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.701688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.701717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.701746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.701800] [drm:intel_power_well_disable [i915]] disabling display
>[  936.701841] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.701878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.701900] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.701921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.701939] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.702211] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.702283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.702315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.702351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.702379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.702410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.702441] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.702470] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.702499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.702526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.702553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.702561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.702588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.702595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.702625] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.702654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.702681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.702710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.702743] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.702773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.702804] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.702834] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.702863] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.702896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.702930] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.703007] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.703026] [drm:intel_power_well_enable [i915]] enabling display
>[  936.703044] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.703079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.703104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.703131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.703157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.703184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.703210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.703265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.703298] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.703330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.703357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.703385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.703417] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  936.703446] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.705509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.705530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.705548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.705566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.709444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.709482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.709514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.712207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.712259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.715297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.718636] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  936.718737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.718777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  936.718829] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.718980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.719049] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.719148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.768991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.769031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.769071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.769112] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.769145] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.769181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.769217] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  936.769312] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  936.769360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.769404] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.769446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.769459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.769501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.769512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.769562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.769824] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.769854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.769882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  936.769916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.769946] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.769976] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  936.770006] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  936.770034] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  936.770075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.770120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  936.770231] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  936.770403] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  936.770597] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  936.787679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  936.787722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  936.787767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.787807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.787847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.787886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.787926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.787964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.788026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.788072] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.788104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.788132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.788159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.788209] [drm:intel_power_well_disable [i915]] disabling display
>[  936.788337] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  936.788589] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.788625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.788660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.788692] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.788876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.788940] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.788982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.789021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.789045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.789067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.789086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.789107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.789128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.789149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.789169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.789195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.789222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.789273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.789315] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  936.789346] [drm:intel_power_well_disable [i915]] disabling always-on
>[  936.792156] [IGT] kms_flip: exiting, ret=0
>[  936.812098] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  936.812136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  936.812175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  936.812215] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  936.812293] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  936.812329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  936.812364] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  936.812401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  936.812428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  936.812460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  936.812493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  936.812500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.812533] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  936.812538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.812572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  936.812605] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  936.812639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  936.812672] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  936.812706] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  936.812738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  936.812771] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  936.812805] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  936.812834] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  936.812869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  936.812906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  936.812997] [drm:intel_power_well_enable [i915]] enabling always-on
>[  936.813027] [drm:intel_power_well_enable [i915]] enabling display
>[  936.813055] [drm:hsw_set_power_well [i915]] Enabling power well
>[  936.813108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  936.813142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  936.813176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  936.813210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  936.813261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  936.813295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  936.813332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  936.813368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  936.813409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.813436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  936.813463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  936.813493] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  936.813520] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  936.815593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  936.815616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  936.815638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.815662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  936.819985] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  936.820019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  936.820049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  936.822826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  936.822858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  936.825950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  936.829460] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  936.829539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  936.829570] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  936.829613] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  936.829713] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  936.829761] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  936.846326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  936.846374] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  936.846443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  936.846684] Console: switching to colour frame buffer device 240x75
>[  936.951434] Console: switching to colour dummy device 80x25
>[  936.951552] [IGT] kms_flip: executing
>[  936.962132] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  936.962183] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  936.964327] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  936.964364] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  936.966463] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  936.966474] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  936.968592] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  936.968630] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  936.970745] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  936.970757] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  936.970764] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  936.970794] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  936.970837] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  936.971936] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  936.972872] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  936.972894] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  936.972913] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  936.972930] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  936.973947] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  936.973969] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  936.975085] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  936.975089] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  936.975187] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  936.975190] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  936.975195] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  936.975245] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  936.975254] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  936.975258] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  936.975274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  936.975280] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  936.975286] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  936.975292] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  936.975298] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  936.975304] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  936.975310] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  936.975317] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  936.975322] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  936.975328] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  936.975334] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  936.975340] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  936.975346] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  936.975352] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  936.975357] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  936.975363] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  936.975370] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  936.975376] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  936.975381] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  936.975387] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  936.975393] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  936.975400] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  936.975405] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  936.975411] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  936.975416] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  936.975423] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  936.975429] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  936.975435] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  936.975440] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  936.975446] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  936.975452] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  936.975509] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  936.975535] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  936.977278] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  936.977298] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  936.979308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  936.979318] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  936.981307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  936.981345] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  936.983312] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  936.983322] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  936.983330] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  936.985344] [IGT] kms_flip: starting subtest 2x-wf_vblank-interruptible
>[  936.987095] [IGT] kms_flip: exiting, ret=77
>[  937.013324] Console: switching to colour frame buffer device 240x75
>[  937.118657] Console: switching to colour dummy device 80x25
>[  937.118772] [IGT] kms_flip: executing
>[  937.130097] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  937.130150] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  937.131303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  937.131342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  937.133302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  937.133313] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  937.135304] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  937.135342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  937.137314] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  937.137325] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  937.137333] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  937.137362] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  937.137404] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  937.138515] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  937.139459] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  937.139480] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  937.139499] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  937.139516] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  937.140532] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  937.140552] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  937.141669] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  937.141673] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  937.141774] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  937.141777] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  937.141782] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  937.141784] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  937.141789] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  937.141791] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  937.141800] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  937.141803] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.141806] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.141809] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.141812] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  937.141815] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  937.141818] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  937.141821] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  937.141824] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.141827] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.141830] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  937.141833] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  937.141836] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  937.141838] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  937.141841] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  937.141844] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  937.141847] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  937.141850] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  937.141853] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  937.141856] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  937.141859] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  937.141862] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  937.141865] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  937.141868] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  937.141871] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  937.141873] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  937.141876] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  937.141879] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  937.141882] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  937.141885] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  937.141888] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  937.141925] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  937.141947] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  937.143265] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  937.143285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  937.145326] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  937.145337] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  937.147300] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  937.147342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  937.149302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  937.149312] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  937.149320] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  937.151394] [IGT] kms_flip: starting subtest 2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible
>[  937.153353] [IGT] kms_flip: exiting, ret=77
>[  937.180082] Console: switching to colour frame buffer device 240x75
>[  937.284887] Console: switching to colour dummy device 80x25
>[  937.285002] [IGT] kms_flip: executing
>[  937.296124] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  937.296176] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  937.298296] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  937.298335] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  937.300297] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  937.300309] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  937.302295] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  937.302337] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  937.304451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  937.304462] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  937.304469] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  937.304498] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  937.304542] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  937.305647] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  937.306587] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  937.306608] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  937.306627] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  937.306645] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  937.307665] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  937.307686] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  937.308813] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  937.308817] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  937.308923] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  937.308926] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  937.308932] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  937.308934] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  937.308939] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  937.308942] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  937.308951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  937.308955] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.308958] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.308961] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.308965] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  937.308968] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  937.308971] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  937.308974] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  937.308977] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.308981] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  937.308984] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  937.308987] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  937.308990] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  937.308993] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  937.308996] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  937.309000] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  937.309003] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  937.309006] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  937.309009] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  937.309012] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  937.309015] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  937.309019] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  937.309022] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  937.309025] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  937.309028] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  937.309031] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  937.309034] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  937.309038] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  937.309041] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  937.309044] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  937.309047] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  937.309086] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  937.309110] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  937.310253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  937.310276] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  937.312275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  937.312286] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  937.314303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  937.314342] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  937.316293] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  937.316304] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  937.316311] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  937.318210] [IGT] kms_flip: starting subtest blocking-absolute-wf_vblank-interruptible
>[  937.318741] [drm:drm_mode_addfb2] [FB:77]
>[  937.318768] [drm:drm_mode_addfb2] [FB:79]
>[  937.372767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  937.372832] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.380062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  937.380109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  937.380182] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  937.399107] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  937.399151] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  937.399184] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  937.399312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.399364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.399420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.399467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.399516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.399565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.399621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.399673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.399724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.399774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.399820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.399865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.399950] [drm:intel_power_well_disable [i915]] disabling display
>[  937.400016] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  937.400078] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  937.400132] [drm:intel_power_well_disable [i915]] disabling always-on
>[  937.400311] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  937.400418] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  937.400513] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  937.400529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  937.400599] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  937.400628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  937.400661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  937.400699] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  937.400731] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  937.400765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  937.400799] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  937.400832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  937.400866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  937.400895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  937.400927] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  937.400933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.400966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  937.400972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  937.401005] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  937.401035] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  937.401068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  937.401098] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  937.401132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  937.401164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  937.401198] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  937.401290] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  937.401322] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  937.401360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  937.401398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  937.404712] [drm:intel_power_well_enable [i915]] enabling always-on
>[  937.404733] [drm:intel_power_well_enable [i915]] enabling display
>[  937.404759] [drm:hsw_set_power_well [i915]] Enabling power well
>[  937.404793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  937.404814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  937.404833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  937.404850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  937.404867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  937.404890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  937.404915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  937.404940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  937.404965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  937.404988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  937.405011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  937.405036] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  937.405060] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  937.407160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  937.407182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  937.407256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.407292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  937.411156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  937.411191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  937.411291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  937.413959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  937.413995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  937.416963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  937.420287] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  937.420347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  937.420380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  937.420422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  937.420518] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  937.420569] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  937.437138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  937.437187] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  937.437353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.461872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.478410] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  947.478465] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  947.478544] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  947.495560] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  947.495605] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  947.495637] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  947.495676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.495710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.495746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.495777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.495897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.495944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.496006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.496060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.496111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.496160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.496189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.496218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.496267] [drm:intel_power_well_disable [i915]] disabling display
>[  947.496295] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  947.496325] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  947.496348] [drm:intel_power_well_disable [i915]] disabling always-on
>[  947.496569] [drm:drm_mode_addfb2] [FB:77]
>[  947.496606] [drm:drm_mode_addfb2] [FB:78]
>[  947.526176] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  947.526278] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  947.526349] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  947.526415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  947.526427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  947.526486] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  947.526508] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  947.526530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  947.526554] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  947.526572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  947.526592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  947.526612] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  947.526631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  947.526655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  947.526677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  947.526700] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  947.526705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.526728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  947.526732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  947.526756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  947.526779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  947.526859] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.526893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  947.526930] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  947.526962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  947.526995] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  947.527027] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  947.527059] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  947.527094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  947.527131] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  947.530558] [drm:intel_power_well_enable [i915]] enabling always-on
>[  947.530577] [drm:intel_power_well_enable [i915]] enabling display
>[  947.530594] [drm:hsw_set_power_well [i915]] Enabling power well
>[  947.530630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  947.530651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  947.530669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  947.530693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  947.530716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  947.530740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  947.530766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  947.530852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  947.530888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  947.530918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  947.530948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  947.530985] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  947.531014] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  947.533098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  947.533120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  947.533143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.533167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  947.534779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  947.534818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  947.534836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  947.536390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  947.536412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  947.538308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  947.541598] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  947.541693] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  947.541732] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  947.541784] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  947.558470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  947.558521] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  947.558588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.583185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.583281] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  957.583328] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  957.583494] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  957.600520] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  957.600558] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  957.600598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.600632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.600667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.600697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.600726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.600758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.600793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.600826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.600857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.600897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.600937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.600976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.601035] [drm:intel_power_well_disable [i915]] disabling display
>[  957.601082] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  957.601133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  957.601170] [drm:intel_power_well_disable [i915]] disabling always-on
>[  957.602272] [drm:drm_mode_addfb2] [FB:77]
>[  957.602314] [drm:drm_mode_addfb2] [FB:78]
>[  957.632098] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  957.632193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  957.632256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  957.632321] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  957.632333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  957.632469] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  957.632503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  957.632538] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  957.632576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  957.632606] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  957.632632] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  957.632655] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  957.632676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  957.632696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  957.632715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  957.632734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  957.632739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.632757] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  957.632761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  957.632780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  957.632798] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  957.632817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  957.632841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  957.632868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  957.632895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  957.632926] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  957.632949] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  957.632968] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  957.632990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  957.633014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  957.636272] [drm:intel_power_well_enable [i915]] enabling always-on
>[  957.636291] [drm:intel_power_well_enable [i915]] enabling display
>[  957.636311] [drm:hsw_set_power_well [i915]] Enabling power well
>[  957.636349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  957.636420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  957.636457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  957.636487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  957.636518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  957.636548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  957.636583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  957.636615] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  957.636649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  957.636675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  957.636703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  957.636737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  957.636766] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  957.638847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  957.638869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  957.638887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.638906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  957.642835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  957.642872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  957.642910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  957.645659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  957.645693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  957.648678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  957.651989] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  957.652061] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  957.652092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  957.652131] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  957.668842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  957.668893] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  957.668959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  967.693553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  967.693650] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  967.693698] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  967.693772] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  967.710774] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  967.710812] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  967.710853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  967.710886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  967.710922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  967.711041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  967.711087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  967.711140] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  967.711196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  967.711247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  967.711296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  967.711346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  967.711387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  967.711430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  967.711516] [drm:intel_power_well_disable [i915]] disabling display
>[  967.711557] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  967.711598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  967.711631] [drm:intel_power_well_disable [i915]] disabling always-on
>[  967.713379] [IGT] kms_flip: exiting, ret=0
>[  967.733913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  967.733948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  967.734013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  967.734051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  967.734080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  967.734113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  967.734146] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  967.734175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  967.734204] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  967.734232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  967.734258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  967.734265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  967.734292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  967.734297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  967.734324] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  967.734350] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  967.734375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  967.734400] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  967.734432] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  967.734458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  967.734485] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  967.734510] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  967.734535] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  967.734574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  967.734616] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  967.734736] [drm:intel_power_well_enable [i915]] enabling always-on
>[  967.734770] [drm:intel_power_well_enable [i915]] enabling display
>[  967.734803] [drm:hsw_set_power_well [i915]] Enabling power well
>[  967.734864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  967.734909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  967.734940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  967.734971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  967.734998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  967.735016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  967.735036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  967.735055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  967.735073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  967.735089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  967.735105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  967.735126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  967.735144] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  967.737218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  967.737240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  967.737262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  967.737286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  967.741214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  967.741246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  967.741274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  967.744024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  967.744060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  967.747115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  967.750477] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  967.750535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  967.750553] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  967.750580] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  967.750644] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  967.750668] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  967.767340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  967.767388] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  967.767457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  967.767699] Console: switching to colour frame buffer device 240x75
>[  967.874135] Console: switching to colour dummy device 80x25
>[  967.874251] [IGT] kms_flip: executing
>[  967.885835] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  967.885887] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  967.887018] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  967.887053] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  967.889019] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  967.889030] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  967.891007] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  967.891040] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  967.893034] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  967.893046] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  967.893054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  967.893084] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  967.893126] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  967.894211] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  967.895130] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  967.895151] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  967.895174] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  967.895197] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  967.896216] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  967.896237] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  967.897351] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  967.897355] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  967.897461] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  967.897463] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  967.897469] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  967.897471] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  967.897476] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  967.897479] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  967.897488] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  967.897491] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  967.897494] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  967.897497] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  967.897500] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  967.897503] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  967.897506] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  967.897510] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  967.897512] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  967.897515] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  967.897518] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  967.897521] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  967.897524] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  967.897527] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  967.897530] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  967.897533] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  967.897536] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  967.897539] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  967.897542] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  967.897545] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  967.897548] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  967.897551] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  967.897554] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  967.897556] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  967.897559] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  967.897562] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  967.897565] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  967.897568] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  967.897571] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  967.897574] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  967.897577] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  967.897616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  967.897638] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  967.898981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  967.899008] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  967.901109] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  967.901124] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  967.903014] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  967.903050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  967.905028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  967.905039] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  967.905046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  967.907015] [IGT] kms_flip: starting subtest 2x-flip-vs-modeset-interruptible
>[  967.908839] [IGT] kms_flip: exiting, ret=77
>[  967.934293] Console: switching to colour frame buffer device 240x75
>[  968.039343] Console: switching to colour dummy device 80x25
>[  968.039459] [IGT] kms_flip: executing
>[  968.051867] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  968.051920] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  968.054130] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  968.054172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  968.056287] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  968.056298] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  968.058416] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  968.058459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  968.060573] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  968.060584] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  968.060592] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  968.060621] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  968.060663] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  968.061766] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  968.062688] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  968.062709] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  968.062728] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  968.062745] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  968.063766] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  968.063787] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  968.064911] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  968.064933] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  968.065033] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  968.065036] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  968.065041] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  968.065043] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  968.065048] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  968.065050] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  968.065059] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  968.065062] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  968.065065] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.065068] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.065071] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  968.065074] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  968.065077] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  968.065080] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  968.065083] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.065086] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.065089] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  968.065092] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  968.065095] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  968.065098] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  968.065101] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  968.065103] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  968.065106] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  968.065109] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  968.065112] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  968.065115] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  968.065118] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  968.065121] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  968.065124] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  968.065127] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  968.065130] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  968.065133] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  968.065136] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  968.065139] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  968.065142] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  968.065144] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  968.065147] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  968.065185] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  968.065208] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  968.067027] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  968.067077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  968.069177] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  968.069187] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  968.071303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  968.071343] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  968.073458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  968.073469] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  968.073476] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  968.075454] [IGT] kms_flip: starting subtest 2x-flip-vs-panning-interruptible
>[  968.077261] [IGT] kms_flip: exiting, ret=77
>[  968.101129] Console: switching to colour frame buffer device 240x75
>[  968.206022] Console: switching to colour dummy device 80x25
>[  968.206139] [IGT] kms_flip: executing
>[  968.218812] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  968.218865] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  968.220990] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  968.221026] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  968.223141] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  968.223154] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  968.225262] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  968.225300] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  968.227396] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  968.227405] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  968.227412] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  968.227437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  968.227469] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  968.228629] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  968.229589] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  968.229620] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  968.229647] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  968.229672] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  968.230690] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  968.230712] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  968.231830] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  968.231834] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  968.232001] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  968.232006] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  968.232016] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  968.232020] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  968.232029] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  968.232034] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  968.232049] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  968.232055] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  968.232061] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.232067] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.232073] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  968.232078] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  968.232084] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  968.232090] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  968.232095] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.232101] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  968.232107] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  968.232113] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  968.232118] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  968.232124] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  968.232130] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  968.232135] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  968.232141] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  968.232147] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  968.232152] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  968.232158] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  968.232164] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  968.232169] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  968.232175] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  968.232181] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  968.232186] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  968.232192] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  968.232197] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  968.232203] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  968.232209] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  968.232214] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  968.232220] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  968.232287] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  968.232319] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  968.233984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  968.234026] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  968.236015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  968.236026] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  968.238030] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  968.238069] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  968.240015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  968.240026] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  968.240033] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  968.240439] [IGT] kms_flip: starting subtest flip-vs-blocking-wf-vblank
>[  968.241325] [drm:drm_mode_addfb2] [FB:58]
>[  968.241354] [drm:drm_mode_addfb2] [FB:79]
>[  968.294652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  968.294715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  968.301086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  968.301140] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  968.301221] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  968.319325] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  968.319370] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  968.319403] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  968.319442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  968.319475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  968.319510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  968.319540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  968.319569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  968.319601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  968.319635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  968.319668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  968.319699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  968.319730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  968.319767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  968.319789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  968.319826] [drm:intel_power_well_disable [i915]] disabling display
>[  968.319854] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  968.319886] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  968.319910] [drm:intel_power_well_disable [i915]] disabling always-on
>[  968.320054] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  968.320174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  968.320275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  968.320294] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  968.320381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  968.320415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  968.320451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  968.320488] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  968.320519] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  968.320552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  968.320585] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  968.320617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  968.320649] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  968.320679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  968.320709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  968.320716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  968.320745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  968.320752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  968.320782] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  968.320812] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  968.320842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  968.320871] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  968.320904] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  968.320963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  968.320997] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  968.321027] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  968.321058] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  968.321093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  968.321129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  968.324578] [drm:intel_power_well_enable [i915]] enabling always-on
>[  968.324600] [drm:intel_power_well_enable [i915]] enabling display
>[  968.324618] [drm:hsw_set_power_well [i915]] Enabling power well
>[  968.324655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  968.324680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  968.324704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  968.324729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  968.324754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  968.324778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  968.324804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  968.324830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  968.324865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  968.324891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  968.324914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  968.325000] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  968.325035] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  968.328238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  968.328274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  968.328312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  968.328353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  968.332254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  968.332291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  968.332323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  968.335077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  968.335111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  968.338125] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  968.341431] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  968.341505] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  968.341532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  968.341568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  968.341634] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  968.341664] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  968.358289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  968.358336] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  968.358398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  978.666874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  978.683169] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  978.683220] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  978.683296] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  978.700294] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  978.700339] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  978.700371] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  978.700410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  978.700444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  978.700487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  978.700611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  978.700658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  978.700693] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  978.700730] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  978.700762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  978.700793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  978.700825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  978.700853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  978.700882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  978.700936] [drm:intel_power_well_disable [i915]] disabling display
>[  978.700977] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  978.701021] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  978.701056] [drm:intel_power_well_disable [i915]] disabling always-on
>[  978.701352] [drm:drm_mode_addfb2] [FB:58]
>[  978.701397] [drm:drm_mode_addfb2] [FB:78]
>[  978.730591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  978.730694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  978.730764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  978.730829] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  978.730842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  978.730901] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  978.730923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  978.730945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  978.730969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  978.730987] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  978.731008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  978.731028] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[  978.731051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  978.731075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  978.731096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  978.731119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  978.731124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  978.731147] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  978.731151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  978.731175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  978.731198] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  978.731221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  978.731244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  978.731268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  978.731291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  978.731314] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[  978.731338] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[  978.731361] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[  978.731386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  978.731411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[  978.734821] [drm:intel_power_well_enable [i915]] enabling always-on
>[  978.734840] [drm:intel_power_well_enable [i915]] enabling display
>[  978.734856] [drm:hsw_set_power_well [i915]] Enabling power well
>[  978.734893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  978.734913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  978.734933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  978.734951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  978.734968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  978.734991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  978.735016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  978.735041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  978.735066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  978.735089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  978.735112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  978.735137] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[  978.735160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  978.737229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  978.737251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  978.737270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  978.737294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  978.741213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  978.741236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  978.741255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  978.743926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  978.743966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  978.746986] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  978.750305] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  978.750357] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  978.750376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  978.750402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  978.767152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  978.767203] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  978.767269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  989.075706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  989.075878] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  989.075981] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  989.076182] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  989.093224] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[  989.093261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  989.093302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  989.093336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  989.093372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  989.093403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  989.093433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  989.093465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  989.093500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  989.093533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  989.093573] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  989.093616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  989.093655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  989.093694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  989.093752] [drm:intel_power_well_disable [i915]] disabling display
>[  989.093798] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  989.093857] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[  989.093876] [drm:intel_power_well_disable [i915]] disabling always-on
>[  989.094196] [drm:drm_mode_addfb2] [FB:58]
>[  989.094250] [drm:drm_mode_addfb2] [FB:78]
>[  989.123476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  989.123577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  989.123646] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  989.123713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  989.123725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  989.123784] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  989.123806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  989.123828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  989.123854] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  989.123877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  989.123901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  989.123925] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[  989.123948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  989.123972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  989.123995] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  989.124018] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  989.124022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  989.124045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  989.124098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  989.124134] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  989.124165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  989.124194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  989.124222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  989.124253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  989.124281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  989.124310] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[  989.124337] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[  989.124363] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[  989.124395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  989.124429] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[  989.127684] [drm:intel_power_well_enable [i915]] enabling always-on
>[  989.127704] [drm:intel_power_well_enable [i915]] enabling display
>[  989.127721] [drm:hsw_set_power_well [i915]] Enabling power well
>[  989.127756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  989.127777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  989.127796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  989.127814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  989.127832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  989.127851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  989.127871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  989.127890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  989.127909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  989.127926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  989.127943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  989.127964] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[  989.127983] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  989.130042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  989.130079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  989.130097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  989.130117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  989.133956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  989.133994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  989.134026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  989.136838] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  989.136877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  989.139865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  989.143205] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  989.143303] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  989.143335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  989.143378] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  989.160113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  989.160167] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  989.160239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  999.468633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  999.468849] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  999.468938] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  999.469081] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  999.486115] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[  999.486153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  999.486194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  999.486227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  999.486263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  999.486294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  999.486323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  999.486355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  999.486398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  999.486441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  999.486485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  999.486517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  999.486545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  999.486571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  999.486621] [drm:intel_power_well_disable [i915]] disabling display
>[  999.486739] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  999.486803] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[  999.486853] [drm:intel_power_well_disable [i915]] disabling always-on
>[  999.490057] [IGT] kms_flip: exiting, ret=0
>[  999.509558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  999.509597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  999.509636] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  999.509703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  999.509735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  999.509770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  999.509806] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  999.509838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  999.509870] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  999.509900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  999.509928] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  999.509936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  999.509964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  999.509969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  999.509998] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  999.510037] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  999.510059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  999.510081] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  999.510108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  999.510130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  999.510161] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  999.510193] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  999.510224] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  999.510259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  999.510294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  999.510381] [drm:intel_power_well_enable [i915]] enabling always-on
>[  999.510409] [drm:intel_power_well_enable [i915]] enabling display
>[  999.510436] [drm:hsw_set_power_well [i915]] Enabling power well
>[  999.510487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  999.510520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  999.510552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  999.510584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  999.510616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  999.510673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  999.510710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  999.510744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  999.510777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  999.510808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  999.510839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  999.510873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  999.510904] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  999.512977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  999.512997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  999.513014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  999.513033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  999.514614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  999.514642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  999.514658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  999.516220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  999.516238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  999.518121] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  999.521139] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  999.521201] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  999.521232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  999.521284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  999.521352] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  999.521377] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  999.537996] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  999.538044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  999.538116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  999.538413] Console: switching to colour frame buffer device 240x75
>[  999.643481] Console: switching to colour dummy device 80x25
>[  999.643599] [IGT] kms_flip: executing
>[  999.656480] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  999.656532] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  999.658077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  999.658116] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  999.660209] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  999.660219] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  999.662336] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  999.662376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  999.664490] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  999.664502] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  999.664509] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  999.664539] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  999.664581] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  999.665762] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  999.666706] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  999.666733] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  999.666767] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  999.666789] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  999.667830] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  999.667851] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  999.668974] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  999.668978] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  999.669078] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  999.669081] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  999.669086] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  999.669089] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  999.669093] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  999.669096] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  999.669105] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  999.669108] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  999.669111] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.669114] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.669117] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  999.669120] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  999.669123] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  999.669126] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  999.669129] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.669132] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.669135] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  999.669138] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  999.669141] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  999.669144] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  999.669147] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  999.669150] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  999.669153] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  999.669156] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  999.669159] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  999.669162] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  999.669165] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  999.669167] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  999.669170] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  999.669173] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  999.669176] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  999.669179] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  999.669182] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  999.669185] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  999.669188] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  999.669191] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  999.669194] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  999.669232] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  999.669255] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  999.670680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  999.670709] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  999.672702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  999.672713] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  999.674700] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  999.674736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  999.676706] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  999.676716] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  999.676724] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  999.678869] [IGT] kms_flip: starting subtest 2x-dpms-vs-vblank-race-interruptible
>[  999.680574] [IGT] kms_flip: exiting, ret=77
>[  999.721698] Console: switching to colour frame buffer device 240x75
>[  999.826565] Console: switching to colour dummy device 80x25
>[  999.826809] [IGT] kms_flip: executing
>[  999.838468] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[  999.838520] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[  999.839710] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  999.839750] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  999.841849] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  999.841860] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  999.843977] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  999.844019] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  999.846133] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  999.846145] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  999.846152] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[  999.846181] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[  999.846223] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[  999.847334] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[  999.848291] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  999.848314] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[  999.848333] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  999.848351] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  999.849367] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[  999.849387] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  999.850496] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[  999.850499] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  999.850644] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  999.850649] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  999.850659] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  999.850664] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  999.850673] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  999.850677] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  999.850692] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[  999.850700] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  999.850706] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.850712] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.850718] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  999.850724] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  999.850730] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  999.850737] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  999.850743] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.850748] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  999.850754] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  999.850761] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  999.850767] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  999.850772] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  999.850778] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  999.850783] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  999.850791] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  999.850797] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  999.850802] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  999.850808] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  999.850813] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  999.850821] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  999.850827] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  999.850832] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  999.850837] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  999.850843] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  999.850850] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  999.850856] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  999.850862] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  999.850867] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  999.850872] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  999.850929] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[  999.850954] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[  999.852672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  999.852693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  999.854830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  999.854839] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  999.856708] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  999.856746] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  999.858706] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  999.858717] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  999.858724] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[  999.860638] [IGT] kms_flip: starting subtest flip-vs-panning-interruptible
>[  999.861160] [drm:drm_mode_addfb2] [FB:58]
>[  999.861187] [drm:drm_mode_addfb2] [FB:79]
>[  999.937692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  999.937755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  999.938246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  999.938278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  999.938339] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  999.957426] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  999.957471] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[  999.957504] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[  999.957544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  999.957577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  999.957613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  999.957705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  999.957760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  999.957806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  999.957864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  999.957919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  999.957962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  999.958007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  999.958041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  999.958078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  999.958150] [drm:intel_power_well_disable [i915]] disabling display
>[  999.958203] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[  999.958256] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  999.958301] [drm:intel_power_well_disable [i915]] disabling always-on
>[  999.958426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[  999.958580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[  999.958776] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  999.958801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[  999.958924] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[  999.958957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  999.958994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  999.959034] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  999.959065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  999.959100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  999.959132] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  999.959165] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  999.959195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  999.959226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  999.959256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  999.959264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  999.959293] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  999.959300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[  999.959331] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[  999.959360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  999.959389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  999.959417] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[  999.959450] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  999.959478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  999.959510] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[  999.959538] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[  999.959565] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[  999.959599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  999.959667] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[  999.966194] [drm:intel_power_well_enable [i915]] enabling always-on
>[  999.966216] [drm:intel_power_well_enable [i915]] enabling display
>[  999.966238] [drm:hsw_set_power_well [i915]] Enabling power well
>[  999.966276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  999.966301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[  999.966326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[  999.966350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[  999.966375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[  999.966399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[  999.966426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[  999.966452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[  999.966477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[  999.966501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[  999.966525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[  999.966551] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[  999.966575] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[  999.968693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  999.968716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  999.968739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  999.968764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  999.970340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  999.970365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  999.970388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  999.971957] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  999.971979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  999.973852] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  999.977190] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  999.977287] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[  999.977325] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  999.977351] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  999.977414] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  999.977435] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  999.994068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[  999.994120] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  999.994192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1000.010841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.010860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.044284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.044302] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.077672] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.077690] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.110986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.111004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.144344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.144362] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.177757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.177775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.211049] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.211067] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.244421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.244439] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.277818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.277836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.311140] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.311158] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.344530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.344548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.377865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.377883] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.411265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.411283] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.444568] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.444629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.477928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.477945] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.511296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.511314] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.544689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.544706] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.578016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.578033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.611380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.611397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.644761] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.644779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.678102] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.678119] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.711444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.711461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.744805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.744822] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.778217] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.778234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.811596] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.811614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.844923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.844941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.878283] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.878300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.911680] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.911698] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.945004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.945021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1000.978346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1000.978363] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.011719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.011736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.045090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.045108] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.078442] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.078461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.111803] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.111820] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.145166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.145183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.178522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.178540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.211886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.211903] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.245201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.245218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.278610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.278628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.311936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.311953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.345294] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.345311] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.378689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.378706] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.412015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.412033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.445372] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.445390] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.478762] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.478779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.512076] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.512093] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.545438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.545456] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.578823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.578840] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.612185] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.612202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.645590] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.645608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.678920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.678937] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.712282] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.712300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.745694] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.745712] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.779013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.779031] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.812355] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.812382] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.845765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.845792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.879087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.879113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.912453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.912491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.945818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.945842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1001.979178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1001.979202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.012575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.012598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.045868] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.045894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.079232] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.079258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.112645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.112671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.145960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.145986] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.179331] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.179357] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.212719] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.212744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.246058] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.246080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.279417] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.279440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.312731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.312747] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.346099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.346116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.379459] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.379476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.412821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.412838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.446178] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.446195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.479583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.479601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.512917] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.512934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.546274] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.546292] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.579646] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.579663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.612972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.612990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.646351] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.646368] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.679738] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.679755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.713072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.713089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.746437] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.746454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.779790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.779808] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.813152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.813169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.846523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.846541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.879867] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.879884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.913228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.913246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.946618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.946635] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1002.979942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1002.979959] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.013308] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.013325] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.046701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.046718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.080034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.080051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.113349] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.113367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.146734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.146752] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.180106] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.180123] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.213462] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.213513] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.246836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.246854] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.280187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.280205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.313578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.313595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.346903] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.346921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.380248] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.380266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.413640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.413658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.446987] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.447005] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.480310] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.480328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.513705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.513723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.547065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.547083] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.580421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.580439] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.613775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.613792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.647128] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.647146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.680523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.680540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.713863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.713881] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.747222] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.747240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.780604] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.780622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.813942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.813960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.847277] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.847294] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.880693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.880710] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.914007] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.914024] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.947367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.947384] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1003.980754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1003.980771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.014099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.014117] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.047489] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.047506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.080820] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.080837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.114183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.114201] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.147576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.147593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.180883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.180900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.214260] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.214278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.247649] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.247667] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.280978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.280995] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.314337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.314354] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.347737] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.347755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.381059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.381076] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.414450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.414468] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.447763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.447781] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.481126] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.481143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.514530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.514548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.547855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.547872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.581196] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.581213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.614606] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.614623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.647940] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.647957] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.681296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.681314] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.714643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.714660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.748000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.748018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.781371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.781388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.814734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.814752] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.848094] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.848111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.881490] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.881508] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.914819] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.914837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.948179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.948197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1004.981552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1004.981570] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.014879] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.014896] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.048251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.048269] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.081631] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.081649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.114972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.114990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.148335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.148352] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.181692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.181709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.215082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.215100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.248371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.248437] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.281756] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.281773] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.315129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.315146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.348565] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.348583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.381849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.381866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.415212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.415229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.448602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.448619] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.481930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.481948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.515279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.515297] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.548635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.548653] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.582010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.582027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.615401] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.615418] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.648730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.648747] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.682088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.682106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.715541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.715559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.748811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.748828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.782153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.782170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.815547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.815564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.848889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.848907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.882245] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.882262] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.915605] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.915623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.948973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.948990] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1005.982325] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1005.982343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.015689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.015706] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.049026] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.049043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.082447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.082465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.115765] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.115783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.149122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.149140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.182512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.182529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.215892] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.215910] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.249205] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.249222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.282592] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.282609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.315905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.315922] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.349266] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.349284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.382643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.382660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.416000] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.416017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.449421] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.449438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.482722] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.482740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.516083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.516100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.549473] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.549490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.582826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.582844] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.616144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.616162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.649547] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.649564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.682877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.682894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.716242] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.716268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.749602] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.749629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.782960] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.782987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.816365] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.816393] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.849653] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.849680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.883016] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.883042] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.916448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.916474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.949774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.949801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1006.983137] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1006.983163] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.016528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.016554] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.049862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.049887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.083265] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.083283] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.116575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.116601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.149909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.149936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.183289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.183352] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.216652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.216679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.250017] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.250041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.283411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.283430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.316739] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.316763] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.350080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.350106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.383440] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.383466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.416773] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.416799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.450174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.450201] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.483541] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.483567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.516873] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.516900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.550231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.550258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.583569] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.583586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.616958] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.616985] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.650346] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.650373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.683650] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.683676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.717027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.717054] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.750443] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.750468] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.783770] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.783795] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.817155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.817178] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.850525] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.850548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.883853] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.883877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.917187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.917214] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.950567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.950585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1007.983928] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1007.983954] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.017329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.017352] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.050648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.050674] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.084013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.084037] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.117406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.117430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.150734] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.150757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.184052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.184079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.217452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.217479] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.250812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.250838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.284163] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.284189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.317580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.317600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.350888] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.350914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.384246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.384310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.417615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.417638] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.450943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.450970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.484342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.484368] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.517684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.517711] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.551056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.551083] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.584438] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.584465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.617769] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.617793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.651127] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.651151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.684523] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.684547] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.717832] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.717858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.751177] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.751204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.784554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.784577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.817921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.817946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.851326] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.851345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.884645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.884670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.918030] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.918053] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.951418] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.951440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1008.984697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1008.984723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.018055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.018082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.051492] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.051514] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.084799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.084825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.118165] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.118189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.151530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.151556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.184882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.184907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.218292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.218310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.251576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.251602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.284948] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.284974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.318353] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.318380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.351677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.351703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.385045] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.385070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.418463] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.418486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.451766] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.451787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.485123] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.485147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.518479] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.518506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.551849] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.551876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.585254] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.585272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.618557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.618582] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.651919] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.651942] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.685366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.685384] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.718627] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.718649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.752002] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.752025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.785370] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.785397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.818691] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.818719] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.852080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.852106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.885468] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.885494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.918795] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.918819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.952157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.952249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1009.985526] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1009.985549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.018874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1010.035339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1010.035385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1010.035457] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1010.053751] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1010.053795] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1010.053827] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1010.053871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1010.053912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1010.053956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1010.053996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1010.054036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1010.054075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1010.054120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1010.054163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1010.054205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1010.054335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1010.054366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1010.054395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1010.054451] [drm:intel_power_well_disable [i915]] disabling display
>[ 1010.054498] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1010.054543] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1010.054580] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1010.054843] [drm:drm_mode_addfb2] [FB:58]
>[ 1010.054876] [drm:drm_mode_addfb2] [FB:78]
>[ 1010.107315] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1010.107418] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.107485] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1010.107547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.107559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.107620] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1010.107643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1010.107665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1010.107692] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1010.107715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1010.107739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1010.107763] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1010.107786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1010.107810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1010.107830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1010.107853] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1010.107857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1010.107880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1010.107884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1010.107908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1010.107931] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1010.107954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1010.107976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1010.107999] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1010.108022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1010.108045] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1010.108069] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1010.108092] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1010.108116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1010.108142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1010.114784] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1010.114806] [drm:intel_power_well_enable [i915]] enabling display
>[ 1010.114825] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1010.114863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1010.114885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1010.114906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1010.114925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1010.114944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1010.114964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1010.114986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1010.115006] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1010.115026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1010.115045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1010.115062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1010.115085] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1010.115105] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1010.117181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1010.117223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1010.117242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1010.117262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1010.121123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1010.121161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1010.121192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1010.123948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1010.123980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1010.126992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1010.130304] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1010.130374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1010.130405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1010.130445] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1010.147164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1010.147299] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1010.147402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1010.163956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.163974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.197421] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.197438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.230745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.230762] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.264104] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.264122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.297444] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.297461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.330794] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.330811] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.364145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.364162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.397516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.397533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.430869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.430886] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.464267] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.464284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.497595] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.497612] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.530958] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.530975] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.564395] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.564413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.597680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.597697] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.631044] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.631061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.664417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.664434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.697810] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.697827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.731136] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.731262] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.764498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.764515] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.797872] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.797890] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.831289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.831307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.864565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.864582] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.897951] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.897978] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.931332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.931359] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.964672] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.964698] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1010.998034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1010.998060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.031426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.031452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.064868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.064894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.098120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.098216] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.131450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.131477] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.164807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.164833] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.198269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.198287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.231553] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.231577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.264965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.264991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.298255] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.298272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.331605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.331622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.364963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.364980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.398356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.398373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.431681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.431698] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.465028] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.465045] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.498387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.498404] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.531776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.531793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.565171] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.565188] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.598491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.598509] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.631855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.631872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.665207] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.665224] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.698558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.698575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.731931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.731948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.765317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.765334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.798648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.798666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.832012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.832029] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.865377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.865394] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.898734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.898751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.932076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.932093] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.965434] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.965451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1011.998806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1011.998823] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.032196] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.032213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.065549] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.065567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.098887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.098904] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.132275] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.132293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.165606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.165624] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.198954] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.198971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.232340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.232357] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.265654] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.265671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.299043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.299061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.332380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.332397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.365743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.365760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.399153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.399172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.432500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.432517] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.465831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.465848] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.499217] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.499235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.532564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.532581] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.565952] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.565979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.599318] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.599335] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.632646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.632663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.665971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.665987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.699401] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.699424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.732708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.732726] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.766103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.766121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.799410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.799428] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.832801] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.832818] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.866192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.866210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.899523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.899540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.932926] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.932943] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.966274] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.966292] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1012.999588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1012.999606] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.032943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.032961] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.066289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.066305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.099680] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.099698] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.133037] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.133129] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.166380] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.166397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.199761] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.199778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.233154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.233172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.266468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.266485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.299855] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.299872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.333228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.333245] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.366558] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.366575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.399915] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.399933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.433340] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.433358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.466633] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.466650] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.499997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.500015] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.533342] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.533360] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.566701] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.566718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.600110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.600127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.633433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.633450] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.666825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.666843] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.700186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.700203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.733521] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.733539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.766881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.766898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.800285] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.800304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.833576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.833603] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.866949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.866976] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.900315] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.900341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.933676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.933703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1013.967082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1013.967109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.000419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.000442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.033778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.033802] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.067142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.067169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.100467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.100493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.133848] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.133875] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.167260] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.167277] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.200571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.200597] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.233933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.233957] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.267294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.267318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.300655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.300678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.333988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.334088] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.367351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.367377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.400730] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.400756] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.434126] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.434143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.467450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.467476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.500807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.500832] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.534226] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.534244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.567534] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.567558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.600865] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.600892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.634252] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.634279] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.667606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.667633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.700968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.701061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.734325] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.734351] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.767692] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.767718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.801092] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.801110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.834415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.834438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.867746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.867772] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.901167] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.901194] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.934487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.934514] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1014.967842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1014.967868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.001236] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.001261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.034571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.034595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.067929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.067953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.101289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.101313] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.134611] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.134637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.168024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.168051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.201366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.201391] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.234719] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.234745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.268155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.268179] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.301443] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.301467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.334806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.334830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.368177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.368195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.401512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.401538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.434846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.434863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.468223] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.468240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.501576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.501593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.534942] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.535115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.568303] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.568321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.601663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.601681] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.635056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.635074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.668367] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.668384] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.701725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.701742] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.735125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.735142] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.768481] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.768498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.801821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.801838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.835214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.835231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.868544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.868561] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.901937] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.901997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.935249] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.935266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1015.968606] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1015.968623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.002007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.002025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.035341] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.035358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.068699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.068717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.102084] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.102101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.135417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.135434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.168781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.168798] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.202156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.202173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.235483] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.235500] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.268834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.268851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.302215] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.302232] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.335576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.335594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.368983] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.369001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.402327] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.402345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.435656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.435674] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.469033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.469050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.502361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.502378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.535737] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.535754] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.569128] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.569145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.602455] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.602472] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.635813] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.635830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.669179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.669196] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.702537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.702554] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.735882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.735898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.769251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.769268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.802613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.802630] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.836003] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.836020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.869335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.869353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.902708] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.902726] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.936083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.936100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1016.969415] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1016.969432] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.002762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.002779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.036141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.036158] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.069494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.069512] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.102846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.102863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.136216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.136233] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.169571] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.169588] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.202967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.202984] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.236293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.236310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.269636] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.269653] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.303027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.303044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.336369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.336386] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.369726] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.369743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.403124] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.403141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.436450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.436467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.469808] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.469825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.503154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.503171] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.536514] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.536532] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.569905] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.569922] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.603246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.603264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.636640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.636657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.670000] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.670018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.703329] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.703346] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.736687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.736704] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.770123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.770140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.803394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.803411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.836756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.836774] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.870129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.870146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.903485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.903502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.936846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.936901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1017.970209] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1017.970225] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.003564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.003581] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.036965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.036982] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.070272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.070289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.103632] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.103649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.137033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.137050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.170363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.170380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.203723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.203740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.237106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.237124] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.270419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.270437] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.303811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.303828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.337151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.337169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.370511] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.370529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.403924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.403942] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.437242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.437259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.470669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.470686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.504011] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.504028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.537338] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.537356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.570685] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.570702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.604059] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.604076] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.637384] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.637401] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.670778] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.670804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.704135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.704160] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.737500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.737525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.770902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.770924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.804225] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.804248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.837584] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.837608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.870946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.870973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.904292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.904319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.937656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.937682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1018.971043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1018.971069] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.004373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.004400] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.037720] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.037737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.071083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.071101] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.104440] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.104457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.137758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.137775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.171144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.171162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.204516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.204533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.237907] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.237925] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.271242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.271260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.304599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.304616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.337992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.338010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.371319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.371336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.404674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.404691] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.438048] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.438065] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.471396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.471414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.504754] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.504771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.538115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.538133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.571476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.571493] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.604869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.604886] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.638199] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.638217] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.671542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.671559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.704932] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.704949] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.738272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.738289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.771660] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.771677] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.805027] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.805044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.838356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.838373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.871710] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.871727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.905098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.905116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.938422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.938439] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1019.971816] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1019.971841] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.005149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1020.005166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.038507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1020.038524] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.071901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1020.071918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.105230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1020.105247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.138567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1020.138584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.171993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1020.172080] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1020.172135] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1020.172233] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1020.189227] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1020.189263] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1020.189307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1020.189348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1020.189393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1020.189433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1020.189474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1020.189513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1020.189558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1020.189601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1020.189643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1020.189686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1020.189725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1020.189764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1020.189910] [drm:intel_power_well_disable [i915]] disabling display
>[ 1020.189977] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1020.190045] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1020.190103] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1020.190431] [drm:drm_mode_addfb2] [FB:58]
>[ 1020.190478] [drm:drm_mode_addfb2] [FB:78]
>[ 1020.250731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1020.250923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1020.251010] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.251076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.251088] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.251148] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1020.251170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1020.251194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1020.251221] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1020.251244] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1020.251269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1020.251293] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1020.251317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1020.251340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1020.251364] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1020.251387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1020.251391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1020.251414] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1020.251418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1020.251442] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1020.251465] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1020.251488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1020.251510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1020.251534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1020.251557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1020.251581] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1020.251604] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1020.251627] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1020.251652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1020.251678] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1020.258043] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1020.258062] [drm:intel_power_well_enable [i915]] enabling display
>[ 1020.258079] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1020.258116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1020.258137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1020.258156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1020.258179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1020.258203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1020.258226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1020.258252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1020.258277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1020.258302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1020.258325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1020.258348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1020.258374] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1020.258397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1020.260621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1020.260644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1020.260664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1020.260684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1020.262259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1020.262280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1020.262298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1020.263880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1020.263901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1020.265766] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1020.269133] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1020.269216] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1020.269247] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1020.269287] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1020.285976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1020.286022] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1020.286087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1020.302862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.302882] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.336220] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.336238] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.369575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.369593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.402961] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.402979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.436291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.436309] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.469649] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.469666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.503004] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.503022] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.536389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.536407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.569738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.569793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.603097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.603115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.636457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.636474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.669854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.669872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.703180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.703198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.736522] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.736539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.769915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.769932] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.803266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.803288] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.836635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.836660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.870025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.870050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.903353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.903378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.936717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.936814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1020.970082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1020.970105] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.003409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.003436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.036799] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.036826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.070152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.070178] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.103512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.103538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.136902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.136928] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.170236] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.170261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.203594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.203618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.236986] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.237009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.270288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.270315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.303695] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.303789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.337031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.337057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.370389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.370415] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.403790] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.403810] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.437111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.437137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.470474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.470498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.503867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.503892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.537141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.537168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.570526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.570552] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.603939] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.603965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.637269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.637294] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.670647] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.670671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.703991] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.704016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.737352] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.737376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.770754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.770782] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.804038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.804066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.837409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.837435] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.870818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.870844] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.904144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.904169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.937508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.937534] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1021.970901] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1021.970926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.004234] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.004257] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.037580] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.037604] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.070953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.070980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.104280] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.104307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.137662] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.137761] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.171056] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.171082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.204385] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.204411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.237783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.237804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.271111] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.271136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.304484] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.304501] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.337832] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.337859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.371159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.371186] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.404551] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.404577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.437937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.437964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.471294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.471320] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.504627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.504650] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.537988] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.538012] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.571347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.571370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.604718] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.604746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.638037] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.638064] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.671398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.671425] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.704809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.704836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.738142] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.738167] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.771498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.771523] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.804928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.804950] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.838226] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.838248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.871555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.871582] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.904915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.904942] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.938310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.938327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1022.971697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1022.971720] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.005021] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.005045] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.038378] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.038402] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.071775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.071799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.105101] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.105125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.138433] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.138460] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.171815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.171842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.205179] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.205205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.238534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.238561] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.271925] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.271949] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.305259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.305285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.338620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.338679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.371983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.372007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.405310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.405337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.438705] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.438732] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.472053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.472080] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.505413] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.505440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.538772] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.538799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.572134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.572159] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.605497] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.605521] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.638890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.638914] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.672194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.672221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.705553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.705580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.738933] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.738959] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.772293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.772318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.805734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.805751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.839015] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.839039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.872381] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.872404] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.905767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.905790] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.939067] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.939094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1023.972430] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1023.972456] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.005840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.005867] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.039165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.039192] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.072533] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.072558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.105892] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.105918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.139256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.139280] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.172683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.172701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.205950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.205976] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.239307] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.239334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.272728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.272755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.306065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.306086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.339409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.339436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.372800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.372825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.406131] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.406155] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.439512] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.439531] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.472855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.472882] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.506184] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.506211] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.539564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.539663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.572940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.572962] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.606288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.606313] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.639682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.639702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.673011] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.673034] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.706374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.706395] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.739739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.739765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.773061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.773087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.806429] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.806454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.839836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.839861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.873167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.873192] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.906530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.906553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.939914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.939937] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1024.973250] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1024.973272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.006620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.006648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.039940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.039967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.073320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.073347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.106712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.106737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.140045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.140070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.173402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.173427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.206798] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.206825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.240130] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.240151] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.273458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.273484] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.306817] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.306844] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.340202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.340228] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.373602] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.373626] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.406926] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.406950] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.440294] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.440319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.473678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.473703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.507006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.507030] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.540333] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.540359] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.573749] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.573775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.607077] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.607103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.640437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.640464] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.673831] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.673857] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.707162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.707187] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.740526] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.740587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.773889] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.773911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.807222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.807248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.840623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.840650] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.873959] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.873986] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.907316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.907342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.940733] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.940750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1025.974040] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1025.974066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.007399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.007423] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.040812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.040836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.074095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.074122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.107458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.107485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.140836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.140862] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.174194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.174221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.207598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.207617] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.240920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.240947] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.274277] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.274301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.307673] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.307696] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.340974] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.341001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.374330] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.374357] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.407779] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.407804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.441075] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.441098] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.474436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.474461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.507796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.507820] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.541159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.541183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.574559] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.574579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.607854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.607880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.641208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.641234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.674625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.674663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.707950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.707976] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.741311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.741335] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.774707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.774732] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.808038] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.808061] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.841398] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.841421] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.874758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.874785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.908112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.908138] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.941474] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.941536] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1026.974851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1026.974876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.008194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.008219] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.041595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.041613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.074915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.074939] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.108275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.108299] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.141653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.141680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.174965] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.174992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.208347] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.208373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.241738] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.241765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.275073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.275098] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.308434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.308457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.341795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.341819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.375154] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.375177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.408547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.408570] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.441843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.441870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.475227] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.475252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.508616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.508642] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.541947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.541973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.575306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.575330] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.608699] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.608724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.642033] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.642055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.675368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.675396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.708725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.708751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.742105] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.742131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.775527] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.775545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.808829] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.808852] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.842187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.842212] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.875581] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.875604] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.908942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.908960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.942242] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.942268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1027.975632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1027.975659] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.008983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.009009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.042343] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.042369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.075739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.075764] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.109068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.109092] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.142478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.142497] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.175793] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.175816] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.209121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.209148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.242510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.242537] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.275866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.275892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.309222] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.309249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.342621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.342644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.375944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.375969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.409303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.409326] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.442698] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.442721] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.475999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.476026] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.509357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.509383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.542739] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.542763] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.576099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.576125] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.609500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.609519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.642795] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.642819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.676187] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.676208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.709603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.709627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.742876] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.742902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.776258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.776285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.809651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.809677] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.842979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.843003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.876337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.876361] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.909704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.909722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.943061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.943084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1028.976461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1028.976483] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.009759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.009786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.043113] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.043140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.076531] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.076557] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.109855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.109882] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.143186] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.143203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.176588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.176605] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.209919] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.209936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.243276] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.243294] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.276636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.276654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.309981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.309999] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.343356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.343374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.376713] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.376730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.410076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.410094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.443468] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.443486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.476796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.476814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.510141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.510159] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.543532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.543549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.576860] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.576878] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.610230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.610247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.643635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.643653] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.676956] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.676973] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.710313] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.710331] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.743672] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.743689] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.777029] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.777047] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.810422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.810440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.843741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.843758] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.877127] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.877145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.910505] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.910522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.943833] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.943851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1029.977189] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1029.977206] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.010597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.010615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.043917] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.043934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.077257] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.077275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.110616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.110633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.143989] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.144007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.177348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.177412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.210712] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.210730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.244043] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.244060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.277463] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.277480] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.310803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1030.310892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1030.310946] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1030.311027] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1030.328050] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1030.328088] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1030.328128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1030.328162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1030.328198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1030.328229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1030.328258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1030.328289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1030.328324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1030.328357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1030.328457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1030.328510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.328541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1030.328568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1030.328623] [drm:intel_power_well_disable [i915]] disabling display
>[ 1030.328670] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1030.328712] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1030.328746] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1030.330377] [IGT] kms_flip: exiting, ret=0
>[ 1030.350932] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1030.350958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1030.350984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1030.351012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1030.351035] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1030.351075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1030.351110] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1030.351140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1030.351169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1030.351196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1030.351222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1030.351228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.351253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1030.351257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.351283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1030.351308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1030.351333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1030.351358] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1030.351433] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1030.351458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1030.351483] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1030.351508] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1030.351532] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1030.351564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1030.351602] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1030.351715] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1030.351746] [drm:intel_power_well_enable [i915]] enabling display
>[ 1030.351776] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1030.351833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1030.351868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1030.351904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1030.351940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1030.351975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1030.352010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1030.352049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1030.352088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1030.352111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.352129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1030.352153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1030.352178] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1030.352202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1030.354263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1030.354284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1030.354307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1030.354332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1030.358004] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1030.358030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1030.358053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1030.360765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1030.360801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1030.363819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1030.367294] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1030.367351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1030.367393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1030.367419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1030.367481] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1030.367509] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1030.384139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1030.384185] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1030.384252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.384533] Console: switching to colour frame buffer device 240x75
>[ 1030.492601] Console: switching to colour dummy device 80x25
>[ 1030.492717] [IGT] kms_flip: executing
>[ 1030.507231] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1030.507278] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1030.509416] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1030.509452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1030.511569] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1030.511581] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1030.513699] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1030.513738] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1030.515852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1030.515865] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1030.515873] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1030.515905] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1030.515947] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1030.517062] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1030.518006] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1030.518028] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1030.518046] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1030.518064] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1030.519096] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1030.519119] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1030.520234] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1030.520238] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1030.520394] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1030.520399] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1030.520409] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1030.520415] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1030.520424] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1030.520428] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1030.520444] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1030.520450] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.520456] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1030.520463] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1030.520469] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1030.520474] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1030.520480] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1030.520487] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1030.520493] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1030.520499] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1030.520505] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1030.520512] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1030.520518] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1030.520523] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1030.520529] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1030.520537] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1030.520543] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1030.520549] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1030.520554] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1030.520561] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1030.520567] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1030.520573] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1030.520579] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1030.520585] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1030.520590] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1030.520597] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1030.520603] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1030.520610] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1030.520615] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1030.520622] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1030.520629] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1030.520684] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1030.520709] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1030.522828] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1030.522871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1030.524461] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1030.524472] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1030.526589] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1030.526628] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1030.528746] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1030.528756] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1030.528764] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1030.529179] [IGT] kms_flip: starting subtest vblank-vs-dpms-suspend
>[ 1030.529961] [drm:drm_mode_addfb2] [FB:77]
>[ 1030.529988] [drm:drm_mode_addfb2] [FB:79]
>[ 1030.583088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.583151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1030.584266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1030.584309] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1030.584439] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1030.601452] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1030.601496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1030.601528] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1030.601568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1030.601601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1030.601636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1030.601675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1030.601715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1030.601754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1030.601799] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1030.601841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1030.601883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1030.601924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.601963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1030.602001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1030.602059] [drm:intel_power_well_disable [i915]] disabling display
>[ 1030.602105] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1030.602157] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1030.602196] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1030.602287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1030.602470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1030.602610] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1030.602629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1030.602717] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1030.602751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1030.602787] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1030.602824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1030.602856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1030.602890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1030.602923] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1030.602955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1030.602987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1030.603017] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1030.603046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1030.603054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.603082] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1030.603089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.603118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1030.603147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1030.603176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1030.603207] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1030.603250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1030.603280] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1030.603311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1030.603340] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1030.603392] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1030.603429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1030.603465] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1030.606741] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1030.606761] [drm:intel_power_well_enable [i915]] enabling display
>[ 1030.606777] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1030.606812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1030.606832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1030.606851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1030.606868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1030.606886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1030.606904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1030.606924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1030.606943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1030.606962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.606984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1030.607007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1030.607032] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1030.607055] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1030.609112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1030.609133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1030.609151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1030.609170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1030.613101] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1030.613139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1030.613170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1030.615904] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1030.615941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1030.619070] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1030.622395] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1030.622455] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1030.622487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1030.622529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1030.622607] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1030.622640] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1030.639246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1030.639296] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1030.639450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.672768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1030.672806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1030.672843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1030.672882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1030.672912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1030.672946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1030.672980] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1030.673011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1030.673042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1030.673071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1030.673099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1030.673107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.673144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1030.673151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.673191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1030.673231] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1030.673270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1030.673308] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1030.673348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1030.673481] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1030.673540] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1030.673590] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1030.673640] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1030.673696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1030.673753] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1030.689257] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1030.689303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1030.689473] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1030.706521] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1030.706564] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1030.706597] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1030.706635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1030.706668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1030.706700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1030.706731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1030.706760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1030.706792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1030.706825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1030.706857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1030.706888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.706916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1030.706944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1030.706996] [drm:intel_power_well_disable [i915]] disabling display
>[ 1030.707037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1030.707068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1030.707101] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1030.707136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.707164] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1030.744108] PM: Syncing filesystems ... done.
>[ 1030.744381] PM: Preparing system for sleep (mem)
>[ 1030.744886] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1030.746756] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1030.748249] PM: Suspending system (mem)
>[ 1030.748392] Suspending console(s) (use no_console_suspend to debug)
>[ 1030.750517] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[ 1030.750617] sd 0:0:0:0: [sda] Stopping disk
>[ 1030.751698] e1000e: EEE TX LPI TIMER: 00000011
>[ 1030.751806] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1030.751834] [drm:intel_power_well_enable [i915]] enabling display
>[ 1030.751863] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1030.753078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1030.753150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1030.753171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1030.753193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1030.753218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1030.753243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1030.753267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1030.753296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1030.753322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1030.753373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1030.753396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.753415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1030.753433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1030.753458] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1030.791135] PM: suspend of devices complete after 41.529 msecs
>[ 1030.792689] [drm:intel_power_well_disable [i915]] disabling display
>[ 1030.792733] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1030.792758] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1030.792793] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1030.804412] PM: late suspend of devices complete after 13.263 msecs
>[ 1030.806631] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1030.806781] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1030.818463] PM: noirq suspend of devices complete after 14.045 msecs
>[ 1030.818839] ACPI: Preparing to enter system sleep state S3
>[ 1030.844043] PM: Saving platform NVS memory
>[ 1030.844198] Disabling non-boot CPUs ...
>[ 1030.856901] smpboot: CPU 1 is now offline
>[ 1030.869391] Broke affinity for irq 23
>[ 1030.869398] Broke affinity for irq 42
>[ 1030.870715] smpboot: CPU 2 is now offline
>[ 1030.880463] Broke affinity for irq 8
>[ 1030.880468] Broke affinity for irq 9
>[ 1030.880475] Broke affinity for irq 23
>[ 1030.880481] Broke affinity for irq 42
>[ 1030.880485] Broke affinity for irq 43
>[ 1030.881559] smpboot: CPU 3 is now offline
>[ 1030.883537] ACPI: Low-level resume complete
>[ 1030.883687] PM: Restoring platform NVS memory
>[ 1030.884235] Suspended for 16.340 seconds
>[ 1030.884331] Enabling non-boot CPUs ...
>[ 1030.884470] x86: Booting SMP configuration:
>[ 1030.884476] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1030.886627]  cache: parent cpu1 should not be sleeping
>[ 1030.888143] CPU1 is up
>[ 1030.888259] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1030.889765]  cache: parent cpu2 should not be sleeping
>[ 1030.890657] CPU2 is up
>[ 1030.890726] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1030.892055]  cache: parent cpu3 should not be sleeping
>[ 1030.893948] CPU3 is up
>[ 1030.902827] ACPI: Waking up from system sleep state S3
>[ 1030.927940] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1030.927948] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1030.928501] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1030.928796] PM: noirq resume of devices complete after 13.344 msecs
>[ 1030.929089] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1030.929183] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1030.929217] [drm:intel_power_well_enable [i915]] enabling display
>[ 1030.931359] PM: early resume of devices complete after 2.424 msecs
>[ 1030.931667] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[ 1030.931728] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1030.931758] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1030.932981] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1030.935241] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1030.937558] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1030.937583] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1030.937608] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1030.937633] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1030.937835] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1030.937859] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1030.937890] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1030.937923] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1030.937951] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1030.937977] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1030.938009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1030.938088] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1030.938115] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1030.938145] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1030.938170] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1030.938198] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1030.938222] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1030.938249] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1030.938275] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1030.938300] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1030.938322] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1030.938344] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1030.938365] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1030.938391] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1030.938414] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1030.938433] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1030.938455] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1030.938477] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1030.938506] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1030.938556] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1030.938579] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1030.938613] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1030.938637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1030.938660] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1030.938682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1030.938689] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1030.938711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1030.938715] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1030.938737] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1030.938755] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1030.938776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1030.938798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1030.938822] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1030.938845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1030.938866] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1030.938888] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1030.938905] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1030.938928] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1030.938949] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1030.938970] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1030.938991] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1030.938995] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1030.939018] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1030.939024] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1030.939046] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1030.939067] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1030.939089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1030.939110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1030.939135] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1030.939152] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1030.939185] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1030.939203] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1030.939218] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1030.939236] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1030.939252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1030.939267] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1030.939282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1030.939286] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1030.939301] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1030.939304] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1030.939320] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1030.939335] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1030.939350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1030.939365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1030.939384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1030.939400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1030.939416] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1030.939432] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1030.939447] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1030.939468] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1030.939486] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1030.939503] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1030.939573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1030.939591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1030.939611] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1030.939633] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1030.939651] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1030.939670] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1030.939688] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1030.939706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1030.939723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1030.939740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1030.939755] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1030.939759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.939775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1030.939778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1030.939795] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1030.939810] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1030.939826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1030.939841] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1030.939860] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1030.939876] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1030.939891] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1030.939907] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1030.939922] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1030.939946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1030.939972] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1030.940063] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1030.940097] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1030.940121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1030.940145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1030.940168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1030.940192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1030.940215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1030.940238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1030.940265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1030.940291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1030.940316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1030.940341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1030.940366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.940389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1030.940412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1030.940438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1030.940465] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1030.940494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1030.940519] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1030.940558] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1030.940676] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1030.940719] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1030.942324] sd 0:0:0:0: [sda] Starting disk
>[ 1030.942766] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1030.942797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1030.944864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1030.944872] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1030.946992] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1030.947030] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1030.949146] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1030.949157] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1030.949165] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1030.949205] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1030.950328] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1030.951265] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1030.951285] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1030.951303] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1030.951321] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1030.952336] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1030.952360] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1030.953307] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1030.953333] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1030.955458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1030.955496] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1030.957628] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1030.957638] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1030.959759] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1030.959797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1030.961910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1030.961920] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1030.961927] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1031.127286] PM: resume of devices complete after 195.930 msecs
>[ 1031.128287] PM: Finishing wakeup.
>[ 1031.128290] Restarting tasks ... 
>[ 1031.128547] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1031.128552] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1031.128640] [drm:intel_power_well_disable [i915]] disabling display
>[ 1031.128666] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1031.128682] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1031.134897] done.
>[ 1031.139891] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1031.139929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1031.139966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1031.140004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1031.140036] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1031.140070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1031.140104] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1031.140135] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1031.140166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1031.140196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1031.140225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.140234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.140262] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.140269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.140300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1031.140329] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1031.140358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.140387] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1031.140420] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.140449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.140479] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1031.140509] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1031.141075] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1031.141112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.141148] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1031.141254] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1031.141286] [drm:intel_power_well_enable [i915]] enabling display
>[ 1031.141317] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1031.141369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.141402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.141433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.141465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.141495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.141770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.141807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.141841] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.141875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.141905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.141935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.141970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1031.142002] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1031.151807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1031.151843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1031.151876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1031.151910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1031.153776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1031.153812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1031.153844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1031.155430] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1031.155467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1031.157368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1031.160122] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1031.160198] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1031.160232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1031.160279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1031.160361] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1031.160394] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1031.160474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.160516] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1031.160623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.177194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1031.177241] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1031.177285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1031.177333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1031.177375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1031.177417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1031.177457] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1031.177499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1031.177603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1031.177654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1031.177706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.177721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.177765] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.177779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.177826] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1031.177869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1031.177916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.177958] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1031.178009] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.178056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.178100] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] FB:79, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1031.178147] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1031.178187] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1031.178237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.178294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1031.193657] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1031.193706] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1031.193791] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1031.210809] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1031.210853] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1031.210885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1031.210925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.210957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.210989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.211018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.211047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.211078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.211113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.211145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.211177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.211205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.211242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.211300] [drm:intel_power_well_disable [i915]] disabling display
>[ 1031.211346] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1031.211387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.211429] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1031.211474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.211508] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1031.249450] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1031.262969] ata1.00: configured for UDMA/133
>[ 1031.294457] PM: Syncing filesystems ... done.
>[ 1031.294735] PM: Preparing system for sleep (mem)
>[ 1031.295190] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1031.296706] Freezing remaining freezable tasks ... (elapsed 0.000 seconds) done.
>[ 1031.297689] PM: Suspending system (mem)
>[ 1031.297800] Suspending console(s) (use no_console_suspend to debug)
>[ 1031.300056] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[ 1031.300134] sd 0:0:0:0: [sda] Stopping disk
>[ 1031.301147] e1000e: EEE TX LPI TIMER: 00000011
>[ 1031.301245] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1031.301273] [drm:intel_power_well_enable [i915]] enabling display
>[ 1031.301302] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1031.312772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.312876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.312909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.312945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.312975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.313003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.313033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.313068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.313100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.313130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.313161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.313187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.313214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.313249] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1031.414735] PM: suspend of devices complete after 115.730 msecs
>[ 1031.416208] [drm:intel_power_well_disable [i915]] disabling display
>[ 1031.416250] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1031.416276] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1031.416310] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1031.427615] PM: late suspend of devices complete after 12.873 msecs
>[ 1031.429737] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1031.429904] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1031.441658] PM: noirq suspend of devices complete after 14.036 msecs
>[ 1031.442034] ACPI: Preparing to enter system sleep state S3
>[ 1031.467305] PM: Saving platform NVS memory
>[ 1031.467460] Disabling non-boot CPUs ...
>[ 1031.477177] smpboot: CPU 1 is now offline
>[ 1031.491748] Broke affinity for irq 23
>[ 1031.491755] Broke affinity for irq 42
>[ 1031.493073] smpboot: CPU 2 is now offline
>[ 1031.509503] Broke affinity for irq 8
>[ 1031.509508] Broke affinity for irq 9
>[ 1031.509514] Broke affinity for irq 23
>[ 1031.509519] Broke affinity for irq 42
>[ 1031.509523] Broke affinity for irq 43
>[ 1031.510587] smpboot: CPU 3 is now offline
>[ 1031.512538] ACPI: Low-level resume complete
>[ 1031.512684] PM: Restoring platform NVS memory
>[ 1031.513224] Suspended for 16.373 seconds
>[ 1031.513326] Enabling non-boot CPUs ...
>[ 1031.513479] x86: Booting SMP configuration:
>[ 1031.513485] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1031.515577]  cache: parent cpu1 should not be sleeping
>[ 1031.517099] CPU1 is up
>[ 1031.517220] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1031.518678]  cache: parent cpu2 should not be sleeping
>[ 1031.519605] CPU2 is up
>[ 1031.519672] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1031.521033]  cache: parent cpu3 should not be sleeping
>[ 1031.522965] CPU3 is up
>[ 1031.531775] ACPI: Waking up from system sleep state S3
>[ 1031.556088] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1031.556096] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1031.556226] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1031.556646] PM: noirq resume of devices complete after 12.296 msecs
>[ 1031.556988] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1031.557076] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1031.557104] [drm:intel_power_well_enable [i915]] enabling display
>[ 1031.559074] PM: early resume of devices complete after 2.252 msecs
>[ 1031.559399] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[ 1031.559461] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1031.559491] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1031.560591] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1031.563020] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1031.564722] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1031.564748] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1031.564771] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1031.564794] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1031.564979] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1031.565006] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1031.565039] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1031.565067] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1031.565098] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1031.565122] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1031.565153] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1031.565241] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1031.565269] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1031.565298] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1031.565322] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1031.565348] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1031.565373] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1031.565400] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1031.565425] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1031.565451] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1031.565475] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1031.565497] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1031.565519] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1031.565544] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1031.565567] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1031.565588] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1031.565609] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1031.565630] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1031.565660] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1031.565683] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1031.565733] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1031.565769] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1031.565792] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1031.565815] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1031.565833] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.565838] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1031.565860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.565866] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1031.565889] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1031.565912] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1031.565935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.565956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1031.565981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.566002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.566026] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1031.566049] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1031.566071] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1031.566096] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1031.566117] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1031.566139] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1031.566157] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.566161] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1031.566180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.566185] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1031.566208] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1031.566229] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1031.566250] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.566267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1031.566292] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.566314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.566335] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1031.566357] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1031.566377] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1031.566400] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1031.566417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1031.566448] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1031.566466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.566469] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1031.566490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.566494] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1031.566517] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1031.566541] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1031.566564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.566587] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1031.566609] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.566632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.566655] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1031.566678] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1031.566714] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1031.566740] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1031.566764] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1031.566787] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1031.566839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1031.566859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1031.566880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1031.566903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1031.566920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1031.566940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1031.566960] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1031.566978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1031.566996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1031.567012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1031.567029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.567033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.567048] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.567052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.567074] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1031.567098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1031.567121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.567144] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1031.567167] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.567190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.567213] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1031.567236] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1031.567259] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1031.567284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.567310] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1031.567391] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1031.567425] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1031.567449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.567473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.567496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.567519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.567543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.567566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1031.567592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1031.567618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.567643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.567668] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.567693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.567727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.567750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.567776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.567803] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1031.567832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.567856] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1031.567885] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1031.567991] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1031.568049] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1031.569944] sd 0:0:0:0: [sda] Starting disk
>[ 1031.570128] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1031.570169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1031.572260] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1031.572269] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1031.574349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1031.574383] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1031.576461] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1031.576469] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1031.576477] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1031.576510] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1031.577611] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1031.578549] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1031.578569] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1031.578587] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1031.578605] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1031.579638] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1031.579656] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1031.580641] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1031.580666] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1031.582802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1031.582840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1031.584956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1031.584966] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1031.587085] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1031.587123] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1031.589243] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1031.589253] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1031.589260] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1031.785216] PM: resume of devices complete after 226.145 msecs
>[ 1031.786240] PM: Finishing wakeup.
>[ 1031.786242] Restarting tasks ... 
>[ 1031.787047] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1031.787053] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1031.787150] [drm:intel_power_well_disable [i915]] disabling display
>[ 1031.787180] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1031.787198] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1031.787769] done.
>[ 1031.791172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.791242] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1031.791280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.791314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.791348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.791379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.791410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.791442] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.791475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.791510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.791543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.791576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.791606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.791635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.791677] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1031.791747] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1031.792060] [drm:drm_mode_addfb2] [FB:77]
>[ 1031.792109] [drm:drm_mode_addfb2] [FB:78]
>[ 1031.839535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1031.839649] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1031.839813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1031.839929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1031.839942] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1031.840002] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1031.840024] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1031.840048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1031.840073] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1031.840097] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1031.840121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1031.840145] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1031.840169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1031.840193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1031.840214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1031.840237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.840242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.840265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.840269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.840293] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1031.840320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1031.840345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.840365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1031.840386] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.840405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.840423] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1031.840440] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1031.840457] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1031.840478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.840500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1031.843881] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1031.843903] [drm:intel_power_well_enable [i915]] enabling display
>[ 1031.843923] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1031.843962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.843986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.844010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.844034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.844057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.844080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.844105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.844130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.844155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.844178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.844201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.844226] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1031.844250] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1031.846325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1031.846346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1031.846369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1031.846393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1031.847975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1031.847996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1031.848014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1031.849579] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1031.849600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1031.851472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1031.854784] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1031.854851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1031.854884] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1031.854928] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1031.871597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.871645] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1031.871760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.875850] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1031.893149] ata1.00: configured for UDMA/133
>[ 1031.905172] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1031.905214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1031.905254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1031.905296] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1031.905336] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1031.905379] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1031.905419] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1031.905461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1031.905503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1031.905538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1031.905578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1031.905587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.905627] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1031.905634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1031.905675] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1031.905805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1031.905850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1031.905893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1031.905941] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1031.905984] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1031.906029] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1031.906069] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1031.906109] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1031.906160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.906209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1031.906340] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1031.906399] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1031.906499] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1031.922253] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1031.922291] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1031.922331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.922365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.922396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.922425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.922454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.922485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.922519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.922559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.922601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.922640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.922679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.922818] [drm:intel_power_well_disable [i915]] disabling display
>[ 1031.922883] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1031.922938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.922996] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1031.923050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.923099] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1031.958247] PM: Syncing filesystems ... done.
>[ 1031.958481] PM: Preparing system for sleep (mem)
>[ 1031.959199] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1031.960886] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1031.962371] PM: Suspending system (mem)
>[ 1031.962480] Suspending console(s) (use no_console_suspend to debug)
>[ 1031.964844] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[ 1031.964915] sd 0:0:0:0: [sda] Stopping disk
>[ 1031.965998] e1000e: EEE TX LPI TIMER: 00000011
>[ 1031.966091] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1031.966119] [drm:intel_power_well_enable [i915]] enabling display
>[ 1031.966148] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1031.966514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1031.966614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1031.966644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1031.966678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1031.966735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1031.966762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1031.966792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1031.966826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1031.966857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1031.966888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1031.966918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1031.966945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1031.966971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1031.967006] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1032.088472] PM: suspend of devices complete after 124.770 msecs
>[ 1032.090080] [drm:intel_power_well_disable [i915]] disabling display
>[ 1032.090114] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1032.090134] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1032.090164] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1032.101828] PM: late suspend of devices complete after 13.349 msecs
>[ 1032.104179] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1032.104442] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1032.115830] PM: noirq suspend of devices complete after 13.993 msecs
>[ 1032.116207] ACPI: Preparing to enter system sleep state S3
>[ 1032.141564] PM: Saving platform NVS memory
>[ 1032.141729] Disabling non-boot CPUs ...
>[ 1032.155104] smpboot: CPU 1 is now offline
>[ 1032.167771] Broke affinity for irq 23
>[ 1032.167778] Broke affinity for irq 42
>[ 1032.169098] smpboot: CPU 2 is now offline
>[ 1032.180770] Broke affinity for irq 8
>[ 1032.180774] Broke affinity for irq 9
>[ 1032.180781] Broke affinity for irq 23
>[ 1032.180786] Broke affinity for irq 42
>[ 1032.180790] Broke affinity for irq 43
>[ 1032.181838] smpboot: CPU 3 is now offline
>[ 1032.183690] ACPI: Low-level resume complete
>[ 1032.183836] PM: Restoring platform NVS memory
>[ 1032.184377] Suspended for 16.330 seconds
>[ 1032.184478] Enabling non-boot CPUs ...
>[ 1032.184622] x86: Booting SMP configuration:
>[ 1032.184628] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1032.186747]  cache: parent cpu1 should not be sleeping
>[ 1032.188278] CPU1 is up
>[ 1032.188394] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1032.189829]  cache: parent cpu2 should not be sleeping
>[ 1032.190696] CPU2 is up
>[ 1032.190764] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1032.192097]  cache: parent cpu3 should not be sleeping
>[ 1032.194052] CPU3 is up
>[ 1032.203092] ACPI: Waking up from system sleep state S3
>[ 1032.227300] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1032.227309] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1032.227352] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1032.227770] PM: noirq resume of devices complete after 12.163 msecs
>[ 1032.228062] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1032.228189] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1032.228224] [drm:intel_power_well_enable [i915]] enabling display
>[ 1032.230647] PM: early resume of devices complete after 2.784 msecs
>[ 1032.231241] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[ 1032.231287] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1032.231306] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1032.231882] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1032.235147] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1032.237437] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1032.237463] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1032.237488] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1032.237514] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1032.237686] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1032.237713] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1032.237744] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1032.237775] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1032.237818] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1032.237849] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1032.237880] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1032.237962] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1032.237989] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1032.238018] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1032.238044] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1032.238075] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1032.238100] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1032.238129] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1032.238157] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1032.238185] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1032.238212] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1032.238238] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1032.238264] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1032.238293] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1032.238322] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1032.238348] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1032.238374] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1032.238400] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1032.238431] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1032.238462] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1032.238492] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1032.238526] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1032.238552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1032.238577] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1032.238603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.238608] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.238633] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.238637] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.238663] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1032.238689] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1032.238715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.238741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.238767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.238793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.238830] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1032.238856] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1032.238882] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1032.238910] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1032.238935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1032.238961] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1032.238987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.238991] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.239016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.239020] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.239046] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1032.239072] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1032.239098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.239124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.239149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.239175] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.239201] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1032.239226] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1032.239252] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1032.239280] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1032.239306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1032.239332] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1032.239356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.239360] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.239385] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.239389] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.239415] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1032.239441] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1032.239467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.239493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.239519] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.239544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.239570] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1032.239595] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1032.239621] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1032.239650] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1032.239676] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1032.239702] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1032.239761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1032.239787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1032.239828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1032.239858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1032.239883] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1032.239910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1032.239937] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1032.239962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1032.239989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1032.240014] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1032.240039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.240044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.240069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.240073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.240099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1032.240125] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1032.240151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.240176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.240202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.240228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.240254] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1032.240280] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1032.240305] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1032.240333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1032.240363] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1032.240463] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1032.240501] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1032.240528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1032.240554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1032.240581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1032.240607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1032.240633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1032.240659] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1032.240689] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1032.240718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1032.240746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1032.240774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1032.240802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.240839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1032.240865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1032.240896] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1032.240927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1032.240957] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1032.240988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.241016] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1032.241142] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1032.241188] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1032.241714] sd 0:0:0:0: [sda] Starting disk
>[ 1032.243238] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1032.243261] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1032.245383] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1032.245394] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1032.247514] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1032.247552] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1032.249663] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1032.249674] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1032.249681] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1032.249721] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1032.250879] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1032.251797] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1032.251834] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1032.251854] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1032.251872] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1032.252894] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1032.252912] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1032.253867] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1032.253901] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1032.256018] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1032.256056] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1032.258173] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1032.258183] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1032.260301] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1032.260339] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1032.262453] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1032.262463] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1032.262470] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1032.454482] PM: resume of devices complete after 223.839 msecs
>[ 1032.455576] PM: Finishing wakeup.
>[ 1032.455583] Restarting tasks ... 
>[ 1032.456474] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1032.456479] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1032.456579] [drm:intel_power_well_disable [i915]] disabling display
>[ 1032.456609] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1032.456626] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1032.461996] done.
>[ 1032.467389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1032.467425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1032.467459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1032.467495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1032.467525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1032.467556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1032.467589] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1032.467617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1032.467647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1032.467675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1032.467703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.467711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.467739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.467745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.467774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1032.467881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1032.467907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.467935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.467965] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.467994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.468026] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1032.468053] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1032.468081] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1032.468114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1032.468149] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1032.468234] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1032.468265] [drm:intel_power_well_enable [i915]] enabling display
>[ 1032.468295] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1032.468347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1032.468378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1032.468406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1032.468434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1032.468461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1032.468491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1032.468525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1032.468557] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1032.468589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.468615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1032.468642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1032.468676] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1032.468705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1032.470827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1032.470863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1032.470894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1032.470926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1032.472530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1032.472564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1032.472596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1032.474162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1032.474198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1032.476088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1032.479096] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1032.479170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1032.479203] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1032.479241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1032.479339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1032.479381] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1032.479445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.496226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1032.496282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1032.496322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1032.496362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1032.496393] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1032.496428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1032.496462] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1032.496494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1032.496525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1032.496554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1032.496582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.496591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.496618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.496625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.496653] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1032.496680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1032.496707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.496734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.496767] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.496806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.496914] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1032.496955] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1032.496997] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1032.497046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1032.497097] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1032.497190] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1032.497232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1032.497303] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1032.513482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1032.513519] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1032.513559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1032.513592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1032.513622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1032.513651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1032.513679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1032.513710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1032.513743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1032.513774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1032.513885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.513927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1032.513969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1032.514054] [drm:intel_power_well_disable [i915]] disabling display
>[ 1032.514123] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1032.514173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1032.514226] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1032.514278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.514313] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1032.548702] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1032.564328] ata1.00: configured for UDMA/133
>[ 1032.595385] PM: Syncing filesystems ... done.
>[ 1032.595646] PM: Preparing system for sleep (mem)
>[ 1032.596327] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1032.598050] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1032.599507] PM: Suspending system (mem)
>[ 1032.599629] Suspending console(s) (use no_console_suspend to debug)
>[ 1032.601675] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[ 1032.601748] sd 0:0:0:0: [sda] Stopping disk
>[ 1032.602860] e1000e: EEE TX LPI TIMER: 00000011
>[ 1032.602939] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1032.602968] [drm:intel_power_well_enable [i915]] enabling display
>[ 1032.602998] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1032.614182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1032.614310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1032.614357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1032.614408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1032.614439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1032.614477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1032.614515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1032.614561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1032.614603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1032.614645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1032.614686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.614725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1032.614764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1032.614851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1032.718016] PM: suspend of devices complete after 117.214 msecs
>[ 1032.719403] [drm:intel_power_well_disable [i915]] disabling display
>[ 1032.719435] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1032.719455] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1032.719480] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1032.730950] PM: late suspend of devices complete after 12.928 msecs
>[ 1032.733350] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1032.733536] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1032.744965] PM: noirq suspend of devices complete after 14.008 msecs
>[ 1032.745342] ACPI: Preparing to enter system sleep state S3
>[ 1032.770603] PM: Saving platform NVS memory
>[ 1032.770760] Disabling non-boot CPUs ...
>[ 1032.784445] smpboot: CPU 1 is now offline
>[ 1032.796939] Broke affinity for irq 23
>[ 1032.796945] Broke affinity for irq 42
>[ 1032.798285] smpboot: CPU 2 is now offline
>[ 1032.809860] Broke affinity for irq 8
>[ 1032.809865] Broke affinity for irq 9
>[ 1032.809871] Broke affinity for irq 23
>[ 1032.809876] Broke affinity for irq 42
>[ 1032.809881] Broke affinity for irq 43
>[ 1032.810929] smpboot: CPU 3 is now offline
>[ 1032.812812] ACPI: Low-level resume complete
>[ 1032.812958] PM: Restoring platform NVS memory
>[ 1032.813501] Suspended for 16.373 seconds
>[ 1032.813603] Enabling non-boot CPUs ...
>[ 1032.813747] x86: Booting SMP configuration:
>[ 1032.813754] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1032.815868]  cache: parent cpu1 should not be sleeping
>[ 1032.817397] CPU1 is up
>[ 1032.817515] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1032.818963]  cache: parent cpu2 should not be sleeping
>[ 1032.819830] CPU2 is up
>[ 1032.819897] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1032.821242]  cache: parent cpu3 should not be sleeping
>[ 1032.823159] CPU3 is up
>[ 1032.832159] ACPI: Waking up from system sleep state S3
>[ 1032.856345] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1032.856354] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1032.856514] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1032.857124] PM: noirq resume of devices complete after 12.391 msecs
>[ 1032.857371] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1032.857486] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1032.857525] [drm:intel_power_well_enable [i915]] enabling display
>[ 1032.859727] PM: early resume of devices complete after 2.548 msecs
>[ 1032.860347] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1032.860395] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[ 1032.860457] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1032.860486] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1032.863837] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1032.866279] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1032.866304] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1032.866327] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1032.866349] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1032.866533] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1032.866559] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1032.866586] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1032.866615] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1032.866646] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1032.866673] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1032.866703] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1032.866785] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1032.866811] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1032.866839] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1032.866863] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1032.866891] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1032.866913] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1032.866937] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1032.866981] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1032.867005] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1032.867023] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1032.867044] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1032.867066] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1032.867089] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1032.867112] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1032.867133] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1032.867153] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1032.867170] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1032.867192] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1032.867213] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1032.867234] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1032.867261] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1032.867281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1032.867300] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1032.867318] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.867323] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.867341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.867345] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.867363] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1032.867381] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1032.867402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.867427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.867453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.867477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.867503] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1032.867528] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1032.867553] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1032.867580] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1032.867605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1032.867630] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1032.867654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.867658] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.867683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.867687] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.867712] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1032.867736] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1032.867761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.867786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.867811] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.867836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.867861] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1032.867886] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1032.867911] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1032.867938] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1032.867977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1032.868001] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1032.868026] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.868030] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.868054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.868058] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1032.868083] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1032.868108] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1032.868133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.868158] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.868183] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.868207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.868232] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1032.868257] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1032.868282] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1032.868311] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1032.868336] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1032.868361] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1032.868418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1032.868443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1032.868470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1032.868498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1032.868523] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1032.868549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1032.868574] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1032.868599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1032.868624] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1032.868649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1032.868673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1032.868678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.868702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1032.868706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1032.868732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1032.868757] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1032.868782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1032.868807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1032.868832] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1032.868856] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1032.868881] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1032.868905] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1032.868926] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1032.868964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1032.868994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1032.869079] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1032.869115] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1032.869141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1032.869166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1032.869191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1032.869217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1032.869242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1032.869266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1032.869295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1032.869323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1032.869350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1032.869377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1032.869404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.869428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1032.869452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1032.869481] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1032.869512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1032.869540] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1032.869571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1032.869598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1032.869717] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1032.869779] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1032.870820] sd 0:0:0:0: [sda] Starting disk
>[ 1032.871736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1032.871768] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1032.873867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1032.873876] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1032.875996] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1032.876034] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1032.878150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1032.878161] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1032.878169] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1032.878208] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1032.879328] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1032.880273] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1032.880301] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1032.880326] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1032.880350] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1032.881372] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1032.881393] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1032.882339] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1032.882373] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1032.884491] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1032.884530] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1032.886643] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1032.886654] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1032.888775] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1032.888817] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1032.890930] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1032.890971] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1032.890978] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1033.083680] PM: resume of devices complete after 223.948 msecs
>[ 1033.084588] PM: Finishing wakeup.
>[ 1033.084591] Restarting tasks ... done.
>[ 1033.095327] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1033.095334] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1033.095483] [drm:intel_power_well_disable [i915]] disabling display
>[ 1033.095528] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1033.095555] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1033.099250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1033.099322] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1033.099360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1033.099393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1033.099428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1033.099459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1033.099489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1033.099520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1033.099553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1033.099586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1033.099619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1033.099652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.099681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1033.099709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1033.099754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1033.099788] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1033.100657] [drm:drm_mode_addfb2] [FB:77]
>[ 1033.100706] [drm:drm_mode_addfb2] [FB:78]
>[ 1033.139681] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1033.139786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1033.139858] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1033.139983] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1033.140003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1033.140096] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1033.140131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1033.140167] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1033.140204] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1033.140235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1033.140269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1033.140303] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1033.140335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1033.140366] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1033.140396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1033.140427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1033.140434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1033.140463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1033.140470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1033.140500] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1033.140530] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1033.140560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1033.140590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1033.140623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1033.140652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1033.140683] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1033.140710] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1033.140739] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1033.140772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1033.140808] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1033.144120] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1033.144142] [drm:intel_power_well_enable [i915]] enabling display
>[ 1033.144160] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1033.144198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1033.144220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1033.144240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1033.144264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1033.144289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1033.144313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1033.144339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1033.144365] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1033.144391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.144415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1033.144439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1033.144465] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1033.144489] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1033.146574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1033.146597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1033.146616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1033.146638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1033.148212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1033.148235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1033.148255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1033.149796] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1033.149819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1033.151666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1033.155008] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1033.155095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1033.155123] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1033.155159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1033.171883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1033.171936] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1033.172101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.184404] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1033.204179] ata1.00: configured for UDMA/133
>[ 1033.205352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1033.205390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1033.205431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1033.205476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1033.205514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1033.205555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1033.205593] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1033.205633] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1033.205673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1033.205707] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1033.205745] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1033.205753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1033.205792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1033.205799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1033.205838] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1033.205873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1033.205920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1033.206008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1033.206061] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1033.206103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1033.206152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1033.206191] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1033.206235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1033.206279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1033.206328] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1033.206449] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1033.206502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1033.206595] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1033.223568] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1033.223605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1033.223645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1033.223678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1033.223708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1033.223738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1033.223766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1033.223798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1033.223840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1033.223882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1033.223927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.224063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1033.224115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1033.224203] [drm:intel_power_well_disable [i915]] disabling display
>[ 1033.224267] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1033.224321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1033.224356] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1033.224390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.224421] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1033.258977] PM: Syncing filesystems ... done.
>[ 1033.259256] PM: Preparing system for sleep (mem)
>[ 1033.259783] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1033.261529] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1033.262871] PM: Suspending system (mem)
>[ 1033.262981] Suspending console(s) (use no_console_suspend to debug)
>[ 1033.265168] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[ 1033.265248] sd 0:0:0:0: [sda] Stopping disk
>[ 1033.266338] e1000e: EEE TX LPI TIMER: 00000011
>[ 1033.266421] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1033.266451] [drm:intel_power_well_enable [i915]] enabling display
>[ 1033.266481] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1033.266852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1033.266984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1033.267016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1033.267051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1033.267080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1033.267107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1033.267137] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1033.267171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1033.267203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1033.267233] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1033.267263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.267290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1033.267317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1033.267354] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1033.380170] PM: suspend of devices complete after 115.999 msecs
>[ 1033.381681] [drm:intel_power_well_disable [i915]] disabling display
>[ 1033.381726] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1033.381752] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1033.381786] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1033.393087] PM: late suspend of devices complete after 12.911 msecs
>[ 1033.395170] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1033.395469] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1033.407091] PM: noirq suspend of devices complete after 13.997 msecs
>[ 1033.407468] ACPI: Preparing to enter system sleep state S3
>[ 1033.432683] PM: Saving platform NVS memory
>[ 1033.432843] Disabling non-boot CPUs ...
>[ 1033.446077] smpboot: CPU 1 is now offline
>[ 1033.457230] Broke affinity for irq 23
>[ 1033.457238] Broke affinity for irq 42
>[ 1033.458561] smpboot: CPU 2 is now offline
>[ 1033.468053] Broke affinity for irq 8
>[ 1033.468058] Broke affinity for irq 9
>[ 1033.468065] Broke affinity for irq 23
>[ 1033.468070] Broke affinity for irq 42
>[ 1033.468075] Broke affinity for irq 43
>[ 1033.469135] smpboot: CPU 3 is now offline
>[ 1033.471053] ACPI: Low-level resume complete
>[ 1033.471203] PM: Restoring platform NVS memory
>[ 1033.471747] Suspended for 16.343 seconds
>[ 1033.471848] Enabling non-boot CPUs ...
>[ 1033.471995] x86: Booting SMP configuration:
>[ 1033.472002] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1033.474172]  cache: parent cpu1 should not be sleeping
>[ 1033.475706] CPU1 is up
>[ 1033.475827] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1033.477359]  cache: parent cpu2 should not be sleeping
>[ 1033.478281] CPU2 is up
>[ 1033.478354] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1033.479714]  cache: parent cpu3 should not be sleeping
>[ 1033.480614] CPU3 is up
>[ 1033.484526] ACPI: Waking up from system sleep state S3
>[ 1033.509485] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1033.509494] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1033.509593] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1033.510118] PM: noirq resume of devices complete after 12.217 msecs
>[ 1033.510344] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1033.510472] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1033.510514] [drm:intel_power_well_enable [i915]] enabling display
>[ 1033.512513] PM: early resume of devices complete after 2.345 msecs
>[ 1033.513052] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1033.513215] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[ 1033.513277] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1033.513306] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1033.516694] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1033.519418] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1033.519446] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1033.519474] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1033.519504] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1033.519726] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1033.519759] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1033.519797] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1033.519842] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1033.519869] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1033.519895] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1033.519926] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1033.520017] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1033.520042] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1033.520071] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1033.520120] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1033.520151] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1033.520176] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1033.520203] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1033.520227] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1033.520251] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1033.520274] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1033.520296] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1033.520318] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1033.520343] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1033.520367] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1033.520384] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1033.520405] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1033.520426] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1033.520454] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1033.520479] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1033.520504] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1033.520535] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1033.520559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1033.520582] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1033.520605] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1033.520611] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1033.520628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1033.520632] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1033.520667] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1033.520685] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1033.520701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1033.520718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1033.520738] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1033.520754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1033.520771] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1033.520788] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1033.520811] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1033.520844] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1033.520866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1033.520889] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1033.520912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1033.520915] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1033.520937] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1033.520941] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1033.520964] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1033.520987] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1033.521010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1033.521033] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1033.521057] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1033.521079] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1033.521116] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1033.521139] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1033.521162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1033.521187] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1033.521210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1033.521233] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1033.521255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1033.521259] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1033.521282] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1033.521285] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1033.521309] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1033.521331] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1033.521355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1033.521378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1033.521399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1033.521422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1033.521445] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1033.521468] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1033.521488] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1033.521515] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1033.521538] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1033.521561] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1033.521614] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1033.521638] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1033.521662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1033.521689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1033.521711] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1033.521735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1033.521758] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1033.521781] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1033.521805] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1033.521827] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1033.521850] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1033.521854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1033.521877] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1033.521881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1033.521904] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1033.521927] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1033.521950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1033.521973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1033.521995] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1033.522017] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1033.522040] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1033.522063] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1033.522086] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1033.522122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1033.522150] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1033.522231] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1033.522265] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1033.522289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1033.522312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1033.522335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1033.522358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1033.522382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1033.522404] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1033.522431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1033.522457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1033.522482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1033.522507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1033.522532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.522555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1033.522578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1033.522604] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1033.522633] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1033.522661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1033.522687] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1033.522715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1033.522825] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1033.522882] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1033.523591] sd 0:0:0:0: [sda] Starting disk
>[ 1033.525022] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1033.525043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1033.527142] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1033.527155] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1033.529276] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1033.529313] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1033.531428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1033.531438] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1033.531446] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1033.531485] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1033.532597] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1033.533603] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1033.533632] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1033.533656] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1033.533680] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1033.534700] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1033.534721] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1033.535669] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1033.535703] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1033.537795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1033.537827] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1033.539910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1033.539918] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1033.542005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1033.542035] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1033.544150] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1033.544159] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1033.544167] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1033.832971] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1033.846936] ata1.00: configured for UDMA/133
>[ 1034.715469] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[ 1035.050249] PM: resume of devices complete after 1537.794 msecs
>[ 1035.051273] PM: Finishing wakeup.
>[ 1035.051276] Restarting tasks ... 
>[ 1035.051517] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1035.051522] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1035.051612] [drm:intel_power_well_disable [i915]] disabling display
>[ 1035.051638] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1035.051653] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1035.052402] done.
>[ 1035.060204] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1035.060240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1035.060276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1035.060314] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1035.060345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1035.060378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1035.060411] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1035.060442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1035.060473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1035.060503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1035.060531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1035.060539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.060568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1035.060575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.060604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1035.060634] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1035.060662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1035.060690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1035.060722] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1035.060751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1035.060782] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1035.060810] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1035.060838] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1035.060870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1035.060905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1035.064071] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1035.064105] [drm:intel_power_well_enable [i915]] enabling display
>[ 1035.064136] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1035.064195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1035.064229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1035.064261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1035.064291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1035.064321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1035.064353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1035.064388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1035.064421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1035.064455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.064484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1035.064513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1035.064548] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1035.064579] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1035.066741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1035.066776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1035.066807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1035.066840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1035.068425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1035.068460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1035.068492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1035.070128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1035.070165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1035.072077] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1035.075464] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1035.075567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1035.075600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1035.075645] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1035.075759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1035.075803] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1035.075870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.092514] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1035.092549] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1035.092585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1035.092623] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1035.092653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1035.092687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1035.092719] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1035.092749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1035.092779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1035.092807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1035.092835] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1035.092844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.092871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1035.092878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.092907] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1035.092936] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1035.092964] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1035.092991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1035.093023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1035.093330] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1035.093364] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] FB:78, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 1035.093394] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1035.093422] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1035.093456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1035.093492] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1035.093587] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1035.093630] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1035.093704] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1035.109569] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1035.109598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1035.109626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1035.109650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1035.109670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1035.109690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1035.109709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1035.109731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1035.109765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1035.109787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1035.109817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.109846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1035.109875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1035.109932] [drm:intel_power_well_disable [i915]] disabling display
>[ 1035.109976] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1035.110008] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1035.110106] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1035.110141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.110173] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1035.151313] PM: Syncing filesystems ... done.
>[ 1035.151607] PM: Preparing system for sleep (mem)
>[ 1035.152268] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 1035.154072] Freezing remaining freezable tasks ... (elapsed 0.003 seconds) done.
>[ 1035.157428] PM: Suspending system (mem)
>[ 1035.157539] Suspending console(s) (use no_console_suspend to debug)
>[ 1035.159586] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[ 1035.159659] sd 0:0:0:0: [sda] Stopping disk
>[ 1035.160712] e1000e: EEE TX LPI TIMER: 00000011
>[ 1035.160929] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1035.160950] [drm:intel_power_well_enable [i915]] enabling display
>[ 1035.160971] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1035.169330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1035.169433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1035.169465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1035.169500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1035.169530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1035.169558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1035.169588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1035.169623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1035.169655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1035.169686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1035.169716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.169742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1035.169769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1035.169806] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1035.274049] hpet1: lost 5 rtc interrupts
>[ 1035.274364] PM: suspend of devices complete after 115.619 msecs
>[ 1035.275879] [drm:intel_power_well_disable [i915]] disabling display
>[ 1035.275908] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1035.275925] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1035.275949] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1035.287200] PM: late suspend of devices complete after 12.830 msecs
>[ 1035.289592] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1035.289941] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1035.301228] PM: noirq suspend of devices complete after 14.020 msecs
>[ 1035.301605] ACPI: Preparing to enter system sleep state S3
>[ 1035.326876] PM: Saving platform NVS memory
>[ 1035.327041] Disabling non-boot CPUs ...
>[ 1035.341296] smpboot: CPU 1 is now offline
>[ 1035.352896] Broke affinity for irq 23
>[ 1035.352903] Broke affinity for irq 42
>[ 1035.354244] smpboot: CPU 2 is now offline
>[ 1035.360136] Broke affinity for irq 8
>[ 1035.360141] Broke affinity for irq 9
>[ 1035.360147] Broke affinity for irq 23
>[ 1035.360152] Broke affinity for irq 42
>[ 1035.360156] Broke affinity for irq 43
>[ 1035.361217] smpboot: CPU 3 is now offline
>[ 1035.363071] ACPI: Low-level resume complete
>[ 1035.363217] PM: Restoring platform NVS memory
>[ 1035.363759] Suspended for 16.110 seconds
>[ 1035.363861] Enabling non-boot CPUs ...
>[ 1035.364006] x86: Booting SMP configuration:
>[ 1035.364013] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1035.366198]  cache: parent cpu1 should not be sleeping
>[ 1035.367706] CPU1 is up
>[ 1035.367824] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1035.369293]  cache: parent cpu2 should not be sleeping
>[ 1035.370175] CPU2 is up
>[ 1035.370243] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1035.371565]  cache: parent cpu3 should not be sleeping
>[ 1035.373483] CPU3 is up
>[ 1035.382293] ACPI: Waking up from system sleep state S3
>[ 1035.410500] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1035.410510] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1035.410653] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1035.410662] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1035.410852] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1035.411281] PM: noirq resume of devices complete after 12.576 msecs
>[ 1035.411570] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1035.411668] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1035.411699] [drm:intel_power_well_enable [i915]] enabling display
>[ 1035.414110] PM: early resume of devices complete after 2.688 msecs
>[ 1035.414404] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[ 1035.414462] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1035.414492] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1035.415731] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1035.417204] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1035.423718] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1035.423754] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1035.423786] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1035.423816] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1035.424042] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1035.424082] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1035.424130] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1035.424213] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1035.424262] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1035.424310] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1035.424356] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1035.424479] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1035.424521] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1035.424568] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1035.424609] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1035.424653] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1035.424692] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1035.424737] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1035.424781] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1035.424824] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1035.424871] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1035.424922] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1035.424971] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1035.425026] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1035.425077] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1035.425124] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1035.425169] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1035.425243] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1035.425244] sd 0:0:0:0: [sda] Starting disk
>[ 1035.425282] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1035.425317] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1035.425365] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1035.425409] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1035.425430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1035.425449] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1035.425467] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1035.425472] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1035.425490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1035.425494] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1035.425512] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1035.425530] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1035.425547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1035.425564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1035.425585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1035.425603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1035.425620] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1035.425637] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1035.425654] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1035.425673] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1035.425690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1035.425706] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1035.425723] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1035.425726] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1035.425743] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1035.425746] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1035.425763] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1035.425787] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1035.425812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1035.425837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1035.425861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1035.425886] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1035.425911] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1035.425936] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1035.425961] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1035.425988] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1035.426012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1035.426037] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1035.426062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1035.426066] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1035.426090] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1035.426094] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1035.426119] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1035.426143] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1035.426194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1035.426216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1035.426238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1035.426262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1035.426288] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1035.426312] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1035.426337] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1035.426365] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1035.426390] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1035.426415] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1035.426472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1035.426498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1035.426524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1035.426552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1035.426576] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1035.426602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1035.426627] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1035.426652] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1035.426677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1035.426702] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1035.426726] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1035.426730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.426755] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1035.426759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.426784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1035.426809] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1035.426834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1035.426859] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1035.426884] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1035.426908] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1035.426933] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1035.426958] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1035.426979] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1035.427005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1035.427035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1035.427122] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1035.427170] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1035.427196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1035.427221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1035.427246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1035.427271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1035.427296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1035.427321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1035.427349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1035.427377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1035.427404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1035.427431] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1035.427457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.427482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1035.427506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1035.427535] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1035.427566] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1035.427596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1035.427625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1035.427656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.427768] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1035.427817] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1035.429886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1035.429925] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1035.432039] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1035.432050] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1035.434165] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1035.434237] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1035.436352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1035.436362] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1035.436370] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1035.436409] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1035.437525] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1035.438473] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1035.438499] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1035.438524] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1035.438547] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1035.439568] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1035.439589] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1035.440535] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1035.440560] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1035.442680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1035.442718] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1035.444833] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1035.444843] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1035.446961] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1035.446999] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1035.449114] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1035.449124] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1035.449131] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1035.612336] PM: resume of devices complete after 198.228 msecs
>[ 1035.613503] PM: Finishing wakeup.
>[ 1035.613508] Restarting tasks ... done.
>[ 1035.623225] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1035.623313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1035.623346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1035.623383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1035.623413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1035.623444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1035.623477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1035.623515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1035.623549] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1035.623583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1035.623616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.623646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1035.623675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1035.623721] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1035.624981] [drm:intel_power_well_disable [i915]] disabling display
>[ 1035.625026] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1035.625054] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1035.631260] [IGT] kms_flip: exiting, ret=0
>[ 1035.631918] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[ 1035.647052] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1035.647087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1035.647122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1035.647225] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1035.647254] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1035.647286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1035.647317] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1035.647345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1035.647374] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1035.647401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1035.647427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1035.647433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.647459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1035.647465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.647492] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1035.647519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1035.647545] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1035.647571] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1035.647601] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1035.647627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1035.647653] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1035.647679] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1035.647705] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1035.647735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1035.647768] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1035.647893] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1035.647925] [drm:intel_power_well_enable [i915]] enabling display
>[ 1035.647953] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1035.648008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1035.648037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1035.648065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1035.648092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1035.648120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1035.648522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1035.648556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1035.648588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1035.648619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.648646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1035.648673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1035.648705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1035.648734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1035.650848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1035.650881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1035.650909] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1035.650940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1035.652543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1035.652575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1035.652605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1035.654570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1035.654604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1035.656520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1035.659802] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1035.659856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1035.659887] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1035.659934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1035.660020] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1035.660050] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1035.676629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1035.676679] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1035.676753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1035.677064] Console: switching to colour frame buffer device 240x75
>[ 1035.731365] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1035.744516] ata1.00: configured for UDMA/133
>[ 1035.830917] Console: switching to colour dummy device 80x25
>[ 1035.831032] [IGT] kms_flip: executing
>[ 1035.844780] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1035.844832] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1035.846439] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1035.846482] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1035.848226] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1035.848239] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1035.850226] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1035.850265] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1035.852227] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1035.852238] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1035.852246] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1035.852277] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1035.852320] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1035.853443] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1035.854389] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1035.854411] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1035.854430] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1035.854447] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1035.855466] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1035.855487] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1035.856610] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1035.856614] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1035.856718] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1035.856720] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1035.856725] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1035.856728] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1035.856732] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1035.856735] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1035.856744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1035.856747] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1035.856750] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1035.856753] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1035.856757] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1035.856760] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1035.856762] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1035.856765] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1035.856768] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1035.856771] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1035.856774] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1035.856777] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1035.856780] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1035.856783] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1035.856786] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1035.856789] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1035.856792] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1035.856795] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1035.856798] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1035.856801] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1035.856804] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1035.856807] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1035.856810] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1035.856812] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1035.856816] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1035.856819] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1035.856821] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1035.856824] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1035.856827] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1035.856830] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1035.856833] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1035.856871] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1035.856893] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1035.858174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1035.858197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1035.860225] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1035.860236] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1035.862237] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1035.862276] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1035.864225] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1035.864236] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1035.864244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1035.866331] [IGT] kms_flip: starting subtest 2x-flip-vs-expired-vblank-interruptible
>[ 1035.868062] [IGT] kms_flip: exiting, ret=77
>[ 1035.893660] Console: switching to colour frame buffer device 240x75
>[ 1036.000670] Console: switching to colour dummy device 80x25
>[ 1036.000785] [IGT] kms_flip: executing
>[ 1036.012030] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1036.012082] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1036.013209] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.013244] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.015210] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.015221] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1036.017226] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.017260] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.019233] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.019245] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.019253] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1036.019284] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1036.019326] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1036.020415] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1036.021356] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1036.021377] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1036.021396] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1036.021414] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1036.022429] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1036.022449] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1036.023570] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1036.023573] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1036.023680] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.023683] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.023688] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1036.023691] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1036.023696] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.023698] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.023707] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1036.023711] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1036.023714] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.023717] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.023720] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.023723] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.023726] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.023729] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1036.023732] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.023735] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.023738] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.023741] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.023744] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.023747] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1036.023750] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.023753] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.023755] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1036.023758] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.023762] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.023764] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1036.023767] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1036.023770] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1036.023773] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1036.023776] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1036.023779] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1036.023782] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.023785] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.023788] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1036.023791] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.023794] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.023797] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1036.023835] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1036.023858] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1036.025175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.025197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.027247] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.027258] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1036.029220] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.029259] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.031219] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.031230] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.031238] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1036.031656] [IGT] kms_flip: starting subtest 2x-dpms-vs-vblank-race
>[ 1036.034946] [IGT] kms_flip: exiting, ret=77
>[ 1036.060459] Console: switching to colour frame buffer device 240x75
>[ 1036.168004] Console: switching to colour dummy device 80x25
>[ 1036.168184] [IGT] kms_flip: executing
>[ 1036.183024] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1036.183077] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1036.185227] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.185263] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.187381] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.187393] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1036.189494] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.189531] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.191645] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.191657] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.191664] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1036.191694] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1036.191736] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1036.192849] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1036.193772] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1036.193794] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1036.193813] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1036.193830] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1036.194854] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1036.194875] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1036.195997] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1036.196001] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1036.196159] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.196167] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.196178] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1036.196182] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1036.196192] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.196196] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.196212] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1036.196218] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1036.196224] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.196230] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.196237] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.196244] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.196251] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.196257] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1036.196262] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.196269] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.196277] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.196283] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.196288] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.196294] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1036.196302] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.196309] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.196315] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1036.196320] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.196326] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.196333] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1036.196340] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1036.196346] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1036.196352] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1036.196358] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1036.196365] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1036.196371] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.196379] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.196384] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1036.196390] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.196397] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.196404] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1036.196474] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1036.196509] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1036.198228] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.198264] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.200215] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.200226] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1036.202235] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.202288] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.204215] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.204227] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.204234] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1036.204631] [IGT] kms_flip: starting subtest 2x-flip-vs-rmfb
>[ 1036.207997] [IGT] kms_flip: exiting, ret=77
>[ 1036.243950] Console: switching to colour frame buffer device 240x75
>[ 1036.349957] Console: switching to colour dummy device 80x25
>[ 1036.350077] [IGT] kms_flip: executing
>[ 1036.361984] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1036.362030] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1036.364178] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.364214] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.366208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.366221] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1036.368220] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.368259] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.370206] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.370219] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.370227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1036.370259] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1036.370302] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1036.371385] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1036.372300] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1036.372321] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1036.372340] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1036.372358] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1036.373375] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1036.373396] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1036.374516] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1036.374520] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1036.374625] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.374627] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.374633] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1036.374635] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1036.374640] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.374642] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.374652] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1036.374655] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1036.374658] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.374661] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.374664] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.374667] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.374670] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.374673] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1036.374676] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.374679] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.374682] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.374685] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.374688] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.374691] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1036.374694] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.374697] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.374700] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1036.374703] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.374706] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.374709] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1036.374712] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1036.374715] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1036.374718] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1036.374721] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1036.374724] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1036.374727] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.374730] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.374733] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1036.374736] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.374738] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.374741] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1036.374781] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1036.374803] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1036.376165] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.376188] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.378217] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.378228] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1036.380188] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.380224] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.382206] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.382217] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.382225] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1036.382647] [IGT] kms_flip: starting subtest 2x-nonexisting-fb
>[ 1036.385922] [IGT] kms_flip: exiting, ret=77
>[ 1036.410735] Console: switching to colour frame buffer device 240x75
>[ 1036.516607] Console: switching to colour dummy device 80x25
>[ 1036.516724] [IGT] kms_flip: executing
>[ 1036.527968] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1036.528021] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1036.529565] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.529606] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.531198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1036.531210] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1036.533197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.533239] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1036.535198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1036.535209] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.535216] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1036.535246] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1036.535289] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1036.536402] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1036.537354] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1036.537387] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1036.537419] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1036.537452] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1036.538471] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1036.538496] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1036.539610] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1036.539613] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1036.539715] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.539717] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.539723] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1036.539725] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1036.539730] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1036.539732] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1036.539742] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1036.539745] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1036.539748] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.539751] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.539754] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.539757] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1036.539760] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.539763] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1036.539766] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.539769] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1036.539772] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1036.539775] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.539778] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1036.539781] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1036.539784] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.539787] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1036.539790] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1036.539793] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.539796] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1036.539799] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1036.539802] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1036.539805] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1036.539808] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1036.539810] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1036.539813] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1036.539816] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.539819] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1036.539822] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1036.539825] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.539828] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1036.539831] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1036.539869] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1036.539892] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1036.541167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.541194] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.543202] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1036.543212] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1036.545204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.545240] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1036.547221] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1036.547236] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1036.547247] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1036.547665] [IGT] kms_flip: starting subtest blocking-wf_vblank
>[ 1036.548551] [drm:drm_mode_addfb2] [FB:58]
>[ 1036.548593] [drm:drm_mode_addfb2] [FB:79]
>[ 1036.601889] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1036.601953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1036.610705] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1036.610756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1036.610832] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1036.629060] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1036.629105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1036.629222] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1036.629280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1036.629327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1036.629383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1036.629429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1036.629475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1036.629519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1036.629572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1036.629622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1036.629672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1036.629721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1036.629761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1036.629804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1036.629881] [drm:intel_power_well_disable [i915]] disabling display
>[ 1036.629930] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1036.629969] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1036.630000] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1036.630129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1036.630297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1036.630420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1036.630433] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1036.630486] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1036.630507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1036.630529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1036.630553] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1036.630571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1036.630591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1036.630611] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1036.630630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1036.630648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1036.630664] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1036.630681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1036.630685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1036.630707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1036.630712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1036.630736] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1036.630759] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1036.630783] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1036.630805] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1036.630829] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1036.630852] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1036.630875] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1036.630899] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1036.630922] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1036.630947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1036.630972] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1036.634258] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1036.634279] [drm:intel_power_well_enable [i915]] enabling display
>[ 1036.634297] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1036.634334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1036.634356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1036.634376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1036.634396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1036.634415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1036.634434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1036.634460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1036.634486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1036.634511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1036.634535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1036.634559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1036.634585] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1036.634610] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1036.636719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1036.636741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1036.636759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1036.636779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1036.638358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1036.638378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1036.638396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1036.639959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1036.639980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1036.641848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1036.645165] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1036.645213] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1036.645233] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1036.645258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1036.645318] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1036.645347] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1036.662022] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1036.662074] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1036.662238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1038.457157] e1000e: enp0s25 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[ 1046.970281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1046.986847] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1046.986900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1046.986978] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1047.003998] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1047.004042] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1047.004075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1047.004115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1047.004148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1047.004184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1047.004215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1047.004246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1047.004277] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1047.004320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1047.004363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1047.004405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1047.004448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1047.004487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1047.004526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1047.004584] [drm:intel_power_well_disable [i915]] disabling display
>[ 1047.004631] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1047.004682] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1047.004803] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1047.005175] [drm:drm_mode_addfb2] [FB:58]
>[ 1047.005205] [drm:drm_mode_addfb2] [FB:78]
>[ 1047.037521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1047.037617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1047.037754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1047.037873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1047.037895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1047.037954] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1047.037976] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1047.038000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1047.038028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1047.038050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1047.038074] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1047.038098] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1047.038122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1047.038145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1047.038168] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1047.038191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1047.038195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1047.038218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1047.038223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1047.038246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1047.038266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1047.038290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1047.038313] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1047.038337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1047.038359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1047.038383] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1047.038407] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1047.038430] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1047.038455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1047.038481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1047.041732] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1047.041750] [drm:intel_power_well_enable [i915]] enabling display
>[ 1047.041767] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1047.041804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1047.041824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1047.041843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1047.041861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1047.041884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1047.041907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1047.041933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1047.041958] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1047.041983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1047.042006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1047.042029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1047.042054] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1047.042077] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1047.044172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1047.044193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1047.044211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.044230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1047.045811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1047.045834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1047.045857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1047.047409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1047.047431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1047.049295] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1047.052578] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1047.052679] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1047.052789] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1047.052858] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1047.069451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1047.069498] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1047.069562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1057.377746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1057.377845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1057.377898] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1057.377977] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1057.394990] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1057.395028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1057.395070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1057.395104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1057.395140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1057.395171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1057.395201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1057.395233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1057.395363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1057.395412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1057.395466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1057.395519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1057.395565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1057.395594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1057.395651] [drm:intel_power_well_disable [i915]] disabling display
>[ 1057.395687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1057.395721] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1057.395745] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1057.395961] [drm:drm_mode_addfb2] [FB:58]
>[ 1057.395992] [drm:drm_mode_addfb2] [FB:78]
>[ 1057.425658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1057.425767] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1057.425844] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1057.425915] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1057.425927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1057.426004] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1057.426036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1057.426059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1057.426085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1057.426109] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1057.426133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1057.426157] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1057.426180] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1057.426205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1057.426225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1057.426302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1057.426312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1057.426347] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1057.426355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1057.426387] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1057.426419] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1057.426452] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1057.426483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1057.426517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1057.426548] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1057.426581] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1057.426613] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1057.426643] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1057.426678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1057.426714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1057.430126] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1057.430147] [drm:intel_power_well_enable [i915]] enabling display
>[ 1057.430166] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1057.430203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1057.430225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1057.430316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1057.430348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1057.430380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1057.430412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1057.430444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1057.430472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1057.430500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1057.430526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1057.430552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1057.430580] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1057.430605] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1057.432659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1057.432683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1057.432706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1057.432730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1057.434298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1057.434319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1057.434338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1057.435899] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1057.435921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1057.437786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1057.441107] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1057.441169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1057.441202] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1057.441245] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1057.457944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1057.457992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1057.458056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1067.766215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1067.766306] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1067.766349] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1067.766420] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1067.783442] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1067.783479] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1067.783520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1067.783553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1067.783588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1067.783617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1067.783646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1067.783678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1067.783713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1067.783746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1067.783777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1067.783808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1067.783898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1067.783950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1067.784035] [drm:intel_power_well_disable [i915]] disabling display
>[ 1067.784101] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1067.784166] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1067.784215] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1067.788141] [IGT] kms_flip: exiting, ret=0
>[ 1067.810652] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1067.810691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1067.810730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1067.810771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1067.810804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1067.810866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1067.810901] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1067.810933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1067.810965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1067.810994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1067.811022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1067.811029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1067.811063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1067.811068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1067.811109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1067.811149] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1067.811189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1067.811221] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1067.811243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1067.811261] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1067.811279] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1067.811297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1067.811314] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1067.811335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1067.811357] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1067.811434] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1067.811454] [drm:intel_power_well_enable [i915]] enabling display
>[ 1067.811471] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1067.811506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1067.811525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1067.811543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1067.811560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1067.811577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1067.811601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1067.811627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1067.811652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1067.811677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1067.811701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1067.811724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1067.811749] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1067.811772] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1067.813867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1067.813887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1067.813905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1067.813923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1067.815475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1067.815494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1067.815512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1067.817065] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1067.817084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1067.818955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1067.822273] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1067.822339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1067.822377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1067.822403] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1067.822468] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1067.822488] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1067.839127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1067.839175] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1067.839245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1067.839502] Console: switching to colour frame buffer device 240x75
>[ 1067.947736] Console: switching to colour dummy device 80x25
>[ 1067.947945] [IGT] kms_flip: executing
>[ 1067.962700] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1067.962754] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1067.964886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1067.964939] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1067.967058] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1067.967071] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1067.969172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1067.969209] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1067.971322] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1067.971334] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1067.971342] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1067.971373] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1067.971416] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1067.972546] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1067.973468] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1067.973490] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1067.973509] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1067.973528] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1067.974557] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1067.974577] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1067.975701] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1067.975704] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1067.975874] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1067.975877] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1067.975883] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1067.975886] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1067.975892] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1067.975895] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1067.975906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1067.975909] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1067.975913] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1067.975916] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1067.975921] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1067.975924] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1067.975927] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1067.975931] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1067.975934] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1067.975937] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1067.975941] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1067.975944] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1067.975947] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1067.975951] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1067.975954] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1067.975958] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1067.975961] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1067.975964] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1067.975968] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1067.975972] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1067.975975] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1067.975978] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1067.975981] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1067.975984] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1067.975989] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1067.975992] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1067.975996] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1067.975999] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1067.976003] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1067.976006] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1067.976009] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1067.976051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1067.976076] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1067.977902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1067.977935] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1067.979885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1067.979896] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1067.981901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1067.981937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1067.983899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1067.983910] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1067.983918] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1067.984320] [IGT] kms_flip: starting subtest dpms-off-confusion
>[ 1067.985238] [drm:drm_mode_addfb2] [FB:77]
>[ 1067.985279] [drm:drm_mode_addfb2] [FB:79]
>[ 1068.038575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1068.038639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1068.039232] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1068.039264] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1068.039323] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1068.058410] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1068.058456] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1068.058488] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1068.058528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1068.058561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1068.058596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1068.058626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1068.058664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1068.058704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1068.058748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1068.058790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1068.058913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1068.058965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1068.059009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1068.059058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1068.059144] [drm:intel_power_well_disable [i915]] disabling display
>[ 1068.059212] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1068.059279] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1068.059322] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1068.059387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1068.059480] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1068.059559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1068.059572] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1068.059625] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1068.059647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1068.059671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1068.059697] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1068.059716] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1068.059738] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1068.059760] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1068.059785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1068.059839] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1068.059868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1068.059896] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1068.059904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1068.059933] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1068.059941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1068.059969] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1068.059996] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1068.060023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1068.060050] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1068.060080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1068.060107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1068.060134] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1068.060160] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1068.060186] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1068.060217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1068.060252] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1068.063530] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1068.063550] [drm:intel_power_well_enable [i915]] enabling display
>[ 1068.063567] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1068.063601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1068.063621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1068.063640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1068.063658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1068.063675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1068.063693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1068.063713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1068.063732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1068.063751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1068.063768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1068.063790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1068.063876] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1068.063906] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1068.065976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1068.065997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1068.066019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1068.066044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1068.067616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1068.067637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1068.067658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1068.069223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1068.069244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1068.071115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1068.074463] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1068.074553] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1068.074593] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1068.074649] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1068.074719] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1068.074750] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1068.091334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1068.091383] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1068.091449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1078.116064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1078.132650] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1078.132701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1078.132794] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1078.149825] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1078.149873] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1078.149914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1078.149959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1078.150000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1078.150045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1078.150085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1078.150125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1078.150164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1078.150209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1078.150252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1078.150294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1078.150336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1078.150375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1078.150499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1078.150591] [drm:intel_power_well_disable [i915]] disabling display
>[ 1078.150648] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1078.150704] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1078.150750] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1078.151048] [drm:drm_mode_addfb2] [FB:77]
>[ 1078.151087] [drm:drm_mode_addfb2] [FB:78]
>[ 1078.180367] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1078.180503] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1078.180588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1078.180656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1078.180667] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1078.180725] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1078.180747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1078.180769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1078.180793] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1078.180811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1078.180831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1078.180851] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1078.180869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1078.180888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1078.180910] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1078.180934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1078.180938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1078.180961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1078.180966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1078.180990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1078.181011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1078.181035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1078.181056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1078.181080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1078.181102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1078.181126] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1078.181149] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1078.181172] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1078.181197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1078.181223] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1078.184534] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1078.184555] [drm:intel_power_well_enable [i915]] enabling display
>[ 1078.184573] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1078.184611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1078.184637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1078.184662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1078.184686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1078.184711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1078.184735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1078.184761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1078.184787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1078.184813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1078.184837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1078.184861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1078.184887] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1078.184911] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1078.187084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1078.187106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1078.187124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1078.187148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1078.188724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1078.188744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1078.188767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1078.190327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1078.190349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1078.192255] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1078.195588] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1078.195684] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1078.195712] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1078.195747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1078.212491] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1078.212541] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1078.212607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1088.237186] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1088.237274] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1088.237321] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1088.237399] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1088.254406] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1088.254444] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1088.254485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1088.254519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1088.254555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1088.254586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1088.254616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1088.254648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1088.254683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1088.254715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1088.254747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1088.254778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1088.254816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1088.254856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1088.254914] [drm:intel_power_well_disable [i915]] disabling display
>[ 1088.254961] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1088.255100] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1088.255147] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1088.255459] [drm:drm_mode_addfb2] [FB:77]
>[ 1088.255490] [drm:drm_mode_addfb2] [FB:78]
>[ 1088.287614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1088.287716] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1088.287787] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1088.287855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1088.287866] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1088.287925] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1088.287946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1088.288023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1088.288060] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1088.288091] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1088.288123] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1088.288155] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1088.288187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1088.288217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1088.288246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1088.288277] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1088.288285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1088.288312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1088.288320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1088.288350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1088.288376] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1088.288403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1088.288428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1088.288460] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1088.288486] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1088.288515] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1088.288541] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1088.288569] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1088.288599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1088.288634] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1088.291905] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1088.291923] [drm:intel_power_well_enable [i915]] enabling display
>[ 1088.291940] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1088.292024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1088.292055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1088.292088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1088.292116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1088.292146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1088.292175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1088.292210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1088.292241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1088.292274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1088.292301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1088.292329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1088.292363] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1088.292392] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1088.294463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1088.294484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1088.294502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1088.294526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1088.296124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1088.296146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1088.296165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1088.297729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1088.297751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1088.299630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1088.302773] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1088.302866] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1088.302906] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1088.302958] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1088.319642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1088.319693] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1088.319759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1098.344359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1098.344448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1098.344500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1098.344665] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1098.361690] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1098.361728] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1098.361772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1098.361814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1098.361859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1098.361899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1098.361939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1098.361979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1098.362023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1098.362066] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1098.362109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1098.362154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1098.362183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1098.362209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1098.362255] [drm:intel_power_well_disable [i915]] disabling display
>[ 1098.362290] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1098.362328] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1098.362354] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1098.365608] [IGT] kms_flip: exiting, ret=0
>[ 1098.388429] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1098.388464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1098.388500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1098.388537] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1098.388594] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1098.388627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1098.388660] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1098.388690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1098.388727] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1098.388765] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1098.388803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1098.388811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1098.388848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1098.388854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1098.388892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1098.388931] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1098.388969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1098.389007] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1098.389045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1098.389083] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1098.389121] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1098.389159] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1098.389192] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1098.389232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1098.389275] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1098.389396] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1098.389431] [drm:intel_power_well_enable [i915]] enabling display
>[ 1098.389463] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1098.389524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1098.389563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1098.389628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1098.389650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1098.389673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1098.389695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1098.389721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1098.389745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1098.389769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1098.389789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1098.389811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1098.389835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1098.389858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1098.391926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1098.391946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1098.391963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1098.391981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1098.395838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1098.395869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1098.395897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1098.398634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1098.398668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1098.401678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1098.405081] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1098.405147] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1098.405165] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1098.405192] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1098.405256] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1098.405276] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1098.421946] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1098.421992] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1098.422059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1098.422300] Console: switching to colour frame buffer device 240x75
>[ 1098.529859] Console: switching to colour dummy device 80x25
>[ 1098.529978] [IGT] kms_flip: executing
>[ 1098.545407] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1098.545460] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1098.547576] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1098.547674] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1098.549793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1098.549805] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1098.551922] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1098.551961] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1098.554074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1098.554086] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1098.554093] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1098.554125] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1098.554170] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1098.555325] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1098.556270] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1098.556294] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1098.556317] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1098.556340] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1098.557352] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1098.557375] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1098.558492] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1098.558495] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1098.558665] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1098.558668] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1098.558673] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1098.558676] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1098.558682] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1098.558685] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1098.558694] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1098.558707] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1098.558710] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.558713] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.558717] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1098.558719] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1098.558722] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1098.558725] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1098.558728] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.558731] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.558734] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1098.558737] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1098.558740] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1098.558743] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1098.558746] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1098.558749] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1098.558752] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1098.558755] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1098.558758] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1098.558761] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1098.558764] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1098.558767] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1098.558770] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1098.558773] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1098.558776] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1098.558779] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1098.558782] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1098.558784] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1098.558787] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1098.558790] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1098.558793] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1098.558836] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1098.558859] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1098.560618] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1098.560655] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1098.562610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1098.562619] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1098.564610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1098.564643] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1098.566643] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1098.566654] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1098.566661] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1098.567074] [IGT] kms_flip: starting subtest 2x-flip-vs-dpms-off-vs-modeset
>[ 1098.570280] [IGT] kms_flip: exiting, ret=77
>[ 1098.605611] Console: switching to colour frame buffer device 240x75
>[ 1098.712435] Console: switching to colour dummy device 80x25
>[ 1098.712620] [IGT] kms_flip: executing
>[ 1098.728408] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1098.728461] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1098.729988] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1098.730028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1098.731635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1098.731648] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1098.733624] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1098.733663] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1098.735626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1098.735637] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1098.735645] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1098.735675] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1098.735717] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1098.736841] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1098.737785] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1098.737807] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1098.737826] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1098.737844] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1098.738862] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1098.738883] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1098.740002] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1098.740006] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1098.740110] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1098.740113] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1098.740118] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1098.740120] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1098.740125] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1098.740127] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1098.740136] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1098.740140] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1098.740143] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.740146] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.740149] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1098.740152] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1098.740155] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1098.740158] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1098.740161] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.740164] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1098.740166] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1098.740169] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1098.740172] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1098.740175] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1098.740178] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1098.740181] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1098.740184] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1098.740187] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1098.740190] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1098.740193] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1098.740196] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1098.740199] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1098.740202] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1098.740205] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1098.740208] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1098.740210] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1098.740213] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1098.740216] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1098.740219] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1098.740222] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1098.740225] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1098.740264] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1098.740287] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1098.741613] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1098.741638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1098.743639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1098.743650] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1098.745625] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1098.745668] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1098.747628] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1098.747639] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1098.747646] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1098.748037] [IGT] kms_flip: starting subtest flip-vs-panning
>[ 1098.748886] [drm:drm_mode_addfb2] [FB:77]
>[ 1098.748926] [drm:drm_mode_addfb2] [FB:79]
>[ 1098.824597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1098.824659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1098.838940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1098.838991] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1098.839067] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1098.856089] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1098.856133] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1098.856166] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1098.856204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1098.856237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1098.856273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1098.856312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1098.856352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1098.856391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1098.856436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1098.856478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1098.856520] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1098.856632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1098.856680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1098.856724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1098.856812] [drm:intel_power_well_disable [i915]] disabling display
>[ 1098.856877] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1098.856942] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1098.856979] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1098.857045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1098.857140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1098.857218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1098.857231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1098.857285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1098.857308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1098.857332] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1098.857357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1098.857378] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1098.857399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1098.857421] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1098.857441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1098.857461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1098.857480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1098.857505] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1098.857511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1098.857560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1098.857569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1098.857597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1098.857625] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1098.857652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1098.857678] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1098.857708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1098.857735] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1098.857762] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1098.857789] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1098.857814] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1098.857846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1098.857878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1098.864274] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1098.864293] [drm:intel_power_well_enable [i915]] enabling display
>[ 1098.864313] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1098.864350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1098.864374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1098.864398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1098.864421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1098.864445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1098.864468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1098.864494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1098.864519] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1098.864608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1098.864638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1098.864670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1098.864707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1098.864737] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1098.866802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1098.866823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1098.866846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1098.866870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1098.870740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1098.870777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1098.870808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1098.873461] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1098.873494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1098.876518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1098.879887] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1098.879979] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1098.880013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1098.880064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1098.880149] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1098.880189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1098.896760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1098.896810] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1098.896875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1098.913506] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1098.913556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1098.946937] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1098.946954] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1098.980292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1098.980309] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.013943] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.013977] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.047013] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.047030] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.080374] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.080391] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.113964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.113997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.147095] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.147112] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.180452] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.180469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.214077] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.214111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.247186] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.247203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.280576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.280594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.313908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.313925] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.347269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.347286] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.380655] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.380673] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.414202] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.414236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.447332] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.447349] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.480969] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.481003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.514335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.514368] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.547424] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.547441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.581053] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.581087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.614386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.614420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.647533] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.647551] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.681105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.681139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.714466] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.714565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.747611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.747628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.780941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.780958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.814328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.814355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.847723] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.847750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.881292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.881339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.914423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.914448] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.947751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.947778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1099.981088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1099.981106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.014522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.014549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.047962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.048001] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.081193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.081219] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.114584] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.114611] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.148203] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.148256] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.181296] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.181319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.214666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.214692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.247991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.248017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.281368] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.281394] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.314730] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.314757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.348089] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.348116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.381493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.381512] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.414775] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.414792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.448144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.448161] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.481684] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.481712] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.514841] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.514859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.548211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.548229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.581645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.581676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.614929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.614945] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.648292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.648310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.681656] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.681674] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.715015] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.715032] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.748386] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.748413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.781720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.781737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.815087] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.815104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.848767] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.848802] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.882073] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.882107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.915174] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.915191] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.948560] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.948577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1100.981908] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1100.981925] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.015234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.015252] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.048847] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.048881] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.081992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.082009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.115344] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.115361] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.148693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.148710] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.182111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.182135] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.215493] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.215520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.249118] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.249166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.282143] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.282169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.315531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.315557] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.348877] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.348904] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.382611] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.382658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.415652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.415669] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.448936] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.448953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.482290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.482308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.515652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.515669] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.548993] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.549010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.582658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.582693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.615986] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.616020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.649084] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.649102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.682491] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.682508] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.715821] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.715838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.749181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.749199] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.782752] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.782786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.815886] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.815903] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.849246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.849263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.882620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.882637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.915978] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.915996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.949341] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.949358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1101.982699] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1101.982716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.016339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.016374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.049793] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.049828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.083034] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.083068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.116339] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.116374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.149528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.149545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.182858] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.182875] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.216218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.216235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.249855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.249889] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.282942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.282959] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.316304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.316322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.349644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.349662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.383206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.383236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.416622] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.416653] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.449971] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.450005] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.483099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.483116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.516488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.516505] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.549818] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.549835] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.583510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.583527] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.616550] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.616567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.650149] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.650183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.683253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.683269] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.716614] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.716631] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.749974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.749991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.783333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.783496] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.816696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.816713] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.850056] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.850073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.883724] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.883759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.916758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.916775] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.950129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.950146] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1102.983700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1102.983734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.016852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.016868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.050212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.050229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.083599] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.083618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.116942] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.116960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.150284] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.150302] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.183640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.183658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.217009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.217027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.250396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.250413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.284005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.284040] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.317090] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.317107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.350481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.350498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.383814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.383831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.417132] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.417150] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.450527] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.450545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.483885] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.483902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.517250] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.517267] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.550608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.550625] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.583967] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.583984] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.617359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.617377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.650688] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.650705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.684299] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.684490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.717447] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.717464] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.750768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.750785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.784125] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.784142] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.817792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.817825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.850911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.850945] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.884208] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.884225] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.917572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.917589] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.950912] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.950929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1103.984272] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1103.984289] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.017645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.017662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.051003] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.051020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.084531] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.084557] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.117725] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.117742] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.151083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.151100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.184659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.184692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.217792] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.217809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.251148] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.251165] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.284647] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.284672] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.317880] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.317897] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.351244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.351261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.384603] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.384621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.417941] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.417957] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.451352] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.451370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.484642] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.484660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.518027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.518044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.551415] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.551432] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.584760] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.584776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.618120] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.618137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.651510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.651527] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.684842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.684858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.718432] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.718450] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.751546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.751563] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.784905] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.784922] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.818301] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.818318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.851637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.851654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.885342] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.885377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.918390] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.918407] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.951717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.951734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1104.985080] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1104.985097] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.018733] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.018768] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.051786] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.051804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.085153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.085170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.118515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.118532] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.151874] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.151891] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.185236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.185323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.218597] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.218614] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.251957] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.251974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.285330] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.285347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.318661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.318678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.352031] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.352049] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.385487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.385504] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.418731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.418749] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.452088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.452104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.485478] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.485495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.518836] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.518853] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.552180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.552197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.585780] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.585798] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.618909] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.618926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.652298] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.652316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.685633] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.685650] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.718992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.719009] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.752382] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.752400] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.785712] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.785729] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.819054] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.819071] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.852448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.852465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.885787] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.885804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.919484] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.919518] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.952508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.952526] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1105.985869] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1105.985887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.019262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.019280] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.052591] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.052608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.086122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.086156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.119328] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.119346] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.152665] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.152682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.186091] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.186112] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.219666] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.219701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.253029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.253063] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.286108] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.286126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.319470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.319487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.352814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.352831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.386173] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.386190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.419521] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.419538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.452882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.452899] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.486276] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.486293] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.519626] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.519643] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.553324] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.553358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.586378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.586396] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.619693] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.619709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.653051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.653068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.686701] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.686734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.719784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.719801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.753144] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.753161] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.786677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.786702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.819865] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.819882] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.853302] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.853322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.886570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.886587] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.919953] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.919979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.953333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.953350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1106.986663] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1106.986680] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.020022] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.020039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.053411] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.053428] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.086744] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.086761] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.120444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.120487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.153448] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.153465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.187068] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.187102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.220209] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.220227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.253539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.253556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.287100] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.287134] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.320291] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.320308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.353620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.353637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.386988] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.387006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.420494] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.420519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.453768] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.453793] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.487051] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.487069] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.520396] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.520414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.553779] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.553795] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.587309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.587334] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.620502] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.620519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.653875] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.653892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.687236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.687254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.720563] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.720580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.753934] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.753951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.787323] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.787340] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.820658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.820676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.854027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.854044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.887658] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.887692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.920743] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.920761] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.954082] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.954100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1107.987686] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1107.987703] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.020815] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.020832] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.054200] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.054217] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.087828] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.087862] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.120896] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.120913] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.154364] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.154389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.187709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.187731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.220962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.220979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.254350] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.254367] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.287702] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.287720] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.321052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.321069] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.354412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.354429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.387774] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.387791] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.421166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.421183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.454469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.454487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.487854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.487872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.521231] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.521248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.554570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.554588] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.587929] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.587946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.621549] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.621579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.654852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.654869] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.688012] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.688029] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.721384] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.721401] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.754721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.754738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.788079] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.788097] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.821449] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.821466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.854813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.854830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.888201] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1108.888218] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1108.921554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1108.938074] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1108.938128] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1108.938309] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1108.957058] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1108.957102] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1108.957228] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1108.957272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1108.957313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1108.957359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1108.957401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1108.957443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1108.957483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1108.957530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1108.957574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1108.957618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1108.957661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1108.957702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1108.957742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1108.957800] [drm:intel_power_well_disable [i915]] disabling display
>[ 1108.957848] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1108.957899] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1108.957939] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1108.958390] [drm:drm_mode_addfb2] [FB:77]
>[ 1108.958419] [drm:drm_mode_addfb2] [FB:78]
>[ 1109.011004] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1109.011178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.011339] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1109.011450] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.011462] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.011520] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1109.011544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1109.011570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1109.011598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1109.011620] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1109.011645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1109.011668] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1109.011692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1109.011716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1109.011736] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1109.011759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1109.011764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1109.011787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1109.011791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1109.011815] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1109.011835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1109.011859] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1109.011879] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1109.011903] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1109.011926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1109.011950] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1109.011974] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1109.011997] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1109.012022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1109.012048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1109.018442] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1109.018462] [drm:intel_power_well_enable [i915]] enabling display
>[ 1109.018479] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1109.018516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1109.018536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1109.018555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1109.018573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1109.018590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1109.018609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1109.018629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1109.018647] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1109.018666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1109.018682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1109.018699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1109.018723] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1109.018747] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1109.020812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1109.020834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1109.020852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1109.020872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1109.024768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1109.024805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1109.024837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1109.027519] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1109.027556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1109.030568] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1109.033918] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1109.034006] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1109.034038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1109.034075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1109.050767] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1109.050818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1109.050888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1109.067574] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.067602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.100991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.101017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.134366] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.134383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.167698] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.167715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.201076] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.201170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.234423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.234440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.267783] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.267800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.301156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.301173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.334494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.334511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.367901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.367926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.401310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.401328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.434587] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.434604] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.467939] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.467956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.501310] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.501327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.534659] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.534676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.568016] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.568033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.601373] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.601390] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.634762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.634788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.668145] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.668173] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.701465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.701491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.735186] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.735213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.768219] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.768245] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.801547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.801574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.835177] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.835203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.868271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.868297] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.901620] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.901647] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.935370] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.935420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1109.968666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1109.968717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.002036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.002235] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.035131] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.035150] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.068447] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.068471] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.101781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.101806] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.135305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.135344] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.168656] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.168694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.201878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.201905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.235272] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.235298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.268601] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.268627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.301964] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.301988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.335419] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.335463] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.368657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.368682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.402017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.402102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.435400] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.435427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.468728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.468745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.502125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.502141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.535460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.535477] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.568821] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.568838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.602212] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.602229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.635524] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.635541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.668885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.668902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.702258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.702275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.735615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.735632] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.769169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.769196] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.802471] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.802494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.835762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.835783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.869135] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.869154] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.902402] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.902419] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.935762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.935779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1110.969435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1110.969452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.002494] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.002511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.036204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.036238] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.069498] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.069532] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.102577] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.102594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.136282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.136324] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.169281] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.169298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.202640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.202657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.236343] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.236377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.269648] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.269681] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.302734] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.302752] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.336123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.336140] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.369453] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.369470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.402815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.402832] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.436191] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.436209] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.469522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.469539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.502890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.502907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.536253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.536270] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.569887] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.569921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.603305] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.603339] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.636615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.636658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.669694] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.669711] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.703068] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.703086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.736662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.736696] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.769768] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.769786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.803160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.803177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.836492] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.836509] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.869851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.869868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.903220] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.903237] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.936576] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.936593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1111.969916] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1111.969933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.003279] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.003297] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.036687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.036714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.070039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.070057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.103369] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.103386] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.137071] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.137092] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.170122] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.170139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.203451] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.203468] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.236795] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.236813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.270277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.270302] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.303523] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.303541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.336931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.337065] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.370245] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.370262] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.403605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.403622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.437045] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.437065] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.470368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.470388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.503673] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.503690] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.537061] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.537078] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.570676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.570709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.604097] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.604131] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.637154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.637172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.670487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.670505] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.703846] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.703863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.737210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.737227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.770815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.770849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.803908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.803926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.837282] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.837300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.870642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.870659] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.904030] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.904048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.937363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.937381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1112.970724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1112.970741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.004111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.004128] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.037432] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.037449] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.070787] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.070804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.104159] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.104176] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.137646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.137672] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.170878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.170895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.204242] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.204259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.237603] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.237620] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.271230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.271260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.304306] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.304323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.337786] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.337811] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.371354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.371371] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.404396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.404414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.437759] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.437777] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.471151] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.471168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.504479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.504496] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.537844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.537861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.571184] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.571201] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.604542] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.604559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.637946] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.637964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.671552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.671586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.704639] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.704657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.738033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.738051] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.771356] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.771374] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.804722] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.804740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.838096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.838113] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.871426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.871443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.904796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.904813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.938157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.938174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1113.971791] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1113.971826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.004876] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.004970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.038238] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.038256] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.071600] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.071618] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.104971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.104989] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.138422] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.138447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.171671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.171688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.205060] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.205078] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.238396] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.238413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.271753] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.271771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.305114] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.305132] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.338473] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.338491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.371819] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.371836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.405179] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.405196] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.438550] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.438567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.471936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.471955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.505246] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.505263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.538605] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.538623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.571991] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.572008] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.605324] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.605341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.638696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.638714] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.672086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.672104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.705426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.705443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.738831] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.738851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.772149] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.772166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.805508] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.805526] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.838918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.838953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.872231] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.872249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.905573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.905591] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.939262] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.939298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1114.972582] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1114.972617] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.005665] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.005682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.039057] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.039075] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.072386] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.072403] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.105749] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.105767] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.139110] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.139128] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.172452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.172469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.205811] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.205828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.239183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.239200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.272547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.272564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.305936] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.305953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.339541] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.339575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.372625] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.372642] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.406015] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.406032] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.439332] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.439349] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.472690] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.472707] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.506062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.506079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.539699] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.539734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.572780] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.572797] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.606144] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.606162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.639505] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.639522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.672893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.672911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.706208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.706225] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.739569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.739586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.773208] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.773239] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.806299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.806317] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.839662] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.839679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.873053] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.873070] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.906382] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.906399] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.939747] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.939765] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1115.973091] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1115.973108] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.006446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.006463] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.039850] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.039867] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.073180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.073197] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.106539] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.106556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.139935] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.139953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.173261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.173278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.206621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.206639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.239997] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.240014] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.273445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.273470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.306696] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.306713] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.340058] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.340075] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.373416] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.373434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.406776] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.406871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.440139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.440157] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.473500] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.473517] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.506874] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.506891] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.540322] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.540347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.573573] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.573591] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.606962] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.606980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.640299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.640316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.673655] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.673673] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.707018] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.707036] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.740657] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.740692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.773721] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.773738] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.807082] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.807099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.840452] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.840470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.873840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.873858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.907172] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.907189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.940751] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.940920] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1116.973923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1116.973940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.007258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.007275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.040599] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.040617] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.073987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.074005] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.107331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.107348] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.140859] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.140884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.174055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.174073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.207410] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.207427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.240807] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.240825] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.274259] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.274284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.307476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.307494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.340869] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.340887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.374280] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.374298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.407580] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.407597] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.440961] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.440979] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.474264] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.474281] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.507652] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.507670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.541142] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.541167] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.574354] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.574371] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.607715] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.607733] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.641086] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.641103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.674449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.674466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.707838] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.707855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.741385] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.741415] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.774525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.774543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.807919] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.807937] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.841235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.841253] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.874591] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.874609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.907965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.907983] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.941414] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.941440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1117.974772] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1117.974800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.008046] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.008072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.041407] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.041434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.074809] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.074836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.108216] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.108254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.141460] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.141486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.174868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.174895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.208202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.208229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.241562] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.241589] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.274956] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.274982] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.308289] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.308315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.341647] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.341674] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.374977] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.375004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.408640] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.408694] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.441781] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.441806] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.475056] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.475073] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.508441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.508459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.541978] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.542004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.575161] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.575179] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.608522] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.608539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.642134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.642169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.675489] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.675523] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.708933] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.708967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.741963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.741981] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.775319] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.775336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.808683] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.808734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.842043] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.842060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.875679] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.875774] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.909070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.909104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.942106] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.942124] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1118.975476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1118.975494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.009169] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1119.009204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.042475] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1119.042509] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.075869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1119.075956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1119.076004] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1119.076079] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1119.093104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1119.093147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1119.093193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1119.093234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1119.093278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1119.093319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1119.093359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1119.093398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1119.093443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1119.093485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1119.093527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1119.093569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1119.093608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1119.093647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1119.093785] [drm:intel_power_well_disable [i915]] disabling display
>[ 1119.093856] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1119.093922] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1119.093975] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1119.094252] [drm:drm_mode_addfb2] [FB:77]
>[ 1119.094281] [drm:drm_mode_addfb2] [FB:78]
>[ 1119.146029] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1119.146134] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1119.146206] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.146274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.146286] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.146344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1119.146366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1119.146388] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1119.146412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1119.146430] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1119.146450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1119.146470] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1119.146493] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1119.146517] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1119.146539] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1119.146562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1119.146567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1119.146590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1119.146594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1119.146617] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1119.146638] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1119.146661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1119.146681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1119.146760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1119.146792] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1119.146823] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1119.146851] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1119.146879] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1119.146911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1119.146944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1119.153310] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1119.153330] [drm:intel_power_well_enable [i915]] enabling display
>[ 1119.153346] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1119.153381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1119.153401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1119.153420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1119.153438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1119.153461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1119.153485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1119.153511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1119.153536] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1119.153561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1119.153584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1119.153607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1119.153633] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1119.153656] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1119.155766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1119.155788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1119.155806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1119.155825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1119.159630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1119.159662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1119.159681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1119.162427] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1119.162467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1119.165457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1119.168819] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1119.168879] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1119.168899] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1119.168925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1119.185674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1119.185756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1119.185823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1119.202446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.202465] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.235898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.235915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.269225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.269242] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.302583] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.302600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.335942] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.335959] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.369304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.369322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.402663] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.402718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.436006] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.436023] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.469371] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.469388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.502764] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.502781] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.536090] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.536107] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.569449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.569466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.602842] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.602859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.636172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.636189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.669532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.669549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.702979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.703003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.736476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.736510] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.769605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.769623] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.802977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.802994] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.836337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.836355] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.869745] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.869763] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.903074] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.903091] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.936438] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.936455] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1119.970103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1119.970137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.003140] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.003157] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.036511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.036528] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.069935] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.069969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.103231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.103249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.136592] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.136608] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.170231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.170266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.203314] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.203331] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.236688] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.236705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.270284] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.270318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.303387] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.303404] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.336775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.336792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.370274] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.370302] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.403469] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.403487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.436862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.436879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.470191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.470208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.503511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.503529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.536870] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.536887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.570239] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.570256] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.603914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.603948] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.636987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.637004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.670692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.670727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.703740] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.703757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.737070] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.737087] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.770685] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.770702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.803800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.803817] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.837144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.837162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.870845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.870879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.903866] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.903884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.937230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.937247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1120.970586] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1120.970678] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.003947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.003964] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.037292] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.037309] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.070690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.070708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.104024] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.104041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.137383] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.137401] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.171081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.171115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.204103] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.204120] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.237465] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.237482] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.270896] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.270936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.304168] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.304185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.337529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.337545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.370900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.370917] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.404427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.404454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.437950] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.437984] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.470981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.470998] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.504341] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.504358] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.537734] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.537751] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.571308] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.571342] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.604407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.604423] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.637813] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.637830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.671138] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.671155] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.704499] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.704516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.737859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.737876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.771348] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.771372] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.804767] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.804785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.837923] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.837940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.871548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.871900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.904690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.904708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.938016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.938033] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1121.971721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1121.971755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.005019] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.005053] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.038099] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.038116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.071804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.071838] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.104804] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.104822] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.138207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.138224] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.171534] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.171631] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.204895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.204912] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.238256] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.238274] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.271834] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.271873] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.304977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.304994] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.338337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.338354] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.371710] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.371727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.405041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.405059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.438412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.438429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.471840] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.471874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.505110] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.505127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.538470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.538487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.572087] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.572120] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.605420] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.605455] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.638814] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.638848] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.672145] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.672179] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.705290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.705307] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.739039] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.739074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.772012] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.772029] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.805372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.805390] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.838766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.838784] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.872094] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.872111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.905437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.905454] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.938796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.938813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1122.972293] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1122.972318] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.005867] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.005900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.038890] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.038907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.072251] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.072268] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.105645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.105663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.138971] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.138988] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.172650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.172685] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.205943] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.205978] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.239320] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.239354] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.272409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.272426] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.306045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.306079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.339403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.339437] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.372489] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.372704] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.405850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.405868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.439190] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.439208] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.472882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.472916] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.505900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.505918] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.539258] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.539275] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.572910] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.572944] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.605979] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.605996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.639346] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.639363] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.672706] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.672724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.706073] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.706090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.739461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.739478] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.772802] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.772819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.806162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.806179] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.839563] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.839590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.873018] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.873043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.906246] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.906264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.940003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.940021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1123.972953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1123.972970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.006311] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.006328] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.039714] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.039731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.073042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.073060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.106403] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.106420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.139765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.139782] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.173400] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.173435] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.206824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.206858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.239828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.239845] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.273457] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.273553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.306587] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.306604] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.339920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.339937] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.373446] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.373541] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.406671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.406688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.440002] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.440019] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.473701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.473735] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.506707] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.506725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.540042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.540059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.573702] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.573736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.606949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.606976] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.640237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.640260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.673797] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.673831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.707112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.707145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.740228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.740245] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.773644] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.773661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.807193] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.807227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.840315] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.840333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.873678] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.873695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.907036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.907054] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.940396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.940413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1124.973758] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1124.973776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.007118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.007135] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.040590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.040613] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.073824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.073841] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.107192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.107210] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.140582] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.140599] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.173914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.173932] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.207275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.207292] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.240922] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.240956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.273996] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.274013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.307340] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.307357] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.340964] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.340997] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.374345] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.374380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.407762] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.407796] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.440792] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.440809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.474153] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.474170] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.507855] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.507900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.541081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.541116] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.574194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.574211] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.607610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.607627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.641225] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.641260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.674310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.674327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.707670] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.707688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.741031] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.741048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.774395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.774447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.807753] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.807770] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.841216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.841241] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.874780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.874814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.908100] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.908134] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.941524] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.941558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1125.974605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1125.974622] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.007924] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.007941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.041270] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.041287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.074634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.074651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.108237] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.108271] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.141335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.141352] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.174704] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.174722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.208334] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.208368] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.241459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.241476] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.275076] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.275110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.308483] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.308518] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.341537] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.341554] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.375112] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.375147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.408209] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.408226] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.441863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.441898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.474944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.474961] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.508590] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.508624] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.541692] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.541709] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.575231] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.575265] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.608686] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.608719] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.641703] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.641720] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.675065] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.675082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.708754] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.708788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.742081] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.742115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.775569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.775602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.808577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.808594] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.841904] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.841921] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.875266] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.875283] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.908610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.908627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.942229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.942264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1126.975677] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1126.975711] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.008981] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.009016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.042337] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.042436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.075763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.075807] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.108783] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.108800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.142144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.142161] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.175516] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.175533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.208847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.208863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.242491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.242522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.275861] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.275895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.309219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.309253] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.342300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.342317] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.375669] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.375686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.409022] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.409039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.442399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.442416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.475847] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.475872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.509095] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.509112] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.542464] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.542482] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.575791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.575808] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.609155] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.609172] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.642546] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.642563] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.675893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.675927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.709625] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.709658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.742604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.742621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.776247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.776281] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.809601] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.809631] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.842977] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.843010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.876057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.876075] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.909449] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.909466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.942781] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.942798] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1127.976211] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1127.976234] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.009756] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.009790] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.042854] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.042871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.076552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.076586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.109851] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.109886] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.142937] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.142954] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.176297] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.176347] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.209656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.209673] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.243000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.243017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.276395] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.276412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.310003] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.310037] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.343093] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.343110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.376481] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.376498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.409811] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.409829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.443172] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.443189] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.476659] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.476684] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.509879] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.509896] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.543213] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.543230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.576610] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.576628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.610045] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.610068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.643331] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.643349] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.676776] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.676801] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.710255] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.710432] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.743424] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.743441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.776757] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.776774] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.810235] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.810260] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.843521] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.843539] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.876944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.876966] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.910356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.910390] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.943569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.943586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1128.977207] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1128.977241] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.010319] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1129.010336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.043899] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1129.043933] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.076993] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1129.077010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.110397] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1129.110414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.143725] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1129.143742] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.177427] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1129.177461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.210749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.210920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1129.211010] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1129.211163] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1129.228290] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1129.228362] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1129.228402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.228436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.228472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.228502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.228531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.228562] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.228597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.228630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.228662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.228693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.228722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.228749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.228804] [drm:intel_power_well_disable [i915]] disabling display
>[ 1129.228845] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1129.228887] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1129.228918] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1129.232178] [IGT] kms_flip: exiting, ret=0
>[ 1129.251115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1129.251153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1129.251191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1129.251233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1129.251265] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1129.251349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1129.251391] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1129.251431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1129.251465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1129.251484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1129.251502] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1129.251507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.251525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1129.251528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.251546] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1129.251564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1129.251581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1129.251597] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1129.251618] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1129.251641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1129.251665] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1129.251689] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1129.251710] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1129.251736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.251762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1129.251828] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1129.251850] [drm:intel_power_well_enable [i915]] enabling display
>[ 1129.251870] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1129.251909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.251933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.251957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.251981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.252005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.252028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.252055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.252079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.252105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.252126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.252149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.252174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1129.252198] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1129.254321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1129.254342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.254361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.254386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.258218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1129.258251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1129.258333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.261067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.261104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.264145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.267672] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1129.267716] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1129.267735] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1129.267762] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1129.267827] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1129.267847] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1129.284527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.284575] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.284645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.284896] Console: switching to colour frame buffer device 240x75
>[ 1129.397662] Console: switching to colour dummy device 80x25
>[ 1129.397777] [IGT] kms_flip: executing
>[ 1129.408812] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1129.408846] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1129.410381] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1129.410422] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1129.412361] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1129.412373] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1129.414377] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1129.414416] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1129.416360] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1129.416372] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1129.416381] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1129.416413] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1129.416455] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1129.417579] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1129.418507] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1129.418529] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1129.418548] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1129.418566] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1129.419586] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1129.419606] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1129.420722] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1129.420726] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1129.420830] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1129.420832] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1129.420838] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1129.420840] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1129.420845] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1129.420847] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1129.420857] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1129.420860] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.420863] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1129.420866] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1129.420869] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1129.420872] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1129.420875] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1129.420878] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1129.420881] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1129.420884] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1129.420887] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1129.420890] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1129.420893] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1129.420896] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1129.420899] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1129.420902] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1129.420905] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1129.420908] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1129.420911] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1129.420914] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1129.420917] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1129.420920] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1129.420923] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1129.420926] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1129.420928] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1129.420931] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1129.420934] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1129.420937] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1129.420940] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1129.420943] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1129.420946] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1129.420986] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1129.421008] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1129.422332] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1129.422361] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1129.424358] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1129.424369] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1129.426358] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1129.426395] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1129.428381] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1129.428396] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1129.428407] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1129.430575] [IGT] kms_flip: starting subtest modeset-vs-vblank-race-interruptible
>[ 1129.431169] [drm:drm_mode_addfb2] [FB:58]
>[ 1129.431199] [drm:drm_mode_addfb2] [FB:79]
>[ 1129.484985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.485049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.501368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1129.501419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1129.501497] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1129.518505] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1129.518550] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1129.518583] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1129.518622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.518656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.518691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.518722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.518751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.518793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.518846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.518880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.518911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.518941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.518969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.518996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.519058] [drm:intel_power_well_disable [i915]] disabling display
>[ 1129.519083] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1129.519110] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.519131] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1129.519192] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1129.519355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1129.519453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.519466] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.519522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1129.519545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1129.519569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1129.519598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1129.519623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1129.519650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1129.519676] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1129.519702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1129.519728] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1129.519754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1129.519779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1129.519786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.519810] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1129.519815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.519841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1129.519867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1129.519894] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1129.519919] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1129.519946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1129.519971] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1129.519997] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1129.520023] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1129.520049] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1129.520077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.520104] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1129.523490] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1129.523513] [drm:intel_power_well_enable [i915]] enabling display
>[ 1129.523533] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1129.523571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.523597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.523622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.523646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.523670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.523693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.523720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.523745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.523771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.523795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.523819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.523845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1129.523869] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1129.527074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1129.527103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.527130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.527158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.531026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1129.531064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1129.531096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.533741] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.533777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.536824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.540172] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1129.540263] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1129.540353] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1129.540412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1129.540488] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1129.540519] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1129.557042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.557091] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.557156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.573872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.573962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.590395] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1129.590444] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1129.590549] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1129.609219] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1129.609263] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1129.609388] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1129.609432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.609466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.609520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.609561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.609592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.609624] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.609661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.609696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.609727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.609759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.609786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.609815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.609868] [drm:intel_power_well_disable [i915]] disabling display
>[ 1129.609910] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1129.609951] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.609973] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1129.610040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.610052] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.610106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1129.610126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1129.610148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1129.610173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1129.610194] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1129.610214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1129.610235] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1129.610285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1129.610314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1129.610341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1129.610367] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1129.610376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.610402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1129.610409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.610436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1129.610463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1129.610489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1129.610516] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1129.610546] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1129.610573] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1129.610600] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1129.610626] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1129.610652] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1129.610684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.610716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1129.610807] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1129.610827] [drm:intel_power_well_enable [i915]] enabling display
>[ 1129.610845] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1129.610879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.610899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.610925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.610951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.610978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.611004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.611032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.611060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.611088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.611114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.611140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.611167] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1129.611193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1129.613238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1129.613279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.613299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.613320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.617147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1129.617178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1129.617205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.619949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.619988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.622980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.626324] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1129.626402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1129.626426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1129.626457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1129.626521] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1129.626543] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1129.643216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.643263] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.643419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.676636] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.676726] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.693229] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1129.693358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1129.693677] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1129.711504] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1129.711548] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1129.711580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1129.711619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.711658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.711702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.711742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.711782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.711822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.711866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.711908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.711950] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.711992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.712031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.712070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.712126] [drm:intel_power_well_disable [i915]] disabling display
>[ 1129.712172] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1129.712224] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.712245] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1129.712405] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.712425] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.712516] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1129.712550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1129.712577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1129.712607] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1129.712632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1129.712659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1129.712685] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1129.712711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1129.712738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1129.712764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1129.712789] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1129.712794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.712819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1129.712824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.712850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1129.712875] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1129.712902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1129.712926] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1129.712952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1129.712977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1129.713004] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1129.713029] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1129.713056] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1129.713083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.713118] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1129.713190] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1129.713209] [drm:intel_power_well_enable [i915]] enabling display
>[ 1129.713227] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1129.713301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.713332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.713361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.713390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.713418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.713447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.713479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.713510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.713541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.713568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.713594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.713626] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1129.713655] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1129.715741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1129.715765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.715787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.715812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.718540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1129.718580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1129.718619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.721341] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.721382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.724417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.727676] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1129.727737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1129.727757] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1129.727793] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1129.727860] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1129.727881] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1129.744512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.744572] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.744642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.777939] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.778027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.794557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1129.794606] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1129.794698] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1129.811734] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1129.811778] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1129.811810] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1129.811849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.811888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.811932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.811972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.812012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.812051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.812095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.812137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.812179] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.812220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.812259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.812363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.812433] [drm:intel_power_well_disable [i915]] disabling display
>[ 1129.812478] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1129.812511] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.812540] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1129.812643] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.812664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.812751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1129.812783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1129.812817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1129.812853] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1129.812882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1129.812913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1129.812944] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1129.812975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1129.813004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1129.813033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1129.813060] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1129.813068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.813095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1129.813102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.813130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1129.813157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1129.813186] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1129.813213] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1129.813244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1129.813407] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1129.813436] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1129.813464] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1129.813493] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1129.813526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.813552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1129.813611] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1129.813631] [drm:intel_power_well_enable [i915]] enabling display
>[ 1129.813649] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1129.813682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.813701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.813721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.813739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.813758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.813777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.813805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.813833] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.813861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.813887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.813912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.813939] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1129.813965] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1129.816025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1129.816047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.816066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.816085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.818798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1129.818839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1129.818878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.821642] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.821674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.824719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.828019] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1129.828115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1129.828142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1129.828178] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1129.828247] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1129.828335] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1129.844886] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.844936] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.845016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.878327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.878416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.894907] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1129.894958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1129.895040] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1129.914062] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1129.914105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1129.914137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1129.914176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.914209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.914243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.914357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.914404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.914451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.914518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.914565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.914610] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.914656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.914688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.914713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.914762] [drm:intel_power_well_disable [i915]] disabling display
>[ 1129.914798] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1129.914836] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.914867] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1129.914973] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.915000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1129.915087] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1129.915115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1129.915148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1129.915195] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1129.915235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1129.915320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1129.915363] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1129.915404] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1129.915443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1129.915483] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1129.915528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1129.915536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.915562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1129.915570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1129.915597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1129.915624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1129.915651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1129.915678] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1129.915707] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1129.915734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1129.915761] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1129.915787] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1129.915816] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1129.915849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.915884] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1129.915976] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1129.916009] [drm:intel_power_well_enable [i915]] enabling display
>[ 1129.916039] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1129.916093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1129.916127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1129.916159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1129.916186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1129.916206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1129.916226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1129.916281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1129.916312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1129.916342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.916369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1129.916395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1129.916430] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1129.916459] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1129.918523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1129.918544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1129.918562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.918580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1129.922396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1129.922431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1129.922468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1129.925129] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1129.925166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1129.928161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1129.931528] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1129.931600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1129.931640] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1129.931692] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1129.931782] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1129.931806] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1129.948380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1129.948430] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1129.948495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1129.981788] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1129.981877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1129.998402] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1129.998453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1129.998547] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.015555] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.015603] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.015644] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.015689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.015729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.015772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.015812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.015852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.015891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.015935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.015978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.016019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.016061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.016100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.016138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.016196] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.016241] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.016379] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.016439] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.016572] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.016585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.016643] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.016665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.016688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.016717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.016743] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.016775] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.016809] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.016833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.016853] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.016879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.016904] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.016910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.016935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.016939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.016965] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.016990] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.017017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.017042] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.017069] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.017094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.017120] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.017146] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.017173] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.017200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.017228] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.017342] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.017374] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.017404] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.017444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.017466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.017487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.017506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.017525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.017546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.017568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.017589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.017610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.017628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.017647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.017670] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.017691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.019753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.019774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.019797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.019821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.022492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.022519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.022541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.025244] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.025309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.028306] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.031666] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.031744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.031777] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.031827] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.031888] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.031909] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.048491] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.048539] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.048602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.081956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.082041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.098555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.098602] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.098692] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.115706] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.115750] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.115783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.115822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.115855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.115890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.115920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.115958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.115998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.116042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.116084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.116125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.116167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.116206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.116246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.116370] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.116437] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.116504] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.116559] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.116689] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.116708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.116794] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.116824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.116857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.116893] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.116921] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.116953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.116983] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.117013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.117041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.117070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.117096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.117103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.117129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.117136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.117165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.117191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.117218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.117269] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.117302] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.117329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.117360] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.117387] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.117416] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.117447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.117481] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.117571] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.117602] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.117631] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.117680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.117709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.117738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.117765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.117793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.117820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.117852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.117883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.117914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.117940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.117968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.117998] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.118028] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.120104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.120127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.120146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.120165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.124084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.124122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.124153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.126919] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.126954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.129957] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.133230] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.133339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.133368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.133406] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.133475] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.133504] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.150130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.150182] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.150253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.183516] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.183602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.200148] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.200197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.200388] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.218060] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.218105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.218137] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.218176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.218210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.218328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.218378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.218427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.218478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.218536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.218574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.218615] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.218656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.218696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.218736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.218796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.218837] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.218869] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.218892] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.218954] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.218966] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.219022] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.219044] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.219067] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.219092] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.219112] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.219134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.219155] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.219176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.219196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.219215] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.219264] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.219274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.219300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.219308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.219336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.219363] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.219390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.219416] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.219446] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.219472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.219499] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.219526] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.219552] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.219583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.219616] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.219709] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.219741] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.219771] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.219824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.219856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.219888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.219918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.219948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.219979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.220007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.220038] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.220069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.220088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.220106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.220129] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.220150] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.223348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.223385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.223416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.223456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.227397] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.227434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.227466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.230163] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.230196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.233307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.236654] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.236745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.236778] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.236820] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.236898] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.236931] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.253526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.253575] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.253641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.286925] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.287023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.303558] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.303604] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.303694] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.320706] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.320751] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.320790] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.320835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.320876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.320920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.320960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.320999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.321039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.321083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.321133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.321168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.321203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.321235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.321328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.321403] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.321460] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.321516] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.321547] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.321632] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.321647] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.321741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.321772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.321802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.321839] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.321872] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.321908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.321942] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.321976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.322010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.322045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.322078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.322086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.322119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.322125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.322162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.322184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.322204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.322225] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.322278] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.322307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.322336] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.322363] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.322391] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.322423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.322455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.322547] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.322573] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.322591] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.322625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.322646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.322666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.322684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.322702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.322722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.322750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.322778] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.322806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.322831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.322857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.322883] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.322910] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.326063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.326088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.326109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.326130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.330044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.330085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.330124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.332791] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.332828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.335881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.339186] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.339340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.339388] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.339459] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.339536] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.339569] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.356046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.356098] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.356169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.389455] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.389566] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.406072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.406125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.406209] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.423328] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.423373] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.423406] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.423445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.423478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.423513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.423543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.423581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.423621] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.423665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.423708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.423750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.423791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.423830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.423869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.423927] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.423972] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.424022] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.424061] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.424161] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.424180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.424335] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.424367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.424400] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.424438] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.424469] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.424503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.424528] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.424550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.424570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.424590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.424608] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.424613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.424631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.424635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.424655] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.424672] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.424691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.424708] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.424730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.424748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.424767] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.424785] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.424803] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.424824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.424848] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.424910] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.424929] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.424947] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.424981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.425001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.425020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.425045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.425070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.425096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.425123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.425151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.425178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.425204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.425256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.425289] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.425319] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.427389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.427411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.427429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.427449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.431303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.431340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.431380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.434049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.434086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.437083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.440425] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.440521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.440560] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.440586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.440647] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.440668] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.457299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.457344] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.457407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.490690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.490774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.507320] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.507367] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.507461] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.524476] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.524520] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.524552] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.524590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.524623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.524665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.524705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.524745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.524784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.524828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.524871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.524912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.524954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.524993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.525032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.525089] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.525134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.525184] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.525222] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.525444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.525460] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.525534] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.525569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.525604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.525643] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.525676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.525711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.525745] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.525779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.525814] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.525848] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.525881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.525889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.525922] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.525928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.525962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.525996] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.526027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.526060] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.526094] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.526127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.526162] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.526195] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.526233] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.526309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.526356] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.526465] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.526496] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.526518] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.526556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.526579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.526602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.526622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.526643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.526664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.526694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.526725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.526755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.526783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.526815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.526854] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.526880] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.528947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.528969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.528988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.529009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.531716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.531757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.531796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.534552] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.534575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.537611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.540908] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.540988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.541016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.541052] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.541118] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.541146] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.557778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.557828] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.557894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.591180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.591351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.607790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.607837] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.607928] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.624952] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.624996] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.625028] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.625067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.625100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.625136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.625167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.625196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.625311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.625370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.625423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.625475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.625526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.625572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.625617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.625690] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.625733] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.625762] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.625784] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.625851] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.625863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.625916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.625936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.625960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.625984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.626004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.626026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.626046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.626067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.626086] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.626112] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.626138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.626144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.626168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.626173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.626201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.626258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.626290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.626318] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.626349] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.626376] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.626404] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.626431] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.626457] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.626489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.626520] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.626613] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.626641] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.626671] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.626723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.626754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.626784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.626814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.626843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.626873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.626907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.626941] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.626964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.626982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.627007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.627034] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.627061] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.630274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.630312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.630344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.630381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.634279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.634320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.634359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.637048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.637081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.640084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.643447] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.643518] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.643555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.643604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.643682] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.643720] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.660300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.660349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.660415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.693708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.693795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.710326] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.710378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.710460] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.727472] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.727516] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.727548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.727587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.727620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.727655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.727686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.727715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.727747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.727783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.727815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.727847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.727879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.727907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.727934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.727967] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.727992] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.728021] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.728055] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.728122] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.728133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.728184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.728204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.728331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.728367] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.728396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.728430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.728463] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.728494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.728526] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.728556] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.728586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.728594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.728623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.728630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.728661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.728680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.728698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.728716] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.728737] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.728762] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.728789] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.728815] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.728841] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.728870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.728899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.728961] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.728984] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.729006] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.729045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.729071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.729097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.729122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.729148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.729173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.729201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.729265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.729299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.729328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.729356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.729390] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.729419] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.732607] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.732646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.732685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.732725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.736661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.736698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.736730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.739425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.739457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.742456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.745787] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.745841] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.745873] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.745924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.746006] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.746046] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.762626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.762675] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.762740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.796038] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.796122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.812640] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.812689] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.812782] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.829806] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.829850] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.829883] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.829922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.829955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.829991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.830021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.830051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.830082] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.830117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.830150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.830181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.830212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.830325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.830367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.830453] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.830517] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.830580] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.830616] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.830721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.830739] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.830822] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.830862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.830904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.830949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.830988] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.831030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.831071] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.831111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.831153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.831182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.831207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.831246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.831284] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.831294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.831332] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.831367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.831404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.831438] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.831479] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.831514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.831550] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.831584] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.831619] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.831660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.831706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.831819] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.831861] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.831888] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.831932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.831959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.831985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.832009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.832042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.832075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.832113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.832151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.832174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.832194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.832241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.832272] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.832302] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.834366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.834387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.834409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.834433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.837104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.837131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.837154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.839891] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.839928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.842936] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.846289] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.846389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.846412] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.846438] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.846499] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.846521] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.863158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.863208] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.863374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.896583] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.896667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.913184] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1130.913262] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1130.913352] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1130.930363] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1130.930406] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1130.930438] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1130.930476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.930508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.930543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.930574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.930603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.930634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.930669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.930701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.930733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.930764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.930792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.930819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.930873] [drm:intel_power_well_disable [i915]] disabling display
>[ 1130.930913] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1130.930954] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.930997] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1130.931050] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.931062] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1130.931112] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1130.931130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1130.931151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1130.931174] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1130.931191] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1130.931276] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1130.931308] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1130.931340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1130.931368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1130.931396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1130.931422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1130.931431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.931456] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1130.931464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1130.931491] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1130.931517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1130.931544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1130.931569] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1130.931599] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1130.931625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1130.931652] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1130.931678] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1130.931705] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1130.931735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1130.931766] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1130.931856] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1130.931888] [drm:intel_power_well_enable [i915]] enabling display
>[ 1130.931918] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1130.931970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1130.932001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1130.932032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1130.932062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1130.932092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1130.932123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1130.932157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1130.932189] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1130.932245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.932272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1130.932299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1130.932331] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1130.932360] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1130.935580] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1130.935617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1130.935648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.935680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1130.939553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1130.939591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1130.939626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1130.942328] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1130.942360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1130.945383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1130.948720] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1130.948818] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1130.948848] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1130.948888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1130.948960] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1130.948991] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1130.965603] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1130.965653] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1130.965718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1130.998992] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1130.999106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.015625] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.015673] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.015750] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.032789] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.032834] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.032866] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.032904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.032948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.033000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.033031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.033060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.033092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.033128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.033161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.033192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.033298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.033325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.033354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.033407] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.033435] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.033464] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.033486] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.033545] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.033557] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.033611] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.033631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.033654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.033678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.033699] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.033720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.033740] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.033760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.033780] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.033800] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.033818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.033824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.033841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.033845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.033865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.033883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.033901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.033918] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.033940] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.033958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.033976] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.033995] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.034012] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.034033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.034056] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.034115] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.034134] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.034152] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.034185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.034239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.034267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.034295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.034324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.034351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.034383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.034414] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.034443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.034470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.034497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.034529] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.034558] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.036625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.036646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.036665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.036683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.040544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.040578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.040605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.043350] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.043400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.046407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.049705] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.049778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.049798] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.049824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.049885] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.049906] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.066592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.066646] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.066714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.099972] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.100067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.116606] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.116652] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.116744] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.133771] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.133815] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.133854] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.133899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.133939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.133983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.134022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.134062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.134101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.134145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.134187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.134306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.134362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.134390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.134421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.134475] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.134515] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.134545] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.134577] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.134652] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.134665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.134720] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.134742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.134765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.134790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.134810] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.134832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.134853] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.134873] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.134898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.134924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.134949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.134955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.134980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.134984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.135010] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.135033] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.135059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.135084] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.135110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.135135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.135162] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.135187] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.135247] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.135282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.135317] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.135406] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.135437] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.135468] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.135505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.135527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.135547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.135566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.135585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.135605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.135627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.135653] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.135680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.135705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.135731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.135759] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.135786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.137832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.137856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.137879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.137903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.141793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.141831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.141863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.144582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.144617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.147658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.150977] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.151036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.151064] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.151100] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.151166] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.151199] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.167827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.167877] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.167942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.201251] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.201338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.217842] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.217891] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.217969] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.236123] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.236166] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.236205] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.236305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.236360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.236413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.236460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.236502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.236549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.236605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.236647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.236689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.236730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.236763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.236799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.236870] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.236923] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.236974] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.237018] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.237151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.237211] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.237324] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.237363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.237407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.237454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.237491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.237533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.237571] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.237615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.237643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.237672] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.237697] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.237705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.237733] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.237740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.237768] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.237794] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.237822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.237847] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.237878] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.237903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.237931] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.237956] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.237983] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.238016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.238050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.238140] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.238170] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.238230] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.238280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.238309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.238341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.238369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.238399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.238427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.238461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.238493] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.238526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.238553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.238582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.238615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.238648] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.241862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.241899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.241931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.241970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.245891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.245930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.245967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.248639] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.248676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.251681] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.254985] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.255051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.255071] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.255097] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.255158] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.255179] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.271851] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.271900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.271965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.305275] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.305362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.321885] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.321934] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.322012] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.339020] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.339068] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.339108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.339152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.339193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.339319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.339367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.339418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.339464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.339516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.339568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.339617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.339665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.339705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.339750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.339833] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.339903] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.339943] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.339977] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.340081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.340100] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.340204] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.340264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.340297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.340335] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.340366] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.340400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.340430] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.340463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.340492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.340522] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.340549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.340556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.340582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.340589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.340617] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.340644] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.340673] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.340699] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.340731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.340756] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.340784] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.340813] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.340839] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.340872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.340905] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.340994] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.341025] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.341054] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.341103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.341132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.341162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.341190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.341242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.341272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.341306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.341339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.341373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.341399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.341428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.341463] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.341493] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.343556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.343577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.343595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.343614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.347482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.347519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.347552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.350264] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.350303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.353301] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.356611] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.356685] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.356718] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.356760] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.356837] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.356869] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.373471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.373522] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.373592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.406864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.406951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.423481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.423528] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.423622] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.440647] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.440691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.440731] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.440775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.440815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.440859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.440899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.440939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.440978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.441022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.441072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.441105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.441135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.441160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.441235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.441305] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.441363] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.441411] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.441441] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.441529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.441545] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.441617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.441646] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.441676] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.441709] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.441737] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.441764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.441791] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.441817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.441843] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.441875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.441908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.441916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.441948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.441954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.441988] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.442022] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.442057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.442094] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.442120] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.442145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.442171] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.442228] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.442259] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.442293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.442327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.442420] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.442452] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.442479] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.442516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.442537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.442562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.442589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.442616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.442641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.442670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.442698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.442726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.442750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.442776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.442802] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.442828] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.444879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.444903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.444926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.444950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.448884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.448921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.448953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.451609] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.451647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.454665] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.457968] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.458053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.458085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.458135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.458284] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.458333] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.474839] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.474891] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.474963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.508311] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.508399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.524869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.524918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.525000] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.542039] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.542084] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.542116] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.542154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.542265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.542322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.542367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.542414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.542460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.542515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.542567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.542616] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.542664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.542704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.542747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.542830] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.542892] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.542953] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.543006] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.543212] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.543254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.543341] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.543363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.543387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.543416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.543441] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.543467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.543493] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.543518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.543543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.543566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.543591] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.543596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.543620] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.543625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.543650] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.543676] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.543701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.543725] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.543751] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.543775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.543801] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.543826] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.543852] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.543879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.543906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.543971] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.543993] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.544015] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.544053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.544079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.544104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.544130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.544156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.544215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.544253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.544287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.544322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.544350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.544380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.544416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.544446] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.546515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.546535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.546554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.546573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.550431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.550463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.550490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.553194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.553249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.556252] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.559593] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.559673] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.559693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.559719] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.559778] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.559808] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.576470] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.576520] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.576585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.609884] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.609972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.626495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.626543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.626641] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.643653] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.643697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.643730] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.643768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.643800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.643836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.643874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.643915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.643954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.643998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.644041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.644082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.644124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.644162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.644271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.644358] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.644424] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.644456] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.644478] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.644546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.644559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.644613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.644639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.644665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.644694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.644719] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.644746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.644772] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.644798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.644825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.644851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.644875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.644881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.644906] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.644911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.644936] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.644962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.644987] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.645013] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.645039] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.645064] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.645089] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.645115] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.645141] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.645169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.645231] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.645319] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.645351] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.645380] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.645429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.645451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.645476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.645502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.645528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.645554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.645582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.645609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.645637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.645662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.645688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.645720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.645753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.647970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.647991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.648010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.648029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.651938] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.651992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.652032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.654767] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.654801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.657856] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.661174] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.661294] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.661328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.661370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.661466] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.661517] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.678073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.678125] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.678278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.711497] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.711582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.728108] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.728154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.728501] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.745538] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.745582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.745614] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.745652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.745685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.745719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.745749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.745788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.745827] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.745871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.745914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.745955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.745997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.746036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.746074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.746131] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.746177] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.746379] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.746419] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.746507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.746525] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.746611] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.746645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.746679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.746704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.746725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.746747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.746772] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.746799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.746825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.746851] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.746876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.746882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.746907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.746912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.746938] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.746964] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.746991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.747016] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.747042] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.747068] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.747094] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.747119] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.747146] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.747201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.747237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.747325] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.747354] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.747385] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.747437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.747460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.747480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.747500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.747518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.747539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.747567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.747594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.747622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.747647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.747673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.747700] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.747727] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.750917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.750955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.750986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.751018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.754915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.754953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.754990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.757730] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.757768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.760753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.763329] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.763380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.763410] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.763450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.763526] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.763557] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.780170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.780254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.780320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.813552] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.813647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.830228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.830278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.830383] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.847348] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.847392] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.847424] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.847462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.847495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.847530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.847560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.847588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.847619] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.847654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.847687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.847718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.847749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.847776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.847803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.847856] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.847896] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.847948] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.847968] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.848020] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.848031] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.848080] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.848098] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.848119] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.848141] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.848159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.848243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.848273] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.848302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.848332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.848360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.848386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.848394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.848420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.848428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.848455] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.848481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.848507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.848533] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.848563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.848589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.848616] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.848642] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.848668] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.848702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.848736] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.848826] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.848858] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.848889] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.848940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.848972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.849003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.849035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.849065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.849096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.849130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.849153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.849206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.849235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.849261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.849294] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.849322] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.851386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.851409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.851432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.851457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.855339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.855376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.855408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.858091] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.858128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.861222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.864521] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.864601] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.864631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.864668] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.864753] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.864798] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.881388] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.881438] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.881510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.914805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.914897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.931412] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1131.931459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1131.931561] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1131.950182] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1131.950259] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1131.950291] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1131.950330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.950364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.950399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.950429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.950458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.950490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.950525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.950558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.950589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.950619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.950659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.950687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.950741] [drm:intel_power_well_disable [i915]] disabling display
>[ 1131.950782] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1131.950824] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.950857] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1131.950956] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1131.950974] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1131.951058] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1131.951090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1131.951124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1131.951161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1131.951245] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1131.951275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1131.951307] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1131.951335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1131.951364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1131.951391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1131.951417] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1131.951426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.951452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1131.951460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1131.951487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1131.951513] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1131.951540] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1131.951566] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1131.951596] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1131.951622] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1131.951649] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1131.951676] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1131.951702] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1131.951733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1131.951765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1131.951854] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1131.951885] [drm:intel_power_well_enable [i915]] enabling display
>[ 1131.951917] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1131.951953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1131.951973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1131.951993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1131.952011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1131.952029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1131.952049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1131.952075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1131.952103] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1131.952130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1131.952156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1131.952208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1131.952242] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1131.952270] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1131.954322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1131.954342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1131.954360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.954379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1131.958251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1131.958288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1131.958327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1131.961027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1131.961069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1131.964081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1131.967476] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1131.967553] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1131.967573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1131.967599] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1131.967659] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1131.967689] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1131.984369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1131.984415] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1131.984478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.017754] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.017842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.034374] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.034422] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.034520] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.051536] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.051580] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.051612] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.051651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.051684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.051719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.051749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.051787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.051826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.051871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.051914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.051955] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.051997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.052035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.052074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.052131] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.052252] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.052324] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.052369] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.052470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.052483] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.052541] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.052563] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.052589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.052618] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.052643] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.052668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.052694] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.052720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.052747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.052773] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.052798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.052804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.052829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.052834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.052860] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.052886] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.052911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.052937] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.052963] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.052988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.053015] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.053041] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.053067] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.053094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.053122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.053224] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.053254] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.053281] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.053335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.053366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.053396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.053426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.053449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.053469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.053492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.053512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.053532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.053551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.053570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.053592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.053613] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.056799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.056836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.056868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.056900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.060781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.060817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.060848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.063584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.063618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.066635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.069948] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.070015] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.070045] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.070083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.070151] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.070239] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.086808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.086857] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.086921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.120262] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.120351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.136836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.136886] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.136988] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.154009] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.154053] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.154086] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.154124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.154157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.154279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.154328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.154377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.154429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.154483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.154529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.154555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.154588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.154620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.154653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.154700] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.154738] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.154778] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.154810] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.154893] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.154908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.154983] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.155016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.155050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.155086] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.155117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.155151] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.155227] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.155265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.155302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.155336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.155368] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.155380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.155412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.155421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.155455] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.155488] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.155530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.155557] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.155590] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.155617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.155645] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.155672] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.155700] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.155733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.155767] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.155861] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.155895] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.155927] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.155981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.156014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.156046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.156077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.156109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.156141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.156202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.156235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.156266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.156294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.156321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.156357] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.156390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.158456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.158479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.158502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.158526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.162378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.162415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.162447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.165089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.165123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.168152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.171519] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.171618] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.171658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.171709] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.171812] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.171856] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.188395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.188444] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.188509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.221817] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.221905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.238428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.238474] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.238574] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.255584] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.255628] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.255660] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.255698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.255738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.255782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.255822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.255866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.255919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.255964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.256006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.256048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.256090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.256129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.256246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.256332] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.256387] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.256436] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.256471] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.256570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.256595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.256650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.256670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.256693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.256718] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.256739] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.256760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.256782] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.256802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.256822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.256840] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.256859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.256864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.256889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.256893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.256919] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.256945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.256971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.256996] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.257023] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.257048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.257074] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.257100] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.257126] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.257181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.257217] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.257307] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.257337] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.257369] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.257406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.257428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.257448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.257468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.257486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.257508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.257531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.257552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.257573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.257591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.257609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.257632] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.257653] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.260870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.260907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.260938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.260971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.264930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.264968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.264999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.267737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.267774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.270767] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.274024] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.274087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.274106] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.274137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.274262] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.274295] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.290878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.290926] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.290989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.324295] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.324381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.340905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.340957] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.341051] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.358068] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.358112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.358144] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.358267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.358314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.358367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.358410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.358455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.358500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.358553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.358602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.358652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.358700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.358741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.358784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.358867] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.358923] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.358962] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.358996] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.359103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.359121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.359244] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.359276] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.359313] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.359351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.359383] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.359417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.359450] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.359481] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.359502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.359520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.359538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.359543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.359567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.359572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.359597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.359624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.359649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.359674] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.359699] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.359724] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.359750] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.359775] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.359801] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.359828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.359855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.359919] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.359942] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.359963] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.360001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.360027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.360053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.360078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.360104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.360128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.360189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.360223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.360259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.360288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.360318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.360355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.360386] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.363581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.363621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.363659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.363699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.367629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.367667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.367698] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.370363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.370395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.373400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.376736] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.376837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.376870] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.376913] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.376991] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.377023] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.393624] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.393675] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.393740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.427025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.427114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.443654] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.443703] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.443799] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.460872] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.460916] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.460959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.461014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.461049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.461085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.461122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.461226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.461259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.461296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.461327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.461360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.461391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.461418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.461447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.461509] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.461574] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.461634] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.461687] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.461790] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.461807] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.461887] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.461917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.461950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.461987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.462016] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.462047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.462078] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.462108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.462137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.462198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.462235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.462240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.462258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.462263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.462282] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.462300] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.462319] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.462336] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.462358] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.462376] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.462394] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.462412] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.462430] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.462452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.462475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.462536] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.462559] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.462580] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.462620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.462646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.462673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.462698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.462724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.462749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.462778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.462806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.462833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.462856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.462881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.462909] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.462934] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.466117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.466169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.466193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.466218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.470088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.470125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.470238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.472918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.472953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.475921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.479246] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.479305] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.479338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.479380] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.479457] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.479497] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.496085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.496135] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.496399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.529520] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.529607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.546132] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.546210] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.546303] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.563339] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.563383] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.563415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.563454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.563487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.563521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.563552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.563590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.563630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.563674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.563716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.563758] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.563800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.563839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.563878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.563935] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.563980] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.564031] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.564069] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.564244] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.564273] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.564386] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.564421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.564456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.564494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.564525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.564549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.564570] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.564592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.564612] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.564631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.564669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.564676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.564704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.564710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.564729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.564748] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.564766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.564784] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.564805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.564823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.564841] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.564859] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.564877] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.564898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.564922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.564972] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.564995] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.565016] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.565056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.565082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.565108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.565135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.565190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.565222] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.565255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.565287] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.565318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.565345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.565371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.565403] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.565432] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.568658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.568695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.568726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.568758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.572726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.572763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.572795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.575555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.575589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.578638] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.581869] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.581906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.581930] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.581962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.582023] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.582053] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.598704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.598756] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.598827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.632088] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.632263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.648710] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.648756] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.648854] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.665875] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.665918] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.665951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.665989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.666022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.666056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.666094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.666134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.666250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.666310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.666358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.666392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.666424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.666455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.666472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.666508] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.666536] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.666564] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.666586] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.666644] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.666657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.666711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.666731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.666754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.666779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.666799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.666820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.666842] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.666862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.666882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.666911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.666940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.666947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.666966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.666971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.666989] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.667007] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.667026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.667043] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.667066] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.667083] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.667102] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.667119] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.667175] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.667206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.667239] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.667327] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.667359] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.667389] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.667437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.667458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.667477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.667497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.667515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.667540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.667568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.667596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.667624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.667649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.667675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.667702] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.667728] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.671070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.671123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.671214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.671269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.674121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.674176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.674207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.676944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.676980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.679952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.683294] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.683391] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.683431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.683482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.683582] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.683634] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.700197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.700248] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.700313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.733570] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.733667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.750203] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.750249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.750351] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.767353] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.767397] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.767429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.767468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.767507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.767551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.767591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.767630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.767669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.767713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.767755] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.767797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.767838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.767877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.767916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.767973] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.768019] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.768069] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.768108] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.768638] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.768651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.768710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.768733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.768758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.768784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.768805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.768827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.768848] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.768869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.768888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.768907] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.768926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.768931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.768948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.768953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.768979] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.769004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.769031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.769056] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.769083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.769108] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.769162] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.769192] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.769221] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.769253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.769286] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.769518] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.769538] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.769556] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.769592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.769614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.769635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.769660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.769686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.769712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.769740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.769768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.769796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.769821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.769847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.769874] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.769900] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.773100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.773138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.773232] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.773286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.776090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.776126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.776222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.778974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.779005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.782002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.785334] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.785390] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.785430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.785481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.785580] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.785632] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.802202] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.802252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.802317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.835586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.835676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.852200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.852245] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.852346] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.869358] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.869402] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.869434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.869473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.869506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.869548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.869589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.869628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.869668] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.869711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.869754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.869795] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.869837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.869876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.869914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.869971] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.870016] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.870067] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.870105] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.870532] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1132.870552] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1132.870632] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1132.870655] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1132.870679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1132.870704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1132.870725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1132.870747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1132.870769] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1132.870790] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1132.870810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1132.870829] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1132.870854] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1132.870860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.870885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1132.870890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1132.870916] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1132.870942] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1132.870968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1132.870993] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1132.871020] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1132.871046] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1132.871072] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1132.871098] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1132.871123] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1132.871181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.871216] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1132.871307] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1132.871516] [drm:intel_power_well_enable [i915]] enabling display
>[ 1132.871536] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1132.871576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.871603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.871628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.871654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.871680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.871705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.871732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.871759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.871787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.871813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.871838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.871866] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1132.871892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1132.875116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1132.875179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1132.875218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.875258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1132.879081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1132.879118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1132.879208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1132.882088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1132.882125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1132.885188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1132.888536] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1132.888626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1132.888660] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1132.888702] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1132.888798] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1132.888848] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1132.905406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.905458] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.905530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.938881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1132.955422] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1132.955471] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1132.955561] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1132.974025] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1132.974070] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1132.974103] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1132.974227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1132.974279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1132.974336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1132.974384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1132.974430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1132.974464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1132.974501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1132.974535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1132.974568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1132.974601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1132.974629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1132.974667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1132.974732] [drm:intel_power_well_disable [i915]] disabling display
>[ 1132.974761] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1132.974790] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1132.974812] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1132.975010] [drm:drm_mode_addfb2] [FB:58]
>[ 1132.975040] [drm:drm_mode_addfb2] [FB:78]
>[ 1133.004183] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1133.004287] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.004359] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1133.004426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.004438] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.004500] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.004524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.004548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.004573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.004593] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.004615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.004636] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.004656] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.004676] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.004695] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.004713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.004717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.004735] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.004738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.004757] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.004774] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.004798] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.004822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.004847] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.004871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.004896] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.004920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.004945] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.004971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.004997] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.008437] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.008458] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.008477] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.008515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.008538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.008558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.008578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.008597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.008617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.008639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.008660] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.008680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.008698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.008716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.008738] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.008758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.010838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.010860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.010878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.010898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.014831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.014868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.014900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.017634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.017656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.020699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.023988] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.024078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.024106] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.024207] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.040865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.040918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.040989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.057617] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.057705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.057807] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.057857] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.057965] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.074982] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.075019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.075058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.075091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.075214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.075265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.075315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.075366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.075426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.075477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.075528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.075577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.075624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.075669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.075753] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.075807] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.075847] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.075879] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.075976] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.075993] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.076072] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.076101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.076178] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.076218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.076250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.076285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.076318] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.076351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.076384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.076415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.076446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.076455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.076484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.076492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.076521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.076550] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.076581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.076612] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.076642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.076670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.076700] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.076729] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.076755] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.076787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.076821] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.076894] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.076925] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.076955] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.077006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.077037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.077068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.077097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.077150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.077183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.077218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.077252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.077285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.077315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.077346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.077381] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.077413] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.079474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.079494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.079512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.079536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.083408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.083449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.083489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.086179] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.086212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.089207] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.092551] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.092644] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.092683] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.092734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.109400] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.109448] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.109512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.142814] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.142902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.143005] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.143050] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.143217] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.160197] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.160235] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.160274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.160308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.160343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.160373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.160402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.160433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.160468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.160508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.160551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.160593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.160632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.160671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.160727] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.160773] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.160822] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.160858] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.160930] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.160941] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.160994] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.161014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.161036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.161062] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.161085] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.161109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.161178] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.161215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.161245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.161277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.161304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.161312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.161341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.161349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.161380] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.161407] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.161437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.161463] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.161496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.161524] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.161553] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.161580] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.161609] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.161643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.161678] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.162147] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.162179] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.162208] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.162263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.162295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.162323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.162352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.162381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.162412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.162446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.162478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.162510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.162536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.162563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.162594] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.162624] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.165825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.165852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.165878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.165905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.169812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.169850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.169882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.172540] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.172575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.175543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.178901] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.178980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.179013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.179054] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.195759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.195810] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.195875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.229188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.229286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.229388] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.229430] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.229539] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.246577] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.246615] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.246656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.246689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.246724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.246754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.246793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.246833] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.246877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.246919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.246961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.247002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.247041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.247080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.247201] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.247271] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.247341] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.247391] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.247544] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.247573] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.247705] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.247753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.247784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.247819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.247847] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.247880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.247910] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.247941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.247969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.247997] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.248023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.248030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.248056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.248063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.248091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.248143] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.248173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.248199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.248232] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.248258] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.248289] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.248316] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.248344] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.248374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.248409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.248497] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.248527] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.248557] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.248607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.248637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.248664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.248693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.248719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.248748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.248782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.248813] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.248844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.248870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.248897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.248929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.248959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.252202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.252239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.252270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.252302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.256198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.256236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.256268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.258963] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.258993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.262002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.265237] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.265270] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.265294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.265325] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.282064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.282118] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.282291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.315468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.315555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.315664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.315715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.315815] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.332851] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.332888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.332928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.332962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.332997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.333027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.333056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.333088] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.333204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.333257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.333309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.333362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.333408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.333455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.333522] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.333564] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.333610] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.333659] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.333745] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.333757] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.333811] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.333832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.333854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.333879] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.333899] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.333920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.333942] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.333962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.333981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.334000] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.334017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.334022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.334040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.334045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.334063] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.334088] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.334141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.334169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.334199] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.334226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.334254] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.334280] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.334307] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.334340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.334372] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.334462] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.334490] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.334521] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.334574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.334605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.334635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.334666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.334697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.334727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.334762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.334794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.334816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.334834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.334852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.334875] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.334896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.336936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.336957] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.336975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.336994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.339629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.339653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.339675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.342368] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.342404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.345414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.348778] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.348851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.348885] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.348921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.365628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.365679] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.365745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.399035] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.399122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.399336] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.399401] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.399516] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.416497] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.416524] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.416553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.416579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.416609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.416635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.416661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.416687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.416715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.416742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.416769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.416796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.416821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.416846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.416887] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.416918] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.416952] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.416975] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.417055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.417068] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.417207] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.417467] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.417502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.417540] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.417572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.417605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.417639] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.417672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.417703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.417733] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.417762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.417770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.417797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.417804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.417834] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.417863] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.417892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.417922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.417952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.417982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.418012] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.418041] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.418070] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.418104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.418163] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.418257] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.418500] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.418531] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.418584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.418616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.418648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.418678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.418709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.418740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.418775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.418807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.418839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.418868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.418904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.418936] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.418965] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.421047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.421068] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.421086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.421155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.425016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.425053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.425085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.427793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.427825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.430830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.434176] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.434268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.434301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.434344] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.451048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.451099] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.451274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.484472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.484560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.484666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.484707] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.484797] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.501829] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.501866] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.501905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.501939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.501974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.502013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.502053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.502092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.502214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.502274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.502330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.502384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.502615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.502644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.502694] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.502721] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.502748] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.502767] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.502828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.502840] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.502888] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.502908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.502929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.502952] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.502970] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.502989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.503019] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.503039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.503060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.503086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.503154] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.503164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.503196] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.503204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.503234] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.503265] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.503297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.503326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.503360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.503391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.503422] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.503452] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.503483] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.503517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.503552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.503895] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.503926] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.503956] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.504009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.504041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.504072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.504103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.504154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.504187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.504220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.504255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.504288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.504428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.504456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.504487] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.504517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.507758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.507795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.507827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.507858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.511837] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.511874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.511913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.514662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.514693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.517735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.521013] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.521062] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.521090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.521188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.537842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.537890] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.537954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.571251] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.571338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.571443] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.571488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.571579] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.588633] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.588670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.588709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.588743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.588777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.588807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.588835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.588866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.588901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.588933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.588964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.588995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.589023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.589050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.589173] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.589238] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.589309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.589342] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.589445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.589464] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.589550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.589579] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.589612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.589647] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.589675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.589705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.589735] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.589765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.589793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.589821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.589847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.589854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.589883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.589890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.589919] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.589945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.589974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.590000] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.590031] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.590057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.590086] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.590139] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.590166] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.590199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.590234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.590321] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.590352] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.590381] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.590431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.590462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.590489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.590519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.590546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.590576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.590609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.590640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.590672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.590698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.590725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.590755] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.590786] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.594026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.594064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.594096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.594205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.598146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.598184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.598215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.600916] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.600954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.603939] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.607252] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.607324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.607356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.607397] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.624102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.624186] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.624258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.657528] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.657632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.657736] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.657778] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.657879] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.674890] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.674928] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.674967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.675000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.675035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.675065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.675094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.675206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.675264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.675324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.675617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.675652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.675685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.675718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.675765] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.675804] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.675846] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.675876] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.675965] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.675980] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.676057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.676091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.676171] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.676224] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.676263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.676309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.676353] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.676385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.676416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.676447] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.676474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.676483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.676512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.676520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.676550] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.676808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.676838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.676864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.676896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.676923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.676953] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.676981] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.677009] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.677038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.677071] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.677335] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.677364] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.677391] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.677440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.677469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.677495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.677521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.677546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.677574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.677604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.677633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.677662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.677686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.677712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.677743] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.677769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.679854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.679876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.679895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.679914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.683846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.683883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.683915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.686656] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.686688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.689751] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.693055] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.693179] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.693231] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.693290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.709914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.709965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.710031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.743344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.743430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.743531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.743579] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.743670] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.760708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.760745] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.760784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.760818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.760853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.760883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.760913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.760944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.760979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.761011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.761042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.761073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.761162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.761215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.761294] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.761359] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.761418] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.761449] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.761537] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.761555] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.761639] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.761670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.761701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.761736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.761764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.761796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.761825] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.761855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.761883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.761911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.761936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.761943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.761969] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.761976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.762004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.762030] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.762057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.762082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.762140] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.762168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.762198] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.762225] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.762254] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.762284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.762319] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.762408] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.762438] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.762468] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.762517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.762545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.762574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.762601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.762630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.762657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.762688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.762720] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.762751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.762776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.762804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.762834] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.762864] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.764952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.764975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.764994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.765014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.768924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.768962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.768994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.771691] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.771722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.774786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.778063] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.778169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.778199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.778237] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.794949] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.794999] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.795065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.828388] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.828481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.828583] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.828630] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.828729] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.845748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.845786] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.845825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.845858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.845893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.845923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.845951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.845982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.846017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.846050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.846081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.846188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.846231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.846279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.846477] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.846505] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.846534] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.846554] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.846610] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.846621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.846674] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.846696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.846719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.846744] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.846764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.846785] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.846811] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.846837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.846864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.846890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.846915] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.846922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.846946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.846951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.846978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.847004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.847030] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.847055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.847082] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.847138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.847170] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.847199] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.847226] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.847258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.847294] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.847383] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.847585] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.847603] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.847643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.847669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.847695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.847721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.847748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.847774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.847803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.847831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.847856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.847882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.847907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.847935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.847960] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.850021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.850044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.850067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.850139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.852906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.852941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.852971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.855689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.855726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.858753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.862126] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.862190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.862223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.862266] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.878939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.878990] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.879060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.912368] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.912461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.912562] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.912604] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.912692] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1133.929697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1133.929734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1133.929776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.929828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.929869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.929900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.929939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.929978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.930023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.930065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.930173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.930220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.930259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.930300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.930591] [drm:intel_power_well_disable [i915]] disabling display
>[ 1133.930628] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1133.930669] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.930697] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1133.930784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.930799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1133.930873] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1133.930902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1133.930934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1133.930969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1133.930996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1133.931026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1133.931055] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1133.931091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1133.931158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1133.931187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1133.931214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1133.931223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.931248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1133.931256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1133.931283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1133.931309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1133.931336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1133.931363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1133.931393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1133.931419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1133.931445] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1133.931471] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1133.931497] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1133.931530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.931742] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1133.931800] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1133.931820] [drm:intel_power_well_enable [i915]] enabling display
>[ 1133.931838] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1133.931877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1133.931909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1133.931937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1133.931956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1133.931975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1133.931995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1133.932017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1133.932040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1133.932068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.932123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1133.932154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1133.932187] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1133.932215] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1133.934386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1133.934407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1133.934425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.934444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1133.937070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1133.937109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1133.937129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1133.939964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1133.940000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1133.943008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1133.946338] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1133.946426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1133.946445] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1133.946471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1133.963221] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1133.963271] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1133.963337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1133.996642] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1133.996730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1133.996832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1133.996874] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1133.996962] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.014015] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.014052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.014173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.014226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.014285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.014335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.014374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.014408] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.014444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.014477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.014510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.014540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.014570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.014599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.014675] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.014721] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.014776] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.014797] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.014862] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.014874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.014929] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.014956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.014983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.015012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.015037] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.015064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.015119] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.015150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.015180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.015208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.015235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.015243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.015269] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.015276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.015303] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.015330] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.015357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.015385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.015414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.015442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.015468] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.015495] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.015520] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.015551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.015583] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.015674] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.015705] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.015735] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.015789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.015820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.015850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.015880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.015911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.015942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.015973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.016001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.016030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.016055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.016107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.016141] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.016172] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.018233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.018254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.018272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.018291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.022172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.022213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.022252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.024949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.024987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.027987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.031274] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.031369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.031391] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.031417] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.048153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.048203] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.048295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.081556] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.081643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.081749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.081794] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.081884] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.098907] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.098945] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.098985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.099019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.099054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.099167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.099212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.099262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.099317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.099368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.099418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.099467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.099508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.099551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.099622] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.099663] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.099702] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.099733] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.099842] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.099860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.099938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.099964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.099994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.100028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.100054] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.100122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.100155] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.100186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.100215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.100245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.100272] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.100281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.100309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.100317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.100347] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.100374] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.100403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.100429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.100461] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.100488] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.100518] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.100544] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.100572] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.100605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.100638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.100725] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.100756] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.100785] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.100836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.100864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.100894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.100920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.100949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.100980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.101012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.101044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.101076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.101125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.101153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.101187] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.101216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.103281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.103301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.103320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.103339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.107207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.107244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.107276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.109961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.109995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.112996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.116319] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.116376] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.116406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.116444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.133161] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.133214] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.133285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.166588] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.166675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.166777] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.166818] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.166905] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.183905] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.183943] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.183983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.184016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.184051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.184161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.184209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.184260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.184317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.184368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.184418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.184466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.184506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.184551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.184618] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.184658] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.184697] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.184728] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.184839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.184857] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.184937] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.184964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.184994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.185027] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.185053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.185122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.185156] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.185187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.185216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.185246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.185273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.185282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.185309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.185317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.185346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.185373] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.185402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.185429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.185462] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.185489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.185519] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.185544] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.185572] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.185607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.185641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.185730] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.185760] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.185789] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.185839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.185870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.185897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.185926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.185952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.185982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.186014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.186046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.186101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.186128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.186157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.186193] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.186222] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.189412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.189442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.189467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.189493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.193372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.193409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.193442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.196122] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.196154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.199163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.202508] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.202600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.202632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.202673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.219378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.219428] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.219494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.252806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.252892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.252994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.253037] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.253438] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.269868] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.269905] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.269945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.269979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.270014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.270044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.270142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.270194] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.270246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.270301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.270348] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.270400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.270420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.270438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.270474] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.270502] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.270529] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.270549] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.270615] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.270628] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.270681] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.270701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.270725] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.270749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.270769] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.270790] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.270811] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.270831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.270850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.270868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.270886] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.270891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.270915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.270920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.270946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.270972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.270998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.271023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.271049] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.271113] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.271143] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.271172] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.271200] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.271231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.271264] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.271353] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.271379] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.271398] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.271433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.271454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.271474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.271492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.271510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.271530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.271552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.271573] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.271594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.271612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.271630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.271652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.271673] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.274871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.274908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.274939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.274972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.278834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.278870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.278902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.281636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.281667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.284679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.287942] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.288005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.288038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.288146] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.304785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.304833] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.304896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.338227] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.338316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.338407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.338457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.338551] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.355631] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.355668] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.355708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.355748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.355792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.355832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.355871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.355910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.355954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.355996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.356038] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.356159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.356207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.356256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.356343] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.356385] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.356426] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.356457] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.356565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.356584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.356668] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.356699] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.356731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.356766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.356794] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.356825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.356855] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.356885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.356914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.356943] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.356969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.356976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.357003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.357009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.357038] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.357092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.357123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.357150] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.357183] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.357211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.357242] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.357269] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.357300] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.357330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.357365] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.357455] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.357485] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.357515] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.357564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.357595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.357622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.357651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.357677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.357707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.357739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.357771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.357803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.357828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.357855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.357886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.357916] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.359997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.360018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.360036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.360055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.363939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.363980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.364019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.366710] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.366744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.369782] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.372780] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.372849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.372868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.372894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.389644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.389694] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.389764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.423115] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.423199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.423300] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.423342] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.423429] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.442003] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.442040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.442150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.442201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.442260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.442308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.442355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.442405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.442461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.442512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.442563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.442613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.442658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.442705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.442790] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.442855] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.442917] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.442968] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.443141] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.443161] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.443284] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.443315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.443347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.443380] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.443403] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.443427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.443451] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.443474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.443498] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.443518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.443541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.443546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.443569] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.443573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.443597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.443617] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.443640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.443664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.443697] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.443722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.443754] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.443773] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.443792] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.443812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.443835] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.443883] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.443900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.443916] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.443948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.443967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.443984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.444001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.444018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.444036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.444104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.444137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.444172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.444203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.444233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.444269] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.444301] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.446378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.446399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.446417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.446437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.450292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.450330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.450368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.453066] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.453127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.456133] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.459476] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.459567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.459586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.459612] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.476328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.476379] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.476449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.509736] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.509821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.509930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.509975] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.510052] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.527365] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.527402] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.527441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.527474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.527510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.527540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.527569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.527601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.527635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.527667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.527699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.527730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.527758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.527785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.527838] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.527882] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.527932] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.527967] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.528125] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.528155] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.528246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.528279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.528314] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.528351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.528384] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.528418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.528451] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.528483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.528515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.528545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.528575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.528582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.528611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.528618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.528648] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.528677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.528707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.528735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.528768] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.528797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.528827] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.528857] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.528887] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.528920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.528954] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.529045] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.529098] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.529131] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.529183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.529217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.529250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.529282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.529312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.529341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.529377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.529411] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.529444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.529475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.529506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.529540] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.529572] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.531684] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.531707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.531726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.531749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.535647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.535684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.535715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.538437] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.538473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.541481] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.544813] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.544863] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.544898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.544944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.561637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.561684] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.561748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.595070] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.595158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.595262] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.595308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.595400] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.613027] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.613099] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.613139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.613172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.613215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.613255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.613295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.613346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.613391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.613433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.613475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.613516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.613555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.613594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.613651] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.613696] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.613747] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.613782] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.613881] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.613900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.613985] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.614006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.614029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.614106] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.614141] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.614176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.614211] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.614244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.614277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.614308] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.614338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.614347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.614376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.614384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.614415] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.614446] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.614476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.614506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.614539] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.614570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.614601] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.614631] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.614662] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.614696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.614731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.615181] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.615212] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.615242] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.615298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.615331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.615363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.615394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.615422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.615454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.615488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.615521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.615554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.615583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.615612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.615646] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.615677] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.617749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.617774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.617797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.617821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.621696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.621734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.621766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.624467] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.624503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.627549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.630848] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.630937] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.630970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.631012] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.647714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.647764] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.647830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.681178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.681262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.681364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.681406] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.681483] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.698459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.698496] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.698536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.698569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.698604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.698634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.698663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.698695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.698729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.698762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.698793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.698824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.698861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.698885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.698932] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.698968] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.699005] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.699032] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.699230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.699256] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.699376] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.699420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.699467] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.699519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.699563] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.699609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.699655] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.699700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.699743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.699786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.699826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.699836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.699881] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.699888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.699916] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.699945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.699974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.700004] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.700036] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.700091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.700120] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.700151] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.700181] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.700214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.700249] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.700339] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.700370] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.700401] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.700451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.700483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.700514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.700544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.700574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.700602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.700636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.700669] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.700701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.700730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.700759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.700792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.700824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.702902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.702924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.702943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.702967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.706868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.706909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.706955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.709641] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.709677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.712686] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.715995] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.716140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.716188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.716235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.732836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.732884] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.732947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.766258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.766344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.766448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.766492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.766588] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.783609] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.783651] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.783696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.783736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.783780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.783820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.783860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.783899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.783943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.783985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.784027] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.784150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.784207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.784259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.784346] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.784672] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.784720] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.784750] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.784867] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.784884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.784958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.784978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.785000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.785023] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.785095] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.785131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.785164] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.785197] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.785230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.785261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.785292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.785301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.785330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.785338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.785368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.785622] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.785653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.785685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.785718] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.785749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.785779] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.785809] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.785838] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.785872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.785907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.786001] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.786019] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.786036] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.786126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.786160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.786191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.786223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.786253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.786452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.786473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.786492] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.786516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.786540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.786563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.786587] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.786611] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.789910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.789946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.789977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.790009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.793962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.794000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.794036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.796784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.796821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.799812] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.803092] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.803130] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.803153] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.803184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.819926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.819976] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.820042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.853331] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.853417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.853523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.853575] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.853674] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.870717] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.870755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.870795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.870829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.870871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.870912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.870951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.870990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.871034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.871167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.871225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.871280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.871328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.871375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.871462] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.871527] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.871590] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.871622] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.871725] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.871744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.871830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.871871] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.871903] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.871936] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.871965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.871995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.872025] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.872095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.872127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.872160] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.872190] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.872199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.872228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.872236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.872267] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.872298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.872325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.872355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.872389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.872419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.872451] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.872481] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.872507] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.872540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.872576] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.872665] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.872696] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.872726] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.872777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.872809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.872839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.872869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.872899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.872931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.872964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.872996] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.873029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.873082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.873113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.873149] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.873181] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.876406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.876443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.876481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.876521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.880466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.880503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.880534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.883344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.883384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.886410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.889748] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.889849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.889882] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.889924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.906625] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.906676] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.906741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.940062] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.940153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.940259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1134.940306] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1134.940393] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1134.957420] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1134.957457] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1134.957497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.957537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.957581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.957620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.957660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.957699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.957743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.957786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.957827] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.957869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.957908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.957947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.958004] [drm:intel_power_well_disable [i915]] disabling display
>[ 1134.958137] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1134.958211] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.958264] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1134.958423] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1134.958442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1134.958532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1134.958565] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1134.958600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1134.958637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1134.958668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1134.958702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1134.958736] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1134.958767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1134.958799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1134.958830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1134.958859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1134.958866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.958895] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1134.958902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1134.958932] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1134.958962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1134.958991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1134.959021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1134.959076] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1134.959107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1134.959136] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1134.959166] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1134.959197] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1134.959232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1134.959267] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1134.959358] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1134.959389] [drm:intel_power_well_enable [i915]] enabling display
>[ 1134.959420] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1134.959472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1134.959504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1134.959535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1134.959565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1134.959594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1134.959625] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1134.959659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1134.959692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1134.959724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1134.959754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1134.959784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1134.959818] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1134.959850] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1134.963137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1134.963175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1134.963206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.963238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1134.967125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1134.967165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1134.967204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1134.969830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1134.969861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1134.972848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1134.976168] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1134.976237] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1134.976277] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1134.976329] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1134.993004] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1134.993135] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1134.993209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.026426] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.026517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.026606] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.026651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.026730] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.043756] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.043798] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.043842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.043883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.043927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.043967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.044006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.044045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.044172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.044228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.044278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.044314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.044344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.044375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.044410] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.044437] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.044465] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.044485] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.044552] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.044564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.044620] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.044646] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.044673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.044703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.044727] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.044754] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.044780] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.044806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.044833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.044859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.044883] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.044890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.044914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.044920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.044946] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.044972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.044998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.045023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.045078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.045109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.045140] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.045168] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.045196] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.045228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.045260] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.045350] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.045378] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.045409] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.045462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.045495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.045525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.045556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.045585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.045617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.045651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.045684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.045717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.045747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.045776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.045804] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.045828] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.047878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.047899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.047918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.047937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.051815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.051849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.051879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.054618] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.054657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.057654] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.060885] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.060922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.060942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.060967] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.077724] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.077776] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.077843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.111155] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.111241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.111343] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.111385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.111482] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.128503] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.128541] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.128580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.128615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.128650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.128680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.128710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.128742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.128776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.128808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.128849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.128891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.128930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.128969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.129027] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.129142] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.129208] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.129254] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.129377] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.129402] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.129458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.129479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.129502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.129528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.129548] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.129569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.129591] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.129611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.129631] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.129650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.129668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.129673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.129697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.129702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.129728] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.129754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.129781] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.129807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.129833] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.129858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.129884] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.129910] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.129936] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.129963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.129996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.130107] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.130134] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.130161] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.130217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.130247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.130276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.130306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.130328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.130348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.130376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.130404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.130431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.130457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.130482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.130510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.130535] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.133746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.133784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.133815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.133847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.137792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.137829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.137860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.140620] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.140641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.143643] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.146936] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.147022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.147119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.147160] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.163804] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.163855] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.163920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.197189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.197285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.197385] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.197428] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.197526] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.214589] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.214632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.214672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.214705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.214740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.214769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.214798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.214829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.214863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.214896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.214927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.214958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.214986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.215013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.215154] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.215360] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.215390] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.215410] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.215465] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.215478] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.215532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.215554] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.215578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.215602] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.215623] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.215643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.215665] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.215685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.215705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.215724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.215742] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.215747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.215764] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.215769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.215787] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.215806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.215824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.215841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.215863] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.215881] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.215898] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.215916] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.215941] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.215968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.215996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.216097] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.216125] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.216152] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.216208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.216416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.216439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.216458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.216484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.216509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.216538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.216566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.216594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.216619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.216650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.216687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.216719] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.218767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.218800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.218819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.218838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.222780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.222817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.222848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.225570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.225602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.228750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.232105] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.232189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.232222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.232264] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.248964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.249017] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.249176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.282435] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.282529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.282634] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.282682] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.282785] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.300872] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.300909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.300949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.300982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.301017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.301129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.301299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.301348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.301388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.301423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.301454] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.301486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.301515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.301543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.301595] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.301636] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.301679] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.301711] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.301806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.301824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.301906] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.301937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.301973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.302011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.302098] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.302140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.302170] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.302199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.302228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.302254] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.302280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.302289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.302315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.302322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.302349] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.302375] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.302402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.302428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.302457] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.302483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.302509] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.302538] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.302758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.302782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.302807] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.302884] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.302902] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.302921] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.302956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.302976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.302996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.303015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.303068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.303096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.303128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.303158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.303190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.303346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.303367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.303401] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.303429] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.305471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.305499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.305517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.305537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.309451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.309486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.309522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.312284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.312316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.315333] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.318626] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.318705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.318724] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.318750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.335498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.335550] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.335616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.368929] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.369034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.369355] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.369399] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.369499] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.386552] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.386594] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.386639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.386680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.386724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.386764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.386803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.386843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.386887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.386937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.386970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.387000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.387087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.387125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.387197] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.387357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.387396] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.387424] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.387507] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.387522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.387593] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.387620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.387651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.387683] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.387710] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.387739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.387766] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.387792] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.387825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.387866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.387899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.387906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.387930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.387937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.387967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.387992] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.388018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.388069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.388101] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.388129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.388157] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.388185] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.388214] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.388245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.388277] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.388533] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.388553] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.388571] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.388608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.388633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.388660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.388686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.388711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.388737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.388765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.388793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.388822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.388848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.388874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.388900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.388926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.392088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.392125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.392157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.392190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.396077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.396122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.396141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.398848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.398890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.401919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.405318] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.405392] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.405411] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.405437] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.422184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.422234] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.422299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.455668] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.455756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.455859] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.455907] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.456010] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.472753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.472790] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.472830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.472865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.472900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.472930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.472960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.472991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.473106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.473161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.473420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.473455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.473493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.473533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.473591] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.473637] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.473687] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.473723] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.473824] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.473842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.473928] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.473951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.473975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.474000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.474052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.474084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.474115] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.474144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.474173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.474201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.474229] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.474239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.474265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.474273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.474300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.474327] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.474356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.474559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.474581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.474601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.474621] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.474640] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.474658] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.474680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.474704] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.474762] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.474782] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.474800] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.474835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.474856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.474874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.474893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.474910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.474930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.474957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.474984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.475013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.475066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.475095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.475128] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.475157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.477402] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.477424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.477442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.477462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.481303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.481338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.481369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.484090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.484126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.487134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.490392] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.490455] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.490479] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.490510] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.507245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.507296] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.507362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.540669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.540757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.540858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.540900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.540999] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.558106] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.558142] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.558183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.558216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.558252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.558282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.558312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.558343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.558378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.558411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.558451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.558494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.558533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.558572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.558629] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.558674] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.558724] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.558759] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.558858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.558876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.558949] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.558970] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.558991] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.559082] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.559111] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.559142] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.559173] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.559202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.559231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.559258] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.559286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.559294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.559320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.559327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.559354] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.559382] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.559408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.559438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.559471] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.559500] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.559527] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.559553] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.559579] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.559612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.559641] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.559701] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.559720] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.559737] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.559771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.559792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.559811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.559830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.559848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.559867] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.559894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.559922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.559949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.559975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.560000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.560054] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.560084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.563281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.563318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.563350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.563382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.567287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.567324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.567356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.570092] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.570128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.573136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.576426] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.576507] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.576526] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.576552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.593289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.593337] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.593401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.626732] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.626819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.626923] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.626972] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.627143] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.644352] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.644389] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.644429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.644463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.644498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.644529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.644559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.644591] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.644626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.644659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.644699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.644748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.644776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.644801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.644849] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.644885] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.644923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.644950] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.645113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.645491] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.645613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.645655] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.645702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.645760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.645789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.645821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.645850] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.645880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.645908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.645937] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.645962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.645970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.645996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.646029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.646059] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.646085] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.646115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.646142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.646174] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.646202] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.646233] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.646260] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.646290] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.646325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.646359] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.646668] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.646696] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.646723] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.646771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.646800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.646826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.646852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.646877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.646904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.646934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.646963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.646992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.647056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.647086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.647120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.647149] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.650539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.650572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.650600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.650628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.654602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.654639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.654671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.657335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.657371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.660373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.663717] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.663812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.663844] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.663894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.680595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.680647] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.680713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.714111] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.714195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.714290] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.714332] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.714431] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.731464] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.731501] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.731541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.731574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.731608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.731638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.731667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.731699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.731734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.731766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.731797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.731837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.731883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.731917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.731968] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.732009] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.732123] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.732165] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.732520] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.732538] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.732616] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.732647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.732681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.732715] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.732742] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.732773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.732803] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.732833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.732860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.732896] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.732914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.732920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.732937] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.732941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.732961] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.732978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.732996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.733052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.733083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.733111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.733138] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.733164] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.733190] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.733221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.733253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.733484] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.733503] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.733521] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.733558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.733579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.733599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.733618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.733637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.733657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.733679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.733700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.733721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.733739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.733758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.733784] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.733810] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.736965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.737006] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.737095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.737146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.739942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.739975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.740008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.742889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.742926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.745915] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.749286] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.749335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.749358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.749389] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.766127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.766177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.766244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.799560] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.799645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.799747] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.799789] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.799899] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.816944] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.816982] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.817115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.817170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.817398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.817431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.817463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.817495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.817532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.817565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.817597] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.817627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.817666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.817703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.817735] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.817760] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.817785] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.817806] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.817860] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.817871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.817925] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.817959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.817984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.818065] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.818098] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.818134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.818168] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.818201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.818233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.818264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.818294] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.818303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.818332] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.818340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.818371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.818401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.818433] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.818463] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.818496] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.818785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.818817] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.818849] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.818880] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.818912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.818948] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.819062] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.819198] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.819225] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.819274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.819303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.819332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.819360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.819387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.819416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.819447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.819477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.819507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.819534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.819561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.819592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.819621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.822849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.822890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.822929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.822970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.826929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.826963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.826996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.829725] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.829763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.832754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.836083] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.836123] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.836142] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.836168] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.852914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.852965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.853118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.886313] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.886398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.886502] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.886546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.886637] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.903673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.903711] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.903751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.903785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.903828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.903868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.903908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.903947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.903991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.904114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.904174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.904231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.904280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.904330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.904699] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.904725] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.904753] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.904771] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.904823] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.904834] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.904883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.904903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.904926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.904953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.904976] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.905049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.905082] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.905116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.905150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.905181] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.905211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.905220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.905249] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.905257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.905287] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.905317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.905348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.905373] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.905642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.905675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.905706] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.905738] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.905769] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.905803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.905838] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.905927] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.905958] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.905989] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.906069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.906103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.906135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.906167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.906197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.906229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.906264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.906473] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.906493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.906511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.906533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.906558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.906582] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.908760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.908782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.908800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.908819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.912696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.912733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.912756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.915459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.915497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1135.918558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1135.921883] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1135.921927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1135.921947] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1135.921972] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1135.938729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.938780] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.938845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.972123] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.972218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.972321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1135.972363] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1135.972462] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1135.989530] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1135.989568] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1135.989606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.989640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.989675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.989705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.989743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.989783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1135.989827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.989870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.989912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.989953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.989992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.990099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.990186] [drm:intel_power_well_disable [i915]] disabling display
>[ 1135.990447] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1135.990479] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1135.990501] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1135.990563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1135.990575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1135.990631] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1135.990653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1135.990679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1135.990708] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1135.990733] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1135.990760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1135.990786] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1135.990812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1135.990838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1135.990864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1135.990889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1135.990895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.990920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1135.990925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1135.990951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1135.990977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1135.991031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1135.991062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1135.991093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1135.991122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1135.991151] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1135.991179] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1135.991205] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1135.991235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1135.991268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1135.991522] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1135.991541] [drm:intel_power_well_enable [i915]] enabling display
>[ 1135.991559] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1135.991595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1135.991616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1135.991636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1135.991661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1135.991687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1135.991713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1135.991740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1135.991768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1135.991796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1135.991822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1135.991849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1135.991876] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1135.991902] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1135.993948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1135.993969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1135.993988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.994054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1135.996856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1135.996894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1135.996925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1135.999631] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1135.999665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.002705] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.006003] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1136.006088] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.006117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1136.006155] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.022872] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.022923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.022989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.056269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.056355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.056461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1136.056512] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.056593] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1136.074949] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1136.074987] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.075117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.075308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.075346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.075378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.075409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.075441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.075477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.075510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.075542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.075572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.075600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.075627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.075678] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.075718] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.075759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.075790] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.075884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.075902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.075982] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.076079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.076131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.076193] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.076241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.076275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.076308] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1136.076340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1136.076372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.076404] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.076434] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.076443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.076471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.076479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.076510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.076540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.076571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.076601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.076634] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.076931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.076964] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1136.076996] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1136.077051] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1136.077087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.077123] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1136.077311] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.077339] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.077367] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.077415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.077445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.077474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.077502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.077529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.077558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.077590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.077621] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.077651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.077678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.077704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.077736] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1136.077765] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.079834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.079855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.079878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.079902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.083810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.083847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.083885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.086590] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.086625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.089708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.093038] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1136.093093] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.093126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1136.093168] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.109881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.109933] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.110005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.143277] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.143363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.143467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1136.143511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.143608] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1136.160654] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1136.160691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.160731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.160771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.160815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.160856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.160895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.160935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.160979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.161096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.161154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.161210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.161258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.161289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.161563] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.161588] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.161626] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.161647] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.161717] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.161727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.161777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.161797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.161818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.161840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.161859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.161878] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.161898] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1136.161916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1136.161934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.161951] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.161967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.162011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.162042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.162051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.162079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.162109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.162136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.162165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.162195] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.162224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.162251] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1136.162280] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1136.162307] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1136.162339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.162374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1136.162737] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.162767] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.162796] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.162847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.162876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.162906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.162933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.162962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.162990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.163045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.163079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.163111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.163139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.163168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.163203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1136.163427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.166643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.166680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.166712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.166744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.170695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.170732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.170763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.173477] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.173517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.176557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.179810] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1136.179877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.179897] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1136.179922] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.196679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.196732] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.196805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.230118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.230207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.230292] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1136.230334] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.230425] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1136.247447] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1136.247485] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.247525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.247559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.247594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.247625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.247663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.247703] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.247747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.247789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.247831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.247873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.247912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.247950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.248083] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.248148] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.248208] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.248240] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.248344] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.248363] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.248450] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.248480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.248514] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.248550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.248578] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.248610] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.248639] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1136.248671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1136.248698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.248728] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.248754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.248761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.248788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.248795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.248824] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.248850] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.248878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.248903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.248934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.248960] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.249014] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1136.249042] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1136.249072] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1136.249106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.249142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1136.249230] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.249260] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.249290] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.249341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.249369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.249399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.249426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.249454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.249486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.249519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.249552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.249583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.249609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.249637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.249671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1136.249699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.252930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.252966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.253073] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.253112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.256958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.256994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.257093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.259862] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.259902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.262872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.266243] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1136.266308] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.266341] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1136.266396] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.283083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.283134] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.283204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.316491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.316579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.316686] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1136.316737] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.316837] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1136.333903] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1136.333940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.333981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.334101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.334159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.334209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.334257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.334299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.334343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.334372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.334399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.334426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.334450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.334473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.334519] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.334554] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.334590] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.334617] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.334703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.334718] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.334787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.334813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.334843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.334875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.334901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.334929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.334956] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1136.334984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1136.335053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.335091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.335129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.335141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.335175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.335185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.335221] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.335256] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.335292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.335326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.335367] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.335393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.335419] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1136.335445] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1136.335472] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1136.335503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.335535] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1136.335626] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.335657] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.335687] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.335740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.335772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.335803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.335834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.335864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.335895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.335922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.335943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.335963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.336013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.336040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.336072] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1136.336101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.339281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.339308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.339330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.339352] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.343262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.343298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.343329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.345984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.346039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.349046] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.352374] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1136.352430] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.352462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1136.352504] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.369206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.369257] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.369328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.402706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.402795] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1136.402847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.402940] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1136.421554] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1136.421592] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.421632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.421666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.421701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.421730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.421758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.421790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.421825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.421858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.421890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.421922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.421949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.421977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.422103] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.422167] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.422208] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1136.422241] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.422559] [drm:drm_mode_addfb2] [FB:58]
>[ 1136.422593] [drm:drm_mode_addfb2] [FB:78]
>[ 1136.453467] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1136.453561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1136.453624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.453683] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.453695] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.453753] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.453778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.453803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.453829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.453852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.453877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.453900] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1136.453924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1136.453947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.453974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.454045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.454056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.454087] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.454094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.454123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.454154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.454181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.454211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.454242] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.454271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.454298] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1136.454329] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1136.454356] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1136.454389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.454425] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1136.457853] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.457875] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.457893] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.457931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.457953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.457984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.458060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.458088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.458119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.458153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.458185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.458216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.458244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.458270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.458303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1136.458332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.460408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.460429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.460448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.460467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.464360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.464400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.464439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.467138] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.467170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.470214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.473529] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1136.473595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.473624] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1136.473662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.490380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.490431] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.490498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.507118] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.507207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.507309] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1136.507355] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.507434] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1136.524156] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1136.524194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.524233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.524267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.524303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.524333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.524362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.524394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.524437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.524479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.524521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.524563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.524601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.524640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.524698] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.524743] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.524794] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.524829] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.524928] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.524947] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.525134] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.525185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.525238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.525298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.525343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.525400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.525440] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1136.525479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1136.525516] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.525555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.525589] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.525599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.525633] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.525642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.525679] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.525713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.525750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.525783] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.525824] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.525857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.525895] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1136.525929] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1136.525965] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1136.526043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.526089] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1136.526207] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.526246] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.526285] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.526350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.526388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.526426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.526468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.526499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.526529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.526565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.526600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.526635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.526663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.526693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.526726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1136.526759] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.529978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.530048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.530080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.530112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.534049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.534087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.534118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.536805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.536843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.539840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.542652] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1136.542729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.542749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1136.542780] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.559493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.559542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.559606] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.592886] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.592969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.593181] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1136.593247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.593356] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1136.611936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1136.611978] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.612100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.612158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.612212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.612255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.612301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.612345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.612398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.612448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.612491] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.612522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.612548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.612576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.612632] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.612673] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.612714] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.612746] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.612846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.612862] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.612916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.612936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.612959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.613037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.613065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.613097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.613126] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1136.613158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1136.613185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.613214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.613240] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.613247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.613274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.613280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.613309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.613335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.613363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.613390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.613422] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.613448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.613477] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1136.613502] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1136.613530] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1136.613559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.613592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1136.613680] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.613710] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.613739] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.613789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.613819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.613847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.613875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.613901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.613930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.613964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.614015] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.614047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.614073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.614101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.614132] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1136.614162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.616232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.616256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.616279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.616303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.620179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.620216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.620247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.622907] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.622939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.625964] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.629336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1136.629419] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.629452] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1136.629493] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.646197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.646248] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.646315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.679600] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.679691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.679779] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1136.679824] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.679921] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1136.696938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1136.696975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.697097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.697143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.697197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.697241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.697286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.697330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.697385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.697430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.697475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.697519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.697555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.697592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.697663] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.697719] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.697772] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.697815] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.697994] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.698020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.698140] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.698170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.698206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.698257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.698287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.698317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.698346] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1136.698382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1136.698408] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.698433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.698458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.698463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.698488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.698492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.698518] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.698541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.698566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.698591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.698617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.698641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.698666] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1136.698692] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1136.698717] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1136.698744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.698771] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1136.698833] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.698855] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.698877] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.698916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.698941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.698967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.699023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.699057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.699088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.699124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.699159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.699193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.699220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.699250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.699286] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1136.699316] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.701389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.701410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.701428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.701448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.705297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.705335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.705367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.708107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.708146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.711136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.714452] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1136.714521] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.714553] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1136.714595] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.731303] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.731354] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.731421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.764690] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.764777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.764882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1136.764926] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.765093] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1136.782122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1136.782160] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.782199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.782233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.782268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.782298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.782327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.782359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.782393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.782425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.782465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.782508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.782547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.782586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.782643] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.782688] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.782738] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.782774] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.782877] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.782895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.783078] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.783134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.783192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.783249] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.783282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.783317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.783350] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1136.783384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1136.783417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.783448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.783478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.783487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.783516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.783525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.783554] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.783584] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.783614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.783643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.783677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.783706] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.783736] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1136.783765] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1136.783793] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1136.783827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.783862] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1136.783953] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.784006] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.784039] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.784092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.784124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.784152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.784183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.784212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.784244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.784278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.784311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.784344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.784373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.784403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.784437] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1136.784469] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.786566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.786586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.786608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.786633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.790541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.790580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.790619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.793428] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.793460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.796534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.799836] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1136.799917] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.799946] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1136.800053] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.816697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.816748] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.816814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.850091] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.850179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.850284] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1136.850333] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.850414] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1136.868918] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1136.868955] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.869085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.869139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.869195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.869243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.869297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.869343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.869398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.869447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.869496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.869545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.869585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.869628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.869707] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.869769] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.869827] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.869873] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.870066] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.870090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.870172] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.870204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.870238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.870279] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.870298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.870320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.870348] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1136.870366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1136.870384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.870401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.870418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.870422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.870438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.870442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.870458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.870475] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.870491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.870507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.870526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.870542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.870559] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1136.870575] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1136.870590] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1136.870610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.870631] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1136.870687] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.870704] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.870720] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.870753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.870777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.870801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.870824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.870848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.870871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.870896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.870921] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.870946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.871017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.871049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.871087] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1136.871120] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.874314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.874352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.874384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.874416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.878312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.878349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.878380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.881120] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.881158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.884210] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.887560] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1136.887631] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.887650] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1136.887676] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.904427] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.904478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.904545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.937856] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.937941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.938154] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1136.938221] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1136.938331] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1136.955368] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1136.955406] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1136.955446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.955479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.955513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.955543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.955572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.955603] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.955638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.955679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.955721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.955763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.955802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.955841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.955898] [drm:intel_power_well_disable [i915]] disabling display
>[ 1136.955944] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1136.956066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.956100] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1136.956188] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1136.956206] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1136.956293] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1136.956323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1136.956356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1136.956392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1136.956420] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1136.956451] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1136.956481] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1136.956510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1136.956538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1136.956567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1136.956592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1136.956600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.956626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1136.956633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1136.956661] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1136.956687] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1136.956715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1136.956740] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1136.956771] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1136.956797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1136.956825] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1136.956851] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1136.956878] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1136.956907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1136.956940] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1136.957051] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1136.957082] [drm:intel_power_well_enable [i915]] enabling display
>[ 1136.957112] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1136.957164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1136.957196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1136.957223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1136.957252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1136.957278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1136.957307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1136.957340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1136.957373] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1136.957404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1136.957430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1136.957458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1136.957489] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1136.957519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1136.960740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1136.960778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1136.960810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.960843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1136.964741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1136.964778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1136.964810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1136.967491] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1136.967524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1136.970528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1136.973837] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1136.973915] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1136.973947] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1136.974070] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1136.990695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1136.990746] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1136.990813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.024092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.024179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.024284] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.024329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.024405] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.042661] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.042699] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.042739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.042772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.042807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.042838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.042867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.042899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.042934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.043041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.043092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.043144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.043186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.043229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.043305] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.043347] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.043390] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.043422] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.043508] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.043526] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.043607] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.043640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.043679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.043724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.043764] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.043806] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.043847] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.043888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.043910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.043930] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.043979] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.043988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.044015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.044022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.044050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.044077] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.044103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.044130] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.044161] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.044187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.044214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.044240] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.044267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.044297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.044330] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.044413] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.044433] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.044451] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.044486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.044506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.044525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.044543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.044562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.044581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.044603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.044623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.044643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.044668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.044694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.044726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.044758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.047923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.047958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.048049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.048103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.052021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.052067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.052090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.054803] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.054842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.057843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.061208] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.061265] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.061284] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.061310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.078058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.078110] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.078175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.111461] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.111558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.111660] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.111710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.111802] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.128813] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.128851] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.128890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.128924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.129039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.129087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.129136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.129181] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.129236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.129290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.129341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.129393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.129435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.129479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.129563] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.129628] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.129670] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.129701] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.129812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.129829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.129909] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.129936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.130007] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.130047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.130075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.130110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.130141] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.130173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.130202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.130233] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.130263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.130271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.130300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.130306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.130335] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.130361] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.130390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.130415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.130446] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.130471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.130499] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.130525] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.130553] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.130581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.130614] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.130703] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.130733] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.130762] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.130812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.130842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.130869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.130897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.130923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.130976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.131009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.131043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.131075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.131102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.131131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.131165] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.131194] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.134363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.134392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.134418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.134446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.138382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.138419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.138450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.141127] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.141161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.144151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.147474] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.147535] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.147568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.147610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.164314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.164365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.164431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.197716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.197803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.197911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.197956] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.198128] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.215153] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.215194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.215239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.215279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.215323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.215363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.215402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.215441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.215485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.215528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.215574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.215607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.215635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.215660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.215708] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.215745] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.215783] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.215810] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.215898] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.215915] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.216081] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.216123] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.216469] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.216519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.216568] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.216601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.216631] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.216661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.216690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.216719] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.216744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.216752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.216778] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.216785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.216814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.216840] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.216867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.216892] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.216924] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.216975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.217006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.217032] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.217061] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.217096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.217131] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.217495] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.217523] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.217551] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.217600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.217629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.217655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.217682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.217706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.217734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.217764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.217794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.217823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.217847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.217872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.217904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.217930] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.220029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.220050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.220069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.220088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.224021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.224058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.224090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.226800] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.226834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.229850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.233187] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.233280] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.233307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.233342] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.250062] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.250116] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.250188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.283472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.283560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.283664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.283710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.283788] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.300806] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.300848] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.300908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.300948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.301073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.301113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.301144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.301179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.301225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.301266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.301310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.301359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.301380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.301400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.301436] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.301463] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.301492] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.301512] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.301578] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.301590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.301644] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.301665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.301688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.301713] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.301733] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.301759] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.301785] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.301811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.301838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.301864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.301889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.301895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.301920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.301948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.301983] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.302013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.302042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.302069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.302100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.302127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.302155] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.302181] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.302208] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.302240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.302272] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.302362] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.302390] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.302408] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.302443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.302463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.302483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.302501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.302526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.302552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.302580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.302608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.302636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.302662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.302687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.302714] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.302741] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.304792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.304814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.304836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.304861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.307527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.307563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.307594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.310281] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.310320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.313320] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.316660] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.316741] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.316761] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.316786] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.333536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.333590] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.333662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.366987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.367075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.367162] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.367204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.367314] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.384338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.384376] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.384415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.384448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.384483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.384513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.384542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.384573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.384608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.384640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.384671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.384712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.384752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.384791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.384848] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.384893] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.384944] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.385060] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.385178] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.385198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.385289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.385321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.385346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.385372] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.385393] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.385414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.385437] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.385458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.385484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.385509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.385535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.385541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.385566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.385571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.385603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.385633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.385654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.385672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.385694] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.385719] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.385745] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.385771] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.385796] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.385824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.385852] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.385906] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.385927] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.385977] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.386032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.386064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.386093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.386121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.386148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.386178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.386210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.386241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.386272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.386299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.386325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.386359] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.386390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.389618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.389656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.389694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.389735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.393632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.393671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.393710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.396429] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.396466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.399689] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.403016] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.403073] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.403107] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.403150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.419852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.419906] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.420069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.453275] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.453363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.453468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.453515] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.453597] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.470654] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.470692] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.470731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.470764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.470799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.470829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.470858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.470889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.470924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.471041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.471096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.471142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.471173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.471204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.471259] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.471301] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.471341] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.471373] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.471491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.471510] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.471596] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.471627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.471669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.471704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.471733] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.471764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.471794] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.471823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.471852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.471880] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.471907] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.471914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.471980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.471990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.472022] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.472053] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.472084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.472113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.472147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.472177] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.472208] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.472235] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.472267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.472301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.472336] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.472427] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.472457] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.472488] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.472539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.472571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.472601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.472631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.472661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.472691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.472725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.472758] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.472790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.472819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.472847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.472881] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.472912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.476102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.476126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.476146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.476167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.480015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.480052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.480085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.482681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.482713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.485729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.489076] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.489167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.489200] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.489242] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.505944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.506026] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.506094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.539350] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.539436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.539541] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.539586] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.539664] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.556719] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.556756] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.556795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.556829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.556864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.556895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.556933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.557068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.557124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.557175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.557222] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.557271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.557314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.557356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.557436] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.557496] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.557555] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.557602] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.557752] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.557777] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.557902] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.557948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.558046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.558100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.558133] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.558167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.558202] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.558235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.558269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.558299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.558330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.558337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.558366] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.558374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.558404] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.558434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.558464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.558490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.558522] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.558551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.558582] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.558608] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.558637] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.558671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.558706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.558796] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.558827] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.558857] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.558908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.558967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.558999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.559032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.559062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.559095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.559131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.559165] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.559198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.559228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.559259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.559292] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.559325] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.562570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.562607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.562638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.562671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.566624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.566662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.566693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.569390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.569423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.572507] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.575833] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.575891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.575921] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.576050] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.592670] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.592723] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.592795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.626082] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.626290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.626389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.626434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.626514] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.643535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.643573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.643613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.643647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.643682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.643712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.643742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.643774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.643809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.643841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.643873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.643905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.644000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.644049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.644122] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.644364] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.644413] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.644443] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.644525] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.644543] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.644623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.644653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.644684] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.644718] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.644747] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.644777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.644808] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.644837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.644866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.644893] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.644920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.644977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.645005] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.645015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.645045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.645075] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.645105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.645136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.645170] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.645200] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.645231] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.645262] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.645292] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.645327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.645362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.645640] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.645659] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.645676] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.645713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.645735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.645755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.645774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.645792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.645812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.645839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.645866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.645894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.645919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.645977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.646012] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.646046] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.648281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.648302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.648321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.648340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.651021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.651049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.651071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.653744] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.653780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.656766] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.660095] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.660150] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.660183] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.660224] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.676927] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.677012] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.677085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.710304] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.710396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.710500] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.710543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.710641] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.727636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.727673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.727713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.727746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.727781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.727811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.727849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.727889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.727933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.728062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.728106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.728137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.728163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.728188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.728236] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.728273] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.728312] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.728340] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.728416] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.728433] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.728507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.728543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.728580] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.728621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.728656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.728693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.728729] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.728765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.728801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.728836] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.728870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.728878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.728913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.728958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.729011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.729045] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.729078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.729110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.729144] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.729179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.729212] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.729243] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.729274] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.729310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.729347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.729449] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.729475] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.729496] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.729539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.729569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.729598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.729627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.729656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.729685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.729717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.729748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.729780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.729809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.729839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.729869] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.729898] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.732025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.732049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.732072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.732097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.734792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.734826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.734856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.737584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.737621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.740600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.743899] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.743986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.744019] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.744061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.760754] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.760808] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.760880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.794141] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.794228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.794334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.794384] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.794467] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.811520] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.811557] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.811597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.811637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.811681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.811721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.811760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.811799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.811843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.811885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.811927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.812048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.812096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.812138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.812212] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.812267] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.812321] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.812363] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.812490] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.812514] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.812627] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.812669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.812714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.812762] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.812802] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.812845] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.812888] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.812930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.813010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.813040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.813071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.813080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.813110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.813118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.813149] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.813180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.813211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.813241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.813275] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.813306] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.813338] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.813368] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.813397] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.813428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.813463] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.813549] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.813580] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.813611] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.813661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.813694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.813726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.813756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.813786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.813818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.813851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.813884] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.813917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.813970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.813999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.814035] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.814067] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.816132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.816152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.816175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.816199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.820029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.820067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.820105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.822829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.822871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.825879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.829233] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.829300] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.829320] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.829346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.846096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.846148] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.846214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.879509] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.879596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.879700] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.879744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.879821] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.896850] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.896888] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.896927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.897056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.897115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.897357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.897390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.897422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.897459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.897492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.897522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.897553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.897581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.897608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.897660] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.897700] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.897741] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.897772] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.897873] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.897884] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.897998] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.898031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.898067] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.898105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.898136] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.898390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.898423] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.898455] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.898487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.898517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.898546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.898554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.898583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.898590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.898619] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.898649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.898678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.898707] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.898737] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.898767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.898796] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.898827] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.898857] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.898890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.898948] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.899243] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.899272] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.899300] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.899348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.899378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.899407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.899434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.899462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.899491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.899522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.899552] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.899581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.899608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.899634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.899666] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.899695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.901767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.901788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.901807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.901825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.905729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.905770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.905810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.908487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.908523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.911509] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1137.914211] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1137.914273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1137.914293] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1137.914318] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1137.931047] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.931096] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.931160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.964452] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.964535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.964640] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1137.964683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1137.964773] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1137.982636] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1137.982674] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1137.982714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.982747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.982790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.982830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.982870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.982909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1137.983016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.983068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.983122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.983171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.983218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.983252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.983305] [drm:intel_power_well_disable [i915]] disabling display
>[ 1137.983347] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1137.983396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1137.983434] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1137.983535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1137.983553] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1137.983637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1137.983670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1137.983706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1137.983744] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1137.983775] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1137.983808] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1137.983848] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1137.983868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1137.983893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1137.983944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1137.983972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1137.983980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.984007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1137.984015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1137.984043] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1137.984070] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1137.984097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1137.984124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1137.984154] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1137.984181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1137.984208] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1137.984235] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1137.984262] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1137.984295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1137.984327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1137.984417] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1137.984446] [drm:intel_power_well_enable [i915]] enabling display
>[ 1137.984465] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1137.984503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1137.984529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1137.984555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1137.984581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1137.984606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1137.984632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1137.984660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1137.984688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1137.984716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1137.984742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1137.984768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1137.984795] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1137.984821] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1137.988012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1137.988050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1137.988088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.988128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1137.992015] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1137.992037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1137.992056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1137.994769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1137.994807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1137.997817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.001222] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.001297] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.001323] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.001357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.018100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.018149] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.018219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.051491] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.051578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.051680] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.051721] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.051810] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.068831] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.068874] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.068918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.069041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.069097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.069145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.069195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.069233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.069271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.069306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.069337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.069369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.069397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.069425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.069478] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.069519] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.069562] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.069593] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.069696] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.069708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.069760] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.069780] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.069802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.069827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.069848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.069868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.069889] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.069939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.069969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.069996] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.070023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.070031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.070057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.070065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.070093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.070120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.070147] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.070173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.070203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.070229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.070255] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.070281] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.070306] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.070336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.070368] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.070458] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.070489] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.070519] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.070571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.070603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.070634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.070665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.070695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.070725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.070759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.070787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.070809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.070827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.070846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.070868] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.070890] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.074092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.074128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.074159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.074190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.077984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.078019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.078049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.080748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.080785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.083807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.087132] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.087177] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.087197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.087223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.103974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.104025] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.104092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.137355] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.137446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.137554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.137598] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.137697] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.155895] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.155967] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.156007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.156041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.156076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.156106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.156135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.156166] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.156201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.156233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.156264] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.156295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.156322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.156349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.156403] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.156443] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.156484] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.156515] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.156615] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.156633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.156715] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.156733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.156754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.156776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.156794] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.156813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.156832] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.156851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.156869] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.156891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.156957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.156969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.156999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.157007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.157038] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.157066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.157095] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.157122] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.157155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.157181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.157212] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.157239] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.157268] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.157302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.157336] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.157410] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.157441] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.157472] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.157522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.157549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.157578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.157604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.157632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.157660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.157692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.157723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.157754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.157780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.157808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.157838] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.157868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.159959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.159980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.159999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.160018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.163847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.163879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.163905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.166633] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.166669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.169657] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.173010] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.173087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.173114] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.173148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.189872] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.190004] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.190105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.223288] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.223374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.223479] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.223524] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.223604] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.240627] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.240665] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.240708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.240749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.240793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.240833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.240873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.240912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.241039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.241098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.241153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.241204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.241246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.241291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.241370] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.241433] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.241496] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.241545] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.241664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.241682] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.241769] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.241798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.241831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.241868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.241896] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.241953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.241985] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.242018] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.242047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.242078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.242104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.242113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.242141] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.242149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.242179] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.242206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.242236] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.242263] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.242294] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.242320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.242349] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.242375] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.242402] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.242434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.242468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.242557] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.242589] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.242615] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.242669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.242697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.242726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.242753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.242781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.242808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.242840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.242872] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.242904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.242954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.242980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.243015] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.243044] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.246263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.246301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.246333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.246365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.250253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.250291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.250324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.252994] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.253027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.256026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.259357] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.259410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.259441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.259481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.276193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.276247] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.276320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.309598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.309683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.309786] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.309830] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.309907] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.327001] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.327051] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.327090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.327123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.327158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.327188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.327217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.327248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.327283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.327315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.327346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.327377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.327404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.327432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.327492] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.327526] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.327560] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.327585] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.327656] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.327671] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.327738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.327764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.327793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.327825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.327851] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.327879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.327972] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.328012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.328055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.328091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.328129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.328140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.328178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.328188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.328227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.328262] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.328300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.328334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.328377] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.328411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.328450] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.328494] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.328524] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.328558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.328592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.328680] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.328711] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.328741] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.328790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.328819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.328847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.328874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.328902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.328954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.328988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.329020] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.329053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.329080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.329107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.329138] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.329169] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.332340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.332366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.332388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.332410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.336305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.336340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.336370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.339029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.339063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.342084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.345429] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.345523] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.345555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.345597] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.362301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.362353] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.362420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.395693] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.395779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.395883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.396006] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.396264] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.413312] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.413357] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.413397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.413431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.413466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.413497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.413525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.413556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.413591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.413623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.413663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.413706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.413745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.413784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.413842] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.413888] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.414029] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.414082] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.414216] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.414243] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.414375] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.414445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.414478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.414512] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.414540] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.414571] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.414601] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.414629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.414658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.414686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.414713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.414719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.414745] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.414751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.414778] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.414805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.414832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.414859] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.414886] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.414950] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.414979] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.415010] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.415040] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.415073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.415109] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.415198] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.415229] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.415259] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.415311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.415342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.415381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.415409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.415437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.415466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.415498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.415529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.415560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.415587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.415614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.415645] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.415673] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.417741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.417762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.417780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.417798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.420458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.420479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.420512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.423332] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.423371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.426376] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.429709] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.429747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.429766] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.429792] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.446542] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.446594] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.446661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.479958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.480044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.480152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.480203] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.480286] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.497307] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.497345] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.497384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.497425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.497469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.497508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.497547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.497586] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.497630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.497672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.497714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.497756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.497794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.497833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.497890] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.498033] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.498103] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.498156] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.498306] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.498335] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.498434] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.498467] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.498501] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.498538] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.498569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.498602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.498635] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.498667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.498699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.498729] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.498758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.498765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.498793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.498800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.498830] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.498860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.498890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.498942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.498977] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.499009] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.499040] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.499070] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.499100] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.499135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.499171] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.499263] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.499294] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.499325] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.499378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.499409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.499440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.499471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.499501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.499532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.499567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.499600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.499633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.499662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.499691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.499725] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.499756] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.504140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.504181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.504220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.504261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.508167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.508205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.508236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.510879] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.510936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.513963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.517317] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.517403] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.517443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.517495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.534196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.534244] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.534314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.567598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.567684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.567785] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.567827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.567987] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.584694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.584732] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.584771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.584804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.584838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.584868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.584982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.585029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.585086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.585352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.585378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.585403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.585426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.585450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.585484] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.585512] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.585542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.585563] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.585627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.585638] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.585693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.585717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.585741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.585767] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.585790] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.585814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.585838] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.585861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.585885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.585956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.585992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.586000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.586031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.586039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.586071] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.586099] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.586129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.586156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.586189] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.586216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.586245] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.586272] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.586301] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.586336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.586371] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.586770] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.586800] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.586829] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.586881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.586936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.586969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.586998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.587029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.587058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.587092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.587239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.587278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.587303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.587328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.587360] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.587386] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.590619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.590656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.590687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.590719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.594661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.594699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.594730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.597459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.597481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.600500] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.603746] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.603818] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.603838] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.603864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.620612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.620662] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.620729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.654016] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.654103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.654209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.654254] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.654332] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.671356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.671393] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.671433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.671466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.671501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.671531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.671561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.671599] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.671643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.671685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.671728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.671770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.671809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.671847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.671970] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.672038] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.672095] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.672127] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.672228] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.672247] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.672334] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.672364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.672397] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.672433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.672462] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.672494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.672523] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.672553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.672581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.672609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.672635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.672642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.672668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.672675] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.672704] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.672730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.672758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.672784] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.672815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.672840] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.672868] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.672919] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.672949] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.672980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.673015] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.673103] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.673133] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.673163] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.673213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.673243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.673270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.673299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.673325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.673356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.673388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.673420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.673451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.673477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.673505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.673535] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.673566] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.676749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.676784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.676814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.676844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.679629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.679670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.679708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.682457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.682491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.685558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.688887] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.688997] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.689030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.689073] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.705748] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.705800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.705871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.739180] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.739267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.739372] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.739416] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.739492] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.756548] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.756585] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.756625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.756659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.756693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.756723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.756751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.756783] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.756817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.756849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.756879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.756989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.757031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.757063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.757118] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.757159] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.757198] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.757230] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.757335] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.757354] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.757439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.757471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.757503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.757539] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.757567] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.757598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.757628] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.757657] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.757685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.757713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.757741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.757748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.757774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.757781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.757810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.757835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.757864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.757915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.757948] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.757975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.758006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.758034] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.758063] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.758096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.758131] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.758220] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.758251] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.758280] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.758331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.758360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.758389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.758418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.758444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.758474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.758506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.758538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.758569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.758595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.758624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.758658] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.758687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.761868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.761915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.761944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.761975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.765850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.765887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.765977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.768665] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.768703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.770601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.773945] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.774036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.774069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.774111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.790814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.790865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.791027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.824269] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.824382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.824483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.824525] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.824598] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.842731] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.842768] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.842812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.842853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.842978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.843033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.843084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.843134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.843191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.843239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.843273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.843305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.843334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.843362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.843416] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.843456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.843499] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.843530] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.843630] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.843648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.843729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.843762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.843797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.843842] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.843882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.843976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.844007] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.844037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.844065] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.844092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.844118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.844126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.844154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.844162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.844190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.844216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.844243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.844269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.844299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.844325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.844352] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.844378] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.844405] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.844434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.844466] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.844557] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.844588] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.844619] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.844671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.844703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.844733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.844764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.844794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.844826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.844850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.844871] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.844926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.844954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.844981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.845013] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.845042] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.847108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.847128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.847147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.847168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.848729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.848750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.848768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.850333] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.850353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.852225] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.855514] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.855604] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.855632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.855685] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.872385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.872439] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.872511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.905803] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.905890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.906100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.906163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.906270] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1138.924828] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1138.924866] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1138.924993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.925179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.925223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.925263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.925302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.925341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.925385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.925428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.925470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.925512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.925551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.925590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.925645] [drm:intel_power_well_disable [i915]] disabling display
>[ 1138.925691] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1138.925720] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.925740] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1138.925818] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.925829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1138.925937] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1138.925974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1138.926010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1138.926050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1138.926082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1138.926117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1138.926150] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1138.926183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1138.926215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1138.926246] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1138.926277] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1138.926286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.926315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1138.926323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1138.926354] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1138.926384] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1138.926700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1138.926732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1138.926766] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1138.926796] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1138.926827] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1138.926858] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1138.926912] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1138.926946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.926985] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1138.927247] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1138.927277] [drm:intel_power_well_enable [i915]] enabling display
>[ 1138.927305] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1138.927353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1138.927384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1138.927413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1138.927441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1138.927469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1138.927498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1138.927529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1138.927559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1138.927589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.927618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1138.927646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1138.927677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1138.927706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1138.929775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1138.929799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1138.929822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.929846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1138.931451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1138.931472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1138.931491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1138.933064] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1138.933087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1138.934953] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1138.938272] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1138.938331] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1138.938360] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1138.938398] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1138.955122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1138.955174] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1138.955240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1138.988548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1138.988637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1138.988742] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1138.988787] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1138.988893] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.006194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.006232] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.006272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.006305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.006339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.006369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.006407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.006448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.006492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.006534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.006576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.006618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.006665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.006686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.006719] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.006744] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.006771] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.006789] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.006841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.006908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.006996] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.007029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.007064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.007101] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.007133] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.007166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.007199] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.007231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.007262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.007293] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.007323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.007331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.007358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.007366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.007395] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.007424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.007453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.007482] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.007514] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.007544] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.007573] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.007602] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.007632] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.007664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.007699] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.007790] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.007821] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.007851] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.007930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.007964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.007996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.008028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.008061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.008093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.008128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.008162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.008196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.008227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.008257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.008293] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.008326] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.010404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.010427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.010466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.010487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.012082] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.012103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.012124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.013677] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.013700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.015567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.018925] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.018986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.019005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.019031] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.035793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.035844] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.035995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.069157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.069243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.069349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.069393] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.069475] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.087803] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.087840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.087955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.088005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.088062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.088269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.088300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.088332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.088369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.088408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.088427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.088445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.088462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.088478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.088510] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.088534] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.088560] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.088579] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.088634] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.088644] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.088693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.088712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.088742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.088767] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.088788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.088816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.088839] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.088863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.088930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.088965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.088993] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.089002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.089030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.089038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.089068] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.089096] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.089125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.089152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.089185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.089211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.089241] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.089268] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.089298] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.089329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.089364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.089804] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.089834] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.089864] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.090038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.090070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.090098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.090128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.090154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.090184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.090218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.090249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.090281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.090307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.090336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.090367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.090397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.092485] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.092506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.092525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.092544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.094110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.094130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.094149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.095698] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.095719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.097585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.100850] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.100965] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.100993] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.101029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.117741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.117790] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.117854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.151126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.151209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.151313] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.151355] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.151427] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.168463] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.168501] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.168541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.168574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.168609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.168640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.168669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.168706] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.168750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.168793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.168835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.168877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.168997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.169043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.169128] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.169183] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.169224] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.169256] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.169354] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.169373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.169458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.169488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.169521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.169557] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.169586] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.169617] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.169647] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.169677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.169705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.169733] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.169758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.169765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.169791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.169798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.169827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.169853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.169907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.169934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.169967] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.169994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.170023] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.170051] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.170080] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.170109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.170143] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.170232] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.170262] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.170292] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.170341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.170369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.170399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.170427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.170456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.170483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.170515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.170546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.170577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.170603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.170630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.170660] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.170691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.172762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.172786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.172809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.172833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.174457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.174480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.174503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.176095] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.176118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.178004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.181341] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.181422] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.181442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.181467] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.198218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.198270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.198337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.231621] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.231707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.231814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.231858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.232177] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.249209] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.249247] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.249286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.249321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.249356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.249386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.249416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.249447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.249482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.249514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.249544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.249575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.249602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.249630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.249683] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.249723] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.249764] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.249795] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.249975] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.250303] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.250414] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.250452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.250494] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.250539] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.250574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.250613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.250650] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.250687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.250722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.250757] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.250791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.250800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.250833] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.250842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.250907] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.250951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.250978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.251007] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.251037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.251067] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.251094] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.251123] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.251149] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.251183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.251218] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.251566] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.251606] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.251645] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.251693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.251722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.251748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.251775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.251800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.251828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.251870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.251930] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.251964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.251990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.252020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.252055] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.252085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.254355] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.254376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.254395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.254413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.256085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.256106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.256124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.257666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.257688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.259546] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.262872] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.262981] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.263015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.263057] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.279751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.279800] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.279864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.313152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.313237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.313339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.313381] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.313470] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.332094] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.332132] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.332171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.332204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.332238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.332267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.332296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.332327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.332362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.332394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.332425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.332455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.332483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.332510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.332566] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.332611] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.332661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.332696] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.332796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.332814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.332984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.333026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.333072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.333119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.333157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.333201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.333240] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.333280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.333317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.333354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.333388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.333398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.333433] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.333441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.333479] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.333514] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.333550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.333584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.333625] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.333658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.333697] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.333731] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.333767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.333806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.333849] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.333972] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.334002] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.334031] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.334082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.334114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.334142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.334170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.334196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.334226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.334258] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.334291] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.334322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.334348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.334376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.334406] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.334437] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.336690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.336713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.336736] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.336760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.338327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.338348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.338366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.339967] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.339989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.341851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.345177] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.345231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.345251] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.345277] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.362028] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.362080] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.362146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.395414] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.395525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.395628] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.395670] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.395743] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.412741] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.412783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.412827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.412867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.412996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.413038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.413072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.413111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.413157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.413201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.413244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.413288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.413328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.413368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.413443] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.413511] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.413579] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.413628] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.413761] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.413779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.413888] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.413920] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.413954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.413990] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.414020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.414051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.414083] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.414114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.414144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.414173] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.414200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.414208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.414235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.414241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.414270] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.414297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.414325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.414352] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.414382] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.414409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.414437] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.414463] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.414489] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.414519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.414552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.414641] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.414672] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.414703] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.414750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.414771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.414791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.414811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.414829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.414853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.414906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.414937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.414968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.414996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.415026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.415060] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.415091] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.417154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.417176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.417195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.417214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.418783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.418807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.418830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.420426] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.420448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.422344] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.425697] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.425779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.425812] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.425854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.442557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.442609] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.442676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.475984] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.476072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.476178] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.476230] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.476324] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.493387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.493429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.493474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.493514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.493558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.493597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.493637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.493676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.493720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.493762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.493804] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.493845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.493952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.494001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.494086] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.494274] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.494322] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.494354] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.494455] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.494474] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.494555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.494577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.494600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.494625] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.494645] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.494671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.494697] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.494723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.494749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.494776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.494801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.494807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.494832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.494860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.494895] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.494925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.494954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.494981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.495012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.495039] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.495067] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.495094] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.495121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.495153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.495184] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.495447] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.495466] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.495484] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.495521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.495543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.495563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.495582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.495607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.495633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.495662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.495690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.495718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.495743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.495769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.495796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.495822] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.497904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.497925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.497943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.497962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.499534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.499554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.499572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.501125] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.501146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.503015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.505704] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.505789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.505809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.505835] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.522566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.522618] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.522685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.555999] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.556087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.556192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.556233] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.556323] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.573385] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.573427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.573471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.573512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.573556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.573595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.573635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.573674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.573718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.573761] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.573802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.573844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.573953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.574001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.574085] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.574140] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.574186] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.574218] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.574318] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.574337] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.574406] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.574427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.574452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.574482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.574511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.574546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.574569] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.574590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.574610] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.574629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.574646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.574652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.574669] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.574673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.574692] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.574710] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.574728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.574746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.574768] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.574785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.574804] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.574821] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.574841] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.574895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.574928] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.575018] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.575047] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.575078] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.575115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.575136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.575160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.575186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.575213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.575239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.575266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.575291] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.575319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.575345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.575371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.575398] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.575424] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.577643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.577687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.577712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.577738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.579318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.579338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.579357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.580951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.580972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.582843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.586210] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.586289] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.586323] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.586365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.603072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.603125] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.603197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.636498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.636587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.636698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.636748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.636833] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.653936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.653974] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.654013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.654046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.654080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.654110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.654139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.654170] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.654205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.654238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.654269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.654300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.654327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.654355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.654410] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.654456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.654506] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.654542] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.654628] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.654646] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.654737] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.654778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.654818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.654949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.655004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.655053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.655087] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.655121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.655153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.655185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.655213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.655222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.655251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.655259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.655289] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.655319] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.655351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.655382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.655415] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.655446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.655476] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.655506] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.655537] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.655572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.655607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.655679] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.655710] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.655741] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.655793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.655824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.655878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.655908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.655939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.655972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.656007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.656039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.656072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.656102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.656131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.656164] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.656196] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.658279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.658301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.658320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.658344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.659949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.659973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.659996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.661555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.661577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.663451] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.666746] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.666838] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.666939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.667014] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.683615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.683667] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.683733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.717007] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.717090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.717192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.717234] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.717330] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.734395] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.734433] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.734473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.734506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.734541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.734572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.734600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.734632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.734667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.734708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.734750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.734792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.734832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.734926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.734979] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.735021] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.735063] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.735096] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.735183] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.735202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.735286] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.735316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.735349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.735385] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.735413] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.735445] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.735475] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.735505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.735533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.735562] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.735589] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.735597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.735623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.735630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.735659] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.735685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.735713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.735738] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.735770] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.735795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.735824] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.735875] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.735904] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.735936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.735972] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.736060] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.736091] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.736120] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.736170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.736201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.736228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.736257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.736284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.736313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.736346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.736378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.736410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.736436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.736463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.736494] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.736524] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.738622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.738644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.738662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.738682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.740261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.740282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.740300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.741867] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.741898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.743768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.747095] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.747137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.747161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.747192] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.763929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.763981] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.764047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.797303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.797391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.797499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.797544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.797619] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.814654] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.814677] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.814700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.814720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.814740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.814758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.814774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.814793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.814814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.814892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.814926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.814962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.814989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.815020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.815076] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.815117] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.815156] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.815188] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.815290] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1139.815308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1139.815394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.815423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.815457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.815494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.815522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.815554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.815583] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1139.815614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1139.815642] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.815671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.815696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.815704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.815731] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.815738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.815767] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.815793] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.815822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.815878] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1139.815911] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.815938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.815968] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1139.815995] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1139.816025] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1139.816059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.816095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1139.816185] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.816215] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.816244] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.816295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.816323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.816353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.816380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.816409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.816436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.816468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.816500] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.816533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.816559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.816587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.816617] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1139.816647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.818710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.818731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.818749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.818768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.820360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.820380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.820398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.822049] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.822070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.823952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.827273] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1139.827332] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.827361] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1139.827399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.844116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.844167] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.844233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.877557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.877643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1139.877687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1139.877759] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1139.894737] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1139.894780] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1139.894825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.894953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.895013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.895063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.895112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.895163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.895208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.895243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.895275] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.895307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.895335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.895364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.895420] [drm:intel_power_well_disable [i915]] disabling display
>[ 1139.895468] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1139.895518] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1139.895555] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1139.897153] [IGT] kms_flip: exiting, ret=0
>[ 1139.918831] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1139.918890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1139.918927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1139.918964] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1139.918994] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1139.919028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1139.919067] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1139.919092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1139.919118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1139.919141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1139.919164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1139.919170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.919193] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1139.919197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1139.919220] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1139.919251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1139.919283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1139.919315] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1139.919347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1139.919379] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1139.919411] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1139.919443] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1139.919471] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1139.919505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1139.919541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1139.919642] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1139.919671] [drm:intel_power_well_enable [i915]] enabling display
>[ 1139.919698] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1139.919750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1139.919783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1139.919815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1139.919870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1139.919903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1139.919935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1139.919971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1139.920006] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1139.920041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.920077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1139.920100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1139.920126] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1139.920147] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1139.922217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1139.922237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1139.922254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.922272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1139.923841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1139.923887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1139.923904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1139.925473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1139.925491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1139.927358] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1139.930839] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1139.930953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1139.930982] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1139.931024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1139.931102] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1139.931132] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1139.947736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1139.947784] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1139.947883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1139.948124] Console: switching to colour frame buffer device 240x75
>[ 1140.056779] Console: switching to colour dummy device 80x25
>[ 1140.056997] [IGT] kms_flip: executing
>[ 1140.067744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1140.067796] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1140.069958] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1140.069994] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1140.072108] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1140.072119] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1140.074236] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1140.074275] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1140.076389] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1140.076400] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1140.076408] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1140.076437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1140.076479] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1140.077596] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1140.078518] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1140.078541] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1140.078560] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1140.078580] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1140.079601] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1140.079622] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1140.080741] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1140.080745] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1140.080912] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1140.080916] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1140.080921] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1140.080924] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1140.080930] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1140.080933] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1140.080942] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1140.080946] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1140.080949] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.080954] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.080957] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1140.080961] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1140.080964] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1140.080967] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1140.080970] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.080974] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.080978] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1140.080982] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1140.080985] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1140.080988] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1140.080991] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1140.080994] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1140.080998] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1140.081002] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1140.081005] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1140.081008] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1140.081012] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1140.081016] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1140.081019] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1140.081022] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1140.081026] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1140.081029] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1140.081033] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1140.081036] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1140.081040] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1140.081043] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1140.081046] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1140.081090] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1140.081115] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1140.082916] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1140.082950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1140.084921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1140.084932] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1140.086905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1140.086942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1140.088907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1140.088918] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1140.088925] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1140.091015] [IGT] kms_flip: starting subtest 2x-flip-vs-dpms-off-vs-modeset-interruptible
>[ 1140.092921] [IGT] kms_flip: exiting, ret=77
>[ 1140.131396] Console: switching to colour frame buffer device 240x75
>[ 1140.239708] Console: switching to colour dummy device 80x25
>[ 1140.239894] [IGT] kms_flip: executing
>[ 1140.251689] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1140.251741] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1140.253897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1140.253933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1140.256024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1140.256035] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1140.258153] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1140.258192] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1140.260306] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1140.260317] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1140.260325] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1140.260357] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1140.260398] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1140.261497] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1140.262422] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1140.262445] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1140.262464] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1140.262482] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1140.263505] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1140.263526] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1140.264635] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1140.264638] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1140.264738] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1140.264741] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1140.264746] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1140.264748] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1140.264753] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1140.264755] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1140.264764] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1140.264768] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1140.264771] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.264774] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.264777] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1140.264780] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1140.264783] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1140.264785] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1140.264788] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.264791] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1140.264794] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1140.264797] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1140.264850] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1140.264855] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1140.264860] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1140.264866] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1140.264872] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1140.264878] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1140.264884] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1140.264889] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1140.264895] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1140.264901] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1140.264907] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1140.264912] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1140.264917] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1140.264923] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1140.264929] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1140.264935] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1140.264941] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1140.264946] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1140.264952] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1140.265018] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1140.265054] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1140.266864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1140.266903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1140.268909] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1140.268920] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1140.270920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1140.270959] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1140.272913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1140.272923] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1140.272931] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1140.273332] [IGT] kms_flip: starting subtest flip-vs-expired-vblank
>[ 1140.274295] [drm:drm_mode_addfb2] [FB:58]
>[ 1140.274340] [drm:drm_mode_addfb2] [FB:79]
>[ 1140.327559] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1140.327625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1140.331378] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1140.331427] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1140.331519] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1140.348576] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1140.348620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1140.348652] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1140.348690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1140.348723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1140.348758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1140.348788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1140.348817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1140.348928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1140.348989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1140.349043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1140.349095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1140.349145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1140.349191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1140.349236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1140.349316] [drm:intel_power_well_disable [i915]] disabling display
>[ 1140.349381] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1140.349422] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1140.349457] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1140.349557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1140.349711] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1140.349852] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1140.349865] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1140.349938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1140.349972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1140.350008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1140.350046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1140.350067] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1140.350089] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1140.350110] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1140.350131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1140.350150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1140.350175] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1140.350201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1140.350206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1140.350231] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1140.350236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1140.350262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1140.350287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1140.350312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1140.350337] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1140.350362] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1140.350387] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1140.350413] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1140.350438] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1140.350464] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1140.350491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1140.350518] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1140.353919] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1140.353940] [drm:intel_power_well_enable [i915]] enabling display
>[ 1140.353958] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1140.353994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1140.354016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1140.354037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1140.354056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1140.354075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1140.354094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1140.354116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1140.354136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1140.354156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1140.354174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1140.354192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1140.354214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1140.354234] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1140.356316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1140.356337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1140.356356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1140.356379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1140.357958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1140.357978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1140.357996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1140.359545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1140.359566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1140.361431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1140.364709] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1140.364748] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1140.364772] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1140.364803] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1140.365072] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1140.365093] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1140.381541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1140.381588] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1140.381651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1150.406292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1150.422807] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1150.422852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1150.422925] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1150.439952] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1150.439998] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1150.440031] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1150.440070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1150.440104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1150.440140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1150.440171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1150.440201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1150.440232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1150.440268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1150.440301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1150.440334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1150.440364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1150.440392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1150.440507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1150.440592] [drm:intel_power_well_disable [i915]] disabling display
>[ 1150.440663] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1150.440729] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1150.440795] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1150.441026] [drm:drm_mode_addfb2] [FB:58]
>[ 1150.441055] [drm:drm_mode_addfb2] [FB:78]
>[ 1150.470306] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1150.470485] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1150.470608] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1150.470681] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1150.470692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1150.470751] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1150.470773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1150.470795] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1150.470819] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1150.470837] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1150.470857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1150.470881] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1150.470905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1150.470929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1150.470952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1150.470975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1150.470979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1150.471002] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1150.471007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1150.471030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1150.471054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1150.471077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1150.471099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1150.471123] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1150.471146] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1150.471169] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1150.471193] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1150.471216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1150.471241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1150.471266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1150.474655] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1150.474676] [drm:intel_power_well_enable [i915]] enabling display
>[ 1150.474695] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1150.474733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1150.474756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1150.474776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1150.474796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1150.474815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1150.474835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1150.474857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1150.474877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1150.474897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1150.474915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1150.474932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1150.474954] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1150.474974] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1150.477039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1150.477061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1150.477080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1150.477100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1150.481021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1150.481059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1150.481090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1150.483779] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1150.483811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1150.486816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1150.490126] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1150.490199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1150.490230] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1150.490277] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1150.506988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1150.507038] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1150.507104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.531715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.531801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1160.531852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1160.531931] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1160.548979] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1160.549051] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1160.549091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.549126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.549162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.549193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.549222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.549254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.549289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.549322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.549354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.549385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.549414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.549441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.549495] [drm:intel_power_well_disable [i915]] disabling display
>[ 1160.549536] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1160.549578] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1160.549609] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1160.550051] [drm:drm_mode_addfb2] [FB:58]
>[ 1160.550127] [drm:drm_mode_addfb2] [FB:78]
>[ 1160.579717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1160.579825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1160.579902] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1160.580025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1160.580045] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1160.580143] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1160.580178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1160.580215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1160.580252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1160.580284] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1160.580319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1160.580353] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1160.580385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1160.580417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1160.580447] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1160.580477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1160.580484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.580513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1160.580521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1160.580551] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1160.580581] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1160.580610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1160.580638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1160.580668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1160.580698] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1160.580727] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1160.580753] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1160.580784] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1160.580817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1160.580852] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1160.584311] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1160.584333] [drm:intel_power_well_enable [i915]] enabling display
>[ 1160.584351] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1160.584389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1160.584411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1160.584432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1160.584456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1160.584481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1160.584511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1160.584535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1160.584556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1160.584576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1160.584595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1160.584613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1160.584636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1160.584657] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1160.586719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1160.586741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1160.586759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.586783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1160.588351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1160.588372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1160.588390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1160.589976] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1160.590014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1160.591875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1160.595195] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1160.595258] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1160.595298] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1160.595350] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1160.612058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1160.612107] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1160.612171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1170.636776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1170.636865] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1170.636918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1170.636998] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1170.654024] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1170.654062] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1170.654102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1170.654135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1170.654170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1170.654208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1170.654249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1170.654288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1170.654333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1170.654376] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1170.654418] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1170.654460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1170.654499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1170.654538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1170.654692] [drm:intel_power_well_disable [i915]] disabling display
>[ 1170.654763] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1170.654813] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1170.654846] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1170.658015] [IGT] kms_flip: exiting, ret=0
>[ 1170.681491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1170.681530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1170.681569] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1170.681634] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1170.681667] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1170.681709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1170.681738] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1170.681766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1170.681793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1170.681818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1170.681842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1170.681848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1170.681872] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1170.681877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1170.681901] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1170.681925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1170.681949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1170.681973] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1170.682002] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1170.682025] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1170.682049] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1170.682073] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1170.682096] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1170.682125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1170.682157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1170.682245] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1170.682275] [drm:intel_power_well_enable [i915]] enabling display
>[ 1170.682304] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1170.682358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1170.682391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1170.682425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1170.682459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1170.682492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1170.682526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1170.682563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1170.682626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1170.682662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1170.682704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1170.682730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1170.682758] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1170.682781] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1170.684849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1170.684869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1170.684886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1170.684908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1170.688709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1170.688742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1170.688772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1170.691418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1170.691442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1170.694482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1170.698001] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1170.698053] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1170.698071] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1170.698098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1170.698163] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1170.698187] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1170.714856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1170.714904] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1170.714974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1170.715224] Console: switching to colour frame buffer device 240x75
>[ 1170.825521] Console: switching to colour dummy device 80x25
>[ 1170.825761] [IGT] kms_flip: executing
>[ 1170.837453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1170.837506] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1170.839635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1170.839672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1170.841768] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1170.841779] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1170.843873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1170.843906] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1170.846024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1170.846036] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1170.846043] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1170.846074] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1170.846116] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1170.847230] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1170.848142] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1170.848166] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1170.848186] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1170.848214] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1170.849233] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1170.849253] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1170.850365] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1170.850369] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1170.850469] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1170.850471] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1170.850476] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1170.850479] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1170.850484] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1170.850486] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1170.850495] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1170.850499] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1170.850502] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1170.850505] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1170.850508] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1170.850511] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1170.850514] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1170.850517] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1170.850519] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1170.850522] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1170.850525] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1170.850528] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1170.850531] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1170.850534] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1170.850573] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1170.850581] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1170.850587] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1170.850593] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1170.850599] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1170.850606] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1170.850613] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1170.850620] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1170.850626] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1170.850633] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1170.850639] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1170.850646] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1170.850652] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1170.850658] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1170.850665] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1170.850671] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1170.850678] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1170.850747] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1170.850780] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1170.852605] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1170.852633] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1170.854797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1170.854808] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1170.856644] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1170.856683] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1170.858644] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1170.858655] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1170.858662] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1170.859070] [IGT] kms_flip: starting subtest flip-vs-absolute-wf_vblank
>[ 1170.860017] [drm:drm_mode_addfb2] [FB:77]
>[ 1170.860061] [drm:drm_mode_addfb2] [FB:79]
>[ 1170.913135] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1170.913201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1170.914999] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1170.915046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1170.915135] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1170.932152] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1170.932196] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1170.932235] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1170.932280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1170.932321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1170.932364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1170.932404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1170.932444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1170.932484] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1170.932528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1170.932630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1170.932684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1170.932735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1170.932778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1170.932820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1170.932905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1170.932975] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1170.933042] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1170.933098] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1170.933180] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1170.933261] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1170.933329] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1170.933341] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1170.933396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1170.933418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1170.933442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1170.933467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1170.933486] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1170.933508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1170.933530] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1170.933581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1170.933611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1170.933640] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1170.933669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1170.933677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1170.933704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1170.933712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1170.933739] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1170.933766] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1170.933794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1170.933820] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1170.933850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1170.933876] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1170.933904] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1170.933930] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1170.933957] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1170.933990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1170.934024] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1170.937503] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1170.937525] [drm:intel_power_well_enable [i915]] enabling display
>[ 1170.937546] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1170.937663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1170.937698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1170.937731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1170.937762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1170.937786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1170.937808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1170.937831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1170.937852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1170.937873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1170.937891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1170.937909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1170.937932] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1170.937957] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1170.941102] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1170.941127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1170.941150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1170.941173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1170.945156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1170.945193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1170.945226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1170.947897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1170.947935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1170.950925] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1170.954270] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1170.954363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1170.954395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1170.954437] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1170.954515] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1170.954549] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1170.971146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1170.971196] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1170.971261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1181.279595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1181.296062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1181.296142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1181.296437] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1181.313471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1181.313515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1181.313548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1181.313587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1181.313620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1181.313656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1181.313687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1181.313716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1181.313747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1181.313783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1181.313824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1181.313867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1181.313909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1181.313949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1181.313988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1181.314046] [drm:intel_power_well_disable [i915]] disabling display
>[ 1181.314093] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1181.314227] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1181.314277] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1181.314580] [drm:drm_mode_addfb2] [FB:77]
>[ 1181.314632] [drm:drm_mode_addfb2] [FB:78]
>[ 1181.346962] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1181.347065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1181.347200] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1181.347317] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1181.347330] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1181.347399] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1181.347423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1181.347448] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1181.347475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1181.347498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1181.347523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1181.347546] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1181.347570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1181.347594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1181.347617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1181.347640] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1181.347644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1181.347667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1181.347671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1181.347695] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1181.347718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1181.347741] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1181.347763] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1181.347787] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1181.347810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1181.347833] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1181.347857] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1181.347880] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1181.347905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1181.347931] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1181.351207] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1181.351228] [drm:intel_power_well_enable [i915]] enabling display
>[ 1181.351247] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1181.351285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1181.351307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1181.351329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1181.351354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1181.351379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1181.351403] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1181.351430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1181.351455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1181.351481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1181.351505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1181.351529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1181.351555] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1181.351580] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1181.353654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1181.353676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1181.353699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1181.353724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1181.355304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1181.355325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1181.355344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1181.356901] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1181.356922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1181.358793] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1181.362129] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1181.362226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1181.362245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1181.362271] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1181.379009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1181.379060] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1181.379126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1191.687516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1191.687692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1191.687966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1191.688178] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1191.705618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1191.705685] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1191.705907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1191.705992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1191.706088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1191.706165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1191.706247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1191.706327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1191.706422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1191.706517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1191.706608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1191.706699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1191.706803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1191.706846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1191.706932] [drm:intel_power_well_disable [i915]] disabling display
>[ 1191.706997] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1191.707062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1191.707111] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1191.707468] [drm:drm_mode_addfb2] [FB:77]
>[ 1191.707515] [drm:drm_mode_addfb2] [FB:78]
>[ 1191.736975] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1191.737080] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1191.737151] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1191.737218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1191.737230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1191.737289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1191.737311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1191.737333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1191.737357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1191.737375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1191.737396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1191.737416] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1191.737435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1191.737453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1191.737470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1191.737487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1191.737491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1191.737508] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1191.737512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1191.737529] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1191.737545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1191.737568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1191.737591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1191.737615] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1191.737638] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1191.737661] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1191.737685] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1191.737767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1191.737801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1191.737836] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1191.741127] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1191.741149] [drm:intel_power_well_enable [i915]] enabling display
>[ 1191.741167] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1191.741205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1191.741229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1191.741255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1191.741279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1191.741304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1191.741329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1191.741356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1191.741382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1191.741408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1191.741432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1191.741456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1191.741482] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1191.741506] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1191.743573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1191.743597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1191.743620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1191.743645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1191.745282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1191.745303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1191.745322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1191.746889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1191.746911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1191.748776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1191.752120] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1191.752205] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1191.752233] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1191.752268] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1191.768969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1191.769016] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1191.769080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1202.077559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1202.077737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1202.077840] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1202.077993] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1202.095059] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1202.095097] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1202.095138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1202.095172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1202.095207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1202.095238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1202.095268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1202.095393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1202.095458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1202.095513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1202.095566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1202.095619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1202.095664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1202.095710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1202.095797] [drm:intel_power_well_disable [i915]] disabling display
>[ 1202.095865] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1202.095928] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1202.095980] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1202.098863] [IGT] kms_flip: exiting, ret=0
>[ 1202.118203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1202.118242] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1202.118305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1202.118346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1202.118382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1202.118424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1202.118465] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1202.118505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1202.118533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1202.118557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1202.118580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1202.118586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1202.118609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1202.118614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1202.118637] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1202.118660] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1202.118683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1202.118705] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1202.118732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1202.118755] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1202.118777] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1202.118799] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1202.118830] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1202.118864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1202.118900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1202.118989] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1202.119017] [drm:intel_power_well_enable [i915]] enabling display
>[ 1202.119045] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1202.119096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1202.119128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1202.119161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1202.119193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1202.119225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1202.119257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1202.119319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1202.119353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1202.119387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1202.119418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1202.119450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1202.119491] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1202.119516] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1202.121580] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1202.121600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1202.121618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1202.121636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1202.123236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1202.123254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1202.123281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1202.124851] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1202.124869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1202.126749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1202.129742] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1202.129813] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1202.129831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1202.129858] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1202.129924] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1202.129949] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1202.146623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1202.146672] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1202.146742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1202.146988] Console: switching to colour frame buffer device 240x75
>[ 1202.255273] Console: switching to colour dummy device 80x25
>[ 1202.255402] [IGT] kms_flip: executing
>[ 1202.267126] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1202.267179] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1202.269315] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1202.269351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1202.271444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1202.271454] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1202.273571] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1202.273610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1202.275724] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1202.275735] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1202.275743] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1202.275773] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1202.275818] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1202.277022] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1202.277968] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1202.277990] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1202.278009] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1202.278027] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1202.279046] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1202.279066] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1202.280185] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1202.280189] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1202.280385] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1202.280390] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1202.280399] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1202.280403] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1202.280412] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1202.280416] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1202.280430] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1202.280435] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1202.280441] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1202.280444] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1202.280447] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1202.280450] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1202.280453] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1202.280456] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1202.280459] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1202.280462] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1202.280465] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1202.280468] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1202.280471] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1202.280474] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1202.280477] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1202.280480] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1202.280483] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1202.280486] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1202.280489] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1202.280492] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1202.280495] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1202.280498] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1202.280501] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1202.280504] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1202.280507] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1202.280509] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1202.280512] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1202.280515] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1202.280518] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1202.280521] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1202.280524] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1202.280562] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1202.280585] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1202.282331] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1202.282377] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1202.284326] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1202.284336] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1202.286332] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1202.286371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1202.288347] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1202.288358] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1202.288365] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1202.290494] [IGT] kms_flip: starting subtest plain-flip-interruptible
>[ 1202.291011] [drm:drm_mode_addfb2] [FB:58]
>[ 1202.291038] [drm:drm_mode_addfb2] [FB:79]
>[ 1202.345099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1202.345161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1202.346766] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1202.346817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1202.346910] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1202.363914] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1202.363958] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1202.363991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1202.364030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1202.364063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1202.364099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1202.364129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1202.364158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1202.364190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1202.364224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1202.364265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1202.364389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1202.364443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1202.364487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1202.364530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1202.364613] [drm:intel_power_well_disable [i915]] disabling display
>[ 1202.364640] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1202.364670] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1202.364692] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1202.364758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1202.364843] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1202.364915] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1202.364927] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1202.364981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1202.365006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1202.365033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1202.365062] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1202.365087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1202.365114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1202.365141] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1202.365166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1202.365192] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1202.365219] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1202.365244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1202.365277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1202.365309] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1202.365316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1202.365348] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1202.365376] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1202.365405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1202.365432] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1202.365463] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1202.365493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1202.365520] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1202.365547] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1202.365574] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1202.365605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1202.365638] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1202.368945] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1202.368968] [drm:intel_power_well_enable [i915]] enabling display
>[ 1202.368989] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1202.369027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1202.369052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1202.369077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1202.369101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1202.369125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1202.369149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1202.369176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1202.369201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1202.369227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1202.369251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1202.369340] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1202.369379] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1202.369412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1202.371482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1202.371503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1202.371526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1202.371550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1202.373137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1202.373162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1202.373185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1202.374734] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1202.374758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1202.376663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1202.379955] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1202.380032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1202.380056] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1202.380088] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1202.380150] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1202.380181] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1202.396820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1202.396868] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1202.396931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1205.749628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1205.766177] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1205.766222] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1205.766294] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1205.783303] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1205.783346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1205.783386] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1205.783431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1205.783472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1205.783516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1205.783556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1205.783596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1205.783635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1205.783680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1205.783723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1205.783765] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1205.783807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1205.783846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1205.783885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1205.783943] [drm:intel_power_well_disable [i915]] disabling display
>[ 1205.783990] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1205.784041] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1205.784080] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1205.784459] [drm:drm_mode_addfb2] [FB:58]
>[ 1205.784488] [drm:drm_mode_addfb2] [FB:78]
>[ 1205.817287] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1205.817389] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1205.817459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1205.817525] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1205.817536] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1205.817598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1205.817621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1205.817644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1205.817668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1205.817686] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1205.817707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1205.817727] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1205.817750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1205.817774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1205.817798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1205.817821] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1205.817826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1205.817849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1205.817853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1205.817877] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1205.817897] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1205.817921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1205.817944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1205.817969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1205.817991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1205.818015] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1205.818038] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1205.818062] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1205.818086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1205.818163] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1205.821457] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1205.821476] [drm:intel_power_well_enable [i915]] enabling display
>[ 1205.821493] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1205.821529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1205.821550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1205.821569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1205.821587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1205.821604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1205.821622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1205.821643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1205.821661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1205.821680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1205.821697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1205.821713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1205.821734] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1205.821754] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1205.823826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1205.823847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1205.823865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1205.823884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1205.825449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1205.825468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1205.825486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1205.827035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1205.827056] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1205.828912] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1205.832217] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1205.832280] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1205.832300] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1205.832326] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1205.849069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1205.849120] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1205.849298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1209.201870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1209.201954] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1209.202092] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1209.202199] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1209.219228] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1209.219266] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1209.219306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1209.219348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1209.219393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1209.219441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1209.219490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1209.219525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1209.219570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1209.219601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1209.219630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1209.219659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1209.219686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1209.219712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1209.219763] [drm:intel_power_well_disable [i915]] disabling display
>[ 1209.219802] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1209.219843] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1209.219872] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1209.220326] [drm:drm_mode_addfb2] [FB:58]
>[ 1209.220398] [drm:drm_mode_addfb2] [FB:78]
>[ 1209.253731] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1209.253832] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1209.253900] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1209.254028] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1209.254046] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1209.254143] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1209.254176] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1209.254211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1209.254248] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1209.254276] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1209.254308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1209.254338] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1209.254369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1209.254397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1209.254428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1209.254454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1209.254462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1209.254489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1209.254496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1209.254525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1209.254551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1209.254579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1209.254604] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1209.254636] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1209.254661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1209.254690] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1209.254716] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1209.254743] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1209.254773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1209.254806] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1209.258263] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1209.258286] [drm:intel_power_well_enable [i915]] enabling display
>[ 1209.258307] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1209.258346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1209.258371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1209.258395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1209.258420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1209.258444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1209.258468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1209.258495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1209.258521] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1209.258547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1209.258571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1209.258595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1209.258621] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1209.258646] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1209.260708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1209.260729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1209.260748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1209.260767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1209.262332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1209.262353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1209.262371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1209.263964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1209.264003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1209.265864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1209.269234] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1209.269299] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1209.269333] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1209.269375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1209.286073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1209.286122] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1209.286186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1212.638932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1212.639018] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1212.639061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1212.639152] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1212.657632] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1212.657669] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1212.657710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1212.657744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1212.657780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1212.657817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1212.657926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1212.657965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1212.658011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1212.658057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1212.658104] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1212.658157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1212.658207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1212.658256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1212.658343] [drm:intel_power_well_disable [i915]] disabling display
>[ 1212.658414] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1212.658465] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1212.658497] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1212.660301] [IGT] kms_flip: exiting, ret=0
>[ 1212.680832] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1212.680894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1212.680934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1212.680975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1212.681007] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1212.681042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1212.681077] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1212.681110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1212.681142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1212.681171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1212.681200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1212.681208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1212.681237] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1212.681251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1212.681275] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1212.681297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1212.681319] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1212.681342] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1212.681368] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1212.681391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1212.681414] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1212.681436] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1212.681457] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1212.681485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1212.681515] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1212.681611] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1212.681639] [drm:intel_power_well_enable [i915]] enabling display
>[ 1212.681666] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1212.681717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1212.681750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1212.681782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1212.681814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1212.681871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1212.681903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1212.681938] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1212.681972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1212.682006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1212.682037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1212.682069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1212.682102] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1212.682134] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1212.684206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1212.684228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1212.684250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1212.684273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1212.685874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1212.685893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1212.685911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1212.687476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1212.687495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1212.689375] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1212.692261] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1212.692354] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1212.692384] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1212.692427] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1212.692515] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1212.692541] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1212.709148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1212.709196] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1212.709265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1212.709508] Console: switching to colour frame buffer device 240x75
>[ 1212.818270] Console: switching to colour dummy device 80x25
>[ 1212.818383] [IGT] kms_flip: executing
>[ 1212.833685] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1212.833738] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1212.835877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1212.835917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1212.838033] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1212.838044] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1212.840163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1212.840201] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1212.842316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1212.842327] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1212.842335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1212.842364] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1212.842407] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1212.843538] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1212.844464] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1212.844486] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1212.844504] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1212.844526] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1212.845564] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1212.845587] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1212.846698] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1212.846702] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1212.846866] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1212.846871] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1212.846882] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1212.846887] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1212.846896] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1212.846900] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1212.846916] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1212.846923] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1212.846929] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1212.846934] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1212.846940] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1212.846946] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1212.846951] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1212.846956] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1212.846962] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1212.846966] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1212.846969] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1212.846972] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1212.846976] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1212.846979] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1212.846983] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1212.846986] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1212.846990] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1212.846993] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1212.846997] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1212.847000] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1212.847003] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1212.847006] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1212.847010] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1212.847014] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1212.847017] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1212.847021] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1212.847024] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1212.847027] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1212.847030] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1212.847033] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1212.847038] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1212.847082] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1212.847107] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1212.848921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1212.848961] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1212.850910] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1212.850921] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1212.852914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1212.852953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1212.854931] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1212.854942] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1212.854949] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1212.855369] [IGT] kms_flip: starting subtest 2x-modeset-vs-vblank-race
>[ 1212.858529] [IGT] kms_flip: exiting, ret=77
>[ 1212.892769] Console: switching to colour frame buffer device 240x75
>[ 1213.000972] Console: switching to colour dummy device 80x25
>[ 1213.001088] [IGT] kms_flip: executing
>[ 1213.017693] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1213.017745] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1213.018919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.018959] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.020904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.020916] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1213.022902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.022942] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.024905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.024916] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.024924] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1213.024954] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1213.024996] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1213.026123] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1213.027069] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1213.027091] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1213.027109] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1213.027127] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1213.028144] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1213.028164] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1213.029281] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1213.029284] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1213.029382] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.029385] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.029390] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1213.029392] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1213.029398] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.029400] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.029409] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1213.029412] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1213.029415] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.029418] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.029421] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.029424] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.029427] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.029430] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1213.029433] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.029436] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.029439] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.029442] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.029445] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.029448] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1213.029451] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.029454] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.029457] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1213.029459] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.029462] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.029465] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1213.029468] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1213.029471] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1213.029474] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1213.029477] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1213.029480] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1213.029483] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.029486] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.029489] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1213.029492] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.029495] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.029497] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1213.029535] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1213.029558] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1213.030865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.030886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.032927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.032942] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1213.034903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.034939] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.036904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.036915] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.036922] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1213.038959] [IGT] kms_flip: starting subtest 2x-vblank-vs-dpms-suspend-interruptible
>[ 1213.041035] [IGT] kms_flip: exiting, ret=77
>[ 1213.076282] Console: switching to colour frame buffer device 240x75
>[ 1213.183139] Console: switching to colour dummy device 80x25
>[ 1213.183255] [IGT] kms_flip: executing
>[ 1213.194690] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1213.194737] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1213.195921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.195962] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.197900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.197912] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1213.199898] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.199937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.201900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.201912] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.201920] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1213.201951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1213.201994] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1213.203101] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1213.204055] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1213.204085] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1213.204111] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1213.204136] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1213.205155] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1213.205175] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1213.206294] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1213.206298] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1213.206402] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.206405] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.206410] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1213.206412] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1213.206417] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.206419] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.206429] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1213.206432] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1213.206435] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.206438] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.206441] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.206444] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.206447] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.206450] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1213.206453] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.206456] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.206459] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.206462] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.206465] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.206468] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1213.206471] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.206474] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.206477] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1213.206480] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.206483] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.206486] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1213.206489] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1213.206492] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1213.206495] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1213.206497] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1213.206500] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1213.206503] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.206506] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.206509] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1213.206512] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.206515] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.206518] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1213.206556] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1213.206579] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1213.207851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.207875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.209983] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.209998] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1213.212120] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.212159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.214272] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.214284] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.214291] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1213.214689] [IGT] kms_flip: starting subtest 2x-plain-flip-fb-recreate
>[ 1213.218037] [IGT] kms_flip: exiting, ret=77
>[ 1213.259754] Console: switching to colour frame buffer device 240x75
>[ 1213.368316] Console: switching to colour dummy device 80x25
>[ 1213.368439] [IGT] kms_flip: executing
>[ 1213.379676] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1213.379728] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1213.380907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.380945] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.382888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.382900] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1213.384889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.384928] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.386892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.386904] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.386911] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1213.386942] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1213.386984] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1213.388113] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1213.389046] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1213.389068] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1213.389087] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1213.389105] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1213.390121] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1213.390144] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1213.391268] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1213.391271] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1213.391374] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.391376] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.391381] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1213.391384] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1213.391389] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.391391] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.391401] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1213.391405] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1213.391408] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.391411] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.391414] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.391417] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.391420] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.391423] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1213.391426] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.391429] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.391431] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.391434] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.391437] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.391440] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1213.391443] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.391446] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.391449] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1213.391452] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.391455] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.391458] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1213.391461] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1213.391464] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1213.391467] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1213.391470] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1213.391473] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1213.391476] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.391478] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.391481] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1213.391484] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.391487] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.391490] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1213.391529] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1213.391552] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1213.392830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.392852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.394880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.394889] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1213.396888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.396927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.398888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.398899] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.398907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1213.401023] [IGT] kms_flip: starting subtest 2x-nonexisting-fb-interruptible
>[ 1213.402752] [IGT] kms_flip: exiting, ret=77
>[ 1213.426557] Console: switching to colour frame buffer device 240x75
>[ 1213.534418] Console: switching to colour dummy device 80x25
>[ 1213.534531] [IGT] kms_flip: executing
>[ 1213.545656] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1213.545708] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1213.547251] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.547291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.548878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.548890] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1213.550876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.550915] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.552879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.552890] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.552898] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1213.552929] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1213.552971] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1213.554093] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1213.555050] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1213.555082] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1213.555111] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1213.555138] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1213.556182] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1213.556213] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1213.557454] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1213.557460] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1213.557631] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.557636] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.557645] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1213.557649] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1213.557658] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.557662] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.557677] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1213.557683] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1213.557688] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.557693] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.557699] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.557704] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.557709] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.557715] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1213.557720] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.557725] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.557730] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.557736] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.557741] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.557746] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1213.557751] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.557756] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.557762] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1213.557767] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.557821] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.557828] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1213.557835] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1213.557841] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1213.557848] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1213.557855] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1213.557862] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1213.557869] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.557876] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.557883] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1213.557889] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.557896] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.557903] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1213.557973] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1213.558007] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1213.559838] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.559877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.561853] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.561862] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1213.563859] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.563889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.565860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.565867] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.565872] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1213.566212] [IGT] kms_flip: starting subtest 2x-absolute-wf_vblank
>[ 1213.569504] [IGT] kms_flip: exiting, ret=77
>[ 1213.593361] Console: switching to colour frame buffer device 240x75
>[ 1213.699976] Console: switching to colour dummy device 80x25
>[ 1213.700091] [IGT] kms_flip: executing
>[ 1213.711680] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1213.711733] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1213.713872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.713909] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.715857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.715868] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1213.717896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.717932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.719888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.719901] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.719909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1213.719942] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1213.719983] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1213.721111] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1213.722046] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1213.722069] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1213.722087] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1213.722105] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1213.723124] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1213.723145] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1213.724254] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1213.724257] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1213.724361] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.724364] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.724369] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1213.724371] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1213.724376] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.724379] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.724388] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1213.724392] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1213.724395] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.724398] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.724401] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.724404] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.724407] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.724410] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1213.724413] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.724416] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.724419] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.724422] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.724425] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.724428] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1213.724430] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.724433] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.724436] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1213.724439] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.724442] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.724445] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1213.724448] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1213.724451] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1213.724454] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1213.724457] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1213.724460] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1213.724463] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.724466] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.724469] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1213.724472] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.724475] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.724478] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1213.724516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1213.724539] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1213.725818] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.725845] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.727859] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.727870] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1213.729896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.729933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.731877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.731888] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.731896] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1213.732283] [IGT] kms_flip: starting subtest 2x-blocking-wf_vblank
>[ 1213.736027] [IGT] kms_flip: exiting, ret=77
>[ 1213.760165] Console: switching to colour frame buffer device 240x75
>[ 1213.866715] Console: switching to colour dummy device 80x25
>[ 1213.866943] [IGT] kms_flip: executing
>[ 1213.878628] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1213.878681] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1213.879894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.879933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.881867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1213.881878] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1213.883865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.883907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1213.885870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1213.885881] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.885889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1213.885920] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1213.885963] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1213.887086] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1213.888011] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1213.888033] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1213.888052] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1213.888069] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1213.889088] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1213.889109] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1213.890230] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1213.890234] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1213.890335] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.890338] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.890343] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1213.890346] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1213.890350] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1213.890353] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1213.890362] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1213.890365] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1213.890368] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.890371] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.890374] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.890377] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1213.890380] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.890383] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1213.890386] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.890389] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1213.890392] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1213.890395] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.890398] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1213.890401] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1213.890404] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.890407] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1213.890410] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1213.890413] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.890416] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1213.890419] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1213.890422] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1213.890425] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1213.890427] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1213.890430] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1213.890433] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1213.890436] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.890439] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1213.890442] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1213.890445] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.890448] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1213.890451] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1213.890489] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1213.890512] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1213.891823] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.891847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.893927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1213.893939] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1213.896057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.896095] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1213.898209] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1213.898220] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1213.898227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1213.898633] [IGT] kms_flip: starting subtest 2x-flip-vs-absolute-wf_vblank
>[ 1213.902011] [IGT] kms_flip: exiting, ret=77
>[ 1213.926962] Console: switching to colour frame buffer device 240x75
>[ 1214.033266] Console: switching to colour dummy device 80x25
>[ 1214.033381] [IGT] kms_flip: executing
>[ 1214.045639] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1214.045691] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1214.046879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1214.046921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1214.048859] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1214.048870] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1214.050859] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1214.050901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1214.052862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1214.052873] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1214.052881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1214.052911] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1214.052956] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1214.054049] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1214.054982] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1214.055004] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1214.055023] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1214.055040] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1214.056071] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1214.056092] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1214.057211] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1214.057215] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1214.057318] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1214.057321] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1214.057326] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1214.057328] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1214.057333] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1214.057336] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1214.057345] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1214.057348] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.057351] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.057354] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.057357] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1214.057360] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1214.057363] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1214.057366] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1214.057369] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.057372] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.057375] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1214.057378] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1214.057381] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1214.057384] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1214.057387] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1214.057390] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1214.057393] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1214.057396] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1214.057399] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1214.057402] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1214.057405] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1214.057408] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1214.057411] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1214.057414] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1214.057417] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1214.057420] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1214.057423] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1214.057425] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1214.057428] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1214.057431] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1214.057434] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1214.057473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1214.057495] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1214.058831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1214.058856] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1214.060953] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1214.060963] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1214.063083] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1214.063122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1214.065215] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1214.065225] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1214.065232] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1214.065637] [IGT] kms_flip: starting subtest 2x-flip-vs-wf_vblank
>[ 1214.068920] [IGT] kms_flip: exiting, ret=77
>[ 1214.093722] Console: switching to colour frame buffer device 240x75
>[ 1214.200773] Console: switching to colour dummy device 80x25
>[ 1214.200892] [IGT] kms_flip: executing
>[ 1214.215669] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1214.215714] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1214.217835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1214.217871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1214.219986] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1214.219997] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1214.222099] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1214.222139] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1214.224255] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1214.224266] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1214.224274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1214.224304] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1214.224346] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1214.225485] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1214.226409] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1214.226431] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1214.226450] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1214.226468] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1214.227491] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1214.227512] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1214.228628] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1214.228631] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1214.228736] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1214.228739] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1214.228781] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1214.228786] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1214.228795] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1214.228800] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1214.228817] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1214.228825] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.228832] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.228839] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.228846] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1214.228852] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1214.228858] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1214.228863] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1214.228869] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.228876] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1214.228883] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1214.228889] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1214.228897] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1214.228904] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1214.228911] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1214.228917] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1214.228923] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1214.228929] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1214.228935] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1214.228942] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1214.228949] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1214.228956] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1214.228963] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1214.228968] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1214.228974] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1214.228981] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1214.228988] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1214.228994] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1214.229000] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1214.229006] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1214.229013] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1214.229083] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1214.229117] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1214.230849] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1214.230891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1214.232832] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1214.232842] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1214.234835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1214.234875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1214.236831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1214.236842] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1214.236849] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1214.238959] [IGT] kms_flip: starting subtest flip-vs-rmfb-interruptible
>[ 1214.239560] [drm:drm_mode_addfb2] [FB:77]
>[ 1214.239591] [drm:drm_mode_addfb2] [FB:79]
>[ 1214.293483] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.293547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.310402] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.310449] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.310523] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.327552] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.327600] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.327641] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.327686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.327727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.327771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.327902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.327957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.328012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.328071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.328124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.328176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.328227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.328273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.328319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.328405] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.328479] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.328521] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.328556] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.328670] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1214.328850] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1214.328991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.329006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.329058] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.329082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.329106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.329133] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.329156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.329180] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.329204] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.329227] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.329251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.329280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.329310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.329315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.329334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.329338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.329356] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.329374] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.329391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.329408] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.329428] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.329445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.329461] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.329478] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.329494] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.329513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.329535] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.332824] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.332847] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.332868] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.332906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.332931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.332956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.332980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.333004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.333029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.333055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.333081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.333106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.333131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.333155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.333180] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.333205] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.335274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.335297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.335320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.335344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.336928] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.336949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.336968] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.338520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.338541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.340418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.343735] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.343839] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.343873] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.343904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.343974] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.344004] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.360643] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.360692] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.360757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.377300] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.377319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.394131] [drm:drm_mode_addfb2] [FB:78]
>[ 1214.394266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.427334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.427380] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.427452] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.446066] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.446110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.446142] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.446181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.446213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.446248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.446279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.446308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.446340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.446374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.446406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.446438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.446468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.446495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.446523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.446576] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.446617] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.446659] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.446693] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.447187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.447205] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.447290] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.447321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.447353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.447388] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.447417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.447448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.447479] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.447508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.447537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.447566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.447590] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.447597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.447624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.447631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.447658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.447685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.447713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.447741] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.447810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.447843] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.447873] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.447903] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.447933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.447968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.448004] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.448346] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.448380] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.448411] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.448463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.448503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.448531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.448559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.448587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.448616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.448647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.448677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.448707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.448734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.448801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.448840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.448872] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.451077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.451098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.451116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.451136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.452751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.452788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.452811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.454373] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.454396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.456287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.459607] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.459669] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.459702] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.459744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.459915] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.459965] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.476452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.476502] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.476567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.476870] [drm:drm_mode_addfb2] [FB:77]
>[ 1214.477001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.509814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.509862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.509951] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.526954] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.526998] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.527030] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.527068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.527101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.527137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.527168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.527197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.527229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.527264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.527297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.527329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.527360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.527389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.527417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.527470] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.527511] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.527553] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.527587] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.527805] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.528060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.528158] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.528190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.528223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.528258] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.528287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.528318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.528348] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.528377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.528406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.528433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.528460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.528467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.528494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.528500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.528528] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.528556] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.528583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.528609] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.528639] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.528678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.528707] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.528754] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.528817] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.528852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.528888] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.529219] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.529251] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.529282] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.529341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.529371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.529401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.529429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.529457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.529485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.529517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.529547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.529578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.529605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.529631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.529663] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.529691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.531802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.531824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.531843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.531862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.533422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.533442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.533465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.535029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.535050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.536920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.540198] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.540246] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.540279] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.540323] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.540407] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.540450] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.557033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.557084] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.557155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.557373] [drm:drm_mode_addfb2] [FB:79]
>[ 1214.557508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.590376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.590425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.590513] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.607512] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.607556] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.607588] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.607626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.607660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.607696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.607726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.607840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.607891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.607950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.608003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.608055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.608108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.608155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.608201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.608262] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.608304] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.608348] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.608383] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.608543] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.608556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.608612] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.608634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.608657] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.608682] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.608702] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.608723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.608787] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.608817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.608846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.608873] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.608901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.608908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.608934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.608942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.608970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.609010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.609036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.609063] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.609093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.609122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.609151] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.609180] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.609209] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.609242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.609276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.609352] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.609385] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.609415] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.609467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.609498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.609528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.609547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.609566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.609586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.609608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.609628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.609648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.609667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.609684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.609706] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.609727] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.611811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.611832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.611851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.611870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.613436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.613457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.613475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.615041] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.615063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.616925] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.620232] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.620309] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.620340] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.620381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.620477] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.620527] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.637090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.637139] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.637204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.637400] [drm:drm_mode_addfb2] [FB:78]
>[ 1214.637536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.670436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.670489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.670581] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.687579] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.687639] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.687680] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.687724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.687849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.687913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.687966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.688017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.688067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.688124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.688177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.688228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.688279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.688325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.688370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.688452] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.688504] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.688555] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.688598] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.688831] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.688856] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.688942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.688971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.689000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.689031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.689055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.689082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.689109] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.689134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.689159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.689182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.689205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.689211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.689232] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.689237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.689260] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.689291] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.689323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.689354] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.689387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.689421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.689444] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.689465] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.689484] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.689507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.689531] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.689594] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.689614] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.689632] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.689667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.689688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.689708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.689736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.689800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.689830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.689864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.689897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.689929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.689957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.689986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.690019] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.690049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.692137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.692160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.692182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.692206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.693797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.693818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.693837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.695402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.695424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.697290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.700577] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.700670] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.700690] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.700715] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.701000] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.701020] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.717449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.717497] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.717560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.718031] [drm:drm_mode_addfb2] [FB:77]
>[ 1214.718148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.750801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.750851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.750926] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.767959] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.768017] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.768051] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.768090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.768123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.768159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.768189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.768218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.768250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.768285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.768318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.768358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.768401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.768441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.768480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.768537] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.768584] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.768634] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.768673] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.768921] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.769258] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.769358] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.769387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.769418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.769451] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.769477] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.769507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.769534] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.769562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.769590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.769617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.769641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.769648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.769673] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.769679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.769706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.769730] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.769796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.769827] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.769857] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.769887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.769914] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.769944] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.769971] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.770004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.770039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.770408] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.770430] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.770448] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.770484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.770506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.770526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.770545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.770564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.770583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.770605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.770626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.770646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.770664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.770682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.770704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.770725] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.772997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.773021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.773044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.773069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.774644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.774665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.774683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.776251] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.776273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.778153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.781445] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.781520] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.781540] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.781565] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.781625] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.781646] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.798320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.798369] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.798435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.798649] [drm:drm_mode_addfb2] [FB:79]
>[ 1214.798853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.831662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.831715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.831883] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.850671] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.850715] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.850838] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.850898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.850951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.851008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.851057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.851105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.851155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.851213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.851265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.851317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.851370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.851416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.851462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.851548] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.851614] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.851676] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.851734] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.851994] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.852007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.852074] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.852094] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.852115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.852138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.852157] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.852177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.852196] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.852219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.852243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.852264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.852287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.852292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.852315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.852319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.852343] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.852366] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.852390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.852412] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.852436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.852469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.852492] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.852522] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.852540] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.852560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.852582] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.852640] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.852658] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.852674] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.852709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.852748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.852805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.852833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.852862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.852891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.852923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.852954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.852984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.853011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.853037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.853069] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.853098] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.855164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.855186] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.855208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.855232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.856839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.856860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.856878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.858437] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.858458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.860332] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.863647] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.863715] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.863829] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.863905] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.864020] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.864071] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.880493] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.880540] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.880603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.880932] [drm:drm_mode_addfb2] [FB:78]
>[ 1214.881119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.913839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.913885] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.913974] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1214.930968] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1214.931013] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1214.931045] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1214.931083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.931117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.931152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.931182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.931211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.931242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.931278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.931311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.931343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.931374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.931402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.931430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.931482] [drm:intel_power_well_disable [i915]] disabling display
>[ 1214.931523] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1214.931566] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.931599] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1214.931854] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1214.931880] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1214.932004] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1214.932046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1214.932093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1214.932141] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1214.932177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1214.932220] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1214.932259] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1214.932298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1214.932335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1214.932372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1214.932406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1214.932416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.932450] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1214.932459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1214.932497] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1214.932531] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1214.932567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1214.932606] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1214.932644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1214.932680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1214.932714] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1214.932788] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1214.932830] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1214.932865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.932903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1214.932988] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1214.933022] [drm:intel_power_well_enable [i915]] enabling display
>[ 1214.933053] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1214.933106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1214.933140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1214.933169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1214.933200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1214.933229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1214.933261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1214.933296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1214.933331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1214.933365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.933394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1214.933423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1214.933456] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1214.933488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1214.935566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1214.935586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1214.935605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.935624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1214.937189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1214.937209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1214.937227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1214.938798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1214.938831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1214.940729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1214.944043] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1214.944110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1214.944130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1214.944156] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1214.944217] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1214.944239] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1214.960909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1214.960959] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1214.961024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1214.961235] [drm:drm_mode_addfb2] [FB:77]
>[ 1214.961364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1214.994246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1214.994295] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1214.994368] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.012887] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.012931] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.012963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.013002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.013035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.013070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.013100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.013129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.013160] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.013195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.013227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.013268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.013310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.013350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.013390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.013448] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.013494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.013552] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.013573] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.013710] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.013755] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.013852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.013883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.013919] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.013955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.013983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.014016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.014046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.014077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.014107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.014137] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.014163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.014170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.014197] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.014203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.014232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.014259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.014287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.014313] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.014345] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.014372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.014399] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.014425] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.014453] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.014482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.014516] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.014594] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.014625] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.014654] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.014703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.014734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.014790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.014818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.014858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.014887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.014921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.014953] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.014987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.015014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.015042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.015077] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.015106] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.017176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.017199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.017219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.017239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.018827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.018847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.018864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.020423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.020444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.022308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.025621] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.025692] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.025725] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.025829] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.026041] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.026062] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.042477] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.042527] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.042592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.042981] [drm:drm_mode_addfb2] [FB:79]
>[ 1215.043111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.075818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.075866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.075940] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.092960] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.093004] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.093036] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.093079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.093120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.093164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.093204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.093244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.093284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.093328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.093371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.093413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.093456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.093495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.093534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.093592] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.093638] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.093689] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.093728] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.094044] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.094074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.094212] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.094256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.094291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.094327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.094355] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.094386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.094416] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.094447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.094475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.094503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.094529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.094537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.094563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.094570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.094598] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.094626] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.094653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.094678] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.094709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.094761] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.094792] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.094819] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.094848] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.094883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.094918] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.095005] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.095036] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.095067] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.095117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.095147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.095175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.095204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.095231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.095260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.095293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.095324] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.095356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.095382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.095409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.095443] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.095471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.097534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.097555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.097574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.097593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.099165] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.099185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.099207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.100783] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.100804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.102675] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.106003] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.106059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.106092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.106135] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.106212] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.106245] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.122834] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.122885] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.122955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.123172] [drm:drm_mode_addfb2] [FB:78]
>[ 1215.123309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.156185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.156234] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.156306] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.173329] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.173373] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.173406] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.173444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.173477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.173512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.173543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.173573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.173604] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.173640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.173673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.173705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.173822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.173865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.173912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.174002] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.174056] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.174109] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.174154] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.174347] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.174373] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.174495] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.174540] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.174586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.174635] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.174675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.174719] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.174801] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.174840] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.174884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.174925] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.174967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.174980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.175025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.175034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.175067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.175100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.175134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.175166] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.175199] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.175231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.175265] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.175297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.175326] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.175361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.175399] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.175482] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.175517] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.175550] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.175619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.175656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.175690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.175723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.175777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.175812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.175851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.175886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.175922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.175956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.175989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.176034] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.176065] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.178150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.178173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.178191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.178211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.179826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.179849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.179868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.181446] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.181469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.183346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.186635] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.186730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.186817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.186888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.186997] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.187043] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.203511] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.203560] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.203626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.203952] [drm:drm_mode_addfb2] [FB:77]
>[ 1215.204070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.236847] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.236893] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.236961] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.253955] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.253999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.254031] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.254070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.254103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.254138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.254169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.254198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.254230] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.254265] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.254298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.254331] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.254362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.254390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.254417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.254471] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.254512] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.254561] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.254600] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.254846] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.254872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.254997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.255042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.255089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.255138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.255179] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.255223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.255267] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.255308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.255349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.255388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.255427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.255437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.255474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.255483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.255522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.255561] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.255601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.255638] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.255681] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.255720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.255795] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.255835] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.255867] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.255902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.255937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.256034] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.256067] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.256097] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.256147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.256179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.256209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.256239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.256269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.256300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.256335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.256368] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.256400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.256429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.256458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.256492] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.256523] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.258594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.258615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.258633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.258652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.260253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.260276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.260299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.261854] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.261877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.263756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.267100] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.267174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.267194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.267220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.267281] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.267302] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.283970] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.284020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.284086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.284284] [drm:drm_mode_addfb2] [FB:79]
>[ 1215.284418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.317310] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.317358] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.317432] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.336154] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.336199] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.336232] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.336271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.336304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.336339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.336369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.336398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.336430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.336465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.336497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.336529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.336559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.336599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.336623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.336668] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.336702] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.336815] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.336864] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.337072] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.337096] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.337211] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.337250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.337293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.337340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.337377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.337418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.337457] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.337496] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.337533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.337572] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.337614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.337621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.337648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.337654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.337684] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.337710] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.337762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.337788] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.337822] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.337849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.337878] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.337905] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.337933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.337964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.337999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.338074] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.338105] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.338134] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.338183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.338213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.338245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.338271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.338299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.338327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.338358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.338390] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.338421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.338447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.338475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.338508] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.338536] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.340602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.340623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.340641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.340659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.342246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.342268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.342287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.343868] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.343891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.345763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.348994] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.349029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.349053] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.349084] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.349147] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.349168] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.365826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.365876] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.365940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.366137] [drm:drm_mode_addfb2] [FB:78]
>[ 1215.366272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.399172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.399221] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.399293] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.417643] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.417692] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.417814] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.417875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.417922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.417974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.418017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.418062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.418107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.418161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.418212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.418262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.418312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.418353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.418402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.418456] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.418498] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.418538] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.418572] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.418746] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.418760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.418855] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.418887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.418920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.418955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.418984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.419006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.419026] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.419049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.419073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.419097] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.419120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.419125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.419148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.419152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.419175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.419196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.419219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.419240] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.419264] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.419287] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.419310] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.419333] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.419356] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.419381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.419406] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.419457] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.419478] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.419497] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.419533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.419557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.419580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.419604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.419627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.419651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.419676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.419701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.419778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.419816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.419848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.419885] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.419917] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.422013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.422036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.422055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.422074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.423647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.423668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.423687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.425291] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.425312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.427182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.430180] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.430264] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.430296] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.430346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.430444] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.430494] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.447043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.447093] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.447159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.447375] [drm:drm_mode_addfb2] [FB:77]
>[ 1215.447504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.480386] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.480434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.480507] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.497526] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.497570] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.497602] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.497646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.497687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.497818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.497872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.497923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.497974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.498032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.498086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.498121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.498162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.498194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.498213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.498249] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.498277] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.498306] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.498328] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.498444] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.498457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.498513] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.498535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.498558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.498583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.498604] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.498625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.498646] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.498667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.498693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.498753] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.498781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.498801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.498828] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.498836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.498864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.498891] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.498918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.498944] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.498975] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.499001] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.499028] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.499056] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.499082] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.499112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.499144] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.499219] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.499251] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.499282] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.499333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.499366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.499397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.499427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.499457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.499489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.499522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.499553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.499575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.499594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.499612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.499634] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.499655] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.501719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.501764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.501783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.501802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.503369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.503390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.503408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.504960] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.504981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.506857] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.510199] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.510292] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.510324] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.510367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.510428] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.510449] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.527072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.527124] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.527194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.527395] [drm:drm_mode_addfb2] [FB:79]
>[ 1215.527537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.560418] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.560467] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.560540] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.577545] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.577601] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.577634] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.577672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.577706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.577823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.577870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.577919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.577966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.578022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.578072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.578122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.578171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.578212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.578256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.578339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.578403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.578468] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.578521] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.578797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.578810] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.578875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.578901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.578927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.578957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.578990] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.579012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.579034] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.579054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.579078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.579099] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.579121] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.579126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.579149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.579153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.579177] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.579200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.579223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.579245] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.579269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.579292] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.579315] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.579338] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.579361] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.579386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.579411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.579462] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.579482] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.579502] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.579538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.579562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.579586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.579609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.579633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.579656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.579701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.579769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.579804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.579836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.579867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.579904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.579938] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.582013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.582034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.582053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.582072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.583636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.583656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.583674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.585279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.585300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.587188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.590532] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.590626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.590666] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.590717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.591104] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.591125] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.607403] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.607453] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.607518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.607953] [drm:drm_mode_addfb2] [FB:78]
>[ 1215.608073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.640774] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.640822] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.640896] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.657911] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.657959] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.658000] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.658044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.658085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.658129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.658170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.658209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.658249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.658293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.658336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.658379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.658414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.658437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.658460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.658495] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.658524] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.658555] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.658578] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.658740] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.658761] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.658858] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.658893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.658928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.658966] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.658996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.659030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.659063] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.659094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.659126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.659156] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.659186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.659207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.659234] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.659241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.659271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.659301] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.659330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.659359] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.659392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.659422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.659451] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.659481] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.659510] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.659543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.659578] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.659674] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.659732] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.659761] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.659814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.659847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.659879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.659911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.659942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.659974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.660010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.660045] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.660079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.660109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.660140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.660176] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.660208] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.662303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.662324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.662342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.662361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.663923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.663945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.663964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.665504] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.665525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.667391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.670675] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.670773] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.670807] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.670852] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.670923] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.670945] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.687512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.687561] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.687627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.687992] [drm:drm_mode_addfb2] [FB:77]
>[ 1215.688128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.720865] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.720912] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.720985] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.738007] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.738051] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.738084] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.738123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.738156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.738192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.738222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.738252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.738284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.738319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.738353] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.738385] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.738416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.738444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.738473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.738526] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.738567] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.738609] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.738643] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.738930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.738959] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.739093] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.739146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.739181] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.739218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.739249] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.739282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.739315] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.739346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.739377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.739407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.739437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.739444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.739472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.739480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.739509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.739538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.739567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.739597] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.739630] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.739659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.739686] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.739741] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.739770] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.739805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.739841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.739933] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.739965] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.739995] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.740045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.740076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.740107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.740135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.740165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.740197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.740232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.740266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.740298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.740327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.740356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.740390] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.740421] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.742504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.742526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.742545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.742565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.744140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.744160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.744178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.745754] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.745778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.747650] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.751011] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.751084] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.751116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.751158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.751253] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.751313] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.767863] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.767913] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.767978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.768190] [drm:drm_mode_addfb2] [FB:79]
>[ 1215.768320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.801211] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.801260] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.801349] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.818351] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.818398] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.818439] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.818483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.818524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.818568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.818608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.818647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.818687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.818821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.818860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.818894] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.818927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.818955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.818984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.819039] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.819080] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.819122] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.819157] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.819335] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.819353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.819429] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.819450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.819472] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.819496] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.819514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.819535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.819555] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.819573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.819592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.819609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.819626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.819630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.819647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.819651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.819668] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.819695] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.819762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.819792] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.819827] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.819858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.819889] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.819920] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.819949] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.819984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.820019] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.820099] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.820132] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.820162] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.820213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.820245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.820276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.820306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.820335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.820366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.820400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.820433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.820464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.820494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.820522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.820557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.820589] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.822658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.822680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.822754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.822789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.824344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.824364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.824382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.825943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.825965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.827833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.831127] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.831208] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.831234] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.831267] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.831344] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.831384] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.847985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.848033] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.848096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.848308] [drm:drm_mode_addfb2] [FB:78]
>[ 1215.848435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.881343] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.881391] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.881480] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.898497] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.898541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.898573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.898612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.898646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.898681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.898795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.898840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.898891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.898948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.898998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.899050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.899098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.899139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.899183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.899263] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.899327] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.899389] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.899443] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.899609] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.899632] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.899700] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.899766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.899803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.899843] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.899875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.899911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.899945] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.899979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.900011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.900041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.900071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.900080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.900108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.900117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.900147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.900176] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.900205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.900233] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.900263] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.900291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.900321] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.900347] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.900376] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.900406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.900440] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.900515] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.900547] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.900587] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.900638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.900670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.900723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.900753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.900785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.900818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.900852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.900886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.900919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.900948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.900978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.901013] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.901045] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.903128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.903150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.903169] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.903188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.904788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.904808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.904826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.906382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.906406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.908280] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.911565] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.911668] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.911750] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.911798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.911873] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.911905] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1215.928444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.928493] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.928558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.928877] [drm:drm_mode_addfb2] [FB:77]
>[ 1215.929086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.961790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1215.961838] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1215.961911] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1215.978936] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1215.978980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1215.979012] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1215.979050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.979083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.979118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.979149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.979178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.979210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1215.979245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.979286] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.979316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.979345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.979372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.979397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.979448] [drm:intel_power_well_disable [i915]] disabling display
>[ 1215.979487] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1215.979526] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1215.979558] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1215.979810] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1215.979839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1215.979979] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1215.980029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1215.980081] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1215.980136] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1215.980181] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1215.980230] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1215.980279] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1215.980329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1215.980368] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1215.980406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1215.980443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1215.980453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.980488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1215.980497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1215.980534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1215.980572] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1215.980610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1215.980647] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1215.980687] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1215.980768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1215.980804] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1215.980843] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1215.980880] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1215.980922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1215.980967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1215.981060] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1215.981100] [drm:intel_power_well_enable [i915]] enabling display
>[ 1215.981138] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1215.981200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1215.981240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1215.981278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1215.981317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1215.981347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1215.981378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1215.981413] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1215.981446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1215.981479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1215.981509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1215.981539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1215.981574] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1215.981605] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1215.983733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1215.983755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1215.983773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.983797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1215.985372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1215.985393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1215.985412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1215.986962] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1215.986984] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1215.988854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1215.992175] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1215.992241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1215.992281] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1215.992332] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1215.992413] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1215.992453] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.009018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.009068] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.009133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.009331] [drm:drm_mode_addfb2] [FB:79]
>[ 1216.009453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.042366] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.042415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.042489] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.059515] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.059558] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.059591] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.059629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.059662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.059779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.059829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.059878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.059928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.059978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.060022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.060069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.060112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.060148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.060187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.060263] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.060320] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.060376] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.060423] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.060608] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.060627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.060796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.060843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.060893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.060942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.060972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.061006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.061040] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.061073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.061104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.061135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.061165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.061172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.061201] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.061208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.061237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.061267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.061297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.061326] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.061360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.061390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.061420] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.061450] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.061479] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.061511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.061546] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.061651] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.061682] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.061757] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.061811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.061845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.061877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.061908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.061940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.061971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.062007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.062040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.062073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.062103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.062132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.062167] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.062199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.064289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.064312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.064331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.064350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.065929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.065950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.065968] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.067517] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.067538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.069400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.072758] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.072836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.072869] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.072911] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.072995] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.073035] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.089611] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.089661] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.089799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.090058] [drm:drm_mode_addfb2] [FB:78]
>[ 1216.090171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.122954] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.123002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.123092] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.141898] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.141942] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.141975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.142013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.142047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.142082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.142113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.142142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.142174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.142209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.142242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.142274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.142304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.142332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.142359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.142412] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.142454] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.142495] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.142530] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.142784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.142812] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.142945] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.142993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.143043] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.143094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.143137] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.143184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.143229] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.143275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.143318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.143360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.143402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.143413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.143453] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.143463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.143504] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.143545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.143585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.143625] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.143670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.143748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.143781] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.143816] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.143850] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.143937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.143977] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.144063] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.144099] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.144133] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.144190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.144226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.144261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.144296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.144330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.144366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.144405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.144442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.144479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.144512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.144545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.144584] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.144620] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.146733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.146754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.146772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.146791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.148368] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.148390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.148410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.149975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.149997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.151868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.155170] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.155247] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.155275] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.155310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.155392] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.155434] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.172035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.172088] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.172159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.172360] [drm:drm_mode_addfb2] [FB:77]
>[ 1216.172499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.205376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.205424] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.205514] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.222522] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.222566] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.222599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.222642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.222684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.222808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.222857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.222907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.222954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.223009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.223060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.223110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.223159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.223200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.223243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.223327] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.223391] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.223454] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.223489] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.223661] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.223708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.223799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.223826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.223852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.223881] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.223913] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.223937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.223961] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.223984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.224008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.224031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.224054] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.224058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.224081] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.224085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.224109] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.224130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.224153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.224176] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.224220] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.224242] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.224272] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.224290] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.224307] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.224327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.224349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.224407] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.224425] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.224441] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.224473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.224491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.224508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.224525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.224542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.224560] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.224580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.224598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.224616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.224633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.224655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.224726] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.224758] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.226845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.226867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.226886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.226910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.228484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.228505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.228523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.230083] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.230105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.231980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.235312] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.235363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.235396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.235437] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.235531] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.235581] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.252145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.252194] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.252260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.252472] [drm:drm_mode_addfb2] [FB:79]
>[ 1216.252601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.285468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.285513] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.285603] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.304601] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.304645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.304678] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.304801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.304849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.304903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.304947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.304993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.305037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.305091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.305141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.305192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.305240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.305266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.305294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.305348] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.305390] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.305430] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.305464] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.305635] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.305648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.305781] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.305815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.305851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.305889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.305920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.305953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.305993] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.306023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.306052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.306081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.306109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.306116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.306143] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.306149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.306177] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.306204] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.306231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.306256] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.306285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.306313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.306341] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.306368] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.306393] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.306434] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.306477] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.306546] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.306576] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.306604] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.306650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.306690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.306756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.306789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.306821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.306853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.306889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.306924] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.306957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.306987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.307017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.307052] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.307084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.309182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.309204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.309223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.309243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.310847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.310871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.310894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.312456] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.312478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.314343] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.317591] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.317661] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.317744] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.317791] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.317869] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.317901] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.334458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.334508] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.334572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.334910] [drm:drm_mode_addfb2] [FB:78]
>[ 1216.335107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.367798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.367847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.367921] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.386748] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.386797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.386837] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.386882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.386922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.386966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.387007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.387046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.387091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.387128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.387160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.387191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.387221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.387248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.387274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.387324] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.387363] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.387404] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.387436] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.387637] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.387730] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.387875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.387926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.387978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.388033] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.388078] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.388134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.388180] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.388225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.388269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.388310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.388350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.388361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.388400] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.388410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.388450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.388491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.388532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.388572] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.388617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.388657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.388785] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.388827] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.388870] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.388917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.388965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.389093] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.389137] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.389167] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.389218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.389250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.389280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.389310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.389337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.389367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.389402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.389435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.389467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.389497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.389526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.389560] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.389591] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.391738] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.391761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.391779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.391801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.393398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.393421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.393440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.394994] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.395016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.396878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.400204] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.400261] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.400299] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.400325] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.400386] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.400407] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.417046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.417095] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.417161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.417377] [drm:drm_mode_addfb2] [FB:77]
>[ 1216.417511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.450385] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.450434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.450508] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.469546] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.469590] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.469623] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.469662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.469779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.469837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.469895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.469941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.469989] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.470027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.470060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.470090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.470121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.470147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.470174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.470226] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.470266] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.470306] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.470338] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.470488] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.470506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.470585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.470616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.470650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.470753] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.470796] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.470843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.470886] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.470932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.470965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.470998] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.471029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.471039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.471070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.471079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.471111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.471194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.471228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.471262] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.471300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.471335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.471369] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.471404] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.471437] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.471477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.471512] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.471571] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.471594] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.471616] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.471655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.471712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.471745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.471778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.471810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.471843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.471880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.471923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.471953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.471979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.472008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.472041] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.472069] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.474160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.474184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.474207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.474231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.475799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.475820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.475839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.477401] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.477422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.479293] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.482005] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.482070] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.482089] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.482115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.482175] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.482196] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.498852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.498904] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.498975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.499194] [drm:drm_mode_addfb2] [FB:79]
>[ 1216.499315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.532195] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.532248] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.532324] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.550605] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.550649] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.550764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.550823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.550870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.550925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.550969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.551014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.551060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.551113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.551164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.551214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.551263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.551304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.551347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.551428] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.551494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.551556] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.551606] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.551802] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.551822] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.551898] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.551921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.551954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.551977] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.551995] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.552015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.552036] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.552055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.552073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.552091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.552107] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.552112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.552128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.552132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.552149] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.552165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.552181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.552197] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.552217] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.552233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.552249] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.552265] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.552288] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.552312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.552338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.552386] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.552407] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.552427] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.552462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.552486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.552510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.552534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.552557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.552580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.552606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.552631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.552655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.552747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.552778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.552812] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.552842] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.554932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.554954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.554976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.555001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.556566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.556588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.556607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.558190] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.558211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.560100] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.563443] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.563539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.563579] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.563630] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.563896] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.563925] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.580311] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.580362] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.580431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.580866] [drm:drm_mode_addfb2] [FB:78]
>[ 1216.581030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.613672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.613755] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.613830] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.630861] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.630905] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.630937] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.630975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.631009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.631044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.631074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.631103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.631134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.631169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.631201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.631239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.631266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.631291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.631316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.631363] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.631402] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.631447] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.631482] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.631696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.631724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.631858] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.631905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.631955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.632007] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.632050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.632096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.632143] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.632187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.632230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.632279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.632316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.632326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.632361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.632370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.632407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.632444] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.632482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.632518] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.632559] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.632595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.632632] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.632668] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.632728] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.632770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.632813] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.632907] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.632947] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.632985] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.633047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.633087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.633126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.633163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.633201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.633240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.633285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.633319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.633351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.633381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.633410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.633445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.633477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.635552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.635573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.635591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.635613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.637191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.637211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.637229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.638800] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.638821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.640711] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.644042] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.644095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.644128] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.644170] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.644268] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.644319] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.660876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.660926] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.660991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.661252] [drm:drm_mode_addfb2] [FB:77]
>[ 1216.661396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.694221] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.694274] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.694366] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.711375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.711419] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.711458] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.711504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.711544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.711589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.711629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.711669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.711791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.711854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.711911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.711964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.712019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.712050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.712080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.712137] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.712181] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.712222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.712257] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.712412] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.712425] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.712491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.712515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.712539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.712566] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.712589] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.712613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.712637] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.712722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.712754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.712783] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.712811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.712820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.712847] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.712855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.712883] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.712910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.712937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.712965] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.712996] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.713026] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.713056] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.713084] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.713113] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.713147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.713182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.713261] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.713293] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.713325] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.713370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.713392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.713412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.713431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.713450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.713475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.713503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.713531] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.713560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.713586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.713612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.713638] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.713689] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.715764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.715785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.715807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.715832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.717403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.717424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.717443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.719007] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.719028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.720897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.724224] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.724265] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.724289] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.724320] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.724382] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.724413] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.741064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.741114] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.741180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.741417] [drm:drm_mode_addfb2] [FB:79]
>[ 1216.741564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.774407] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.774455] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.774545] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.791550] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.791593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.791626] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.791665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.791783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.791843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.791890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.791937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.791982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.792036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.792087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.792138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.792187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.792228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.792271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.792354] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.792418] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.792480] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.792534] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.792751] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.792771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.792862] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.792886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.792910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.792935] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.792964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.792984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.793004] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.793023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.793041] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.793059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.793076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.793080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.793097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.793101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.793118] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.793135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.793152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.793168] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.793187] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.793204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.793220] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.793236] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.793252] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.793272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.793293] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.793350] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.793368] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.793385] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.793416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.793435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.793452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.793469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.793485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.793502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.793522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.793540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.793564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.793588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.793610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.793635] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.793725] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.795813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.795836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.795854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.795874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.797441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.797463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.797482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.799051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.799072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.800933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.804240] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.804316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.804353] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.804401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.804495] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.804542] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.821102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.821152] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.821217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.821415] [drm:drm_mode_addfb2] [FB:78]
>[ 1216.821553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.854437] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.854485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.854575] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.872737] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.872780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.872812] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.872850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.872884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.872919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.872950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.872979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.873010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.873045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.873086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.873129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.873172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.873211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.873250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.873308] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.873356] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.873416] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.873438] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.873576] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.873589] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.873658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.873734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.873773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.873812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.873843] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.873879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.873913] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.873947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.873980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.874012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.874042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.874051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.874079] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.874086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.874116] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.874147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.874176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.874205] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.874237] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.874266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.874295] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.874324] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.874353] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.874386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.874420] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.874520] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.874553] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.874584] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.874635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.874690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.874721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.874754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.874785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.874814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.874849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.874882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.874916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.874945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.874975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.875010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.875042] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.877119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.877142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.877160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.877179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.878779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.878801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.878820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.880378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.880399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.882284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.885576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.885701] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.885738] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.885781] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.885856] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.885878] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.902448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.902500] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.902572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.902919] [drm:drm_mode_addfb2] [FB:77]
>[ 1216.903044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.935813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1216.935859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1216.935928] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1216.952936] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1216.952981] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1216.953014] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1216.953052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.953085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.953120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.953150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.953179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.953210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.953245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.953278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.953310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.953342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.953369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.953396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.953450] [drm:intel_power_well_disable [i915]] disabling display
>[ 1216.953491] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1216.953533] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.953567] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1216.953784] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1216.953814] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1216.953962] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1216.954017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.954073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1216.954131] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.954176] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1216.954209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.954243] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1216.954275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1216.954306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1216.954336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1216.954365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.954373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.954401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.954408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1216.954438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1216.954467] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1216.954497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.954525] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1216.954558] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1216.954587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.954617] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1216.954646] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1216.954715] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1216.954749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.954784] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1216.954860] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1216.954892] [drm:intel_power_well_enable [i915]] enabling display
>[ 1216.954923] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1216.954973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1216.955006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1216.955036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1216.955063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1216.955092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1216.955123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1216.955158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1216.955191] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1216.955223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.955252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1216.955281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1216.955316] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1216.955347] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1216.957428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1216.957451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1216.957470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.957489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1216.959063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1216.959084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1216.959103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1216.960660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1216.960692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1216.962560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1216.965920] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1216.965994] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1216.966033] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1216.966085] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1216.966167] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1216.966207] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1216.982774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1216.982824] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1216.982889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1216.983124] [drm:drm_mode_addfb2] [FB:79]
>[ 1216.983267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.016115] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.016168] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.016244] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.034970] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.035014] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.035047] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.035085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.035119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.035154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.035184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.035214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.035245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.035280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.035313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.035345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.035376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.035403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.035431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.035485] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.035526] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.035569] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.035603] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.035882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.035902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.035991] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.036021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.036054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.036090] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.036118] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.036149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.036179] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.036209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.036238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.036266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.036293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.036300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.036327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.036333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.036362] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.036388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.036417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.036444] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.036475] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.036501] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.036531] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.036556] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.036584] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.036613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.036647] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.036758] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.036790] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.036819] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.036870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.036900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.036927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.036956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.036983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.037012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.037046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.037078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.037109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.037135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.037163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.037198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.037226] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.039301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.039323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.039343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.039362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.040941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.040965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.040985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.042526] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.042548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.044420] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.047761] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.047855] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.047888] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.047938] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.048020] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.048061] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.064634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.064718] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.064783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.065020] [drm:drm_mode_addfb2] [FB:78]
>[ 1217.065168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.097994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.098063] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.098134] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.116414] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.116458] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.116490] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.116529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.116561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.116596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.116627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.116714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.116770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.116830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.116884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.116934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.116984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.117025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.117069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.117153] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.117218] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.117279] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.117332] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.117577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.117595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.117719] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.117754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.117791] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.117829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.117860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.117894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.117928] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.117961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.117993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.118023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.118053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.118060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.118089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.118097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.118126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.118156] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.118186] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.118215] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.118248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.118278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.118305] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.118335] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.118364] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.118397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.118431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.118506] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.118538] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.118569] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.118619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.118695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.118727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.118759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.118789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.118822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.118857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.118891] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.118924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.118954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.118984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.119020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.119051] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.121148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.121171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.121190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.121214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.122883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.122903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.122922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.124470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.124491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.126355] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.129700] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.129791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.129824] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.129860] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.129921] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.129943] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.146573] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.146623] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.146886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.147096] [drm:drm_mode_addfb2] [FB:77]
>[ 1217.147224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.179914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.179963] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.180035] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.197059] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.197107] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.197147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.197192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.197232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.197277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.197317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.197356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.197396] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.197440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.197483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.197525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.197568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.197607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.197646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.197800] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.197870] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.197942] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.197999] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.198243] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.198263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.198342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.198365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.198389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.198414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.198433] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.198456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.198478] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.198499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.198519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.198539] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.198557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.198562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.198580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.198584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.198604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.198624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.198681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.198708] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.198738] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.198765] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.198792] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.198818] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.198845] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.198877] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.198910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.198986] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.199018] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.199048] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.199100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.199132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.199163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.199195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.199226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.199257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.199284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.199305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.199326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.199344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.199363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.199385] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.199407] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.201455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.201477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.201495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.201514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.203086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.203105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.203123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.204678] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.204699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.206557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.209348] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.209437] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.209470] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.209516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.209577] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.209598] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.226215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.226265] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.226331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.226551] [drm:drm_mode_addfb2] [FB:79]
>[ 1217.226764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.259573] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.259622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.259807] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.278573] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.278616] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.278734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.278797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.278853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.278911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.278960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.279008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.279059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.279119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.279153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.279186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.279219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.279249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.279277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.279333] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.279376] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.279422] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.279455] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.279616] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.279664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.279758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.279782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.279805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.279830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.279850] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.279872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.279893] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.279914] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.279936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.279961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.279986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.279993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.280025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.280034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.280058] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.280078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.280096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.280114] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.280136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.280155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.280173] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.280191] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.280209] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.280230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.280253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.280305] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.280325] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.280343] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.280377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.280402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.280428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.280453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.280479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.280505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.280533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.280560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.280587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.280613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.280668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.280702] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.280733] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.282804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.282825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.282843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.282862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.284432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.284453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.284474] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.286039] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.286061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.287929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.291259] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.291312] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.291346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.291391] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.291453] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.291475] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.308092] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.308145] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.308216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.308456] [drm:drm_mode_addfb2] [FB:78]
>[ 1217.308592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.341428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.341477] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.341568] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.358756] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.358802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.358824] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.358851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.358875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.358899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.358920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.358940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.358962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.358986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.359009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.359031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.359052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.359072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.359091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.359129] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.359158] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.359188] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.359212] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.359363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.359377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.359445] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.359472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.359499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.359528] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.359551] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.359576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.359601] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.359625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.359705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.359741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.359775] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.359784] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.359816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.359825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.359878] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.359920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.359962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.360005] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.360051] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.360094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.360135] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.360177] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.360218] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.360266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.360314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.360480] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.360524] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.360566] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.360635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.360714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.360757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.360799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.360840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.360879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.360912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.360945] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.360979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.361008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.361039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.361075] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.361107] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.363291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.363313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.363332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.363351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.364914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.364935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.364952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.366497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.366520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.368362] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.371153] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.371225] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.371248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.371279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.371340] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.371370] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.387999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.388045] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.388109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.388346] [drm:drm_mode_addfb2] [FB:77]
>[ 1217.388473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.421367] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.421416] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.421506] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.438490] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.438534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.438567] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.438606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.438722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.438779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.438825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.438872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.438918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.438974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.439025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.439074] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.439125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.439166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.439209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.439295] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.439360] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.439412] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.439446] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.439648] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.439669] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.439759] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.439783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.439815] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.439838] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.439857] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.439877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.439898] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.439917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.439936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.439953] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.439970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.439974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.439991] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.439994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.440011] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.440028] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.440045] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.440060] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.440080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.440096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.440112] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.440135] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.440159] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.440184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.440209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.440269] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.440290] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.440310] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.440346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.440370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.440393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.440417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.440440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.440463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.440488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.440514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.440538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.440562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.440605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.440672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.440703] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.442773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.442796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.442815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.442834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.444396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.444417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.444435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.445999] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.446020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.447891] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.451251] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.451325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.451357] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.451400] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.451496] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.451546] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.468113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.468163] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.468228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.468444] [drm:drm_mode_addfb2] [FB:79]
>[ 1217.468595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.501449] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.501498] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.501586] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.518621] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.518700] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.518751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.518798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.518832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.518868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.518898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.518927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.518958] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.518994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.519027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.519058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.519089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.519117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.519154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.519188] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.519216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.519247] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.519270] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.519408] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.519420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.519479] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.519502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.519527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.519555] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.519579] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.519605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.519684] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.519714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.519745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.519773] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.519800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.519808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.519835] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.519843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.519870] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.519897] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.519924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.519950] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.519981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.520007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.520035] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.520061] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.520087] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.520119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.520151] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.520247] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.520280] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.520310] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.520362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.520395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.520427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.520458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.520487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.520518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.520553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.520583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.520605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.520662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.520688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.520721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.520749] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.522825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.522849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.522869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.522890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.524454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.524475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.524493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.526058] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.526079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.527947] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.531275] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.531329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.531362] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.531410] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.531470] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.531500] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.548115] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.548165] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.548234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.548477] [drm:drm_mode_addfb2] [FB:78]
>[ 1217.548625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.581456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.581505] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.581594] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.598624] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.598702] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.598734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.598772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.598805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.598840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.598870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.598898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.598930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.598973] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.599017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.599047] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.599082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.599124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.599152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.599203] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.599242] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.599281] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.599313] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.599512] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.599530] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.599619] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.599728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.599780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.599832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.599875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.599922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.599967] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.600022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.600068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.600111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.600153] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.600166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.600211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.600222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.600269] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.600311] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.600353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.600398] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.600449] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.600494] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.600539] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.600584] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.600628] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.600721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.600775] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.600894] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.600941] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.600984] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.601050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.601082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.601113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.601144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.601174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.601201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.601236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.601258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.601278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.601296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.601315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.601337] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.601358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.603407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.603428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.603446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.603465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.605055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.605078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.605097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.606680] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.606702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.608572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.611839] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.611902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.611932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.611972] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.612062] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.612109] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.628675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.628725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.628795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.629036] [drm:drm_mode_addfb2] [FB:77]
>[ 1217.629180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.662032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.662081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.662171] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.679185] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.679229] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.679262] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.679300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.679334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.679369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.679400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.679429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.679461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.679496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.679528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.679560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.679591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.679625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.679720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.679794] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.679852] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.679908] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.679954] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.680164] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.680188] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.680303] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.680346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.680391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.680439] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.680480] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.680523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.680566] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.680608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.680685] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.680717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.680747] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.680756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.680786] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.680794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.680825] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.680856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.680887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.680917] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.680951] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.680981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.681013] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.681042] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.681073] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.681107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.681142] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.681229] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.681261] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.681291] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.681342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.681374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.681405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.681435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.681465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.681496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.681530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.681562] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.681594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.681649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.681680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.681716] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.681748] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.683810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.683831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.683850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.683869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.685438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.685458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.685476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.687037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.687057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.688927] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.692228] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.692311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.692342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.692382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.692471] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.692520] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.709101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.709151] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.709216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.709451] [drm:drm_mode_addfb2] [FB:79]
>[ 1217.709604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.742436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.742489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.742583] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.759624] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.759712] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.759744] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.759782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.759815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.759850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.759881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.759910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.759941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.759976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.760009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.760040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.760071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.760099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.760127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.760180] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.760221] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.760262] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.760296] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.760465] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.760477] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.760535] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.760558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.760581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.760620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.760699] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.760736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.760772] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.760805] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.760838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.760869] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.760900] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.760908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.760937] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.760945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.760975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.761005] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.761036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.761066] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.761100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.761130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.761161] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.761189] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.761218] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.761252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.761287] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.761363] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.761396] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.761427] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.761477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.761508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.761536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.761564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.761590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.761620] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.761678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.761713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.761747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.761777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.761805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.761882] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.761913] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.763993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.764015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.764034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.764053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.765617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.765653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.765672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.767223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.767245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.769106] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.772421] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.772489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.772522] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.772564] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.772704] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.772737] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.789276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.789327] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.789392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.789658] [drm:drm_mode_addfb2] [FB:78]
>[ 1217.789835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.822616] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.822701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.822794] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.839784] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.839829] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.839862] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.839900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.839933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.839968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.839998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.840027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.840059] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.840102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.840134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.840171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.840212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.840249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.840286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.840340] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.840384] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.840432] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.840469] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.840705] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.840734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.840873] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.840925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.840977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.841032] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.841078] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.841130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.841172] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.841212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.841252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.841290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.841327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.841336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.841372] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.841381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.841418] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.841455] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.841492] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.841528] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.841568] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.841604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.841680] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.841716] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.841754] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.841799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.841843] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.841938] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.841978] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.842017] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.842097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.842139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.842170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.842201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.842228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.842259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.842294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.842327] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.842359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.842389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.842418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.842452] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.842484] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.844564] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.844586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.844605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.844683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.846249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.846272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.846290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.847842] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.847863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.849724] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.853037] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.853107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.853139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.853181] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.853276] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.853321] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.869890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.869940] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.870005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.870218] [drm:drm_mode_addfb2] [FB:77]
>[ 1217.870346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.903234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.903283] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.903381] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1217.921546] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1217.921590] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1217.921710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1217.921770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.921823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.921880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.921937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.921977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.922007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.922040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.922071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.922107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.922146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.922182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.922218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.922270] [drm:intel_power_well_disable [i915]] disabling display
>[ 1217.922313] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1217.922372] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.922410] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1217.922562] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1217.922580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1217.922750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1217.922797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1217.922844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1217.922898] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1217.922949] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1217.922983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1217.923016] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1217.923047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1217.923078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1217.923100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1217.923118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1217.923124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.923142] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1217.923146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1217.923165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1217.923183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1217.923202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1217.923219] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1217.923241] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1217.923259] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1217.923285] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1217.923311] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1217.923335] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1217.923362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.923391] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1217.923444] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1217.923468] [drm:intel_power_well_enable [i915]] enabling display
>[ 1217.923489] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1217.923529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1217.923555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1217.923581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1217.923608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1217.923663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1217.923696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1217.923729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1217.923760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1217.923791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.923818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1217.923845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1217.923878] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1217.923907] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1217.925977] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1217.925998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1217.926017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.926036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1217.927601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1217.927633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1217.927651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1217.929224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1217.929245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1217.931137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1217.934456] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1217.934513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1217.934546] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1217.934590] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1217.934928] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1217.934962] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1217.951304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1217.951354] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1217.951418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1217.951698] [drm:drm_mode_addfb2] [FB:79]
>[ 1217.951900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1217.984674] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1217.984722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1217.984796] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.002441] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.002485] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.002517] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.002555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.002588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.002711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.002763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.002813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.002865] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.002923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.002961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.002995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.003026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.003056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.003084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.003139] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.003181] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.003224] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.003259] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.003427] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.003447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.003532] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.003571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.003624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.003728] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.003757] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.003789] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.003820] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.003851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.003881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.003908] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.003935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.003943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.003972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.003979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.004008] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.004035] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.004061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.004090] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.004122] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.004151] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.004180] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.004209] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.004239] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.004272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.004307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.004366] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.004386] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.004404] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.004438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.004458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.004477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.004496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.004514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.004533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.004555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.004575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.004594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.004646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.004673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.004705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.004734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.006804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.006825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.006844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.006863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.008434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.008455] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.008473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.010037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.010058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.011919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.015212] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.015309] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.015338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.015374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.015441] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.015474] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.032086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.032136] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.032229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.032440] [drm:drm_mode_addfb2] [FB:78]
>[ 1218.032568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.065429] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.065478] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.065550] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.082568] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.082612] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.082737] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.082797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.082849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.082904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.082953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.083002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.083048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.083104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.083157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.083208] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.083259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.083305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.083358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.083413] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.083456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.083497] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.083532] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.083732] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.083745] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.083810] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.083834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.083865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.083889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.083907] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.083927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.083947] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.083966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.083985] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.084007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.084031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.084035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.084059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.084063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.084087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.084110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.084133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.084156] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.084179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.084201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.084224] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.084247] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.084270] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.084295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.084320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.084380] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.084401] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.084421] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.084456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.084481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.084505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.084528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.084551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.084574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.084600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.084688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.084723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.084751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.084780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.084814] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.084843] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.086914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.086935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.086954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.086973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.088550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.088573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.088591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.090193] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.090214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.092127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.095438] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.095511] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.095544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.095586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.095904] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.095933] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.112293] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.112343] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.112409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.112868] [drm:drm_mode_addfb2] [FB:77]
>[ 1218.113001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.145666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.145715] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.145792] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.164160] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.164205] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.164238] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.164277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.164310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.164346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.164377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.164406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.164438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.164474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.164507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.164539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.164570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.164598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.164714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.164799] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.164867] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.164931] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.164986] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.165228] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.165255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.165380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.165421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.165482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.165530] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.165567] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.165611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.165690] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.165729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.165771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.165808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.165847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.165857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.165893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.165904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.165944] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.165980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.166018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.166052] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.166097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.166123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.166151] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.166177] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.166205] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.166235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.166268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.166347] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.166379] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.166408] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.166458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.166488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.166516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.166545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.166571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.166602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.166656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.166690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.166724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.166751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.166780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.166816] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.166845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.168930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.168952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.168971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.168990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.170654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.170690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.170710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.172299] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.172321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.174192] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.177210] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.177265] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.177285] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.177311] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.177375] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.177397] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.194065] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.194115] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.194181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.194418] [drm:drm_mode_addfb2] [FB:79]
>[ 1218.194537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.227411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.227461] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.227536] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.244552] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.244596] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.244725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.244786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.244838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.244894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.244942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.244990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.245040] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.245097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.245149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.245200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.245251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.245297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.245343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.245428] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.245494] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.245558] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.245652] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.245799] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.245812] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.245872] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.245894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.245925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.245948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.245966] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.245986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.246005] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.246024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.246042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.246059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.246076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.246080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.246096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.246100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.246117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.246134] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.246150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.246166] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.246185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.246201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.246218] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.246234] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.246250] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.246269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.246290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.246348] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.246366] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.246382] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.246413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.246432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.246449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.246466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.246488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.246512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.246537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.246562] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.246601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.246649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.246684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.246720] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.246753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.248829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.248850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.248868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.248888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.250463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.250484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.250504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.252061] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.252091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.253980] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.257285] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.257360] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.257389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.257427] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.257498] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.257527] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.274155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.274205] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.274270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.274485] [drm:drm_mode_addfb2] [FB:78]
>[ 1218.274611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.307502] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.307550] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.307711] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.324729] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.324773] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.324805] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.324844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.324878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.324913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.324944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.324974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.325011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.325056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.325099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.325141] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.325183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.325223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.325262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.325319] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.325366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.325406] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.325427] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.325561] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.325619] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.325717] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.325751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.325787] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.325825] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.325856] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.325890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.325923] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.325955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.325987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.326018] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.326048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.326055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.326084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.326103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.326131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.326162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.326191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.326219] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.326252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.326281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.326310] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.326339] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.326367] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.326400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.326435] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.326513] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.326545] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.326575] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.326652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.326686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.326719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.326752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.326782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.326815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.326851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.326885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.326919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.326950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.326982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.327017] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.327049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.329120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.329141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.329159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.329178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.330781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.330803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.330822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.332373] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.332404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.334277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.337591] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.337697] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.337717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.337742] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.337802] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.337832] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.354496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.354545] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.354690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.354982] [drm:drm_mode_addfb2] [FB:77]
>[ 1218.355120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.387837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.387884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.387974] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.404987] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.405035] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.405076] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.405120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.405161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.405206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.405246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.405285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.405325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.405370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.405412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.405455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.405497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.405536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.405575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.405720] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.405789] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.405857] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.405912] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.406145] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.406163] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.406253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.406286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.406321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.406358] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.406389] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.406422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.406456] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.406487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.406519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.406549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.406578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.406613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.406645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.406653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.406687] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.406717] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.406745] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.406775] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.406809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.406839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.406870] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.406900] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.406930] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.406966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.407000] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.407091] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.407123] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.407154] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.407205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.407237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.407268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.407299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.407329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.407360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.407394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.407428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.407460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.407489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.407520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.407553] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.407585] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.409668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.409689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.409708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.409727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.411289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.411309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.411327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.412889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.412910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.414782] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.418074] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.418164] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.418197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.418239] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.418335] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.418388] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.434949] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.435015] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.435079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.435317] [drm:drm_mode_addfb2] [FB:79]
>[ 1218.435461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.468289] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.468337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.468427] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.485412] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.485456] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.485489] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.485527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.485561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.485681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.485739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.485788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.485849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.485897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.485942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.485985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.486027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.486066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.486105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.486171] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.486226] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.486279] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.486326] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.486507] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.486523] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.486724] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.486771] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.486819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.486870] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.486905] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.486930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.486954] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.486977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.486999] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.487020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.487040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.487045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.487065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.487070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.487090] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.487109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.487130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.487148] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.487173] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.487199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.487228] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.487257] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.487284] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.487314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.487344] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.487404] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.487428] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.487451] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.487493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.487521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.487551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.487579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.487643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.487678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.487715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.487749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.487783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.487812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.487841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.487877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.487914] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.489989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.490010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.490029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.490048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.491636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.491656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.491679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.493247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.493269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.495141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.498391] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.498472] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.498503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.498542] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.498681] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.498731] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.515258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.515308] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.515374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.515836] [drm:drm_mode_addfb2] [FB:78]
>[ 1218.515978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.548598] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.548682] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.548773] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.565761] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.565809] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.565850] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.565894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.565935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.565979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.566019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.566059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.566098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.566143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.566186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.566228] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.566270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.566309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.566348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.566406] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.566452] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.566502] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.566541] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.567028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.567055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.567141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.567170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.567201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.567234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.567260] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.567290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.567318] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.567346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.567372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.567399] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.567423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.567430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.567455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.567461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.567487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.567511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.567537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.567561] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.567631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.567661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.567690] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.567718] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.567749] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.567784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.567819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.568138] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.568159] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.568177] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.568212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.568235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.568255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.568280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.568306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.568331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.568359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.568386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.568413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.568438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.568463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.568489] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.568515] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.570557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.570578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.570650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.570680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.572362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.572385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.572408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.573964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.573985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.575855] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.579120] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.579185] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.579220] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.579266] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.579353] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.579400] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.595971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.596020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.596086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.596298] [drm:drm_mode_addfb2] [FB:77]
>[ 1218.596414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.629312] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.629363] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.629453] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.647553] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.647677] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.647724] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.647782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.647828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.647880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.647923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.647968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.648013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.648067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.648118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.648168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.648217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.648258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.648301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.648372] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.648414] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.648460] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.648492] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.648664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.648685] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.648782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.648816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.648851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.648896] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.648924] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.648955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.648987] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.649016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.649046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.649074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.649098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.649105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.649131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.649137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.649164] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.649191] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.649217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.649267] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.649309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.649344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.649374] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.649399] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.649427] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.649459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.649492] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.649634] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.649669] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.649698] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.649751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.649786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.649818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.649850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.649880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.649913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.649948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.649981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.650013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.650044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.650074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.650108] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.650139] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.652226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.652250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.652273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.652297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.653865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.653887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.653906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.655466] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.655494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.657363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.660643] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.660678] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.660698] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.660724] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.660783] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.660813] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.677478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.677527] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.677668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.677987] [drm:drm_mode_addfb2] [FB:79]
>[ 1218.678104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.710824] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.710872] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.710962] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.727967] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.728015] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.728056] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.728100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.728140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.728185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.728224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.728265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.728304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.728349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.728391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.728434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.728476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.728515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.728554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.728705] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.728773] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.728842] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.728896] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.729103] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.729121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.729210] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.729240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.729274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.729310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.729338] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.729370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.729400] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.729430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.729458] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.729487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.729517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.729524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.729552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.729583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.729615] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.729643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.729672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.729699] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.729732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.729759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.729788] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.729815] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.729845] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.729875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.729908] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.729998] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.730029] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.730058] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.730107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.730138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.730165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.730194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.730221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.730250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.730283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.730314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.730346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.730372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.730399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.730434] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.730462] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.732516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.732537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.732555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.732618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.734188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.734208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.734226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.735788] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.735809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.737680] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.741022] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.741115] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.741147] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.741190] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.741270] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.741300] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.757896] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.757946] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.758010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.758221] [drm:drm_mode_addfb2] [FB:78]
>[ 1218.758349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.791237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.791286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.791376] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.808387] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.808432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.808464] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.808508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.808550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.808676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.808724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.808775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.808825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.808874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.808918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.808963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.809006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.809042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.809081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.809155] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.809214] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.809269] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.809316] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.809522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.809540] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.809710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.809759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.809816] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.809859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.809894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.809933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.809970] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.810005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.810028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.810050] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.810071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.810077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.810098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.810103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.810125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.810145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.810167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.810187] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.810215] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.810248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.810280] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.810312] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.810343] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.810379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.810417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.810522] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.810558] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.810616] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.810675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.810710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.810744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.810776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.810815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.810845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.810877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.810908] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.810939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.810967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.810994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.811027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.811057] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.813156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.813178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.813197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.813216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.814789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.814810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.814828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.816380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.816403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.818277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.821618] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.821712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.821745] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.821787] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.821883] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.821933] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.838494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.838544] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.838705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.838973] [drm:drm_mode_addfb2] [FB:77]
>[ 1218.839102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.871838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.871887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.871977] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.888988] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.889032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.889064] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.889103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.889142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.889187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.889227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.889267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.889306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.889351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.889394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.889439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.889463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.889486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.889509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.889545] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.889639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.889686] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.889723] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.889883] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.889900] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.889989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.890023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.890058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.890096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.890127] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.890161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.890194] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.890225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.890256] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.890286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.890315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.890323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.890351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.890358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.890388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.890418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.890447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.890477] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.890511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.890540] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.890569] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.890622] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.890652] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.890686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.890722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.890813] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.890845] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.890876] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.890925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.890957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.890987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.891018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.891048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.891079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.891113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.891146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.891178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.891208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.891237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.891271] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.891302] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.893376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.893401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.893424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.893448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.895029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.895051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.895070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.896687] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.896709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.898566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.901883] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.901963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.901991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.902026] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.902109] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.902152] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.918752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.918802] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.918867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.919082] [drm:drm_mode_addfb2] [FB:79]
>[ 1218.919214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.952095] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1218.952146] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1218.952236] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1218.969256] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1218.969300] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1218.969333] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1218.969371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.969405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.969440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.969470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.969499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.969531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.969566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.969680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.969735] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.969788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.969830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.969875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.969961] [drm:intel_power_well_disable [i915]] disabling display
>[ 1218.970025] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1218.970087] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.970139] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1218.970303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1218.970322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1218.970410] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1218.970439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1218.970474] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1218.970510] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1218.970540] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1218.970573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1218.970629] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1218.970659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1218.970690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1218.970717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1218.970747] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1218.970755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.970784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1218.970791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1218.970821] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1218.970848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1218.970877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1218.970906] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1218.970939] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1218.970965] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1218.970993] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1218.971020] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1218.971047] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1218.971076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1218.971109] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1218.971198] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1218.971229] [drm:intel_power_well_enable [i915]] enabling display
>[ 1218.971258] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1218.971307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1218.971335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1218.971364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1218.971390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1218.971419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1218.971446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1218.971478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1218.971509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1218.971540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.971569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1218.971620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1218.971652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1218.971685] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1218.973748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1218.973769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1218.973788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.973807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1218.975372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1218.975392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1218.975411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1218.976973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1218.976997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1218.978860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1218.982133] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1218.982190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1218.982223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1218.982264] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1218.982358] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1218.982412] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1218.998978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1218.999027] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1218.999093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1218.999301] [drm:drm_mode_addfb2] [FB:78]
>[ 1218.999433] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.032315] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.032363] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.032452] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.050660] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.050704] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.050743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.050789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.050830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.050874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.050915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.050955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.050995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.051040] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.051082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.051125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.051167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.051206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.051245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.051303] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.051350] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.051401] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.051440] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.051697] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.051728] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.051881] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.051940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.051987] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.052024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.052051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.052081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.052110] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.052143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.052177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.052212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.052245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.052253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.052285] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.052292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.052326] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.052360] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.052395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.052435] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.052477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.052506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.052532] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.052558] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.052626] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.052669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.052712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.052836] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.052880] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.052929] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.052982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.053015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.053047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.053077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.053097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.053117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.053140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.053161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.053188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.053214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.053239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.053267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.053293] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.055358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.055381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.055400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.055419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.056993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.057014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.057032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.058604] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.058627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.060480] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.063836] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.063919] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.063959] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.064011] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.064111] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.064159] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.080696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.080746] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.080811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.081025] [drm:drm_mode_addfb2] [FB:77]
>[ 1219.081141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.114039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.114087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.114178] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.131194] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.131238] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.131277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.131322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.131363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.131407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.131447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.131487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.131532] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.131640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.131694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.131746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.131796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.131836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.131880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.131961] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.132028] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.132090] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.132145] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.132360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.132389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.132514] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.132548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.132617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.132656] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.132689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.132725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.132770] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.132801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.132832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.132863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.132892] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.132899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.132930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.132937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.132968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.132997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.133024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.133053] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.133085] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.133115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.133144] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.133171] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.133200] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.133233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.133268] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.133348] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.133381] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.133412] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.133463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.133494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.133525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.133555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.133604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.133637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.133673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.133707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.133740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.133770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.133801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.133836] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.133868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.135934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.135958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.135978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.135999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.137556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.137593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.137612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.139176] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.139197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.141081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.144397] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.144465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.144498] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.144541] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.144834] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.144860] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.161246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.161296] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.161362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.161640] [drm:drm_mode_addfb2] [FB:79]
>[ 1219.161836] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.194621] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.194669] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.194744] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.211719] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.211762] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.211798] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.211838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.211874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.211913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.211948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.211983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.212018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.212058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.212102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.212132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.212160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.212183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.212206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.212249] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.212282] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.212317] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.212345] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.212522] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.212592] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.212715] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.212758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.212802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.212850] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.212889] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.212932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.212969] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.212997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.213022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.213048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.213071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.213078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.213108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.213113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.213137] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.213158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.213180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.213200] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.213227] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.213248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.213270] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.213300] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.213331] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.213364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.213398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.213478] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.213506] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.213533] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.213620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.213657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.213693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.213728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.213762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.213797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.213836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.213873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.213909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.213941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.213973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.214011] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.214046] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.216153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.216184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.216202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.216222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.217794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.217814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.217833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.219400] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.219423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.221298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.224564] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.224677] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.224706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.224747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.224822] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.224857] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.241466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.241517] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.241675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.241940] [drm:drm_mode_addfb2] [FB:78]
>[ 1219.242068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.274809] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.274861] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.274938] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.291952] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.291996] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.292029] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.292067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.292101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.292136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.292167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.292197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.292229] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.292264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.292297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.292329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.292361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.292389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.292417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.292470] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.292512] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.292554] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.292694] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.292857] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.292876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.292963] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.292996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.293031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.293069] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.293100] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.293134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.293167] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.293199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.293231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.293261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.293291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.293298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.293326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.293334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.293363] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.293393] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.293422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.293451] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.293485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.293514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.293544] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.293600] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.293631] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.293662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.293698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.293789] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.293822] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.293852] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.293902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.293933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.293961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.293990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.294021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.294053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.294087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.294119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.294151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.294180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.294209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.294243] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.294275] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.296339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.296360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.296378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.296397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.297969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.297989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.298007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.299554] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.299602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.301471] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.304786] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.304853] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.304886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.304928] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.304993] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.305023] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.321637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.321687] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.321751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.322009] [drm:drm_mode_addfb2] [FB:77]
>[ 1219.322138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.354981] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.355033] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.355110] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.372135] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.372179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.372212] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.372250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.372284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.372319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.372350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.372379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.372411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.372446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.372479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.372511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.372542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.372653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.372699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.372780] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.372848] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.372911] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.372966] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.373211] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.373240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.373382] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.373415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.373451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.373488] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.373519] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.373552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.373608] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.373640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.373672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.373704] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.373736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.373744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.373774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.373782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.373813] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.373842] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.373873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.373899] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.373933] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.373963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.373993] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.374022] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.374048] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.374080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.374114] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.374205] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.374238] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.374269] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.374318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.374350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.374382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.374412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.374442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.374472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.374506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.374539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.374597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.374629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.374660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.374696] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.374728] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.376786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.376808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.376828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.376849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.378411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.378431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.378450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.380002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.380025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.381895] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.385205] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.385278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.385310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.385351] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.385428] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.385461] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.402061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.402110] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.402175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.402385] [drm:drm_mode_addfb2] [FB:79]
>[ 1219.402516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.435405] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.435457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.435534] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.452628] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.452672] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.452704] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.452742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.452775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.452811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.452841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.452869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.452900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.452936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.452968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.452999] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.453030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.453057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.453089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.453123] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.453148] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.453174] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.453195] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.453333] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.453345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.453403] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.453425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.453451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.453479] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.453503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.453528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.453612] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.453643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.453672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.453701] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.453728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.453737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.453764] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.453771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.453799] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.453825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.453852] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.453878] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.453909] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.453935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.453962] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.453989] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.454015] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.454046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.454081] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.454159] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.454192] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.454223] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.454276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.454308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.454340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.454370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.454400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.454434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.454468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.454496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.454518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.454536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.454582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.454613] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.454643] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.456724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.456746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.456765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.456784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.458348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.458368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.458387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.459951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.459972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.461841] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.465171] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.465224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.465257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.465299] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.465376] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.465403] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.482007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.482057] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.482121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.482378] [drm:drm_mode_addfb2] [FB:78]
>[ 1219.482493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.515351] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.515400] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.515472] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.532489] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.532533] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.532659] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.532721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.532773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.532829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.532877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.532925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.532974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.533031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.533083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.533134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.533186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.533229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.533274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.533359] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.533425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.533487] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.533544] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.533781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.533794] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.533859] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.533882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.533906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.533933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.533956] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.533980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.534004] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.534027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.534051] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.534071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.534094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.534099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.534122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.534126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.534149] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.534173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.534196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.534218] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.534242] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.534264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.534288] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.534311] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.534334] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.534359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.534384] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.534441] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.534462] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.534482] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.534517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.534541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.534615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.534648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.534682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.534715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.534752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.534787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.534821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.534853] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.534884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.534920] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.534953] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.537044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.537066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.537085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.537104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.538671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.538692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.538710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.540259] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.540280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.542149] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.544902] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.544979] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.545007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.545043] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.545111] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.545144] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.561751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.561799] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.561862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.562076] [drm:drm_mode_addfb2] [FB:77]
>[ 1219.562201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.595097] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.595146] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.595235] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.613540] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.613615] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.613648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.613686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.613720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.613755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.613785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.613813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.613845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.613880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.613913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.613945] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.613976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.614004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.614032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.614086] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.614127] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.614169] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.614203] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.614414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.614434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.614528] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.614651] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.614706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.614761] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.614807] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.614857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.614904] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.614950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.614994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.615038] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.615079] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.615092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.615136] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.615148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.615193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.615235] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.615277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.615318] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.615368] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.615413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.615461] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.615512] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.615541] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.615601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.615635] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.615731] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.615764] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.615793] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.615848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.615880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.615912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.615943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.615972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.615993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.616016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.616037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.616057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.616075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.616093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.616115] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.616136] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.618357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.618380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.618398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.618418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.619993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.620013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.620031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.621578] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.621601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.623452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.626769] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.626820] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.626839] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.626869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.626930] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.626960] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.643620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.643673] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.643744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.643964] [drm:drm_mode_addfb2] [FB:79]
>[ 1219.644097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.676960] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.677008] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.677097] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.694114] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.694158] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.694191] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.694234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.694276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.694320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.694360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.694400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.694439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.694484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.694527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.694653] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.694715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.694765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.694815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.694903] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.694969] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.695034] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.695089] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.695313] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.695333] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.695431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.695459] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.695491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.695534] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.695594] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.695630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.695662] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.695695] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.695739] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.695766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.695796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.695803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.695831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.695839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.695869] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.695895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.695923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.695949] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.695980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.696006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.696034] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.696060] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.696088] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.696121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.696155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.696231] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.696264] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.696293] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.696343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.696371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.696400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.696427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.696455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.696483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.696515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.696568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.696601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.696629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.696658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.696693] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.696722] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.698793] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.698815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.698836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.698860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.700431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.700451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.700470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.702045] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.702066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.703950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.707279] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.707335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.707375] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.707426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.707519] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.707609] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.724113] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.724164] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.724229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.724423] [drm:drm_mode_addfb2] [FB:78]
>[ 1219.724645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.757468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.757519] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.757708] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.776485] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.776534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.776653] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.776718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.776774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.776832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.776878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.776927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.776977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.777028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.777061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.777094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.777127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.777156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.777185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.777241] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.777283] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.777330] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.777363] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.777586] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.777606] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.777697] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.777720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.777744] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.777773] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.777803] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.777824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.777845] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.777863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.777881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.777898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.777914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.777918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.777934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.777938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.777960] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.777984] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.778014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.778032] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.778053] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.778071] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.778088] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.778105] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.778122] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.778142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.778164] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.778221] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.778239] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.778256] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.778288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.778313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.778337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.778362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.778386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.778410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.778437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.778463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.778489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.778513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.778622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.778657] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.778686] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.780757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.780779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.780798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.780818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.782392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.782412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.782431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.783992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.784013] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.785882] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.789197] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.789250] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.789273] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.789304] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.789368] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.789394] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.806035] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.806085] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.806150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.806365] [drm:drm_mode_addfb2] [FB:77]
>[ 1219.806496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.839394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.839442] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.839516] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.856608] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.856656] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.856707] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.856760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.856800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.856845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.856886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.856926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.856966] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.857010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.857053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.857096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.857138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.857178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.857216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.857274] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.857321] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.857371] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.857410] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.857687] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.857713] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.857839] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.857885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.857933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.857984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.858016] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.858047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.858076] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.858104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.858131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.858158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.858190] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.858198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.858230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.858237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.858271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.858305] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.858339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.858373] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.858408] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.858441] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.858476] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.858510] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.858586] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.858636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.858671] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.858767] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.858800] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.858833] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.858887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.858920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.858953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.858982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.859001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.859026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.859055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.859083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.859111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.859137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.859163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.859191] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.859216] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.861285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.861307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.861326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.861345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.862921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.862949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.862973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.864528] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.864565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.866437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.869799] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.869855] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.869874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.869900] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.869961] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.869982] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.886654] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.886703] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.886769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.886979] [drm:drm_mode_addfb2] [FB:79]
>[ 1219.887094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.919988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1219.920034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1219.920124] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1219.937147] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1219.937195] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1219.937236] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1219.937280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.937321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.937366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.937406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.937446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.937485] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.937530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.937637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.937696] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.937751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.937796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.937843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.937929] [drm:intel_power_well_disable [i915]] disabling display
>[ 1219.937994] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1219.938057] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.938111] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1219.938336] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1219.938356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1219.938451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1219.938492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1219.938536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1219.938608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1219.938639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1219.938674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1219.938708] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1219.938740] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1219.938773] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1219.938803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1219.938833] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1219.938840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.938869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1219.938876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1219.938906] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1219.938936] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1219.938963] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1219.938992] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1219.939024] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1219.939053] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1219.939080] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1219.939110] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1219.939140] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1219.939174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1219.939208] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1219.939285] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1219.939317] [drm:intel_power_well_enable [i915]] enabling display
>[ 1219.939347] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1219.939398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1219.939430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1219.939461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1219.939491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1219.939521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1219.939575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1219.939611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1219.939646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1219.939679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.939709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1219.939740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1219.939775] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1219.939806] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1219.941876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1219.941896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1219.941914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.941933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1219.943522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1219.943559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1219.943578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1219.945156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1219.945179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1219.947051] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1219.950364] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1219.950436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1219.950476] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1219.950528] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1219.950814] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1219.950836] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1219.967214] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1219.967267] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1219.967338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1219.967626] [drm:drm_mode_addfb2] [FB:78]
>[ 1219.967800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.000585] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.000633] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.000707] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.018934] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.018978] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.019010] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.019049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.019083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.019118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.019148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.019176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.019208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.019243] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.019276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.019321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.019352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.019380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.019408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.019461] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.019502] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.019631] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.019688] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.019923] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.019951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.020090] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.020150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.020185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.020222] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.020251] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.020283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.020312] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.020344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.020374] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.020403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.020428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.020436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.020463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.020469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.020498] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.020551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.020581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.020608] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.020640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.020668] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.020697] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.020724] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.020754] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.020788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.020823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.020914] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.020946] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.020977] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.021029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.021061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.021092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.021119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.021145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.021175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.021208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.021240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.021272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.021298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.021326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.021356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.021387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.023456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.023479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.023499] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.023569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.025143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.025163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.025182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.026755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.026779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.028644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.032002] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.032078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.032111] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.032153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.032231] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.032264] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.048844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.048892] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.048955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.049175] [drm:drm_mode_addfb2] [FB:77]
>[ 1220.049301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.082219] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.082272] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.082351] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.100456] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.100501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.100618] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.100676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.100724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.100777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.100820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.100874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.100912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.100958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.101001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.101043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.101084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.101118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.101154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.101226] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.101280] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.101334] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.101379] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.101692] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.101716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.101799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.101830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.101861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.101904] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.101934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.101965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.101995] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.102025] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.102056] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.102081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.102111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.102117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.102146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.102151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.102182] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.102209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.102238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.102265] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.102296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.102325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.102355] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.102385] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.102415] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.102446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.102479] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.102597] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.102637] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.102675] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.102738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.102781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.102820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.102859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.102902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.102935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.102971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.103005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.103039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.103070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.103100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.103134] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.103166] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.105240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.105261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.105280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.105299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.106863] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.106883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.106901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.108447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.108468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.110333] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.113675] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.113768] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.113801] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.113843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.113922] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.113955] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.130572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.130619] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.130682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.130895] [drm:drm_mode_addfb2] [FB:79]
>[ 1220.131019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.163891] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.163936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.164006] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.182452] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.182495] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.182620] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.182684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.182736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.182792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.182840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.182888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.182938] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.182995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.183048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.183099] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.183151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.183197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.183242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.183327] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.183393] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.183455] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.183513] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.183772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.183788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.183861] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.183890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.183920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.183953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.183978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.184006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.184034] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.184060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.184085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.184110] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.184133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.184139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.184163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.184168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.184193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.184216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.184248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.184282] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.184315] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.184347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.184381] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.184414] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.184447] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.184482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.184518] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.184675] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.184720] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.184763] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.184820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.184857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.184891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.184924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.184957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.184992] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.185029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.185064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.185100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.185132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.185164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.185201] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.185235] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.187341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.187363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.187382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.187401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.188978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.188998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.189016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.190620] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.190642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.192515] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.195849] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.195909] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.195928] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.195954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.196015] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.196036] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.212695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.212745] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.212810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.213007] [drm:drm_mode_addfb2] [FB:78]
>[ 1220.213143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.246036] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.246084] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.246157] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.264601] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.264649] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.264690] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.264735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.264775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.264819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.264860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.264900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.264939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.264984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.265027] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.265069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.265111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.265151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.265190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.265248] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.265294] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.265351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.265372] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.265546] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.265567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.265661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.265684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.265709] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.265735] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.265756] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.265778] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.265800] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.265821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.265841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.265866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.265891] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.265897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.265922] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.265927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.265953] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.265979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.266005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.266031] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.266057] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.266082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.266106] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.266127] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.266147] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.266170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.266194] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.266246] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.266266] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.266284] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.266319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.266340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.266365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.266391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.266417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.266443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.266471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.266499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.266594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.266625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.266654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.266687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.266716] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.268799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.268821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.268840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.268859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.270433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.270454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.270473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.272069] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.272090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.273978] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.277332] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.277412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.277444] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.277486] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.277824] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.277851] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.294199] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.294249] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.294316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.294796] [drm:drm_mode_addfb2] [FB:77]
>[ 1220.294930] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.327584] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.327653] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.327726] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.344741] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.344785] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.344818] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.344856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.344889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.344924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.344955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.344993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.345034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.345078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.345121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.345164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.345206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.345252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.345273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.345307] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.345332] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.345360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.345380] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.345540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.345560] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.345659] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.345693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.345728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.345765] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.345795] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.345829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.345862] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.345894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.345925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.345956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.345985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.345992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.346021] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.346028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.346057] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.346087] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.346116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.346145] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.346177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.346206] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.346236] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.346265] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.346294] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.346327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.346362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.346460] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.346491] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.346550] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.346606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.346639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.346672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.346704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.346734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.346767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.346802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.346837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.346870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.346901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.346931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.346967] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.346999] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.349111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.349132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.349150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.349169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.350760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.350792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.350811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.352373] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.352395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.354269] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.357568] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.357635] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.357655] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.357680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.357741] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.357762] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.374432] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.374482] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.374646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.374906] [drm:drm_mode_addfb2] [FB:79]
>[ 1220.375018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.407777] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.407826] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.407917] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.424929] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.424973] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.425005] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.425044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.425077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.425113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.425144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.425173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.425204] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.425240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.425273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.425305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.425336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.425364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.425392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.425445] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.425486] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.425615] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.425674] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.425920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.425951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.426069] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.426101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.426135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.426171] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.426200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.426232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.426262] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.426293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.426321] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.426350] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.426376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.426383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.426410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.426417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.426446] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.426472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.426501] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.426558] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.426589] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.426619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.426646] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.426677] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.426705] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.426740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.426774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.426906] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.426938] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.426967] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.427017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.427049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.427077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.427105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.427132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.427162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.427195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.427227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.427259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.427285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.427313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.427347] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.427375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.429455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.429477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.429496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.429573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.431133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.431153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.431171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.432736] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.432759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.434628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.437966] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.438066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.438105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.438157] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.438239] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.438278] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.454852] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.454901] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.454966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.455168] [drm:drm_mode_addfb2] [FB:78]
>[ 1220.455299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.488216] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.488270] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.488340] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.506437] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.506482] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.506605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.506664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.506717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.506783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.506819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.506848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.506878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.506914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.506946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.506976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.507007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.507033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.507061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.507113] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.507158] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.507206] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.507257] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.507423] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.507441] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.507594] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.507640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.507689] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.507741] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.507792] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.507823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.507853] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.507882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.507911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.507938] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.507965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.507974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.507999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.508007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.508037] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.508066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.508094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.508122] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.508155] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.508183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.508213] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.508242] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.508271] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.508304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.508339] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.508413] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.508435] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.508453] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.508487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.508536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.508564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.508593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.508619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.508648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.508679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.508710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.508742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.508770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.508797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.508832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.508863] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.510941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.510964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.510983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.511003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.512623] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.512647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.512670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.514230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.514252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.516125] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.519409] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.519510] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.519622] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.519691] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.520011] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.520046] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.536289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.536339] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.536404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.536889] [drm:drm_mode_addfb2] [FB:77]
>[ 1220.537023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.569635] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.569687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.569766] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.586787] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.586835] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.586876] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.586921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.586962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.587006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.587046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.587086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.587125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.587170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.587212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.587255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.587297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.587336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.587376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.587427] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.587452] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.587481] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.587567] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.587757] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.587777] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.587873] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.587904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.587938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.587975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.588003] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.588035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.588065] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.588096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.588124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.588153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.588179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.588186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.588213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.588220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.588248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.588274] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.588303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.588329] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.588361] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.588387] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.588415] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.588441] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.588468] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.588501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.588563] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.588640] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.588672] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.588702] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.588751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.588779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.588809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.588836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.588864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.588892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.588926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.588958] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.588989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.589015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.589043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.589074] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.589103] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.591172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.591194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.591213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.591232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.592813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.592833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.592852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.594397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.594418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.596290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.599634] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.599709] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.599728] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.599754] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.599814] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.599836] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.616509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.616593] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.616659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.616900] [drm:drm_mode_addfb2] [FB:79]
>[ 1220.617078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.649851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.649900] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.649972] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.667026] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.667070] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.667101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.667139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.667173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.667207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.667237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.667266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.667298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.667333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.667365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.667395] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.667426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.667454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.667491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.667634] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.667703] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.667768] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.667825] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.668065] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.668084] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.668175] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.668209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.668244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.668281] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.668312] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.668346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.668378] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.668409] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.668441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.668471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.668526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.668535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.668565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.668573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.668604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.668635] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.668665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.668695] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.668729] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.668759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.668789] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.668816] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.668847] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.668881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.668916] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.669006] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.669039] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.669069] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.669120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.669151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.669182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.669211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.669241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.669272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.669305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.669337] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.669369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.669398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.669427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.669461] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.669492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.671578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.671599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.671618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.671636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.673206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.673226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.673244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.674807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.674828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.676702] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.680014] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.680085] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.680118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.680161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.680243] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.680264] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.696869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.696919] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.696984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.697217] [drm:drm_mode_addfb2] [FB:78]
>[ 1220.697372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.730211] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.730260] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.730334] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.747348] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.747392] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.747424] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.747463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.747496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.747624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.747676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.747726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.747785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.747833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.747877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.747920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.747963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.748002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.748040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.748113] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.748168] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.748221] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.748268] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.748450] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.748467] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.748638] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.748680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.748724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.748772] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.748817] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.748852] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.748884] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.748918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.748948] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.748979] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.749007] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.749015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.749044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.749051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.749082] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.749110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.749140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.749167] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.749201] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.749229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.749259] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.749287] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.749317] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.749352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.749389] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.749471] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.749531] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.749566] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.749621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.749654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.749689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.749719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.749753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.749784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.749828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.749862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.749897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.749924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.749951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.749986] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.750015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.752114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.752136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.752155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.752175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.753751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.753772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.753790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.755339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.755360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.757232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.760543] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.760614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.760646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.760688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.760765] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.760798] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.777399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.777448] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.777602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.777866] [drm:drm_mode_addfb2] [FB:77]
>[ 1220.777979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.810731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.810780] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.810854] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.827877] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.827921] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.827954] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.827993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.828026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.828061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.828091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.828120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.828152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.828187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.828220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.828251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.828282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.828310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.828338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.828392] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.828441] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.828478] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.828559] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.828709] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.828727] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.828815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.828849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.828884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.828922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.828953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.828986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.829018] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.829050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.829082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.829112] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.829141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.829149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.829177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.829184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.829213] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.829242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.829273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.829302] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.829334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.829364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.829395] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.829424] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.829455] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.829488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.829545] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.829637] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.829670] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.829700] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.829751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.829783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.829811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.829841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.829867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.829899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.829932] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.829965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.829997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.830027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.830056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.830090] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.830122] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.832181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.832202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.832221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.832239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.833816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.833836] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.833855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.835402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.835423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.837286] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.840634] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.840704] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.840723] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.840748] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.840808] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.840829] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.857503] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.857587] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.857653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.857870] [drm:drm_mode_addfb2] [FB:79]
>[ 1220.858018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.890846] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.890895] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.890967] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.908020] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.908065] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.908096] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.908135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.908175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.908220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.908260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.908300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.908340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.908385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.908427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.908470] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.908588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.908647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.908698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.908786] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.908852] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.908917] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.908972] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.909179] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.909198] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.909286] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.909320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.909356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.909392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.909423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.909456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.909489] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.909548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.909581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.909613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.909645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.909654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.909683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.909691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.909721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.909751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.909782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.909809] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.909842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.909872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.909902] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.909933] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.909962] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.909996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.910030] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.910120] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.910152] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.910183] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.910232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.910264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.910294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.910324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.910354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.910385] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.910418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.910450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.910483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.910534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.910565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.910600] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.910632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.912694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.912715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.912734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.912753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.914314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.914334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.914352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.915914] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.915935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.917805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1220.921131] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1220.921187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1220.921220] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1220.921261] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1220.921343] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1220.921363] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1220.937971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.938020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.938086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.938296] [drm:drm_mode_addfb2] [FB:78]
>[ 1220.938425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.971313] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1220.971361] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1220.971434] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1220.988468] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1220.988546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1220.988587] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1220.988631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.988672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.988716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.988756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.988796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.988843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1220.988880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.988911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.988940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.988968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.988993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.989017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.989065] [drm:intel_power_well_disable [i915]] disabling display
>[ 1220.989102] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1220.989140] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1220.989170] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1220.989359] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1220.989390] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1220.989485] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1220.989576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1220.989623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1220.989673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1220.989713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1220.989758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1220.989800] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1220.989841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1220.989881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1220.989920] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1220.989961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1220.989972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.990011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1220.990024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1220.990062] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1220.990104] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1220.990145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1220.990184] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1220.990229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1220.990269] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1220.990311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1220.990351] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1220.990390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1220.990436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1220.990484] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1220.990626] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1220.990671] [drm:intel_power_well_enable [i915]] enabling display
>[ 1220.990713] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1220.990780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1220.990811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1220.990837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1220.990865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1220.990894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1220.990915] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1220.990937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1220.990957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1220.990978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1220.990996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1220.991015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1220.991037] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1220.991062] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1220.993127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1220.993149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1220.993168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.993187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1220.994754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1220.994774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1220.994792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1220.996340] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1220.996361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1220.998233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.001573] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.001669] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.001701] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.001743] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.001820] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.001854] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.018449] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.018585] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.018687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.018993] [drm:drm_mode_addfb2] [FB:77]
>[ 1221.019129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.051793] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.051845] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.051923] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.068941] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.068985] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.069019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.069057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.069091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.069126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.069157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.069186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.069217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.069260] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.069302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.069345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.069387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.069426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.069466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.069596] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.069639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.069683] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.069719] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.069882] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.069901] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.069990] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.070020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.070053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.070089] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.070117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.070149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.070179] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.070208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.070236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.070264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.070290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.070297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.070323] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.070330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.070359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.070384] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.070412] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.070437] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.070469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.070523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.070551] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.070580] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.070607] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.070641] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.070675] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.070765] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.070796] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.070826] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.070875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.070906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.070933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.070962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.070988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.071018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.071051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.071082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.071113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.071139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.071168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.071201] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.071230] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.073305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.073327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.073346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.073365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.074935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.074955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.074973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.076528] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.076549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.078412] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.081747] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.081849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.081868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.081894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.081956] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.081977] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.098635] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.098685] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.098750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.098968] [drm:drm_mode_addfb2] [FB:79]
>[ 1221.099101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.132011] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.132060] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.132138] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.149135] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.149183] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.149224] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.149268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.149309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.149353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.149393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.149433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.149472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.149608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.149665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.149704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.149739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.149769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.149798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.149852] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.149894] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.149938] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.149975] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.150153] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.150171] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.150301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.150323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.150346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.150370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.150391] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.150412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.150434] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.150454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.150517] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.150547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.150575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.150583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.150609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.150617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.150644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.150670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.150697] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.150723] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.150754] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.150780] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.150806] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.150832] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.150859] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.150889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.150921] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.150998] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.151031] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.151062] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.151114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.151148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.151179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.151211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.151242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.151273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.151301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.151329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.151356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.151381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.151407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.151434] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.151460] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.153552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.153573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.153593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.153612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.155201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.155223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.155246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.156814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.156836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.158708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.162048] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.162144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.162177] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.162218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.162314] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.162364] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.178925] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.178977] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.179048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.179265] [drm:drm_mode_addfb2] [FB:78]
>[ 1221.179385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.212266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.212314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.212404] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.229374] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.229418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.229458] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.229585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.229633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.229688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.229731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.229778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.229823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.229879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.229931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.229981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.230030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.230079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.230107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.230162] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.230203] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.230244] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.230277] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.230433] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.230447] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.230584] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.230612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.230637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.230662] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.230682] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.230704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.230730] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.230755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.230781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.230806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.230831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.230836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.230861] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.230865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.230891] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.230916] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.230941] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.230967] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.230992] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.231017] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.231042] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.231067] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.231093] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.231120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.231147] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.231213] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.231235] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.231257] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.231296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.231322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.231347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.231373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.231398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.231423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.231451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.231510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.231545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.231574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.231602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.231636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.231666] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.233742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.233764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.233782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.233801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.235370] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.235390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.235408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.236997] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.237018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.238901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.242259] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.242319] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.242339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.242369] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.242432] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.242453] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.259124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.259176] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.259246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.259450] [drm:drm_mode_addfb2] [FB:77]
>[ 1221.259695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.292473] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.292553] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.292627] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.309630] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.309674] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.309707] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.309746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.309779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.309815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.309846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.309876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.309907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.309943] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.309976] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.310016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.310059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.310098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.310137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.310195] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.310241] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.310292] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.310331] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.310598] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.310629] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.310766] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.310813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.310860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.310910] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.310953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.310992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.311023] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.311051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.311084] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.311118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.311152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.311159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.311192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.311198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.311232] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.311266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.311301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.311333] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.311368] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.311401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.311435] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.311468] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.311542] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.311588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.311633] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.311730] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.311762] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.311796] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.311854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.311890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.311924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.311958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.311991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.312025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.312051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.312073] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.312103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.312131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.312159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.312189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.312217] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.314275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.314296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.314315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.314334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.315907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.315928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.315946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.317514] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.317535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.319404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.322341] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.322434] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.322467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.322600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.322887] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.322918] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.339195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.339244] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.339315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.339720] [drm:drm_mode_addfb2] [FB:79]
>[ 1221.339859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.372560] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.372612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.372705] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.389716] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.389760] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.389791] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.389829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.389863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.389898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.389930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.389959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.389991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.390026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.390059] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.390091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.390122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.390150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.390178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.390231] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.390272] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.390314] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.390350] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.390530] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.390551] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.390635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.390659] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.390684] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.390711] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.390751] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.390780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.390802] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.390824] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.390844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.390863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.390881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.390887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.390905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.390909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.390929] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.390947] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.390966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.390983] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.391010] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.391035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.391062] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.391087] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.391113] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.391141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.391169] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.391235] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.391258] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.391280] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.391320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.391346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.391373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.391398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.391425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.391450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.391508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.391542] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.391574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.391602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.391630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.391664] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.391693] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.393766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.393787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.393805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.393824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.395404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.395426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.395445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.397045] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.397066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.398931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.402245] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.402314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.402346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.402389] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.402484] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.402616] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.419099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.419148] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.419213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.419427] [drm:drm_mode_addfb2] [FB:78]
>[ 1221.419669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.452438] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.452520] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.452610] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.469597] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.469640] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.469673] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.469712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.469746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.469781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.469812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.469841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.469873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.469908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.469942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.469973] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.470004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.470032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.470062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.470095] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.470121] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.470146] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.470166] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.470303] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.470315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.470372] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.470395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.470418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.470444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.470534] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.470567] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.470598] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.470627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.470657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.470684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.470711] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.470719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.470746] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.470753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.470780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.470807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.470834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.470860] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.470890] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.470917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.470947] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.470976] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.471005] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.471039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.471071] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.471152] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.471171] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.471189] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.471224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.471250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.471277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.471303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.471330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.471355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.471384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.471412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.471440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.471493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.471524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.471558] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.471587] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.473675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.473697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.473716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.473735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.475307] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.475328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.475346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.476900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.476920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.478794] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.482133] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.482232] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.482272] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.482324] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.482420] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.482462] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.499010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.499059] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.499124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.499338] [drm:drm_mode_addfb2] [FB:77]
>[ 1221.499470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.532352] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.532401] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.532554] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.551145] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.551189] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.551221] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.551260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.551293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.551328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.551358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.551387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.551419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.551454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.551574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.551627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.551675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.551716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.551763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.551850] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.551920] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.551984] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.552021] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.552155] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.552168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.552224] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.552245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.552268] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.552293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.552314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.552334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.552355] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.552376] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.552395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.552420] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.552446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.552481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.552510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.552519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.552547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.552574] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.552602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.552627] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.552658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.552685] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.552711] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.552737] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.552764] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.552795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.552828] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.552904] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.552936] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.552967] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.553018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.553051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.553081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.553111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.553141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.553164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.553186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.553206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.553226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.553244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.553262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.553285] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.553310] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.555351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.555372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.555391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.555410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.556989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.557009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.557031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.558599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.558621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.560502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.563862] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.563936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.563975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.564027] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.564110] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.564150] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.580726] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.580784] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.580848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.581063] [drm:drm_mode_addfb2] [FB:79]
>[ 1221.581190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.614061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.614107] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.614177] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.631198] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.631246] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.631287] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.631331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.631372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.631416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.631456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.631583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.631633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.631694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.631726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.631759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.631783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.631802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.631821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.631856] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.631883] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.631912] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.631934] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.632040] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.632053] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.632108] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.632128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.632154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.632183] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.632208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.632235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.632261] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.632288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.632314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.632340] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.632364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.632371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.632396] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.632401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.632426] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.632458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.632521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.632550] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.632582] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.632610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.632638] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.632666] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.632693] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.632725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.632758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.632850] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.632870] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.632888] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.632923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.632943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.632963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.632982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.633000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.633019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.633041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.633061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.633081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.633098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.633116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.633139] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.633158] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.635236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.635260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.635283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.635307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.636880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.636901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.636919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.638487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.638508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.640385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.643699] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.643767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.643800] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.643842] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.643915] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.643936] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.660555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.660604] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.660669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.660882] [drm:drm_mode_addfb2] [FB:78]
>[ 1221.660997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.693894] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.693947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.694024] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.711031] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.711074] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.711106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.711145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.711178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.711214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.711245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.711275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.711306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.711341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.711373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.711405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.711444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.711535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.711573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.711650] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.711712] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.711766] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.711798] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.711938] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.711955] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.712033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.712061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.712094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.712128] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.712156] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.712185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.712214] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.712242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.712269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.712295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.712320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.712327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.712352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.712358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.712394] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.712430] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.712506] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.712535] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.712566] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.712594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.712621] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.712648] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.712674] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.712706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.712738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.712813] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.712843] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.712873] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.712910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.712931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.712956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.712981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.713007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.713033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.713061] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.713088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.713116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.713142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.713168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.713196] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.713221] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.715274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.715296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.715314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.715338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.716906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.716927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.716945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.718502] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.718524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.720393] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.723712] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.723759] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.723782] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.723814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.723877] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.723899] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.740561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.740610] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.740676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.740891] [drm:drm_mode_addfb2] [FB:77]
>[ 1221.741018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.773904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.773953] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.774027] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.792348] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.792396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.792437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.792566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.792622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.792681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.792731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.792780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.792822] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.792860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.792895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.792927] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.792959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.792988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.793017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.793072] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.793113] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.793155] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.793178] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.793292] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.793304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.793360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.793381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.793403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.793433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.793495] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.793528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.793559] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.793587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.793617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.793644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.793672] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.793680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.793706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.793713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.793740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.793767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.793793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.793818] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.793849] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.793875] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.793902] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.793927] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.793954] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.793988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.794022] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.794101] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.794133] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.794164] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.794216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.794248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.794280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.794310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.794340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.794373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.794407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.794432] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.794483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.794513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.794540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.794572] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.794600] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.796665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.796686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.796704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.796723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.798283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.798306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.798329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.799883] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.799905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.801765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.805126] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.805199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.805232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.805274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.805352] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.805385] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.821974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.822021] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.822084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.822326] [drm:drm_mode_addfb2] [FB:79]
>[ 1221.822546] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.855325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.855374] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.855449] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.872527] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.872578] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.872611] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.872650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.872683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.872718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.872749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.872778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.872810] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.872845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.872879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.872911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.872942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.872971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.873004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.873049] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.873084] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.873119] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.873148] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.873327] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.873343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.873422] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.873528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.873578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.873630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.873673] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.873718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.873763] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.873807] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.873849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.873891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.873930] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.873942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.873980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.873990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.874030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.874078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.874119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.874161] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.874208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.874250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.874292] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.874333] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.874374] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.874420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.874505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.874612] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.874661] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.874702] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.874771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.874815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.874858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.874899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.874940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.874983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.875030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.875082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.875119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.875153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.875186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.875222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.875258] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.877343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.877367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.877390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.877415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.879021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.879042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.879061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.880619] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.880643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.882515] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.885842] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.885899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.885931] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.885973] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.886050] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.886082] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.902679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.902728] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.902793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.903005] [drm:drm_mode_addfb2] [FB:78]
>[ 1221.903135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.936019] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1221.936068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1221.936141] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1221.954376] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1221.954420] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1221.954539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1221.954586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.954620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.954657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.954688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.954718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.954750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.954787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.954822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.954877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.954901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.954919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.954938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.954973] [drm:intel_power_well_disable [i915]] disabling display
>[ 1221.955001] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1221.955029] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.955051] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1221.955190] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1221.955209] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1221.955268] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1221.955289] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1221.955312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1221.955337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1221.955356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1221.955383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1221.955409] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1221.955438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1221.955497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1221.955525] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1221.955553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1221.955561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.955588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1221.955595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1221.955623] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1221.955649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1221.955676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1221.955702] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1221.955732] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1221.955759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1221.955786] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1221.955812] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1221.955838] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1221.955868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1221.955900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1221.955978] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1221.956011] [drm:intel_power_well_enable [i915]] enabling display
>[ 1221.956042] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1221.956094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1221.956125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1221.956156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1221.956186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1221.956215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1221.956246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1221.956282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1221.956315] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1221.956341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.956360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1221.956378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1221.956400] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1221.956422] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1221.958514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1221.958535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1221.958555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.958580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1221.960152] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1221.960173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1221.960191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1221.961744] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1221.961765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1221.963632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1221.966961] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1221.967015] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1221.967048] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1221.967089] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1221.967161] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1221.967182] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1221.983797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1221.983847] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1221.983913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1221.984126] [drm:drm_mode_addfb2] [FB:77]
>[ 1221.984267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.017143] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.017191] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.017263] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.034273] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.034317] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.034350] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.034389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.034422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.034544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.034596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.034645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.034700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.034752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.034784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.034822] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.034862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.034897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.034934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.034987] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.035029] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.035075] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.035113] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.035286] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.035304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.035384] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.035416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.035510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.035559] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.035598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.035643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.035691] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.035720] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.035749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.035777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.035803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.035812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.035837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.035845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.035872] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.035898] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.035924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.035950] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.035980] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.036010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.036038] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.036065] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.036092] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.036124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.036159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.036234] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.036267] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.036298] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.036350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.036382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.036413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.036435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.036489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.036517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.036550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.036580] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.036613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.036639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.036666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.036701] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.036734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.038804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.038827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.038850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.038874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.040437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.040474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.040493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.042053] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.042074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.043973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.047277] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.047355] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.047386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.047426] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.047791] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.047824] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.064135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.064185] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.064254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.064557] [drm:drm_mode_addfb2] [FB:79]
>[ 1222.064728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.097510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.097556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.097626] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.114635] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.114678] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.114710] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.114748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.114781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.114815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.114846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.114885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.114924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.114969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.115012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.115055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.115096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.115136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.115175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.115233] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.115271] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.115300] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.115320] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.115480] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.115500] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.115597] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.115629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.115666] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.115703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.115735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.115768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.115802] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.115833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.115864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.115894] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.115919] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.115925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.115950] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.115955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.115981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.116007] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.116033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.116059] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.116086] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.116111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.116134] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.116160] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.116186] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.116213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.116240] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.116297] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.116320] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.116341] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.116380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.116406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.116435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.116494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.116526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.116556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.116590] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.116622] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.116652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.116679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.116706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.116738] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.116767] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.118851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.118873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.118892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.118911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.120479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.120500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.120518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.122078] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.122099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.123974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.127257] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.127357] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.127390] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.127432] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.127589] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.127630] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.144141] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.144191] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.144256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.144559] [drm:drm_mode_addfb2] [FB:78]
>[ 1222.144754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.177503] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.177555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.177631] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.194636] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.194680] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.194713] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.194751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.194785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.194820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.194851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.194880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.194912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.194948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.194981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.195013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.195044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.195080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.195096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.195129] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.195155] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.195181] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.195201] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.195334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.195346] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.195403] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.195435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.195506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.195544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.195574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.195609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.195640] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.195672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.195703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.195734] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.195761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.195770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.195798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.195848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.195876] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.195908] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.195935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.195963] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.195993] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.196021] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.196047] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.196076] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.196102] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.196133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.196166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.196243] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.196274] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.196303] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.196352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.196381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.196410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.196460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.196492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.196520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.196554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.196586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.196619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.196646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.196675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.196710] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.196739] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.198825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.198847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.198866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.198886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.200478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.200499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.200518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.202075] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.202106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.203963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.207280] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.207334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.207353] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.207379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.207494] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.207528] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.224108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.224156] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.224220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.224509] [drm:drm_mode_addfb2] [FB:77]
>[ 1222.224705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.257499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.257545] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.257615] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.274615] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.274659] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.274691] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.274730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.274764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.274799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.274830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.274859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.274891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.274926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.274959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.274991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.275022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.275049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.275076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.275130] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.275171] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.275220] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.275260] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.275515] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.275546] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.275692] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.275745] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.275803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.275853] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.275892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.275936] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.275977] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.276019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.276059] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.276098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.276137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.276148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.276186] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.276195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.276235] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.276274] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.276313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.276348] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.276391] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.276427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.276506] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.276543] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.276585] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.276633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.276682] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.276814] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.276850] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.276883] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.276938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.276970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.277004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.277034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.277066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.277097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.277133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.277169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.277205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.277234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.277267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.277302] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.277336] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.279463] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.279484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.279503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.279522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.281107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.281129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.281151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.282716] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.282737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.284597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.287876] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.287932] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.287966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.287993] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.288054] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.288084] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.304721] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.304773] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.304843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.305049] [drm:drm_mode_addfb2] [FB:79]
>[ 1222.305190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.338055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.338103] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.338193] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.355216] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.355261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.355293] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.355332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.355366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.355401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.355432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.355548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.355597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.355656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.355693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.355727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.355759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.355788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.355816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.355872] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.355920] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.355972] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.356011] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.356188] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.356207] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.356295] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.356330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.356366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.356415] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.356482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.356510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.356533] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.356558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.356585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.356611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.356636] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.356642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.356667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.356672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.356698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.356724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.356750] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.356776] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.356802] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.356827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.356853] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.356879] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.356904] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.356931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.356960] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.357024] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.357047] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.357068] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.357107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.357134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.357159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.357185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.357210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.357236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.357264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.357289] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.357317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.357343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.357368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.357394] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.357422] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.359496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.359518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.359537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.359557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.361138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.361160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.361179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.362734] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.362766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.364630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.367936] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.368011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.368039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.368084] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.368158] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.368193] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.384797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.384846] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.384911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.385146] [drm:drm_mode_addfb2] [FB:78]
>[ 1222.385293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.418138] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.418187] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.418259] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.436258] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.436302] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.436335] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.436374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.436408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.436527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.436571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.436620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.436665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.436719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.436770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.436820] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.436869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.436910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.436953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.437037] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.437101] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.437158] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.437193] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.437363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.437380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.437511] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.437546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.437583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.437622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.437654] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.437688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.437721] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.437754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.437785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.437816] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.437845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.437853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.437883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.437890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.437919] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.437949] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.437978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.438007] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.438037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.438066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.438095] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.438124] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.438150] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.438183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.438218] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.438294] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.438326] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.438356] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.438414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.438484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.438515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.438547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.438578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.438611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.438647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.438680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.438714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.438744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.438774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.438809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.438884] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.440963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.440985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.441004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.441023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.442593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.442614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.442632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.444185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.444207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.446080] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.449391] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.449499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.449522] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.449552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.449617] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.449649] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.466246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.466295] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.466360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.466691] [drm:drm_mode_addfb2] [FB:77]
>[ 1222.466814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.499592] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.499645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.499737] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.517869] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.517913] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.517946] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.517985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.518018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.518052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.518083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.518111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.518143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.518178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.518211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.518243] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.518274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.518302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.518330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.518384] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.518509] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.518574] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.518633] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.518850] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.518886] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.518972] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.518994] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.519018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.519043] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.519063] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.519086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.519107] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.519128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.519148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.519169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.519197] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.519206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.519227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.519232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.519250] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.519268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.519287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.519304] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.519330] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.519355] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.519382] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.519409] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.519467] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.519500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.519532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.519622] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.519651] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.519682] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.519734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.519768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.519799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.519830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.519860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.519892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.519917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.519943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.519971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.519997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.520023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.520051] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.520074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.522122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.522145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.522168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.522192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.523755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.523776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.523795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.525344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.525366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.527238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.530577] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.530674] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.530706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.530748] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.530844] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.530894] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.547482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.547533] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.547598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.547815] [drm:drm_mode_addfb2] [FB:79]
>[ 1222.547929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.580792] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.580841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.580931] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.599582] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.599626] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.599665] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.599710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.599751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.599795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.599835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.599875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.599914] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.599959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.600002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.600044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.600086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.600126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.600165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.600222] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.600269] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.600320] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.600359] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.600645] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.600679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.600768] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.600803] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.600835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.600861] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.600882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.600904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.600926] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.600947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.600968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.600987] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.601006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.601011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.601029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.601034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.601052] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.601071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.601096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.601121] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.601147] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.601173] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.601199] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.601225] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.601251] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.601279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.601306] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.601368] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.601391] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.601439] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.601495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.601526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.601555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.601583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.601610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.601639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.601671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.601702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.601733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.601759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.601785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.601817] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.601847] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.603926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.603948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.603966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.603985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.605652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.605672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.605690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.607245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.607266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.609134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.612421] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.612519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.612552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.612594] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.612691] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.612741] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.629280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.629328] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.629391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.629725] [drm:drm_mode_addfb2] [FB:78]
>[ 1222.629861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.662643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.662692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.662782] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.681205] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.681249] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.681282] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.681320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.681353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.681388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.681490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.681536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.681581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.681640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.681689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.681740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.681778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.681807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.681835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.681890] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.681931] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.681974] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.682008] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.682214] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.682242] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.682345] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.682401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.682465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.682500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.682528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.682559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.682589] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.682618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.682648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.682675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.682706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.682713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.682740] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.682748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.682776] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.682806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.682835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.682863] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.682896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.682925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.682955] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.682984] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.683013] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.683037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.683060] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.683113] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.683132] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.683150] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.683184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.683204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.683229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.683255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.683281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.683307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.683336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.683364] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.683391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.683446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.683477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.683510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.683540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.685611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.685632] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.685651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.685670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.687239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.687260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.687278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.688828] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.688849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.690723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.694049] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.694106] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.694138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.694180] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.694276] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.694326] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.710888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.710940] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.711010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.711228] [drm:drm_mode_addfb2] [FB:77]
>[ 1222.711363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.744231] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.744279] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.744369] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.761415] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.761493] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.761526] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.761564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.761598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.761634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.761664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.761703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.761742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.761787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.761830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.761872] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.761914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.761954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.761993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.762041] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.762067] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.762095] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.762116] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.762253] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.762265] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.762323] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.762349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.762374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.762412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.762517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.762553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.762586] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.762617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.762650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.762681] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.762713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.762721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.762750] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.762757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.762788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.762818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.762847] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.762876] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.762902] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.762927] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.762954] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.762980] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.763005] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.763034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.763061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.763127] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.763150] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.763172] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.763211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.763238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.763264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.763290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.763316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.763341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.763369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.763397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.763454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.763486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.763515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.763548] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.763577] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.765648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.765669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.765687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.765707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.767270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.767290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.767308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.768863] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.768884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.770761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.774076] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.774143] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.774176] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.774218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.774298] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.774319] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.790935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.790984] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.791048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.791266] [drm:drm_mode_addfb2] [FB:79]
>[ 1222.791398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.824283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.824331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.824406] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.841500] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.841544] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.841576] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.841614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.841647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.841683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.841713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.841750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.841780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.841813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.841844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.841874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.841903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.841930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.841956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.842006] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.842045] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.842084] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.842116] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.842317] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.842336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.842506] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.842555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.842605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.842657] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.842699] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.842755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.842802] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.842848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.842893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.842941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.842987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.843001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.843045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.843056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.843103] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.843148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.843195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.843240] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.843291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.843336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.843381] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.843473] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.843515] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.843563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.843613] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.843764] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.843822] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.843863] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.843932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.843974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.844003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.844029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.844055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.844081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.844112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.844138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.844166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.844190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.844215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.844244] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.844272] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.846358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.846379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.846402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.846472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.848041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.848062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.848103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.849648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.849669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.851542] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.854872] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.854927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.854968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.854996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.855056] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.855087] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.871707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.871757] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.871822] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.872060] [drm:drm_mode_addfb2] [FB:78]
>[ 1222.872206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.905050] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.905104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.905196] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1222.922206] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1222.922254] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1222.922295] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1222.922339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.922379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.922502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.922551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.922605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.922653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.922713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.922767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.922817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.922867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.922908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.922952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.923036] [drm:intel_power_well_disable [i915]] disabling display
>[ 1222.923100] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1222.923164] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.923217] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1222.923574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1222.923602] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1222.923682] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1222.923704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1222.923726] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1222.923749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1222.923768] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1222.923788] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1222.923808] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1222.923827] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1222.923845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1222.923861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1222.923878] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1222.923883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.923899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1222.923903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1222.923920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1222.923936] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1222.923952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1222.923968] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1222.923988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1222.924004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1222.924021] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1222.924037] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1222.924052] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1222.924072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.924093] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1222.924151] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1222.924169] [drm:intel_power_well_enable [i915]] enabling display
>[ 1222.924185] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1222.924217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1222.924235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1222.924253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1222.924291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1222.924309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1222.924329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1222.924357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1222.924376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1222.924400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.924469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1222.924503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1222.924536] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1222.924566] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1222.926656] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1222.926678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1222.926697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.926717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1222.928288] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1222.928309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1222.928327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1222.929890] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1222.929912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1222.931802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1222.935163] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1222.935238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1222.935278] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1222.935329] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1222.935430] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1222.935541] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1222.952017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1222.952069] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1222.952140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1222.952381] [drm:drm_mode_addfb2] [FB:77]
>[ 1222.952777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1222.985362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1222.985411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1222.985586] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.004341] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.004386] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.004510] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.004568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.004616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.004668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.004711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.004757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.004803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.004857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.004908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.004957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.005007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.005048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.005091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.005175] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.005247] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.005285] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.005317] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.005482] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.005502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.005598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.005630] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.005663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.005698] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.005726] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.005758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.005789] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.005818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.005847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.005875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.005902] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.005909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.005935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.005942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.005969] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.005997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.006024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.006051] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.006078] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.006105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.006129] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.006156] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.006183] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.006213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.006244] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.006330] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.006360] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.006388] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.006478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.006510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.006542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.006573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.006603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.006634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.006668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.006701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.006734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.006763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.006793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.006827] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.006861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.008964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.008987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.009006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.009025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.010606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.010629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.010649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.012199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.012221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.014097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.017385] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.017481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.017501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.017527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.017587] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.017609] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.034253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.034302] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.034367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.034730] [drm:drm_mode_addfb2] [FB:79]
>[ 1223.034869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.067607] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.067656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.067729] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.084741] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.084784] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.084816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.084854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.084888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.084924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.084954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.084984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.085016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.085052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.085085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.085117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.085148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.085177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.085205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.085259] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.085300] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.085342] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.085375] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.085729] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.085760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.085907] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.085960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.086020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.086060] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.086091] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.086125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.086159] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.086190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.086221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.086251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.086280] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.086287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.086315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.086322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.086351] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.086380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.086439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.086466] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.086500] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.086530] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.086560] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.086587] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.086616] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.086648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.086683] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.086760] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.086792] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.086822] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.086873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.086904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.086934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.086965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.086993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.087025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.087060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.087095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.087128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.087158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.087188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.087223] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.087255] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.089338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.089359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.089382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.089454] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.091020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.091043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.091066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.092630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.092652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.094531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.097860] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.097913] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.097946] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.097988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.098065] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.098098] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.114696] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.114746] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.114811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.115048] [drm:drm_mode_addfb2] [FB:78]
>[ 1223.115191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.148041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.148090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.148163] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.166330] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.166374] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.166492] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.166552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.166605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.166662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.166701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.166733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.166766] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.166803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.166846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.166888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.166910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.166930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.166949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.166984] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.167011] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.167038] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.167060] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.167172] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.167185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.167241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.167267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.167310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.167337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.167356] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.167383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.167443] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.167472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.167500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.167527] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.167554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.167562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.167588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.167596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.167622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.167649] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.167674] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.167700] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.167731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.167757] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.167783] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.167809] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.167836] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.167867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.167899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.167975] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.168008] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.168038] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.168090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.168122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.168154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.168184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.168214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.168246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.168281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.168314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.168337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.168355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.168381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.168438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.168466] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.170528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.170559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.170577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.170596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.172158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.172178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.172197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.173747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.173768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.175618] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.178948] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.179001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.179034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.179076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.179156] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.179177] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.195785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.195834] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.195900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.196116] [drm:drm_mode_addfb2] [FB:77]
>[ 1223.196270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.229126] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.229174] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.229247] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.246281] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.246329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.246370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.246506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.246561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.246618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.246666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.246714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.246764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.246821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.246874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.246925] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.246977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.247023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.247068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.247153] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.247218] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.247282] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.247337] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.247618] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.247639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.247717] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.247738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.247762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.247789] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.247812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.247836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.247860] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.247884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.247907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.247930] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.247953] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.247958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.247981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.247985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.248009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.248032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.248056] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.248079] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.248102] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.248125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.248149] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.248172] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.248195] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.248220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.248245] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.248294] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.248314] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.248334] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.248370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.248453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.248485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.248514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.248543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.248572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.248605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.248636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.248667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.248694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.248721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.248753] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.248782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.250870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.250894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.250917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.250941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.252529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.252551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.252570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.254131] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.254153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.256026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.259282] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.259360] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.259393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.259665] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.259752] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.259781] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.276138] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.276190] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.276261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.276667] [drm:drm_mode_addfb2] [FB:79]
>[ 1223.276797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.309482] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.309530] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.309619] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.327321] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.327365] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.327486] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.327546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.327600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.327656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.327704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.327752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.327802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.327859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.327911] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.327962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.328012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.328057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.328102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.328188] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.328253] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.328316] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.328349] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.328557] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.328575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.328659] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.328689] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.328713] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.328740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.328763] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.328787] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.328811] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.328834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.328858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.328878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.328901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.328905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.328928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.328932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.328956] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.328979] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.329002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.329024] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.329048] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.329071] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.329094] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.329118] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.329141] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.329166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.329191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.329238] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.329259] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.329279] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.329314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.329338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.329362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.329386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.329458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.329491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.329529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.329565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.329599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.329629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.329661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.329697] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.329730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.331801] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.331822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.331841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.331860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.333426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.333446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.333465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.335026] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.335049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.336931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.339502] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.339540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.339559] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.339585] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.339646] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.339676] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.356339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.356389] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.356548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.356803] [drm:drm_mode_addfb2] [FB:78]
>[ 1223.356916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.389682] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.389730] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.389820] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.406832] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.406875] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.406907] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.406946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.406980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.407016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.407047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.407076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.407108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.407143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.407175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.407206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.407237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.407265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.407292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.407345] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.407469] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.407539] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.407596] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.407814] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.407842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.407989] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.408022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.408056] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.408095] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.408126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.408161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.408194] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.408225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.408257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.408286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.408315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.408323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.408352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.408359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.408414] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.408444] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.408476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.408506] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.408540] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.408570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.408602] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.408632] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.408662] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.408698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.408733] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.408824] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.408856] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.408887] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.408937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.408968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.409001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.409030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.409060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.409092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.409126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.409158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.409191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.409220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.409249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.409284] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.409316] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.411391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.411436] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.411455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.411474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.413056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.413077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.413095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.414658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.414678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.416546] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.419871] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.419928] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.419961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.420003] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.420098] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.420149] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.436712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.436764] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.436836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.437053] [drm:drm_mode_addfb2] [FB:77]
>[ 1223.437184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.470054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.470102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.470191] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.487203] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.487247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.487280] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.487318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.487351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.487393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.487517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.487579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.487627] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.487679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.487726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.487773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.487818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.487858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.487899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.487976] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.488034] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.488091] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.488140] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.488337] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.488424] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.488547] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.488580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.488615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.488640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.488668] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.488689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.488709] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.488728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.488751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.488774] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.488797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.488802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.488825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.488829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.488853] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.488873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.488897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.488920] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.488944] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.488967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.488990] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.489014] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.489037] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.489062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.489087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.489138] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.489158] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.489178] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.489214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.489238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.489262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.489286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.489309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.489331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.489357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.489428] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.489468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.489496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.489528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.489565] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.489595] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.491680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.491703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.491722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.491741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.493311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.493332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.493350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.494945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.494966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.496851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.500014] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.500066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.500086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.500111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.500173] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.500194] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.516861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.516908] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.516971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.517187] [drm:drm_mode_addfb2] [FB:79]
>[ 1223.517338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.550205] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.550250] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.550320] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.567355] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.567435] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.567467] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.567506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.567540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.567576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.567606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.567636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.567667] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.567702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.567735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.567766] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.567797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.567824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.567852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.567905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.567946] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.567988] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.568022] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.568230] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.568249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.568342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.568380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.568482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.568538] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.568584] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.568635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.568684] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.568733] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.568781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.568825] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.568866] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.568880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.568921] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.568933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.568975] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.569017] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.569059] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.569100] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.569152] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.569196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.569240] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.569282] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.569324] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.569377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.569437] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.569503] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.569523] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.569541] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.569576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.569596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.569616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.569635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.569653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.569673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.569694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.569715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.569741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.569767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.569792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.569820] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.569846] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.571893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.571914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.571933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.571951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.573544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.573568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.573595] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.575160] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.575181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.577055] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.580367] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.580500] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.580519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.580545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.580605] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.580626] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.597270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.597321] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.597473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.597772] [drm:drm_mode_addfb2] [FB:78]
>[ 1223.597901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.630608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.630661] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.630738] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.649311] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.649355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.649475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.649530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.649580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.649618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.649650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.649680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.649713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.649748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.649783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.649823] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.649867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.649907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.649948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.650010] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.650038] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.650068] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.650091] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.650229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.650248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.650307] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.650329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.650353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.650425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.650455] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.650486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.650517] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.650546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.650575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.650603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.650630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.650638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.650664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.650672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.650698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.650725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.650751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.650777] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.650808] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.650837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.650865] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.650894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.650922] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.650953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.650989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.651067] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.651099] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.651129] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.651182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.651214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.651244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.651270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.651289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.651309] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.651331] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.651351] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.651402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.651429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.651456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.651488] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.651516] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.653582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.653603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.653622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.653641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.655212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.655232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.655250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.656813] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.656834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.658703] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.662046] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.662139] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.662173] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.662219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.662280] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.662302] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.678922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.678991] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.679056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.679268] [drm:drm_mode_addfb2] [FB:77]
>[ 1223.679484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.712258] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.712311] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.712478] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.729471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.729515] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.729547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.729586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.729620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.729656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.729688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.729726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.729770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.729836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.729870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.729900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.729930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.729956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.729982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.730032] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.730071] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.730111] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.730143] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.730343] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.730434] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.730578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.730629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.730683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.730738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.730783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.730832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.730887] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.730931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.730973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.731015] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.731056] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.731066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.731105] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.731115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.731156] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.731198] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.731240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.731281] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.731326] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.731367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.731447] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.731487] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.731528] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.731577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.731626] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.731732] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.731777] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.731819] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.731887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.731919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.731950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.731977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.732007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.732037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.732072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.732104] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.732137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.732166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.732192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.732225] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.732256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.734345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.734387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.734406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.734426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.735999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.736023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.736046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.737623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.737645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.739506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.742835] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.742887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.742920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.742963] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.743040] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.743082] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.759673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.759723] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.759795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.760014] [drm:drm_mode_addfb2] [FB:79]
>[ 1223.760136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.793016] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.793068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.793146] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.811287] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.811332] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.811364] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.811488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.811530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.811609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.811655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.811687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.811718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.811753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.811785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.811815] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.811846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.811873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.811900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.811951] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.811990] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.812031] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.812064] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.812236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.812263] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.812446] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.812490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.812539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.812589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.812633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.812671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.812707] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.812742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.812776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.812808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.812839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.812849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.812880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.812889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.812924] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.812957] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.812990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.813021] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.813060] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.813094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.813128] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.813162] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.813196] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.813237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.813279] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.813370] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.813434] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.813467] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.813529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.813568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.813613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.813644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.813666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.813687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.813709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.813729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.813750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.813767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.813785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.813808] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.813828] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.815876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.815900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.815923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.815947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.817556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.817577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.817596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.819153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.819176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.821051] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.824334] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.824456] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.824503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.824570] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.824684] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.824729] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.841217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.841266] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.841330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.841687] [drm:drm_mode_addfb2] [FB:78]
>[ 1223.841809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.874561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.874612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.874689] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.893294] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.893338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.893449] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.893511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.893560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.893613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.893657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.893702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.893750] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.893804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.893856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.893906] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.893956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.893997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.894040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.894124] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.894189] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.894253] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.894306] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.894535] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.894547] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.894606] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.894627] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.894650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.894675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.894695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.894725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.894745] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.894764] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.894787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.894809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.894832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.894837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.894860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.894864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.894888] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.894909] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.894933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.894953] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.894977] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.895000] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.895023] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.895047] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.895070] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.895095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.895120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.895178] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.895198] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.895218] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.895254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.895277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.895301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.895324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.895348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.895415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.895454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.895489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.895524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.895552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.895582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.895618] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.895648] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.897705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.897726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.897748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.897772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.899357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.899394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.899413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.900984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.901005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.902887] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.906201] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.906270] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.906303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.906345] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.906714] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.906745] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1223.923052] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.923101] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.923166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.923438] [drm:drm_mode_addfb2] [FB:77]
>[ 1223.923634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.956426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1223.956475] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1223.956550] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1223.973548] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1223.973593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1223.973626] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1223.973665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.973698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.973733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.973764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.973794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.973831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1223.973877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.973919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.973962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.974004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.974043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.974082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.974140] [drm:intel_power_well_disable [i915]] disabling display
>[ 1223.974186] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1223.974237] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1223.974285] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1223.974481] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1223.974506] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1223.974623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1223.974667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1223.974712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1223.974758] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1223.974797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1223.974839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1223.974880] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1223.974920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1223.974959] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1223.974994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1223.975031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1223.975040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.975075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1223.975084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1223.975121] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1223.975158] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1223.975195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1223.975231] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1223.975272] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1223.975312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1223.975343] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1223.975410] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1223.975438] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1223.975472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1223.975509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1223.975585] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1223.975618] [drm:intel_power_well_enable [i915]] enabling display
>[ 1223.975648] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1223.975698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1223.975730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1223.975757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1223.975787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1223.975818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1223.975849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1223.975883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1223.975916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1223.975948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1223.975978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1223.976008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1223.976042] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1223.976073] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1223.978146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1223.978168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1223.978187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.978206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1223.979770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1223.979790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1223.979809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1223.981364] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1223.981403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1223.983265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1223.986564] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1223.986636] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1223.986660] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1223.986691] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1223.986754] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1223.986776] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1224.003433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.003482] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.003549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.003764] [drm:drm_mode_addfb2] [FB:79]
>[ 1224.003895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.036776] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1224.036826] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.036900] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1224.055305] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1224.055349] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1224.055461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.055511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.055547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.055591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.055631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.055673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.055714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.055759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.055809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.055834] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.055857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.055876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.055895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.055931] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.055958] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.055988] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.056010] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.056152] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1224.056171] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.056232] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.056254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.056277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.056302] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.056323] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.056349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.056410] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1224.056440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1224.056470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.056499] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.056526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.056535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.056561] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.056569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.056596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.056622] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.056649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.056674] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1224.056705] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.056731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.056757] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1224.056783] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1224.056810] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1224.056840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.056873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1224.056952] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.056984] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.057014] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.057065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.057097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.057128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.057158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.057188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.057219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.057254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.057285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.057317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.057335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.057381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.057414] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1224.057443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.059511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.059532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.059551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.059570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.061139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.061160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.061178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.062739] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.062760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.064632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.067991] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1224.068066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.068104] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1224.068130] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.068192] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1224.068213] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1224.084845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.084895] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.084961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.085173] [drm:drm_mode_addfb2] [FB:78]
>[ 1224.085304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.118194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1224.118243] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.118316] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1224.135341] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1224.135422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1224.135466] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.135527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.135564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.135600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.135631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.135660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.135700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.135734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.135765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.135794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.135823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.135849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.135875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.135926] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.135964] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.136011] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.136048] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.136239] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1224.136259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.136360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.136458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.136515] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.136572] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.136619] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.136671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.136733] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1224.136785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1224.136836] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.136886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.136933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.136947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.136993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.137005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.137051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.137097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.137145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.137192] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1224.137244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.137290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.137337] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1224.137413] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1224.137458] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1224.137507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.137561] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1224.137677] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.137726] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.137759] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.137809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.137840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.137870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.137901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.137930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.137961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.137996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.138029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.138062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.138091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.138117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.138151] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1224.138183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.140263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.140285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.140304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.140323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.141931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.141951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.141969] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.143557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.143580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.145448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.148783] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1224.148884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.148920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1224.148945] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.149007] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1224.149028] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1224.165676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.165727] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.165791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.166011] [drm:drm_mode_addfb2] [FB:77]
>[ 1224.166144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.199022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1224.199074] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.199152] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1224.217261] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1224.217305] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1224.217338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.217470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.217526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.217582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.217631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.217678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.217728] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.217784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.217837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.217888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.217938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.217985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.218030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.218115] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.218183] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.218248] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.218303] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.218579] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1224.218595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.218671] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.218704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.218739] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.218776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.218809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.218843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.218877] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1224.218910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1224.218944] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.218977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.219009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.219016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.219048] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.219054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.219087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.219121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.219154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.219185] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1224.219218] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.219250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.219283] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1224.219317] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1224.219350] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1224.219459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.219499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1224.219575] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.219607] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.219637] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.219689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.219718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.219749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.219776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.219805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.219833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.219866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.219898] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.219929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.219956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.219984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.220018] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1224.220047] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.222132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.222154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.222173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.222192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.223757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.223777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.223796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.225348] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.225385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.227245] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.230601] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1224.230662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.230682] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1224.230708] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.230768] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1224.230797] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1224.247463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.247514] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.247586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.247834] [drm:drm_mode_addfb2] [FB:79]
>[ 1224.247969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.280803] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1224.280852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.280941] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1224.297956] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1224.297999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1224.298031] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.298070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.298103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.298139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.298170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.298200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.298231] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.298266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.298298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.298330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.298440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.298482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.298524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.298609] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.298680] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.298746] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.298804] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.298991] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1224.299011] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.299097] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.299129] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.299152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.299177] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.299197] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.299219] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.299240] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1224.299260] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1224.299280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.299298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.299317] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.299322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.299384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.299392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.299420] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.299447] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.299474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.299500] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1224.299530] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.299556] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.299583] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1224.299609] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1224.299636] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1224.299668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.299700] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1224.299777] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.299809] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.299840] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.299891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.299923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.299954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.299984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.300014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.300044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.300070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.300092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.300112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.300131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.300149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.300173] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1224.300193] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.302241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.302262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.302284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.302309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.303918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.303938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.303957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.305514] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.305535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.307402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.310755] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1224.310837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.310870] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1224.310912] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.310991] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1224.311024] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1224.327610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.327658] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.327720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.327959] [drm:drm_mode_addfb2] [FB:78]
>[ 1224.328110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.360961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1224.361007] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.361077] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1224.378073] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1224.378124] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1224.378173] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.378214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.378254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.378298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.378339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.378459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.378509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.378568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.378621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.378671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.378721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.378763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.378807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.378876] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.378920] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.378960] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1224.378994] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.379283] [drm:drm_mode_addfb2] [FB:77]
>[ 1224.379311] [drm:drm_mode_addfb2] [FB:78]
>[ 1224.408863] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1224.408971] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.409049] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1224.409119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.409130] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.409187] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.409212] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.409237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.409265] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.409288] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.409312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.409336] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.409418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.409454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.409487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.409519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.409528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.409557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.409565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.409596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.409627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.409659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.409688] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.409723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.409754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.409785] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.409814] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.409843] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.409879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.409914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.413236] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.413255] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.413272] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.413308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.413328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.413394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.413426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.413456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.413486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.413521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.413554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.413587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.413614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.413642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.413676] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.413705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.415780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.415801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.415819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.415838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.417450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.417470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.417489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.419040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.419061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.420923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.424236] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.424306] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.424339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.424449] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.441077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.441125] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.441189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.457760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.457780] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.474591] [drm:drm_mode_addfb2] [FB:79]
>[ 1224.474728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.491118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.491165] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.491237] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.508261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.508298] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.508338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.508467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.508525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.508574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.508621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.508676] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.508726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.508772] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.508818] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.508863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.508903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.508943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.509019] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.509078] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.509133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.509178] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.509417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.509443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.509549] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.509581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.509618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.509672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.509699] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.509727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.509756] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.509787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.509817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.509847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.509877] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.509882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.509912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.509917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.509947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.509978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.510007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.510037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.510068] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.510097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.510127] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.510156] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.510186] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.510218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.510250] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.510311] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.510336] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.510408] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.510473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.510510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.510545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.510578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.510612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.510646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.510689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.510721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.510754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.510783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.510811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.510845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.510868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.512930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.512950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.512993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.513019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.514614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.514637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.514656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.516206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.516228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.518090] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.521407] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.521472] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.521505] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.521547] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.538255] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.538305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.538464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.538707] [drm:drm_mode_addfb2] [FB:77]
>[ 1224.538820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.554971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.555019] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.555092] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.573274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.573312] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.573438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.573479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.573518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.573550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.573582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.573614] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.573651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.573685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.573717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.573759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.573800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.573840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.573899] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.573956] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.573986] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.574007] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.574129] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.574148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.574215] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.574237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.574261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.574286] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.574305] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.574334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.574394] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.574423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.574453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.574480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.574518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.574526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.574552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.574560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.574587] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.574613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.574640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.574666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.574696] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.574722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.574751] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.574780] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.574806] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.574838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.574873] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.574950] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.574981] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.575012] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.575066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.575099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.575130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.575160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.575190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.575215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.575244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.575272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.575301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.575326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.575383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.575420] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.575449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.577519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.577541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.577559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.577578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.579144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.579168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.579191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.580752] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.580773] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.582645] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.585955] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.586032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.586072] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.586123] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.602806] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.602856] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.602921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.603136] [drm:drm_mode_addfb2] [FB:78]
>[ 1224.603262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.619511] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.619560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.619633] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.636634] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.636672] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.636711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.636745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.636780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.636819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.636860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.636900] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.636945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.636987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.637030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.637072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.637111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.637150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.637208] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.637255] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.637310] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.637390] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.637546] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.637564] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.637654] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.637688] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.637713] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.637739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.637759] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.637781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.637803] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.637824] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.637844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.637863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.637881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.637886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.637904] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.637908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.637927] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.637945] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.637969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.637996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.638022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.638047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.638073] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.638099] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.638124] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.638152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.638180] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.638243] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.638266] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.638287] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.638327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.638390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.638423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.638454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.638482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.638512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.638544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.638576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.638607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.638635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.638662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.638694] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.638723] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.640785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.640806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.640825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.640846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.642444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.642464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.642483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.644039] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.644059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.645932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.649224] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.649316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.649406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.649479] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.666083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.666133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.666199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.666556] [drm:drm_mode_addfb2] [FB:79]
>[ 1224.666682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.682811] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.682859] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.682942] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.701272] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.701309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.701435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.701489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.701549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.701598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.701647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.701699] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.701737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.701774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.701811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.701848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.701882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.701916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.701983] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.702020] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.702061] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.702088] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.702229] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.702245] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.702323] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.702411] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.702459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.702508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.702546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.702592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.702632] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.702673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.702711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.702756] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.702785] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.702795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.702824] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.702833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.702865] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.702895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.702924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.702951] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.702988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.703017] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.703049] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.703076] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.703107] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.703142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.703175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.703257] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.703289] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.703322] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.703407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.703439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.703473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.703502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.703534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.703565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.703603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.703637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.703672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.703700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.703731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.703770] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.703800] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.705894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.705915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.705938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.705962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.707556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.707580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.707603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.709157] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.709179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.711054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.714401] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.714501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.714536] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.714587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.731268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.731319] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.731644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.731852] [drm:drm_mode_addfb2] [FB:77]
>[ 1224.731980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.748025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.748070] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.748138] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.766279] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.766317] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.766440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.766488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.766544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.766587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.766633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.766678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.766732] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.766783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.766833] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.766882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.766926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.766953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.767007] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.767057] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.767094] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.767124] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.767284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.767298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.767432] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.767468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.767504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.767544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.767575] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.767608] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.767643] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.767668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.767688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.767708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.767726] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.767732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.767750] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.767754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.767774] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.767792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.767811] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.767828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.767854] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.767879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.767906] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.767932] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.767959] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.767986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.768014] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.768070] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.768092] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.768114] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.768153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.768180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.768206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.768232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.768258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.768284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.768313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.768369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.768403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.768431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.768459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.768493] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.768522] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.770596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.770618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.770637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.770655] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.772226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.772249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.772272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.773852] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.773874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.775843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.779136] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.779168] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.779188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.779220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.795965] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.796018] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.796089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.796520] [drm:drm_mode_addfb2] [FB:78]
>[ 1224.796687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.812642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.812690] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.812762] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.829778] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.829816] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.829856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.829890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.829925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.829956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.829985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.830017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.830052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.830085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.830116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.830147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.830175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.830202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.830256] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.830297] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.830431] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.830477] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.830691] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.830715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.830830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.830875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.830920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.830969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.831008] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.831052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.831094] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.831135] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.831177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.831215] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.831253] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.831263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.831301] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.831343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.831387] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.831418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.831451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.831484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.831516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.831550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.831584] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.831617] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.831650] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.831688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.831726] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.831825] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.831859] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.831892] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.831947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.831981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.832015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.832047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.832079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.832113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.832149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.832185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.832220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.832252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.832284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.832321] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.832387] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.834452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.834472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.834491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.834509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.836078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.836098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.836117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.837669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.837690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.839562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.842844] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.842889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.842922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.842966] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.859677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.859728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.859793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.860006] [drm:drm_mode_addfb2] [FB:79]
>[ 1224.860121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.876394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.876440] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.876509] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.893501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.893539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.893583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.893624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.893668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.893708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.893748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.893788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.893832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.893875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.893917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.893959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.893999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.894038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.894095] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.894141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.894192] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.894227] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.894439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.894470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.894618] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.894667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.894728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.894764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.894793] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.894825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.894856] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.894887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.894916] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.894944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.894970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.894978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.895004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.895011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.895040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.895066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.895093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.895119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.895150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.895175] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.895203] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.895229] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.895256] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.895286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.895320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.895431] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.895461] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.895493] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.895544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.895572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.895603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.895630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.895658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.895686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.895717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.895749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.895780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.895806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.895834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.895865] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.895895] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.897982] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.898004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.898023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.898043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.899621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.899642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.899664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.901224] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.901245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.903117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.906428] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.906499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.906538] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.906589] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.923280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.923330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.923494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.923751] [drm:drm_mode_addfb2] [FB:77]
>[ 1224.923882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.939956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1224.940005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1224.940094] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1224.957104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1224.957143] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1224.957183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.957217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.957253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.957284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.957314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.957433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.957494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.957547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.957600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.957651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.957697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.957742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.957823] [drm:intel_power_well_disable [i915]] disabling display
>[ 1224.957888] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1224.957950] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.958003] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1224.958153] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1224.958175] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1224.958231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1224.958256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1224.958280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1224.958317] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1224.958391] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1224.958425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1224.958457] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1224.958486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1224.958515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1224.958543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1224.958573] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1224.958581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.958608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1224.958616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1224.958643] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1224.958674] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1224.958703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1224.958732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1224.958764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1224.958794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1224.958826] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1224.958855] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1224.958876] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1224.958898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1224.958922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1224.958987] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1224.959009] [drm:intel_power_well_enable [i915]] enabling display
>[ 1224.959031] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1224.959071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1224.959098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1224.959125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1224.959151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1224.959178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1224.959204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1224.959232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1224.959260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1224.959287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.959314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1224.959371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1224.959407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1224.959436] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1224.961523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1224.961547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1224.961570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.961595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1224.963168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1224.963189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1224.963208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1224.964764] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1224.964785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1224.966655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1224.969985] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1224.970039] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1224.970072] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1224.970115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1224.986818] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1224.986868] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1224.986934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1224.987159] [drm:drm_mode_addfb2] [FB:78]
>[ 1224.987288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.003495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.003543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.003632] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.020645] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.020682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.020722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.020756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.020791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.020821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.020850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.020882] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.020925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.020968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.021010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.021052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.021091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.021131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.021189] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.021235] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.021287] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.021306] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.021516] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.021535] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.021624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.021654] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.021688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.021724] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.021752] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.021784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.021814] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.021846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.021874] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.021903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.021929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.021936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.021963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.021970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.021999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.022025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.022053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.022078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.022110] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.022135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.022163] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.022189] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.022216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.022245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.022278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.022388] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.022419] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.022450] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.022502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.022530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.022562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.022590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.022619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.022647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.022680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.022712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.022743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.022770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.022797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.022828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.022859] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.024924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.024944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.024962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.024981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.026571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.026595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.026619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.028175] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.028197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.030065] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.033371] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.033448] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.033482] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.033527] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.050239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.050289] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.050460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.050752] [drm:drm_mode_addfb2] [FB:79]
>[ 1225.050892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.066935] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.066984] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.067057] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.084108] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.084145] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.084185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.084219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.084254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.084284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.084313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.084440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.084500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.084554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.084606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.084640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.084669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.084698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.084754] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.084798] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.084838] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.084871] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.085014] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.085036] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.085091] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.085116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.085140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.085167] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.085190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.085214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.085237] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.085261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.085284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.085316] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.085387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.085396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.085428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.085436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.085468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.085498] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.085528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.085558] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.085592] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.085619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.085650] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.085678] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.085707] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.085741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.085776] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.085855] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.085885] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.085915] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.085965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.085996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.086023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.086053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.086079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.086109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.086142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.086173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.086205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.086230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.086258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.086289] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.086344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.088401] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.088424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.088451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.088470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.090044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.090065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.090083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.091637] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.091658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.093521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.096825] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.096889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.096912] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.096944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.113687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.113738] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.113803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.114012] [drm:drm_mode_addfb2] [FB:77]
>[ 1225.114146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.130394] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.130443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.130531] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.147524] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.147562] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.147601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.147635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.147671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.147701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.147731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.147762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.147798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.147838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.147868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.147896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.147923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.147948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.147998] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.148037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.148076] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.148105] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.148293] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.148369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.148511] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.148561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.148613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.148668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.148713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.148764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.148811] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.148866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.148911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.148952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.148994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.149005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.149043] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.149054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.149094] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.149135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.149175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.149217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.149262] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.149303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.149372] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.149415] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.149454] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.149502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.149552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.149657] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.149713] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.149756] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.149828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.149876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.149913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.149947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.149980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.150016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.150055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.150092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.150129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.150160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.150193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.150233] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.150268] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.152379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.152401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.152419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.152439] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.154009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.154030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.154048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.155610] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.155630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.157498] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.160821] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.160884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.160923] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.160974] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.177660] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.177711] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.177776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.177989] [drm:drm_mode_addfb2] [FB:78]
>[ 1225.178104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.194364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.194413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.194502] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.211461] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.211496] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.211534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.211566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.211598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.211626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.211653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.211682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.211716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.211747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.211776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.211805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.211840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.211877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.211940] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.211973] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.212007] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.212031] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.212189] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.212204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.212276] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.212305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.212395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.212442] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.212480] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.212524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.212564] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.212604] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.212643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.212680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.212717] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.212728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.212762] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.212771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.212806] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.212842] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.212879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.212914] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.212954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.212988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.213023] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.213059] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.213095] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.213134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.213175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.213291] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.213357] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.213391] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.213453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.213491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.213528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.213564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.213599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.213632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.213671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.213709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.213747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.213778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.213813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.213854] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.213892] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.216001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.216024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.216042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.216062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.217628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.217650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.217668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.219228] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.219259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.221131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.224413] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.224458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.224486] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.224522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.241238] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.241291] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.241456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.241745] [drm:drm_mode_addfb2] [FB:79]
>[ 1225.241859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.257918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.257967] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.258056] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.275071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.275109] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.275149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.275182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.275218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.275249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.275279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.275312] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.275430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.275485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.275539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.275590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.275632] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.275677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.275764] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.275828] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.275891] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.275943] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.276187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.276223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.276402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.276464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.276511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.276561] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.276606] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.276650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.276693] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.276735] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.276777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.276817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.276852] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.276862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.276899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.276908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.276947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.276986] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.277025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.277065] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.277108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.277148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.277189] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.277236] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.277265] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.277298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.277358] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.277435] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.277466] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.277498] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.277550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.277581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.277613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.277643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.277673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.277704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.277737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.277770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.277802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.277831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.277861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.277895] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.277926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.280006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.280034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.280057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.280081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.281650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.281670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.281688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.283235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.283256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.285120] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.288465] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.288550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.288579] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.288614] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.305395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.305444] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.305508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.305746] [drm:drm_mode_addfb2] [FB:77]
>[ 1225.305885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.322014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.322064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.322137] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.339156] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.339194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.339234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.339268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.339303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.339428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.339479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.339530] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.339591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.339637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.339681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.339723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.339762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.339802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.339874] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.339930] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.339984] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.340027] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.340214] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.340231] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.340311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.340397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.340443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.340492] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.340531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.340585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.340616] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.340650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.340680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.340709] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.340737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.340746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.340774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.340782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.340812] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.340839] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.340867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.340893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.340924] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.340951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.340979] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.341005] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.341033] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.341066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.341100] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.341181] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.341212] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.341242] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.341293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.341349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.341378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.341409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.341436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.341468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.341503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.341537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.341571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.341598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.341628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.341662] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.341691] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.343752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.343773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.343792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.343811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.345408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.345428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.345446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.347006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.347028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.348903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.352188] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.352287] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.352380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.352448] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.369068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.369118] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.369183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.369590] [drm:drm_mode_addfb2] [FB:78]
>[ 1225.369720] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.385781] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.385829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.385903] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.402889] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.402931] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.402977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.403018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.403062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.403102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.403142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.403182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.403226] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.403269] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.403312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.403417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.403466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.403510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.403597] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.403667] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.403736] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.403788] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.403968] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.403983] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.404054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.404082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.404112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.404143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.404167] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.404195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.404226] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.404259] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.404296] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.404373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.404408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.404419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.404453] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.404463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.404498] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.404532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.404567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.404601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.404644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.404679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.404714] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.404749] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.404786] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.404827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.404870] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.404962] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.404993] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.405023] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.405058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.405079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.405099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.405118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.405137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.405161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.405190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.405219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.405254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.405280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.405330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.405363] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.405392] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.407459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.407480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.407503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.407527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.409098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.409119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.409137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.410681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.410704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.412563] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.415862] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.415946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.415978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.416019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.432723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.432773] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.432840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.433052] [drm:drm_mode_addfb2] [FB:79]
>[ 1225.433182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.449371] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.449417] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.449488] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.466511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.466549] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.466589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.466623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.466666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.466707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.466747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.466787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.466832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.466874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.466917] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.466959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.466999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.467038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.467095] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.467141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.467192] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.467229] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.467393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.467413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.467509] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.467544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.467580] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.467617] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.467648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.467682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.467715] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.467747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.467778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.467808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.467837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.467845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.467873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.467880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.467912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.467941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.467972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.468001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.468033] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.468063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.468093] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.468123] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.468154] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.468187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.468222] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.468359] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.468392] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.468423] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.468477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.468511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.468543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.468575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.468606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.468639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.468673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.468706] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.468739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.468768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.468798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.468833] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.468864] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.470934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.470958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.470981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.471005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.472580] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.472602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.472621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.474179] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.474202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.476075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.479416] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.479493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.479513] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.479538] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.496285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.496371] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.496437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.496647] [drm:drm_mode_addfb2] [FB:77]
>[ 1225.496779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.512962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.513011] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.513083] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.530080] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.530119] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.530158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.530192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.530228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.530259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.530288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.530409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.530468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.530520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.530554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.530588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.530609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.530628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.530678] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.530706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.530735] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.530756] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.530858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.530870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.530926] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.530947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.530970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.530995] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.531015] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.531036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.531058] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.531078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.531097] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.531122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.531147] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.531153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.531178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.531183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.531209] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.531235] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.531262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.531291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.531353] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.531383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.531413] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.531441] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.531468] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.531499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.531532] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.531619] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.531649] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.531680] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.531733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.531765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.531796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.531827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.531857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.531889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.531924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.531957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.531990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.532019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.532047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.532070] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.532092] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.534143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.534164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.534182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.534202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.535764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.535784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.535806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.537399] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.537421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.539289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.542647] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.542725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.542749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.542780] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.559507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.559557] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.559623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.559819] [drm:drm_mode_addfb2] [FB:78]
>[ 1225.559939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.576196] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.576248] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.576403] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.593377] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.593415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.593455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.593489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.593524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.593555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.593584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.593616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.593651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.593683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.593714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.593745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.593773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.593800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.593859] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.593885] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.593910] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.593928] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.594055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.594066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.594124] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.594147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.594170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.594195] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.594214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.594236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.594257] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.594287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.594367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.594395] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.594426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.594435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.594464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.594472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.594503] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.594533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.594564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.594594] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.594628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.594658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.594688] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.594718] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.594749] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.594783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.594818] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.594914] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.594946] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.594976] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.595027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.595058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.595089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.595119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.595149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.595178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.595211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.595244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.595277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.595331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.595359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.595395] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.595427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.597499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.597520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.597538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.597557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.599113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.599139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.599163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.600723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.600745] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.602610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.605947] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.606045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.606078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.606121] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.622831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.622881] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.622947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.623170] [drm:drm_mode_addfb2] [FB:79]
>[ 1225.623298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.639531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.639580] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.639655] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.658229] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.658266] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.658393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.658447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.658503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.658552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.658599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.658649] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.658706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.658758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.658810] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.658860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.658906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.658951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.659036] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.659107] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.659168] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.659218] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.659433] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.659452] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.659546] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.659577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.659610] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.659638] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.659656] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.659676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.659697] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.659715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.659733] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.659750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.659767] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.659771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.659788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.659792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.659808] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.659825] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.659841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.659863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.659887] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.659910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.659934] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.659957] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.659981] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.660005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.660031] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.660088] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.660108] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.660128] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.660164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.660188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.660212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.660236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.660259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.660282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.660355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.660393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.660430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.660459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.660490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.660525] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.660555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.662636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.662659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.662697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.662718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.664293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.664330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.664350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.665923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.665946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.667823] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.671163] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.671258] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.671291] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.671415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.688053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.688101] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.688164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.688470] [drm:drm_mode_addfb2] [FB:77]
>[ 1225.688660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.704734] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.704781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.704869] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.721865] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.721903] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.721942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.721975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.722011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.722042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.722071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.722103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.722138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.722170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.722202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.722233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.722271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.722382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.722467] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.722532] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.722574] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.722607] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.722766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.722785] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.722875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.722908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.722943] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.722980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.723011] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.723044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.723076] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.723109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.723140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.723171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.723201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.723208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.723237] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.723244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.723273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.723328] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.723357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.723387] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.723422] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.723453] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.723484] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.723514] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.723544] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.723578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.723614] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.723688] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.723719] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.723748] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.723799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.723831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.723862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.723892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.723922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.723953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.723987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.724019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.724051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.724080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.724109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.724143] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.724174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.726234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.726255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.726273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.726342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.727910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.727930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.727948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.729498] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.729519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.731400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.734699] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.734767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.734790] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.734822] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.751561] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.751612] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.751677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.751913] [drm:drm_mode_addfb2] [FB:78]
>[ 1225.752057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.768262] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.768353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.768446] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.785440] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.785478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.785518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.785552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.785586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.785617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.785646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.785678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.785713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.785746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.785777] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.785809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.785837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.785864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.785920] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.785955] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.785997] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.786027] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.786210] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.786227] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.786382] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.786424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.786470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.786516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.786554] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.786596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.786640] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.786682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.786723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.786763] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.786803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.786813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.786852] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.786861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.786901] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.786939] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.786978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.787016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.787059] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.787090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.787116] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.787139] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.787162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.787190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.787222] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.787334] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.787370] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.787405] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.787475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.787514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.787550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.787591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.787628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.787670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.787714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.787757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.787800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.787838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.787869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.787899] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.787927] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.790014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.790036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.790054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.790074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.791650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.791671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.791689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.793286] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.793325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.795195] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.798508] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.798575] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.798605] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.798646] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.815356] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.815407] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.815472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.815716] [drm:drm_mode_addfb2] [FB:79]
>[ 1225.815861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.832051] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.832103] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.832208] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.849176] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.849214] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.849254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.849289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.849411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.849457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.849506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.849551] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.849609] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.849660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.849710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.849760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.849800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.849843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.849929] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.849995] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.850057] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.850109] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.850339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.850359] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.850437] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.850460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.850492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.850519] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.850542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.850566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.850590] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.850613] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.850637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.850660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.850683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.850688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.850711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.850715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.850738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.850762] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.850785] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.850807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.850831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.850853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.850876] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.850900] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.850923] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.850948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.850973] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.851022] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.851042] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.851062] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.851099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.851122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.851146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.851189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.851215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.851248] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.851271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.851343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.851376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.851404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.851430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.851463] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.851493] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.853568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.853591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.853610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.853630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.855200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.855220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.855241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.856840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.856861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.858750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.862071] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.862133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.862165] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.862207] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.878908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.878961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.879033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.879256] [drm:drm_mode_addfb2] [FB:77]
>[ 1225.879502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.895578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.895626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.895701] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.912733] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.912771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.912811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.912845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.912879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.912910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.912948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.912988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.913032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.913075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.913117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.913159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.913199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.913238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.913385] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.913456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.913512] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.913545] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.913687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.913705] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.913795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.913828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.913863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.913901] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.913932] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.913966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.913999] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.914031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.914063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.914093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.914122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.914130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.914159] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.914166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.914196] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.914226] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.914255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.914309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.914343] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.914373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.914405] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.914435] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.914466] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.914501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.914536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.914624] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.914655] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.914685] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.914736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.914767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.914799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.914829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.914859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.914890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.914924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.914957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.914989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.915018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.915047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.915081] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.915112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.917180] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.917200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.917219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.917237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.918850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.918870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.918888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.920467] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.920490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.922359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.925712] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.925777] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.925797] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.925823] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1225.942574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.942624] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.942690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.942905] [drm:drm_mode_addfb2] [FB:78]
>[ 1225.943055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.959262] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1225.959337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1225.959425] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1225.976409] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1225.976447] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1225.976486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.976520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.976555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.976586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.976615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.976646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1225.976680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.976721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.976751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.976780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.976806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.976832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.976882] [drm:intel_power_well_disable [i915]] disabling display
>[ 1225.976921] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1225.976960] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1225.976990] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1225.977185] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1225.977203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1225.977300] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1225.977398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1225.977449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1225.977500] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1225.977543] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1225.977591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1225.977640] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1225.977685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1225.977739] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1225.977786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1225.977849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1225.977863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.977897] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1225.977904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1225.977934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1225.977962] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1225.977991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1225.978019] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1225.978055] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1225.978082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1225.978123] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1225.978163] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1225.978205] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1225.978247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1225.978296] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1225.978479] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1225.978529] [drm:intel_power_well_enable [i915]] enabling display
>[ 1225.978576] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1225.978661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1225.978715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1225.978758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1225.978789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1225.978820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1225.978851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1225.978886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1225.978910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1225.978930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1225.978949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1225.978974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1225.979002] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1225.979028] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1225.981096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1225.981118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1225.981137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.981156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1225.982731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1225.982751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1225.982769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1225.984325] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1225.984346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1225.986224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1225.989553] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1225.989607] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1225.989646] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1225.989697] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.006384] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.006437] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.006508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.006724] [drm:drm_mode_addfb2] [FB:79]
>[ 1226.006857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.023105] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.023156] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.023246] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.041405] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.041442] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.041482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.041516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.041551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.041581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.041610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.041642] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.041677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.041710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.041742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.041774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.041802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.041830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.041883] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.041925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.041967] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.041998] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.042162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.042174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.042231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.042254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.042350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.042391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.042423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.042459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.042493] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.042527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.042559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.042591] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.042622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.042631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.042661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.042668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.042697] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.042727] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.042760] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.042790] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.042823] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.042852] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.042882] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.042911] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.042941] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.042974] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.043008] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.043106] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.043137] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.043167] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.043219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.043251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.043316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.043348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.043378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.043411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.043446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.043480] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.043513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.043542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.043573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.043605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.043636] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.045704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.045725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.045744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.045763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.047362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.047383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.047402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.048951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.048974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.050840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.054135] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.054224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.054256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.054381] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.071001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.071052] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.071118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.071601] [drm:drm_mode_addfb2] [FB:77]
>[ 1226.071730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.087702] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.087749] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.087838] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.104827] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.104865] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.104905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.104940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.104976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.105007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.105037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.105069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.105104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.105137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.105168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.105199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.105227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.105255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.105408] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.105455] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.105498] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.105532] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.105663] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.105675] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.105731] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.105753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.105776] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.105801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.105821] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.105843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.105868] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.105894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.105921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.105947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.105972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.105978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.106002] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.106007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.106033] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.106059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.106085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.106110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.106136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.106161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.106187] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.106213] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.106239] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.106272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.106339] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.106417] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.106447] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.106478] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.106533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.106565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.106597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.106628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.106658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.106691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.106724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.106747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.106768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.106787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.106805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.106832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.106858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.108911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.108932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.108951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.108974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.110551] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.110571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.110590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.112137] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.112158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.114019] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.117333] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.117401] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.117439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.117491] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.134196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.134247] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.134412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.134684] [drm:drm_mode_addfb2] [FB:78]
>[ 1226.134824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.150836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.150881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.150969] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.168000] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.168039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.168079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.168119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.168164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.168204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.168244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.168357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.168418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.168474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.168529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.168581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.168624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.168668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.168735] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.168777] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.168819] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.168850] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.169017] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.169029] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.169085] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.169107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.169129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.169152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.169171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.169191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.169211] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.169230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.169248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.169335] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.169367] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.169376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.169406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.169414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.169445] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.169476] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.169507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.169537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.169571] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.169600] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.169630] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.169661] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.169687] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.169720] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.169754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.169830] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.169861] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.169892] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.169943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.169975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.170006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.170036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.170065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.170095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.170129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.170161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.170193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.170222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.170251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.170303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.170337] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.172386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.172408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.172428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.172449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.173983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.174004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.174029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.175560] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.175583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.177427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.180461] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.180544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.180565] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.180593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.197375] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.197427] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.197492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.197713] [drm:drm_mode_addfb2] [FB:79]
>[ 1226.197827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.214056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.214105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.214195] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.231155] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.231194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.231234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.231268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.231391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.231442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.231491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.231542] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.231593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.231628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.231663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.231694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.231724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.231752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.231799] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.231827] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.231855] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.231876] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.231982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.231995] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.232051] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.232072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.232094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.232138] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.232159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.232181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.232202] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.232223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.232242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.232301] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.232328] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.232337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.232363] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.232371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.232398] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.232424] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.232451] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.232477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.232507] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.232533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.232560] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.232586] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.232612] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.232643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.232676] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.232753] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.232780] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.232811] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.232848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.232869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.232889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.232914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.232941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.232966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.232994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.233022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.233049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.233075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.233100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.233129] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.233154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.235213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.235234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.235255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.235334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.236893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.236914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.236932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.238488] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.238509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.240387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.243716] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.243769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.243802] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.243852] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.260552] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.260605] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.260676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.260878] [drm:drm_mode_addfb2] [FB:77]
>[ 1226.261005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.277223] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.277271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.277440] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.294441] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.294479] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.294519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.294553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.294589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.294620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.294649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.294680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.294716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.294749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.294780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.294811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.294839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.294867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.294922] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.294969] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.295025] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.295044] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.295178] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.295190] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.295257] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.295333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.295368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.295407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.295439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.295475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.295509] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.295542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.295574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.295606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.295637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.295646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.295675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.295682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.295711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.295741] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.295772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.295802] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.295834] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.295863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.295892] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.295921] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.295949] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.295982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.296016] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.296113] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.296145] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.296175] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.296227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.296259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.296314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.296346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.296375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.296407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.296445] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.296478] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.296512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.296541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.296572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.296607] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.296639] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.298786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.298817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.298836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.298856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.300428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.300448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.300466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.302012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.302034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.303898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.307214] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.307342] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.307376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.307422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.324060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.324113] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.324185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.324517] [drm:drm_mode_addfb2] [FB:78]
>[ 1226.324656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.340774] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.340825] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.340915] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.357934] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.357972] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.358012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.358045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.358081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.358112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.358142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.358173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.358208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.358241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.358363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.358404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.358444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.358481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.358554] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.358613] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.358669] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.358713] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.358870] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.358886] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.358960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.358988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.359018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.359051] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.359077] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.359105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.359133] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.359160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.359193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.359227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.359266] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.359315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.359353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.359372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.359404] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.359435] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.359464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.359493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.359527] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.359556] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.359586] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.359615] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.359643] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.359679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.359716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.359798] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.359832] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.359866] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.359924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.359959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.359993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.360016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.360037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.360064] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.360101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.360126] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.360149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.360169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.360189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.360214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.360242] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.362343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.362364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.362383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.362402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.363972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.363992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.364010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.365572] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.365594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.367465] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.370771] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.370843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.370871] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.370907] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.387626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.387676] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.387742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.387934] [drm:drm_mode_addfb2] [FB:79]
>[ 1226.388068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.404370] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.404418] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.404508] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.421496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.421538] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.421583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.421624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.421668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.421709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.421749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.421788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.421833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.421879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.421912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.421942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.421969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.421994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.422042] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.422078] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.422117] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.422145] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.422393] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.422420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.422553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.422602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.422651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.422703] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.422746] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.422793] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.422839] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.422889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.422926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.422962] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.422997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.423006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.423042] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.423050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.423086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.423121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.423156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.423191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.423231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.423266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.423333] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.423420] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.423456] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.423497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.423538] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.423629] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.423665] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.423701] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.423762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.423800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.423837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.423881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.423912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.423940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.423974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.424006] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.424038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.424067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.424096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.424129] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.424161] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.426232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.426254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.426322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.426357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.427930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.427950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.427968] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.429520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.429543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.431410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.433822] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.433882] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.433915] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.433957] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.450661] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.450712] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.450777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.450972] [drm:drm_mode_addfb2] [FB:77]
>[ 1226.451110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.467380] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.467429] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.467518] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.484502] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.484539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.484579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.484613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.484648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.484688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.484728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.484768] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.484812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.484855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.484897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.484939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.484979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.485018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.485076] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.485122] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.485173] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.485209] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.485420] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.485440] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.485531] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.485562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.485595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.485631] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.485659] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.485691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.485721] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.485751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.485779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.485808] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.485833] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.485840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.485868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.485874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.485903] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.485928] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.485956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.485981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.486012] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.486038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.486066] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.486091] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.486118] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.486148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.486181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.486252] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.486307] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.486337] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.486390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.486422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.486450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.486480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.486507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.486537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.486572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.486605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.486638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.486665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.486695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.486729] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.486757] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.488848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.488877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.488896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.488919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.490499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.490521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.490541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.492104] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.492128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.494005] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.497323] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.497388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.497420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.497450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.514172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.514223] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.514366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.514620] [drm:drm_mode_addfb2] [FB:78]
>[ 1226.514751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.530886] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.530939] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.531032] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.549813] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.549851] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.549891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.549925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.549960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.549991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.550020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.550051] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.550086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.550119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.550151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.550182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.550211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.550239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.550379] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.550445] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.550507] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.550559] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.550704] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.550723] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.550809] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.550839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.550871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.550907] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.550934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.550966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.550995] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.551024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.551052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.551081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.551106] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.551114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.551140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.551147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.551175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.551201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.551230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.551280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.551313] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.551340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.551369] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.551396] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.551424] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.551458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.551493] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.551586] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.551617] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.551646] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.551697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.551727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.551754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.551782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.551809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.551838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.551870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.551902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.551933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.551959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.551986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.552017] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.552046] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.554109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.554132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.554155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.554179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.555742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.555763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.555781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.557359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.557379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.559241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.562587] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.562641] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.562674] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.562716] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.579418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.579470] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.579542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.579780] [drm:drm_mode_addfb2] [FB:79]
>[ 1226.579899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.596135] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.596184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.596273] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.613324] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.613362] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.613402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.613436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.613479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.613520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.613560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.613600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.613644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.613687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.613729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.613771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.613811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.613850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.613900] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.613925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.613954] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.613973] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.614098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.614110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.614167] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.614190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.614213] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.614250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.614321] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.614359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.614395] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.614430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.614462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.614494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.614524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.614533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.614562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.614570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.614600] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.614630] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.614661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.614690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.614724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.614753] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.614784] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.614813] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.614844] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.614878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.614913] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.614993] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.615025] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.615055] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.615108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.615140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.615170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.615200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.615231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.615283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.615316] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.615350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.615383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.615413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.615439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.615473] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.615504] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.617580] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.617603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.617623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.617644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.619261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.619301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.619320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.620884] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.620906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.622779] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.626123] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.626198] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.626218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.626244] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.643011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.643059] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.643123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.643532] [drm:drm_mode_addfb2] [FB:77]
>[ 1226.643659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.659669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.659717] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.659805] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.676817] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.676860] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.676904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.676945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.676989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.677029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.677069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.677109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.677154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.677196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.677239] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.677351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.677382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.677411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.677467] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.677513] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.677557] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.677591] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.677724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.677737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.677794] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.677815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.677838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.677866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.677892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.677918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.677944] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.677971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.677996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.678022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.678047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.678053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.678077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.678083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.678108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.678135] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.678160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.678186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.678212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.678241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.678301] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.678331] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.678360] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.678393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.678426] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.678503] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.678533] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.678564] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.678617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.678650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.678680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.678711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.678740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.678771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.678805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.678838] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.678867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.678894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.678924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.678953] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.678974] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.681033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.681054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.681072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.681091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.682666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.682686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.682704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.684247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.684292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.686158] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.689503] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.689591] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.689625] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.689651] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.706370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.706419] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.706483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.706692] [drm:drm_mode_addfb2] [FB:78]
>[ 1226.706818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.723048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.723097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.723186] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.741978] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.742020] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.742066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.742107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.742151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.742191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.742231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.742351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.742412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.742467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.742516] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.742566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.742608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.742652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.742742] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.742786] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.742827] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.742859] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.743022] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.743034] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.743089] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.743114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.743138] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.743164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.743187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.743211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.743245] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.743326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.743357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.743386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.743414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.743422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.743449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.743457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.743487] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.743515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.743543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.743569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.743604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.743633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.743663] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.743693] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.743723] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.743756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.743791] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.743840] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.743859] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.743878] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.743912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.743932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.743951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.743970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.743988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.744008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.744036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.744058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.744080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.744098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.744117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.744139] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.744160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.746203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.746223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.746297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.746330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.747905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.747927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.747948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.749513] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.749534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.751411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.754741] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.754794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.754827] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.754868] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.771572] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.771625] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.771696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.771912] [drm:drm_mode_addfb2] [FB:79]
>[ 1226.772049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.788249] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.788328] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.788418] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.806527] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.806564] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.806604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.806638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.806673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.806704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.806734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.806765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.806801] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.806833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.806865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.806896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.806924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.806952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.807005] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.807047] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.807086] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.807105] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.807292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.807313] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.807402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.807426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.807450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.807476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.807500] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.807527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.807554] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.807578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.807605] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.807631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.807656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.807662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.807687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.807692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.807718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.807744] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.807770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.807796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.807822] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.807847] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.807874] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.807900] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.807926] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.807953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.807982] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.808032] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.808054] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.808076] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.808115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.808142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.808186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.808215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.808238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.808291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.808324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.808356] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.808387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.808415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.808442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.808474] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.808504] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.810576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.810601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.810621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.810642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.812246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.812284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.812305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.813875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.813897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.815770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.819085] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.819154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.819187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.819229] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.835929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.835980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.836050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.836341] [drm:drm_mode_addfb2] [FB:77]
>[ 1226.836539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.852664] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.852713] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.852786] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.871181] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.871218] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.871347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.871400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.871457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.871505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.871553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.871602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.871659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.871712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.871764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.871814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.871860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.871905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.871990] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.872056] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.872119] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.872170] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.872446] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.872460] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.872525] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.872548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.872579] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.872602] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.872620] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.872640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.872660] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.872679] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.872697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.872715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.872732] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.872736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.872752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.872756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.872773] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.872790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.872807] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.872823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.872842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.872864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.872888] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.872911] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.872935] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.872960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.872985] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.873045] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.873065] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.873085] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.873122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.873146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.873170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.873193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.873217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.873300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.873335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.873367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.873399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.873426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.873454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.873487] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.873516] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.875596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.875620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.875641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.875661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.877242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.877280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.877299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.878859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.878882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.880781] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.884083] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.884166] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.884198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.884240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.900947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.901000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.901071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.901473] [drm:drm_mode_addfb2] [FB:78]
>[ 1226.901589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.917666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.917736] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.917825] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.934802] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.934839] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.934879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.934912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.934947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.934978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.935007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.935039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.935082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.935125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.935167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.935209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.935249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.935364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.935450] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.935518] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.935584] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.935640] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.935785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.935803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.935893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.935925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.935960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.935997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.936028] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.936061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.936093] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.936124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.936156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.936186] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.936215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.936247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.936279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.936287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.936315] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.936345] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.936376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.936405] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.936440] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.936470] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.936501] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.936531] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.936561] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.936593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.936628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.936716] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.936747] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.936778] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.936830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.936862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.936893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.936923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.936953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.936984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.937018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.937050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.937082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.937111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.937140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.937174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1226.937205] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1226.939298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1226.939318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1226.939337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.939355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1226.940918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1226.940942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1226.940963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1226.942505] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1226.942527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1226.944406] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1226.947753] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1226.947826] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1226.947850] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1226.947881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1226.964624] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.964677] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.964749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.964967] [drm:drm_mode_addfb2] [FB:79]
>[ 1226.965102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.981282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1226.981329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1226.981401] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1226.998388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1226.998426] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1226.998466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.998501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1226.998537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1226.998567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1226.998597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1226.998629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1226.998664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1226.998696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1226.998727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1226.998759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1226.998787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1226.998824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1226.998882] [drm:intel_power_well_disable [i915]] disabling display
>[ 1226.998929] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1226.998966] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1226.998985] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1226.999118] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1226.999129] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1226.999186] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1226.999209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1226.999244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1226.999316] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1226.999346] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1226.999378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1226.999409] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1226.999438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1226.999467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1226.999494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1226.999521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1226.999529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.999555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1226.999563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1226.999593] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1226.999622] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1226.999648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1226.999674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1226.999704] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1226.999733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1226.999758] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1226.999778] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1226.999796] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1226.999818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1226.999841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1226.999894] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1226.999914] [drm:intel_power_well_enable [i915]] enabling display
>[ 1226.999932] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1226.999971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1226.999997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.000023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.000049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.000076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.000102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.000131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.000168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.000199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.000219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.000269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.000302] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.000332] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.002403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.002424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.002442] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.002461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.004031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.004055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.004078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.005640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.005662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.007534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.010864] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.010920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.010961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.011012] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.027706] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.027759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.027832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.028051] [drm:drm_mode_addfb2] [FB:77]
>[ 1227.028185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.044374] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.044424] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.044514] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.061519] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.061556] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.061596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.061630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.061665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.061695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.061724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.061755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.061790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.061822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.061854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.061886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.061913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.061941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.061995] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.062036] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.062078] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.062109] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.062371] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.062397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.062522] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.062568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.062614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.062664] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.062705] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.062749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.062793] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.062835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.062877] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.062917] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.062956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.062966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.063003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.063013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.063051] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.063090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.063128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.063166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.063208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.063292] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.063320] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.063350] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.063381] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.063418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.063453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.063550] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.063582] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.063613] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.063666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.063697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.063725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.063756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.063785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.063813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.063846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.063880] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.063912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.063942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.063972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.064006] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.064038] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.066109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.066131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.066150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.066169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.067766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.067786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.067804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.069434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.069454] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.071336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.074566] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.074602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.074626] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.074657] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.091398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.091448] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.091514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.091725] [drm:drm_mode_addfb2] [FB:78]
>[ 1227.091855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.108072] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.108124] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.108216] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.125247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.125316] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.125355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.125389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.125424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.125463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.125503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.125543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.125587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.125630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.125672] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.125714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.125753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.125792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.125851] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.125897] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.125948] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.125984] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.126200] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.126298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.126449] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.126503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.126566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.126620] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.126665] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.126714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.126764] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.126811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.126857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.126902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.126946] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.126956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.126998] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.127009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.127054] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.127097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.127140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.127182] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.127229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.127314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.127354] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.127399] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.127443] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.127494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.127557] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.127633] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.127665] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.127695] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.127746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.127779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.127807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.127837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.127868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.127900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.127935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.127968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.128001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.128030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.128056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.128090] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.128122] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.130193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.130214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.130289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.130325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.131884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.131905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.131922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.133489] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.133509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.135375] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.138708] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.138804] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.138831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.138867] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.155598] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.155651] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.155722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.155945] [drm:drm_mode_addfb2] [FB:79]
>[ 1227.156083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.172282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.172331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.172406] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.189408] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.189446] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.189486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.189520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.189555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.189586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.189615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.189647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.189682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.189715] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.189746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.189778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.189805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.189833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.189886] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.189928] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.189972] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.189997] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.190188] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.190272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.190392] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.190436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.190481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.190529] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.190569] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.190608] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.190636] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.190662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.190687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.190711] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.190734] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.190740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.190763] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.190768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.190792] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.190814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.190838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.190860] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.190888] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.190910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.190933] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.190955] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.190985] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.191011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.191040] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.191101] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.191123] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.191145] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.191185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.191209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.191269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.191302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.191334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.191368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.191404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.191439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.191475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.191506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.191538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.191578] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.191613] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.193711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.193732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.193751] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.193771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.195349] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.195373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.195396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.196967] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.196991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.198855] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.202178] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.202222] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.202304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.202349] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.219015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.219068] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.219139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.219481] [drm:drm_mode_addfb2] [FB:77]
>[ 1227.219635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.235695] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.235744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.235817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.254158] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.254196] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.254312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.254362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.254421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.254466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.254512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.254557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.254610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.254661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.254710] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.254760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.254800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.254843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.254927] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.254991] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.255053] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.255103] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.255357] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.255378] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.255455] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.255478] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.255510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.255534] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.255553] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.255594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.255616] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.255645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.255664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.255681] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.255703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.255708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.255730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.255735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.255758] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.255782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.255806] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.255829] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.255852] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.255875] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.255899] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.255922] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.255946] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.255970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.255996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.256055] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.256075] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.256095] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.256131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.256155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.256179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.256202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.256286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.256318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.256351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.256382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.256413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.256441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.256467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.256501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.256530] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.258600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.258621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.258644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.258668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.260311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.260332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.260351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.261917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.261940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.263815] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.267131] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.267198] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.267313] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.267384] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.283980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.284031] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.284097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.284508] [drm:drm_mode_addfb2] [FB:78]
>[ 1227.284624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.300693] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.300742] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.300813] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.319136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.319173] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.319213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.319329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.319387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.319432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.319477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.319523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.319577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.319627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.319686] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.319717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.319743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.319770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.319825] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.319868] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.319909] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.319940] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.320113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.320126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.320184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.320218] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.320293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.320330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.320359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.320392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.320422] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.320452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.320481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.320508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.320538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.320546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.320574] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.320581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.320609] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.320639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.320668] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.320697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.320730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.320759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.320788] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.320817] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.320848] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.320878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.320903] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.320968] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.320999] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.321025] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.321061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.321081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.321100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.321125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.321151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.321177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.321205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.321259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.321293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.321320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.321349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.321382] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.321411] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.323486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.323507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.323526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.323546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.325108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.325130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.325150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.326710] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.326731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.328625] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.331932] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.331992] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.332011] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.332036] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.348785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.348836] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.348901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.349113] [drm:drm_mode_addfb2] [FB:79]
>[ 1227.349329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.365459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.365508] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.365581] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.384334] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.384381] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.384422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.384456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.384491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.384521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.384550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.384581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.384627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.384676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.384709] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.384740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.384768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.384796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.384844] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.384869] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.384895] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.384914] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.385051] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.385064] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.385123] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.385146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.385170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.385195] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.385225] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.385297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.385328] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.385358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.385387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.385415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.385441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.385450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.385476] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.385483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.385510] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.385537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.385564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.385590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.385620] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.385650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.385679] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.385708] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.385736] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.385766] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.385801] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.385856] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.385875] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.385893] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.385927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.385947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.385972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.385998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.386024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.386050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.386078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.386107] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.386135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.386161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.386186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.386215] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.386271] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.388327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.388347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.388366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.388385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.389949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.389969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.389988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.391560] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.391584] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.393457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.396788] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.396902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.396943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.396995] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.413678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.413739] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.413820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.414035] [drm:drm_mode_addfb2] [FB:77]
>[ 1227.414162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.430374] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.430423] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.430515] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.447561] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.447612] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.447653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.447687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.447723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.447753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.447783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.447814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.447849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.447882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.447914] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.447945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.447973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.448001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.448055] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.448097] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.448122] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.448141] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.448302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.448323] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.448397] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.448421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.448446] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.448471] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.448491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.448514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.448536] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.448557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.448578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.448597] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.448617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.448622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.448640] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.448645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.448664] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.448682] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.448701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.448718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.448740] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.448758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.448777] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.448801] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.448828] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.448857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.448886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.448953] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.448975] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.448996] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.449036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.449062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.449088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.449114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.449140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.449165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.449193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.449266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.449300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.449329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.449356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.449389] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.449418] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.451492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.451514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.451533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.451552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.453113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.453134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.453153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.454731] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.454755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.456616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.459285] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.459347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.459374] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.459408] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.476130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.476182] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.476347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.476615] [drm:drm_mode_addfb2] [FB:78]
>[ 1227.476744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.492820] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.492868] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.492961] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.510023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.510061] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.510101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.510135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.510170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.510199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.510324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.510385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.510439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.510486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.510533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.510578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.510619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.510660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.510737] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.510796] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.510852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.510898] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.511103] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.511120] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.511201] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.511306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.511354] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.511417] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.511450] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.511489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.511527] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.511563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.511599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.511633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.511668] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.511677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.511702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.511708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.511730] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.511750] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.511771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.511799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.511830] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.511859] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.511889] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.511918] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.511948] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.511979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.512011] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.512073] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.512097] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.512123] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.512167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.512197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.512258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.512294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.512327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.512360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.512397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.512440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.512471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.512497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.512524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.512557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.512586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.514654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.514677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.514700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.514724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.516320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.516341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.516359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.517917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.517939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.519813] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.523127] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.523197] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.523298] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.523369] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.539977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.540027] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.540092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.540521] [drm:drm_mode_addfb2] [FB:79]
>[ 1227.540671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.556669] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.556714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.556784] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.575153] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.575191] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.575313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.575368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.575423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.575466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.575513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.575557] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.575611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.575661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.575711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.575760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.575802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.575830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.575884] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.575925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.575971] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.576001] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.576148] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.576162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.576289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.576327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.576364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.576443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.576474] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.576508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.576550] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.576580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.576609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.576637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.576664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.576671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.576698] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.576704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.576732] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.576759] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.576786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.576821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.576853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.576881] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.576910] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.576936] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.576963] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.576995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.577028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.577099] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.577129] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.577158] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.577208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.577279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.577309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.577342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.577373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.577406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.577441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.577475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.577508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.577539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.577570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.577605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.577637] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.579707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.579727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.579745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.579764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.581335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.581355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.581374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.582921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.582942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.584809] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.588083] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.588124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.588143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.588169] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.604929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.604980] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.605046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.605494] [drm:drm_mode_addfb2] [FB:77]
>[ 1227.605610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.621625] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.621677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.621757] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.640153] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.640192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.640325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.640379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.640436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.640485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.640532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.640582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.640639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.640693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.640745] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.640796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.640842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.640887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.640974] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.641040] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.641102] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.641162] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.641387] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.641410] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.641519] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.641547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.641579] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.641616] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.641646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.641679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.641711] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.641743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.641775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.641802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.641828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.641834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.641865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.641871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.641903] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.641934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.641966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.641996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.642028] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.642057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.642089] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.642120] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.642151] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.642191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.642273] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.642351] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.642382] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.642414] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.642468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.642500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.642533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.642562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.642592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.642622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.642655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.642688] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.642722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.642749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.642778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.642812] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.642842] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.644936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.644958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.644977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.644996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.646573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.646597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.646620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.648207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.648247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.650125] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.653468] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.653543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.653563] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.653589] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.670337] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.670387] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.670453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.670667] [drm:drm_mode_addfb2] [FB:78]
>[ 1227.670794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.687013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.687061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.687148] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.705264] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.705301] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.705340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.705374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.705409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.705439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.705468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.705499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.705535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.705568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.705600] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.705640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.705664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.705687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.705732] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.705767] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.705802] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.705828] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.706009] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.706026] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.706106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.706139] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.706172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.706208] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.706295] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.706338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.706378] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.706417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.706456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.706492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.706527] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.706538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.706573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.706582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.706618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.706653] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.706701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.706740] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.706785] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.706827] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.706870] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.706909] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.706948] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.706998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.707048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.707184] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.707263] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.707308] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.707386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.707434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.707479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.707523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.707564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.707607] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.707654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.707704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.707751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.707787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.707821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.707862] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.707900] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.709985] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.710010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.710030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.710051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.711627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.711648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.711666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.713245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.713266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.715126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.718458] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.718560] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.718592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.718634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.735342] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.735408] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.735485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.735699] [drm:drm_mode_addfb2] [FB:79]
>[ 1227.735824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.752057] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.752105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.752193] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.769279] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.769317] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.769357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.769391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.769426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.769456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.769486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.769517] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.769552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.769584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.769624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.769668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.769707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.769746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.769804] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.769851] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.769902] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.769938] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.770096] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.770108] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.770165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.770198] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.770312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.770350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.770382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.770416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.770449] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.770482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.770513] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.770544] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.770574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.770582] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.770610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.770617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.770647] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.770677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.770706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.770735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.770769] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.770798] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.770827] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.770856] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.770885] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.770918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.770953] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.771045] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.771076] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.771107] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.771158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.771190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.771241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.771273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.771301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.771333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.771369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.771403] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.771437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.771467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.771497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.771532] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.771564] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.773643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.773667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.773688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.773708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.775303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.775323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.775341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.776902] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.776923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.778786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.782069] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.782170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.782210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.782293] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.798951] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.799001] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.799068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.799393] [drm:drm_mode_addfb2] [FB:77]
>[ 1227.799535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.815666] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.815714] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.815804] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.832790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.832828] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.832868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.832903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.832938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.832969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.832998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.833030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.833074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.833117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.833159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.833201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.833298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.833347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.833414] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.833457] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.833488] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.833509] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.833646] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.833665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.833734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.833757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.833780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.833805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.833826] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.833848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.833874] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.833900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.833926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.833952] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.833978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.833983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.834008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.834013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.834039] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.834065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.834090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.834115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.834141] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.834166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.834196] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.834258] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.834287] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.834321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.834354] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.834431] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.834460] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.834492] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.834546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.834578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.834609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.834640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.834670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.834701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.834731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.834753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.834779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.834806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.834832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.834860] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.834886] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.836932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.836954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.836972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.836991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.838566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.838586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.838604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.840195] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.840241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.842099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.845442] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.845534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.845568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.845610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.862313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.862364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.862429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.862641] [drm:drm_mode_addfb2] [FB:78]
>[ 1227.862774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.879029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.879077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.879167] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.896205] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.896275] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.896319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.896361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.896406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.896446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.896486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.896526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.896570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.896613] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.896655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.896698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.896739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.896760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.896793] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.896819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.896847] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.896866] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.897001] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.897013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.897070] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.897093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.897116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.897142] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.897166] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.897201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.897274] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.897308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.897342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.897374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.897405] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.897413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.897443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.897451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.897481] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.897512] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.897542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.897572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.897606] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.897636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.897668] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.897697] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.897728] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.897761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.897796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.897876] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.897907] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.897937] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.897991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.898023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.898053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.898083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.898113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.898144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.898179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.898237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.898270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.898302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.898374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.898408] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.898440] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.900528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.900550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.900569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.900588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.902201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.902239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.902257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.903821] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.903845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.905730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.909020] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.909098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.909118] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.909143] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.925880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.925928] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.925991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.926436] [drm:drm_mode_addfb2] [FB:79]
>[ 1227.926557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.942569] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1227.942617] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1227.942706] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1227.959739] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1227.959777] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1227.959816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.959849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.959884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.959914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.959944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.959976] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.960011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.960051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.960081] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.960110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.960136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.960162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.960283] [drm:intel_power_well_disable [i915]] disabling display
>[ 1227.960350] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1227.960412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.960461] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1227.960666] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1227.960683] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1227.960766] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1227.960799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1227.960835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1227.960871] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1227.960901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1227.960934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1227.960965] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1227.961003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1227.961048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1227.961071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1227.961096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1227.961102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.961127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1227.961132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1227.961158] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1227.961183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1227.961238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1227.961268] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1227.961299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1227.961329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1227.961358] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1227.961388] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1227.961416] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1227.961447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1227.961479] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1227.961569] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1227.961601] [drm:intel_power_well_enable [i915]] enabling display
>[ 1227.961631] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1227.961686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1227.961718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1227.961750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1227.961781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1227.961811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1227.961835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1227.961857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1227.961878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1227.961899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.961917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1227.961936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1227.961959] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1227.961980] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1227.964020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1227.964041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1227.964060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.964079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1227.965650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1227.965670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1227.965687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1227.967256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1227.967277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1227.969143] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1227.972420] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1227.972460] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1227.972484] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1227.972516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1227.989256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1227.989309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1227.989381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1227.989595] [drm:drm_mode_addfb2] [FB:77]
>[ 1227.989727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.005931] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.005997] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.006102] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.023073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.023111] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.023151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.023185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.023313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.023364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.023413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.023463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.023510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.023546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.023579] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.023610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.023638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.023666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.023721] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.023763] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.023806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.023838] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.024004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.024023] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.024109] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.024141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.024185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.024284] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.024332] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.024373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.024410] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.024447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.024482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.024516] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.024548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.024559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.024592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.024601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.024635] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.024668] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.024701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.024734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.024772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.024805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.024839] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.024875] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.024910] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.025001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.025045] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.025156] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.025196] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.025264] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.025334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.025367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.025397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.025426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.025454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.025484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.025520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.025554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.025588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.025617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.025648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.025676] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.025698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.027774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.027795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.027813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.027832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.029398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.029419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.029437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.030984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.031006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.032869] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.036232] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.036305] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.036346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.036398] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.053082] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.053133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.053198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.053562] [drm:drm_mode_addfb2] [FB:78]
>[ 1228.053712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.069765] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.069811] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.069880] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.088131] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.088169] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.088299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.088335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.088375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.088406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.088437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.088469] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.088506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.088540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.088572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.088604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.088636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.088655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.088690] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.088717] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.088745] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.088765] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.088901] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.088919] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.088980] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.089001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.089024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.089049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.089069] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.089090] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.089112] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.089132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.089152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.089172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.089239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.089249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.089279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.089287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.089319] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.089346] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.089375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.089401] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.089434] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.089461] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.089490] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.089518] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.089546] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.089576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.089610] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.089687] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.089717] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.089747] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.089797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.089828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.089856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.089884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.089910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.089940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.089972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.090003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.090034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.090060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.090088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.090121] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.090162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.092249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.092280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.092298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.092317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.093889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.093909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.093927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.095489] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.095511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.097382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.100708] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.100769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.100809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.100855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.117558] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.117609] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.117674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.117907] [drm:drm_mode_addfb2] [FB:79]
>[ 1228.118055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.134291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.134339] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.134411] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.151394] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.151432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.151473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.151507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.151542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.151573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.151603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.151634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.151669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.151701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.151733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.151764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.151791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.151818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.151872] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.151913] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.151963] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.151990] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.152157] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.152244] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.152368] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.152400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.152433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.152466] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.152492] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.152522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.152551] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.152579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.152613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.152647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.152680] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.152688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.152721] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.152727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.152761] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.152795] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.152830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.152863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.152898] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.152931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.152976] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.153004] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.153030] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.153059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.153088] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.153162] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.153215] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.153249] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.153311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.153347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.153381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.153414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.153498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.153531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.153559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.153583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.153609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.153631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.153653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.153680] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.153705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.155852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.155874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.155893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.155912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.157480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.157502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.157522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.159062] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.159086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.160959] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.164255] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.164327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.164347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.164373] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.181120] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.181171] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.181335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.181594] [drm:drm_mode_addfb2] [FB:77]
>[ 1228.181723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.197814] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.197863] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.197935] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.215963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.216001] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.216041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.216075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.216113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.216154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.216194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.216314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.216380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.216442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.216486] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.216529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.216569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.216608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.216675] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.216730] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.216783] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.216826] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.217033] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.217049] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.217126] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.217157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.217188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.217278] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.217317] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.217363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.217405] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.217456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.217485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.217515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.217542] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.217549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.217576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.217585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.217614] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.217641] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.217669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.217695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.217726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.217751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.217779] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.217804] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.217833] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.217866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.217900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.217977] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.218006] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.218036] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.218086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.218116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.218143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.218172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.218221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.218250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.218283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.218316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.218349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.218376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.218405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.218440] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.218468] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.220540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.220564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.220587] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.220611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.222176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.222208] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.222227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.223794] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.223817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.225725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.229003] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.229054] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.229085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.229124] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.245838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.245889] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.245954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.246165] [drm:drm_mode_addfb2] [FB:78]
>[ 1228.246405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.262554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.262602] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.262675] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.280298] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.280336] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.280376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.280410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.280445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.280476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.280505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.280537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.280572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.280605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.280637] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.280668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.280696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.280723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.280777] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.280820] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.280846] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.280865] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.280992] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.281004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.281062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.281085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.281109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.281133] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.281153] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.281185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.281249] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.281279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.281308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.281336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.281362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.281371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.281397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.281404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.281431] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.281458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.281484] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.281510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.281541] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.281567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.281594] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.281620] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.281646] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.281676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.281712] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.281801] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.281821] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.281839] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.281874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.281894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.281913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.281931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.281949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.281969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.281990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.282017] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.282045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.282071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.282096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.282124] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.282150] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.284249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.284271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.284290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.284309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.285885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.285906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.285924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.287494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.287517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.289391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.292721] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.292774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.292807] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.292850] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.309553] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.309604] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.309670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.309880] [drm:drm_mode_addfb2] [FB:79]
>[ 1228.309995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.326275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.326324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.326396] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.343382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.343419] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.343459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.343493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.343528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.343558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.343588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.343620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.343655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.343686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.343718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.343749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.343777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.343803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.343857] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.343898] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.343940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.343971] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.344162] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.344248] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.344389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.344425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.344461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.344497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.344527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.344560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.344592] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.344622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.344652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.344680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.344707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.344715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.344741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.344747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.344775] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.344808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.344847] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.344882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.344922] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.344959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.344997] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.345036] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.345074] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.345114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.345155] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.345307] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.345340] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.345376] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.345443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.345483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.345520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.345557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.345593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.345631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.345673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.345712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.345751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.345787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.345815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.345843] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.345869] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.347932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.347956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.347980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.348004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.349582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.349604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.349622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.351180] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.351218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.353086] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.356421] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.356453] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.356476] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.356508] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.373294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.373344] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.373410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.373620] [drm:drm_mode_addfb2] [FB:77]
>[ 1228.373748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.389916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.389964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.390036] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.408954] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.408991] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.409031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.409066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.409101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.409131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.409161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.409268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.409324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.409380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.409432] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.409484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.409539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.409576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.409640] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.409694] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.409744] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.409784] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.409981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.410004] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.410114] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.410155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.410247] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.410294] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.410334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.410376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.410417] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.410457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.410497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.410540] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.410567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.410575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.410605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.410612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.410642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.410673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.410700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.410730] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.410763] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.410795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.410822] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.410856] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.410887] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.410922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.410959] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.411053] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.411085] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.411118] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.411174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.411235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.411264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.411296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.411326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.411359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.411394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.411429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.411464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.411495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.411535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.411570] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.411601] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.413686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.413707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.413730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.413754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.415352] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.415374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.415394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.416968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.416991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.418866] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.421777] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.421829] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.421849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.421874] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.438634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.438687] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.438758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.438969] [drm:drm_mode_addfb2] [FB:78]
>[ 1228.439133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.455325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.455375] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.455467] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.474110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.474147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.474270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.474324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.474383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.474432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.474472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.474507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.474544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.474579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.474612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.474644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.474673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.474702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.474755] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.474803] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.474831] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.474852] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.474989] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.475002] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.475062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.475089] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.475116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.475145] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.475177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.475240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.475271] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.475302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.475331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.475358] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.475385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.475393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.475420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.475427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.475454] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.475481] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.475508] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.475533] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.475563] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.475590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.475617] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.475645] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.475674] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.475706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.475738] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.475814] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.475845] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.475875] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.475929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.475961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.475991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.476022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.476052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.476083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.476112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.476135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.476155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.476207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.476233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.476266] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.476294] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.478364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.478384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.478403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.478421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.479997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.480017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.480035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.481603] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.481625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.483499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.486834] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.486934] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.486967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.487009] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.503709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.503760] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.503825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.504041] [drm:drm_mode_addfb2] [FB:79]
>[ 1228.504170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.520411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.520459] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.520532] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.538608] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.538645] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.538685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.538719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.538753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.538783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.538811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.538842] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.538877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.538910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.538941] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.538973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.539000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.539028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.539083] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.539109] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.539133] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.539152] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.539363] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.539382] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.539468] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.539493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.539517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.539542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.539562] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.539584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.539605] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.539625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.539645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.539663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.539682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.539686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.539704] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.539709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.539734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.539760] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.539785] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.539811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.539837] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.539862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.539888] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.539914] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.539939] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.539967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.539994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.540056] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.540078] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.540099] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.540139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.540165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.540220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.540251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.540282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.540311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.540345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.540377] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.540407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.540434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.540460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.540492] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.540523] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.542605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.542629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.542652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.542677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.544293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.544314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.544332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.545891] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.545912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.547784] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.551069] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.551171] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.551272] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.551339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.567944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.567995] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.568061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.568398] [drm:drm_mode_addfb2] [FB:77]
>[ 1228.568606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.584630] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.584691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.584780] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.601767] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.601806] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.601846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.601880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.601915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.601945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.601975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.602007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.602042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.602074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.602105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.602137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.602165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.602272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.602359] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.602403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.602445] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.602478] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.602621] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.602640] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.602729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.602762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.602796] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.602833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.602865] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.602898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.602931] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.602962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.602993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.603023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.603053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.603061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.603089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.603097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.603126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.603155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.603214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.603243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.603276] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.603307] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.603337] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.603367] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.603397] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.603432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.603468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.603542] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.603573] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.603606] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.603658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.603689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.603719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.603749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.603781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.603812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.603846] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.603879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.603911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.603940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.603969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.604003] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.604034] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.606112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.606133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.606152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.606221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.607792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.607812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.607834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.609409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.609429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.611294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.614604] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.614661] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.614681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.614712] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.631457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.631508] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.631575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.631788] [drm:drm_mode_addfb2] [FB:78]
>[ 1228.631904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.648130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.648178] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.648358] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.665332] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.665370] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.665409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.665443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.665477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.665508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.665537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.665568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.665603] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.665636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.665667] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.665703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.665728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.665752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.665800] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.665839] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.665884] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.665916] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.666095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.666112] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.666288] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.666333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.666380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.666433] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.666474] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.666522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.666559] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.666588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.666616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.666643] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.666669] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.666676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.666701] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.666706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.666734] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.666759] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.666784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.666808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.666839] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.666865] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.666896] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.666935] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.666968] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.666998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.667032] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.667106] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.667133] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.667158] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.667263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.667303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.667343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.667381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.667418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.667457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.667502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.667545] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.667587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.667623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.667660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.667705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.667748] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.669816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.669837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.669855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.669874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.671454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.671474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.671492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.673042] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.673063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.674932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.678264] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.678314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.678345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.678385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.695099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.695150] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.695357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.695609] [drm:drm_mode_addfb2] [FB:79]
>[ 1228.695734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.711791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.711844] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.711923] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.730103] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.730153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.730284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.730333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.730392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.730436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.730482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.730527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.730581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.730634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.730685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.730734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.730774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.730818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.730896] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.730937] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.730983] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.731012] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.731204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.731225] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.731313] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.731337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.731360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.731386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.731406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.731428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.731450] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.731471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.731492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.731511] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.731529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.731534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.731551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.731555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.731580] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.731606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.731632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.731657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.731683] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.731708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.731733] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.731759] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.731784] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.731811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.731839] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.731891] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.731913] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.731935] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.731974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.732000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.732026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.732051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.732077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.732102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.732129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.732158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.732230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.732259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.732288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.732322] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.732351] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.734421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.734443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.734462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.734481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.736047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.736067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.736085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.737635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.737656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.739563] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.742862] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.742948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.742981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.743022] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.759727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.759779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.759850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.760073] [drm:drm_mode_addfb2] [FB:77]
>[ 1228.760349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.776442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.776490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.776580] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.793577] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.793615] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.793655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.793690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.793733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.793774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.793814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.793854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.793898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.793941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.793983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.794025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.794065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.794103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.794161] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.794292] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.794339] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.794373] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.794530] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.794549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.794637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.794667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.794700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.794738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.794767] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.794799] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.794828] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.794859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.794887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.794916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.794944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.794951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.794978] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.794985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.795013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.795040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.795067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.795093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.795125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.795150] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.795204] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.795230] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.795261] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.795295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.795330] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.795406] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.795437] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.795467] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.795516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.795547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.795574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.795602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.795628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.795658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.795690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.795722] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.795753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.795779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.795807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.795837] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.795867] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.797924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.797946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.797966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.797986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.799562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.799582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.799601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.801152] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.801184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.803054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.806354] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.806441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.806481] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.806537] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.823216] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.823276] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.823362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.823575] [drm:drm_mode_addfb2] [FB:78]
>[ 1228.823701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.839934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.839987] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.840080] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.857039] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.857077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.857117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.857150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.857269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.857315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.857366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.857414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.857471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.857522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.857572] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.857624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.857660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.857687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.857740] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.857782] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.857823] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.857855] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.857996] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.858019] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.858075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.858097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.858119] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.858152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.858231] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.858267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.858301] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.858335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.858367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.858399] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.858429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.858438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.858466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.858473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.858503] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.858533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.858565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.858594] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.858628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.858656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.858683] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.858711] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.858740] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.858770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.858805] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.858881] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.858913] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.858943] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.858994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.859026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.859057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.859087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.859116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.859147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.859201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.859235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.859269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.859299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.859329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.859364] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.859397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.861465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.861489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.861510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.861530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.863082] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.863102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.863120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.864713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.864734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.866601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.869945] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.870019] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.870039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.870065] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.886794] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.886841] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.886905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.887114] [drm:drm_mode_addfb2] [FB:79]
>[ 1228.887367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.903491] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.903539] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.903610] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.920635] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.920672] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.920712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.920745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.920780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.920810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.920838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.920869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.920904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.920936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.920967] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.920998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.921025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.921053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.921103] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.921128] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.921213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.921250] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.921413] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.921431] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.921518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.921550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.921594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.921632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.921662] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.921695] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.921728] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.921760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.921791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.921821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.921851] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.921859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.921887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.921895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.921924] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.921954] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.921984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.922014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.922047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.922077] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.922106] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.922137] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.922190] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.922223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.922258] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.922350] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.922381] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.922412] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.922464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.922496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.922526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.922556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.922586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.922617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.922651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.922684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.922716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.922745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.922773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.922807] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.922838] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.924918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.924947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.924967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.924986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.926577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.926599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.926622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.928194] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.928217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.930084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.933386] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.933452] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.933471] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.933497] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1228.950254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.950305] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.950370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.950580] [drm:drm_mode_addfb2] [FB:77]
>[ 1228.950696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.966925] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1228.966974] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1228.967046] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1228.984067] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1228.984105] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1228.984146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.984276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.984335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.984384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.984439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.984483] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1228.984534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.984581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.984627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.984672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.984712] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.984753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.984829] [drm:intel_power_well_disable [i915]] disabling display
>[ 1228.984888] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1228.984944] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1228.984989] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1228.985234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1228.985262] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1228.985369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1228.985401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1228.985443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1228.985472] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1228.985496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1228.985522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1228.985547] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1228.985571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1228.985594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1228.985616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1228.985637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1228.985642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.985663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1228.985668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1228.985689] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1228.985710] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1228.985731] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1228.985751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1228.985776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1228.985797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1228.985818] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1228.985839] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1228.985859] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1228.985884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1228.985911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1228.985969] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1228.985991] [drm:intel_power_well_enable [i915]] enabling display
>[ 1228.986012] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1228.986051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1228.986075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1228.986098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1228.986119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1228.986149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1228.986218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1228.986257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1228.986294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1228.986330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1228.986363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1228.986394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1228.986433] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1228.986473] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1228.988532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1228.988553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1228.988571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.988590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1228.990156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1228.990192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1228.990210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1228.991780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1228.991801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1228.993681] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1228.996956] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1228.997007] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1228.997036] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1228.997073] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.013788] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.013841] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.013913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.014127] [drm:drm_mode_addfb2] [FB:78]
>[ 1229.014378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.030467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.030515] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.030588] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.049222] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.049259] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.049299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.049333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.049370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.049408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.049449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.049488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.049533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.049576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.049618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.049660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.049700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.049739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.049796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.049843] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.049873] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.049892] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.050026] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.050038] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.050096] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.050121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.050158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.050230] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.050260] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.050294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.050325] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.050355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.050385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.050413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.050440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.050447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.050474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.050481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.050509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.050539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.050568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.050597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.050628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.050654] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.050680] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.050707] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.050735] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.050762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.050787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.050852] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.050874] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.050896] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.050937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.050963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.050990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.051016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.051042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.051068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.051097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.051125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.051219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.051248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.051268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.051291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.051317] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.053359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.053383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.053406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.053430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.054993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.055014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.055033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.056599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.056620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.058491] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.061821] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.061874] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.061907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.061949] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.078651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.078705] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.078776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.078993] [drm:drm_mode_addfb2] [FB:79]
>[ 1229.079129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.095370] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.095419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.095492] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.114088] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.114125] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.114253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.114308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.114364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.114413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.114461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.114512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.114569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.114622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.114673] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.114724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.114770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.114815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.114901] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.114967] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.115029] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.115080] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.115335] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.115353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.115436] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.115468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.115500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.115525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.115544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.115564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.115584] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.115603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.115621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.115638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.115655] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.115659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.115676] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.115679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.115696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.115713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.115729] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.115745] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.115764] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.115786] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.115810] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.115833] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.115857] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.115881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.115907] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.115956] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.115976] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.115995] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.116031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.116055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.116079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.116103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.116126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.116212] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.116250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.116285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.116320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.116351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.116382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.116419] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.116452] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.118516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.118539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.118559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.118580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.120155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.120202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.120221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.121781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.121804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.123695] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.127012] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.127077] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.127110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.127230] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.143858] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.143909] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.143975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.144282] [drm:drm_mode_addfb2] [FB:77]
>[ 1229.144449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.160519] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.160565] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.160633] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.177690] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.177727] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.177766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.177800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.177835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.177865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.177894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.177926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.177961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.178003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.178046] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.178088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.178128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.178240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.178322] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.178389] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.178454] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.178508] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.178669] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.178688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.178777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.178807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.178840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.178876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.178904] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.178935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.178965] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.178995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.179023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.179052] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.179078] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.179085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.179111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.179118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.179147] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.179202] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.179229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.179259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.179290] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.179320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.179347] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.179377] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.179404] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.179437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.179472] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.179560] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.179590] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.179619] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.179670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.179701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.179728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.179757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.179783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.179812] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.179845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.179877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.179909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.179935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.179962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.179993] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.180023] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.182093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.182114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.182133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.182207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.183767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.183788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.183806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.185381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.185405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.187277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.190633] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.190712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.190743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.190769] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.207479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.207526] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.207589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.207790] [drm:drm_mode_addfb2] [FB:78]
>[ 1229.207922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.224207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.224256] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.224331] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.241271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.241309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.241349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.241384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.241419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.241449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.241478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.241510] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.241545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.241578] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.241609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.241640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.241667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.241694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.241749] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.241790] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.241828] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.241847] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.241988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.242000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.242057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.242080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.242104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.242139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.242208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.242240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.242271] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.242300] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.242329] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.242357] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.242383] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.242391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.242417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.242425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.242452] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.242478] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.242505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.242531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.242561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.242587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.242614] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.242644] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.242673] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.242703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.242739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.242820] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.242851] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.242881] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.242936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.242968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.243001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.243032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.243060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.243082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.243105] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.243125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.243180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.243207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.243234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.243267] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.243295] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.245366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.245387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.245405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.245424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.246983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.247003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.247022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.248586] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.248607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.250488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.253825] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.253924] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.253957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.253999] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.270702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.270751] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.270816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.271020] [drm:drm_mode_addfb2] [FB:79]
>[ 1229.271137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.287404] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.287453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.287528] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.305601] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.305638] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.305678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.305711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.305746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.305777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.305806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.305838] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.305874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.305907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.305939] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.305970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.305998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.306025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.306079] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.306125] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.306219] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.306250] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.306394] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.306412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.306502] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.306535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.306561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.306586] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.306607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.306629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.306650] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.306675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.306701] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.306728] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.306753] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.306759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.306784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.306789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.306815] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.306841] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.306867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.306892] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.306919] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.306944] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.306970] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.306996] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.307022] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.307049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.307078] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.307140] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.307197] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.307225] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.307278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.307309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.307338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.307367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.307394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.307424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.307456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.307490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.307522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.307550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.307581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.307615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.307647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.309730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.309751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.309769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.309788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.311369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.311389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.311407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.312956] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.312977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.314845] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.318187] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.318283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.318329] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.318357] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.335064] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.335117] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.335291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.335544] [drm:drm_mode_addfb2] [FB:77]
>[ 1229.335659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.351761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.351810] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.351886] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.368937] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.368975] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.369015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.369049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.369083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.369112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.369220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.369267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.369325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.369372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.369407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.369438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.369468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.369502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.369539] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.369567] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.369600] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.369624] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.369760] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.369779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.369845] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.369868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.369891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.369920] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.369945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.369969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.369992] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.370012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.370032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.370057] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.370082] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.370088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.370113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.370154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.370186] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.370217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.370245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.370272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.370303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.370331] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.370358] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.370386] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.370412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.370443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.370475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.370554] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.370582] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.370614] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.370669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.370701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.370732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.370763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.370793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.370824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.370858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.370890] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.370912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.370930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.370949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.370972] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.370997] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.373041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.373061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.373079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.373098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.374726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.374749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.374768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.376344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.376367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.378246] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.381589] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.381682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.381723] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.381749] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.398454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.398505] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.398570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.398784] [drm:drm_mode_addfb2] [FB:78]
>[ 1229.398915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.415192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.415240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.415315] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.432329] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.432366] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.432407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.432441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.432475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.432505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.432534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.432566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.432601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.432634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.432665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.432696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.432724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.432751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.432802] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.432828] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.432853] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.432872] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.433006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.433018] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.433076] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.433099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.433132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.433213] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.433242] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.433275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.433305] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.433337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.433366] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.433394] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.433420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.433429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.433454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.433462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.433489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.433519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.433547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.433576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.433607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.433634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.433660] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.433686] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.433715] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.433747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.433782] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.433861] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.433883] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.433905] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.433945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.433971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.433998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.434024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.434050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.434075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.434103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.434130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.434186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.434216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.434246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.434279] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.434309] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.436382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.436404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.436422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.436441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.438020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.438041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.438059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.439621] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.439642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.441554] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.444858] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.444941] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.444981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.445034] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.461716] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.461768] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.461833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.462049] [drm:drm_mode_addfb2] [FB:79]
>[ 1229.462273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.478392] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.478441] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.478529] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.495543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.495580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.495620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.495654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.495688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.495719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.495749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.495780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.495815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.495856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.495899] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.495941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.495980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.496019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.496077] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.496123] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.496237] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.496271] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.496449] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.496469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.496564] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.496598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.496634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.496671] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.496702] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.496736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.496769] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.496801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.496832] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.496863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.496893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.496901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.496930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.496937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.496967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.496997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.497026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.497055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.497088] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.497117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.497172] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.497204] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.497279] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.497313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.497348] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.497425] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.497457] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.497487] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.497538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.497570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.497600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.497630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.497660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.497691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.497726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.497759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.497791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.497820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.497849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.497883] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.497915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.499985] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.500009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.500032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.500055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.501655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.501676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.501699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.503270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.503293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.505180] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.508489] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.508557] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.508585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.508621] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.525349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.525400] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.525466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.525666] [drm:drm_mode_addfb2] [FB:77]
>[ 1229.525804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.542040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.542094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.542245] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.560565] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.560602] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.560642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.560676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.560711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.560742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.560771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.560803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.560838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.560871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.560902] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.560942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.560982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.561021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.561080] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.561126] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.561269] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.561323] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.561561] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.561580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.561668] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.561702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.561736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.561774] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.561805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.561839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.561871] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.561903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.561933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.561963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.561992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.562000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.562028] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.562035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.562065] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.562094] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.562123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.562180] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.562213] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.562244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.562274] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.562305] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.562336] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.562370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.562406] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.562482] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.562511] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.562541] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.562594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.562625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.562656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.562686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.562715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.562746] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.562779] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.562811] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.562844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.562873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.562901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.562935] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.562966] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.565038] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.565061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.565079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.565098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.566707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.566735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.566754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.568335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.568358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.570223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.573558] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.573659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.573693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.573735] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.590444] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.590494] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.590559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.590775] [drm:drm_mode_addfb2] [FB:78]
>[ 1229.590907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.607137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.607216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.607291] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.624311] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.624348] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.624387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.624420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.624455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.624486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.624515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.624546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.624581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.624614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.624645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.624677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.624705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.624733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.624787] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.624835] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.624860] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.624879] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.625007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.625020] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.625078] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.625103] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.625193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.625231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.625260] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.625294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.625324] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.625355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.625383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.625413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.625439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.625448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.625474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.625481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.625508] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.625537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.625565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.625591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.625622] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.625648] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.625677] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.625702] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.625721] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.625743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.625767] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.625819] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.625839] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.625878] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.625921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.625942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.625961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.625980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.625998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.626018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.626039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.626060] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.626080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.626098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.626117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.626173] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.626202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.628275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.628296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.628314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.628334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.629902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.629922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.629941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.631506] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.631527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.633399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.636718] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.636783] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.636816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.636858] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.653560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.653611] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.653677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.653872] [drm:drm_mode_addfb2] [FB:79]
>[ 1229.653991] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.670257] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.670304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.670393] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.687391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.687428] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.687468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.687502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.687538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.687569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.687598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.687630] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.687665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.687706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.687749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.687791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.687830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.687869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.687926] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.687973] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.688024] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.688060] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.688271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.688290] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.688381] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.688412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.688447] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.688483] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.688512] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.688544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.688573] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.688604] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.688632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.688660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.688686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.688693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.688720] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.688726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.688755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.688782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.688810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.688835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.688866] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.688892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.688921] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.688947] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.688974] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.689004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.689037] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.689108] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.689162] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.689193] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.689245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.689278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.689307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.689337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.689364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.689396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.689430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.689464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.689496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.689523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.689553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.689588] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.689617] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.691717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.691738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.691760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.691784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.693385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.693407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.693430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.694993] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.695015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.696889] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.700229] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.700325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.700357] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.700405] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.717101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.717226] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.717293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.717502] [drm:drm_mode_addfb2] [FB:77]
>[ 1229.717629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.733778] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.733827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.733916] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.750924] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.750962] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.751001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.751036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.751071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.751102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.751215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.751263] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.751322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.751377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.751426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.751476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.751517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.751564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.751618] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.751660] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.751700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.751732] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.751873] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.751887] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.751952] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.751974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.751996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.752019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.752041] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.752065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.752089] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.752123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.752195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.752229] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.752263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.752271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.752302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.752310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.752341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.752373] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.752404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.752434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.752469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.752499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.752572] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.752602] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.752631] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.752665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.752699] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.752775] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.752806] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.752837] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.752889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.752920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.752951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.752981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.753011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.753043] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.753076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.753109] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.753169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.753201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.753229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.753265] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.753297] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.755373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.755397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.755420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.755444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.757016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.757037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.757056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.758626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.758648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.760534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.763826] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.763902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.763922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.763948] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.780695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.780746] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.780811] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.781024] [drm:drm_mode_addfb2] [FB:78]
>[ 1229.781263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.797373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.797425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.797518] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.814522] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.814560] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.814599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.814633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.814668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.814698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.814728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.814760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.814795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.814828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.814860] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.814891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.814919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.814947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.815001] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.815042] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.815084] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.815115] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.815462] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.815492] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.815640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.815694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.815749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.815810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.815841] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.815887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.815921] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.815955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.815988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.816019] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.816050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.816059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.816089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.816096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.816154] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.816182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.816212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.816237] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.816270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.816297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.816327] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.816357] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.816386] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.816420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.816455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.816531] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.816561] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.816592] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.816644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.816675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.816706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.816733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.816763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.816795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.816829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.816862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.816895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.816924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.816953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.816987] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.817018] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.819087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.819109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.819183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.819216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.820774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.820793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.820811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.822370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.822392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.824254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.827558] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.827637] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.827676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.827727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.844398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.844447] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.844510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.844720] [drm:drm_mode_addfb2] [FB:79]
>[ 1229.844847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.861090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.861172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.861261] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.879052] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.879102] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.879222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.879273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.879329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.879373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.879418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.879463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.879517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.879570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.879620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.879669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.879710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.879753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.879837] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.879901] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.879962] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.880012] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.880269] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.880285] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.880356] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.880383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.880412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.880443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.880467] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.880494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.880521] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.880547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.880571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.880594] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.880624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.880631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.880662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.880668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.880700] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.880732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.880763] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.880794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.880826] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.880857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.880889] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.880920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.880951] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.880985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.881019] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.881094] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.881166] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.881199] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.881254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.881291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.881321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.881354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.881383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.881416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.881453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.881489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.881524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.881553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.881583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.881620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.881651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.883729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.883750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.883768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.883787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.885385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.885419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.885437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.886997] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.887018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.888884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.892226] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.892302] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.892322] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.892347] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.909095] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.909179] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.909245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.909457] [drm:drm_mode_addfb2] [FB:77]
>[ 1229.909591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.925773] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.925821] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.925910] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1229.942922] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1229.942959] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1229.942999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.943033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.943068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.943098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.943210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.943258] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.943323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.943370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.943414] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.943459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.943496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.943536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.943608] [drm:intel_power_well_disable [i915]] disabling display
>[ 1229.943664] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1229.943720] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.943764] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1229.943959] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1229.943978] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1229.944062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1229.944094] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1229.944208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1229.944263] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1229.944315] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1229.944351] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1229.944384] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1229.944417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1229.944445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1229.944476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1229.944547] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1229.944555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.944584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1229.944591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1229.944621] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1229.944651] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1229.944680] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1229.944707] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1229.944739] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1229.944768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1229.944795] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1229.944824] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1229.944853] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1229.944887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.944921] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1229.944997] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1229.945028] [drm:intel_power_well_enable [i915]] enabling display
>[ 1229.945059] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1229.945110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1229.945166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1229.945196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1229.945228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1229.945258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1229.945291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1229.945326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1229.945360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1229.945393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.945423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1229.945454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1229.945489] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1229.945521] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1229.947616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1229.947638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1229.947659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.947684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1229.949262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1229.949283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1229.949302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1229.950850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1229.950871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1229.952733] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1229.956017] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1229.956116] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1229.956222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1229.956299] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1229.972897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1229.972948] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1229.973013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1229.973334] [drm:drm_mode_addfb2] [FB:78]
>[ 1229.973460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1229.989594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1229.989641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1229.989731] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.006747] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.006784] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.006824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.006859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.006895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.006925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.006955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.006986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.007021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.007054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.007086] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.007194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.007238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.007279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.007365] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.007435] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.007501] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.007554] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.007709] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.007722] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.007779] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.007800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.007824] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.007854] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.007882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.007905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.007926] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.007953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.007979] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.008005] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.008030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.008035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.008060] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.008065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.008093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.008153] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.008184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.008213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.008244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.008273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.008300] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.008328] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.008355] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.008385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.008418] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.008494] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.008522] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.008553] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.008607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.008639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.008671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.008701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.008732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.008763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.008797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.008830] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.008856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.008874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.008892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.008915] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.008940] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.010979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.011002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.011025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.011050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.012647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.012668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.012687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.014243] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.014266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.016141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.019480] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.019533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.019566] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.019608] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.036314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.036365] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.036431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.036669] [drm:drm_mode_addfb2] [FB:79]
>[ 1230.036810] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.053001] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.053046] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.053200] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.071303] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.071341] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.071381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.071416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.071451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.071481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.071510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.071542] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.071577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.071610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.071641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.071681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.071720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.071762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.071795] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.071821] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.071850] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.071871] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.072006] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.072019] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.072076] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.072110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.072184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.072220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.072249] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.072282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.072312] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.072342] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.072370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.072398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.072424] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.072432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.072461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.072468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.072497] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.072524] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.072551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.072580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.072613] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.072641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.072670] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.072699] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.072729] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.072762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.072796] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.072885] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.072905] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.072927] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.072967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.073010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.073037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.073057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.073082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.073110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.073165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.073198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.073229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.073256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.073282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.073314] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.073344] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.075427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.075449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.075469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.075488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.077049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.077071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.077091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.078680] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.078701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.080584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.083921] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.084002] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.084022] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.084048] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.100800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.100853] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.100925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.101338] [drm:drm_mode_addfb2] [FB:77]
>[ 1230.101469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.117510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.117558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.117647] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.134633] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.134670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.134710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.134744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.134779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.134810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.134840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.134873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.134908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.134949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.134979] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.135009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.135045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.135082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.135220] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.135286] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.135331] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.135362] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.135555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.135582] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.135707] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.135740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.135776] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.135813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.135842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.135875] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.135907] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.135947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.135966] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.135986] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.136003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.136009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.136026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.136031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.136050] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.136067] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.136093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.136151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.136182] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.136210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.136236] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.136263] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.136288] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.136319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.136351] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.136427] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.136456] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.136487] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.136540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.136571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.136602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.136632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.136661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.136693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.136728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.136757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.136778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.136796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.136815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.136837] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.136858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.138904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.138926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.138945] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.138964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.140535] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.140557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.140580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.142154] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.142176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.144046] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.147327] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.147371] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.147398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.147434] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.164162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.164213] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.164278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.164493] [drm:drm_mode_addfb2] [FB:78]
>[ 1230.164623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.180876] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.180924] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.181014] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.197980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.198018] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.198058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.198092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.198210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.198257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.198305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.198351] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.198407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.198458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.198507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.198557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.198597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.198641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.198724] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.198788] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.198851] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.198901] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.199190] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.199228] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.199305] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.199329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.199362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.199386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.199406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.199426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.199449] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.199473] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.199497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.199518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.199541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.199545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.199568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.199572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.199596] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.199616] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.199639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.199661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.199685] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.199707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.199731] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.199754] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.199777] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.199802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.199827] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.199888] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.199908] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.199927] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.199964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.199988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.200012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.200035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.200078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.200142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.200178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.200210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.200242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.200269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.200297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.200330] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.200360] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.202445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.202467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.202485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.202504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.204106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.204143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.204162] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.205735] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.205758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.207653] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.210992] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.211089] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.211183] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.211253] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.227867] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.227918] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.227985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.228384] [drm:drm_mode_addfb2] [FB:79]
>[ 1230.228513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.244570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.244616] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.244687] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.261694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.261732] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.261771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.261804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.261847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.261887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.261927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.261968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.262012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.262055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.262098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.262220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.262268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.262318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.262405] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.262469] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.262534] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.262590] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.262758] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.262779] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.262875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.262908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.262940] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.262975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.263004] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.263035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.263065] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.263105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.263169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.263201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.263232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.263241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.263270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.263278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.263308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.263339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.263366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.263396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.263431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.263460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.263492] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.263522] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.263548] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.263580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.263617] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.263692] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.263723] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.263753] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.263804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.263836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.263867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.263897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.263926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.263957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.263991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.264023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.264055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.264085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.264135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.264167] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.264199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.266270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.266291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.266309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.266328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.267893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.267913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.267931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.269498] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.269519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.271396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.274741] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.274825] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.274857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.274899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.291609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.291661] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.291733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.291946] [drm:drm_mode_addfb2] [FB:77]
>[ 1230.292072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.308328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.308381] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.308458] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.325437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.325475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.325516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.325550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.325585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.325616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.325655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.325695] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.325740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.325783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.325826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.325868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.325907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.325948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.325981] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.326007] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.326035] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.326054] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.326232] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.326251] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.326310] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.326332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.326356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.326380] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.326400] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.326422] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.326443] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.326464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.326484] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.326503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.326527] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.326534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.326558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.326563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.326589] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.326615] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.326641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.326666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.326693] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.326718] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.326744] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.326770] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.326796] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.326823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.326851] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.326903] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.326925] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.326947] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.326988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.327014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.327041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.327067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.327093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.327147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.327182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.327214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.327246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.327273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.327299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.327334] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.327364] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.329424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.329445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.329463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.329482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.331088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.331125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.331143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.332707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.332729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.334624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.337937] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.338008] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.338041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.338083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.354787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.354838] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.354903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.355197] [drm:drm_mode_addfb2] [FB:78]
>[ 1230.355372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.371506] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.371554] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.371628] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.388644] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.388682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.388722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.388755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.388790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.388820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.388859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.388899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.388944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.388987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.389030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.389072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.389194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.389225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.389282] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.389324] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.389365] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.389397] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.389563] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.389583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.389685] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.389717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.389750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.389784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.389812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.389843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.389874] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.389903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.389932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.389960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.389987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.389994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.390020] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.390026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.390054] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.390092] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.390166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.390198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.390236] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.390266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.390299] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.390331] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.390361] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.390395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.390430] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.390509] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.390540] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.390571] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.390623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.390656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.390686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.390716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.390746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.390777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.390810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.390843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.390875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.390905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.390934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.390968] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.391009] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.393096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.393139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.393158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.393177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.394757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.394782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.394805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.396375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.396397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.398268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.401576] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.401647] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.401679] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.401721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.418410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.418456] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.418521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.418730] [drm:drm_mode_addfb2] [FB:79]
>[ 1230.418855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.435108] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.435200] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.435270] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.454029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.454065] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.454187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.454236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.454293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.454336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.454380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.454425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.454478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.454529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.454576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.454609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.454636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.454663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.454718] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.454760] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.454799] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.454840] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.455023] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.455035] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.455106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.455172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.455207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.455245] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.455275] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.455309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.455334] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.455360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.455386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.455413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.455438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.455444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.455468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.455473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.455499] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.455525] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.455551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.455577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.455604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.455629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.455655] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.455680] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.455706] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.455734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.455762] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.455817] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.455839] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.455862] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.455901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.455927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.455954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.455980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.456006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.456032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.456060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.456090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.456151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.456181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.456210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.456244] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.456273] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.458337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.458363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.458388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.458414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.459979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.460001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.460020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.461585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.461606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.463505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.466798] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.466874] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.466894] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.466920] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.483669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.483722] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.483794] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.484008] [drm:drm_mode_addfb2] [FB:77]
>[ 1230.484234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.500346] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.500395] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.500468] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.519028] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.519065] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.519187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.519236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.519293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.519336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.519384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.519429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.519483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.519535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.519585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.519635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.519676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.519725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.519780] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.519821] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.519861] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.519893] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.520032] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.520045] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.520172] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.520208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.520244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.520282] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.520314] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.520348] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.520382] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.520411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.520433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.520452] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.520471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.520476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.520494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.520498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.520517] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.520538] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.520565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.520590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.520617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.520642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.520669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.520694] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.520721] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.520748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.520777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.520831] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.520852] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.520874] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.520913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.520940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.520967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.520993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.521019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.521044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.521073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.521125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.521160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.521188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.521216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.521249] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.521278] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.523350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.523371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.523390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.523409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.524974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.524995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.525013] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.526566] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.526597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.528493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.531810] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.531877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.531910] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.531958] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.548656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.548707] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.548773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.548969] [drm:drm_mode_addfb2] [FB:78]
>[ 1230.549184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.565377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.565425] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.565498] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.582485] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.582522] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.582562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.582596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.582632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.582663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.582701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.582742] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.582786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.582829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.582872] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.582914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.582950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.582970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.583003] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.583028] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.583056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.583075] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.583292] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.583311] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.583402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.583432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.583466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.583502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.583530] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.583562] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.583593] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.583624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.583652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.583680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.583709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.583717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.583744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.583750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.583779] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.583804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.583832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.583857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.583888] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.583913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.583941] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.583966] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.583994] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.584023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.584057] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.584153] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.584184] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.584215] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.584266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.584294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.584324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.584351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.584379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.584406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.584438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.584469] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.584500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.584526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.584554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.584584] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.584614] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.586686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.586707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.586725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.586746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.588333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.588356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.588379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.589930] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.589962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.591824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.595132] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.595191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.595210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.595236] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.611988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.612038] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.612183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.612468] [drm:drm_mode_addfb2] [FB:79]
>[ 1230.612610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.628686] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.628734] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.628804] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.645806] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.645844] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.645884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.645917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.645953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.645983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.646013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.646044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.646080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.646202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.646252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.646300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.646338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.646378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.646453] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.646510] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.646567] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.646611] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.646812] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.646839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.646973] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.647021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.647071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.647168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.647219] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.647260] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.647300] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.647337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.647374] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.647409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.647442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.647452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.647485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.647493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.647526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.647558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.647591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.647621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.647658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.647690] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.647720] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.647754] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.647788] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.647825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.647864] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.647950] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.647986] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.648020] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.648077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.648138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.648171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.648214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.648245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.648277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.648311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.648344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.648377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.648407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.648438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.648473] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.648505] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.650588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.650609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.650627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.650647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.652248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.652270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.652289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.653848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.653870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.655734] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.659062] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.659172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.659212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.659264] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.675947] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.675997] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.676064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.676430] [drm:drm_mode_addfb2] [FB:77]
>[ 1230.676570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.692662] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.692710] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.692782] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.709772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.709809] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.709849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.709883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.709918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.709948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.709977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.710009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.710044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.710076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.710198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.710253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.710302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.710349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.710424] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.710467] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.710508] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.710540] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.710687] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.710708] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.710794] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.710817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.710841] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.710867] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.710887] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.710908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.710930] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.710951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.710971] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.710989] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.711008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.711013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.711031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.711035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.711053] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.711071] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.711135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.711162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.711193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.711220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.711248] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.711274] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.711301] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.711332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.711364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.711441] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.711465] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.711484] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.711519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.711539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.711558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.711577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.711596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.711615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.711637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.711658] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.711678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.711696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.711714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.711736] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.711757] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.713815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.713837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.713856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.713875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.715441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.715461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.715479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.717074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.717112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.718982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.722278] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.722366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.722399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.722441] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.739146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.739197] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.739263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.739478] [drm:drm_mode_addfb2] [FB:78]
>[ 1230.739606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.755862] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.755910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.755983] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.772977] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.773015] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.773055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.773184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.773244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.773293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.773343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.773394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.773450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.773503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.773554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.773604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.773648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.773677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.773732] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.773775] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.773815] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.773848] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.774013] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.774025] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.774155] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.774188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.774225] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.774262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.774292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.774325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.774356] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.774389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.774418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.774449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.774478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.774487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.774517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.774524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.774556] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.774585] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.774615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.774644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.774677] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.774706] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.774734] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.774764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.774790] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.774822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.774856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.774928] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.774957] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.774987] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.775037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.775070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.775128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.775156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.775186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.775215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.775250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.775282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.775316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.775345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.775375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.775407] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.775439] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.777508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.777529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.777548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.777567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.779134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.779154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.779172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.780731] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.780753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.782632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.785914] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.785948] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.785968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.785998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.802735] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.802784] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.802848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.803151] [drm:drm_mode_addfb2] [FB:79]
>[ 1230.803346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.819446] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.819495] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.819570] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.838015] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.838052] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.838173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.838221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.838278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.838321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.838366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.838410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.838463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.838514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.838563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.838612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.838652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.838696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.838781] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.838844] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.838906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.838951] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.839166] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.839180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.839244] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.839276] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.839297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.839320] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.839339] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.839359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.839382] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.839406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.839429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.839451] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.839474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.839478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.839501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.839505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.839529] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.839553] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.839576] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.839599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.839623] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.839645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.839669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.839692] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.839715] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.839740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.839765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.839813] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.839833] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.839853] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.839889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.839913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.839937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.839960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.839984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.840007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.840032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.840057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.840133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.840165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.840193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.840226] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.840256] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.842341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.842363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.842382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.842401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.843971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.843994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.844017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.845597] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.845619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.847592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.850905] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.850976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.851008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.851051] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.867755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.867806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.867872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.868266] [drm:drm_mode_addfb2] [FB:77]
>[ 1230.868438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.884472] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.884520] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.884609] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.902971] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.903009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.903049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.903166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.903225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.903276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.903324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.903376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.903432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.903468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.903501] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.903533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.903563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.903591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.903646] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.903689] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.903732] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.903764] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.903931] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.903950] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.904035] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.904076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.904172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.904235] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.904271] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.904363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.904404] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.904443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.904482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.904519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.904556] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.904565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.904588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.904594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.904617] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.904639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.904661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.904682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.904709] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.904732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.904754] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.904776] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.904797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.904824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.904852] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.904916] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.904939] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.904962] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.905004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.905028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.905052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.905112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.905146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.905182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.905221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.905261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.905292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.905319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.905347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.905380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.905409] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.907484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.907505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.907523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.907542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.909134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.909155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.909173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.910746] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.910767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.912643] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.915973] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.916029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.916069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.916186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.932805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.932856] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.932922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.933313] [drm:drm_mode_addfb2] [FB:78]
>[ 1230.933484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.949521] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1230.949570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1230.949643] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1230.967994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1230.968031] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1230.968071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.968186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.968244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.968288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.968333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.968377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.968432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.968482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.968532] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.968588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.968614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.968641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.968696] [drm:intel_power_well_disable [i915]] disabling display
>[ 1230.968737] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1230.968778] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.968812] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1230.968988] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1230.969000] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1230.969068] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1230.969140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1230.969178] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1230.969216] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1230.969247] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1230.969283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1230.969317] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1230.969351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1230.969383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1230.969415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1230.969444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1230.969453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.969483] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1230.969489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1230.969519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1230.969548] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1230.969577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1230.969603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1230.969635] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1230.969664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1230.969694] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1230.969720] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1230.969750] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1230.969780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1230.969816] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1230.969898] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1230.969929] [drm:intel_power_well_enable [i915]] enabling display
>[ 1230.969959] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1230.970010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1230.970042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1230.970072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1230.970127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1230.970159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1230.970191] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1230.970225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1230.970259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1230.970293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.970322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1230.970353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1230.970388] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1230.970420] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1230.972496] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1230.972518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1230.972537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.972556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1230.974125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1230.974145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1230.974164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1230.975712] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1230.975733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1230.977598] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1230.980900] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1230.980964] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1230.980984] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1230.981010] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1230.997756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1230.997807] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1230.997873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1230.998167] [drm:drm_mode_addfb2] [FB:79]
>[ 1230.998347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.014471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.014519] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.014592] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.033185] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.033223] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.033263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.033298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.033333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.033364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.033393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.033425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.033461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.033493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.033525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.033555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.033583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.033611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.033665] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.033705] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.033747] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.033778] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.033973] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.033992] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.034173] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.034220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.034269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.034321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.034363] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.034410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.034454] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.034498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.034544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.034588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.034630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.034641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.034681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.034692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.034738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.034772] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.034799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.034825] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.034856] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.034884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.034911] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.034938] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.034964] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.034997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.035035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.035143] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.035163] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.035201] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.035244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.035265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.035290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.035316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.035342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.035368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.035396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.035424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.035451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.035477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.035502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.035531] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.035556] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.037619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.037642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.037661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.037681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.039272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.039296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.039316] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.040859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.040880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.042753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.046037] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.046170] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.046225] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.046270] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.062915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.062965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.063031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.063404] [drm:drm_mode_addfb2] [FB:77]
>[ 1231.063541] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.079620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.079668] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.079740] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.096743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.096781] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.096821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.096855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.096891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.096921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.096951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.096983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.097018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.097051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.097169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.097226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.097274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.097323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.097394] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.097437] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.097478] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.097510] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.097671] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.097691] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.097792] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.097821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.097852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.097886] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.097912] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.097942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.097969] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.097997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.098023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.098059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.098123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.098132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.098161] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.098168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.098198] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.098225] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.098256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.098285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.098317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.098344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.098375] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.098403] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.098432] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.098506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.098540] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.098617] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.098648] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.098677] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.098728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.098758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.098786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.098814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.098840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.098871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.098903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.098935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.098966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.098992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.099020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.099055] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.099113] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.101182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.101204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.101222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.101241] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.102811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.102831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.102849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.104413] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.104436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.106307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.109621] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.109674] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.109693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.109719] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.126468] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.126519] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.126585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.126796] [drm:drm_mode_addfb2] [FB:78]
>[ 1231.126923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.143144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.143193] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.143265] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.160292] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.160329] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.160368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.160402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.160437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.160468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.160498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.160529] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.160565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.160598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.160629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.160667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.160690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.160713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.160759] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.160794] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.160829] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.160855] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.161034] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.161122] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.161246] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.161278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.161309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.161343] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.161369] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.161399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.161427] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.161456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.161482] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.161507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.161532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.161539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.161562] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.161568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.161594] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.161617] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.161642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.161665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.161704] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.161726] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.161749] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.161771] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.161801] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.161843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.161878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.161944] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.161968] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.161990] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.162034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.162061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.162121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.162156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.162190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.162224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.162264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.162303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.162341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.162374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.162408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.162448] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.162483] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.164576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.164599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.164617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.164641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.166232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.166254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.166273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.167835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.167856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.169735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.172991] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.173052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.173141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.173189] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.189830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.189881] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.189947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.190278] [drm:drm_mode_addfb2] [FB:79]
>[ 1231.190466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.206563] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.206612] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.206685] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.223673] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.223711] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.223751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.223785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.223820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.223850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.223879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.223910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.223946] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.223979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.224011] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.224048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.224140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.224179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.224255] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.224311] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.224364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.224407] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.224613] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.224637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.224750] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.224793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.224837] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.224885] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.224925] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.224968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.225011] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.225058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.225129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.225164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.225198] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.225207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.225240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.225249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.225282] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.225316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.225349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.225382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.225419] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.225452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.225486] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.225518] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.225547] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.225583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.225622] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.225715] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.225748] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.225781] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.225836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.225870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.225903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.225935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.225968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.226013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.226058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.226115] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.226149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.226179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.226210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.226245] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.226278] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.228344] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.228365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.228387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.228411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.229983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.230003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.230022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.231624] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.231646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.233521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.236856] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.236956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.236989] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.237032] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.253732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.253783] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.253848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.254115] [drm:drm_mode_addfb2] [FB:77]
>[ 1231.254318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.270412] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.270460] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.270550] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.288714] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.288752] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.288792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.288826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.288861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.288892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.288922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.288954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.288989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.289022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.289053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.289179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.289229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.289278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.289365] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.289430] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.289472] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.289504] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.289675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.289696] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.289795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.289824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.289856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.289889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.289918] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.289948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.289976] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.290004] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.290030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.290068] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.290127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.290135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.290164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.290172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.290202] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.290229] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.290260] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.290286] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.290319] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.290346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.290377] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.290403] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.290432] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.290465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.290499] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.290577] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.290607] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.290637] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.290689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.290719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.290747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.290776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.290802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.290831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.290865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.290897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.290928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.290954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.290982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.291012] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.291042] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.293139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.293161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.293180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.293199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.294777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.294799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.294818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.296387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.296408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.298285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.301620] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.301653] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.301677] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.301708] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.318441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.318492] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.318558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.318759] [drm:drm_mode_addfb2] [FB:78]
>[ 1231.318879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.335147] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.335196] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.335272] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.352274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.352316] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.352361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.352402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.352446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.352486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.352526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.352566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.352610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.352653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.352695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.352737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.352777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.352817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.352850] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.352876] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.352905] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.352924] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.353075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.353095] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.353191] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.353226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.353262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.353299] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.353331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.353364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.353397] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.353422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.353443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.353462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.353481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.353486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.353503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.353508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.353526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.353544] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.353563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.353581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.353603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.353621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.353640] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.353658] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.353684] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.353711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.353740] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.353817] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.353836] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.353855] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.353891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.353913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.353934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.353954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.353974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.353993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.354017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.354037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.354088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.354115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.354143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.354176] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.354204] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.356276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.356298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.356317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.356336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.357893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.357914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.357951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.359497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.359518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.361390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.364709] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.364772] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.364805] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.364847] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.381550] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.381601] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.381666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.381903] [drm:drm_mode_addfb2] [FB:79]
>[ 1231.382030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.398237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.398285] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.398375] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.415376] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.415414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.415455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.415488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.415524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.415554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.415584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.415616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.415651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.415684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.415724] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.415767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.415806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.415846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.415903] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.415950] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.416000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.416036] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.416257] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.416276] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.416365] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.416396] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.416431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.416467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.416496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.416528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.416557] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.416588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.416618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.416647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.416673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.416680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.416707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.416714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.416743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.416769] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.416797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.416822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.416853] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.416879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.416907] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.416932] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.416959] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.416989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.417021] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.417120] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.417151] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.417182] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.417234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.417266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.417294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.417325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.417352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.417383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.417417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.417450] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.417482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.417513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.417539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.417571] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.417599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.419666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.419689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.419712] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.419736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.421323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.421345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.421367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.422921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.422942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.424817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.427732] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.427796] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.427830] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.427872] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.444577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.444625] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.444688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.444888] [drm:drm_mode_addfb2] [FB:77]
>[ 1231.445016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.461249] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.461294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.461364] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.478378] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.478415] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.478455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.478494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.478539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.478579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.478619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.478658] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.478702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.478745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.478787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.478829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.478868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.478907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.478965] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.479011] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.479061] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.479183] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.479424] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.479459] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.479548] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.479582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.479617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.479654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.479685] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.479719] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.479752] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.479784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.479816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.479846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.479875] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.479882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.479910] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.479917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.479947] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.479976] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.480006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.480035] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.480091] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.480123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.480151] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.480183] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.480212] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.480247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.480283] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.480356] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.480387] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.480417] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.480469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.480501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.480529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.480559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.480586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.480619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.480653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.480687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.480719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.480749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.480778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.480813] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.480845] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.482925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.482947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.482965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.482985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.484571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.484601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.484619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.486178] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.486199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.488088] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.491427] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.491524] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.491556] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.491597] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.508301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.508354] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.508425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.508640] [drm:drm_mode_addfb2] [FB:78]
>[ 1231.508774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.524975] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.525023] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.525195] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.542164] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.542202] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.542241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.542275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.542310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.542341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.542370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.542402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.542438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.542471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.542503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.542533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.542561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.542599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.542657] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.542704] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.542755] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.542791] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.542948] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.542961] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.543018] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.543052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.543126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.543166] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.543199] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.543235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.543271] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.543305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.543337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.543369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.543399] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.543407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.543435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.543442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.543472] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.543504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.543534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.543565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.543598] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.543628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.543658] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.543688] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.543717] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.543762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.543798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.543879] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.543910] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.543940] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.543991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.544023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.544074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.544104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.544135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.544167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.544202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.544236] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.544269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.544299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.544328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.544363] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.544396] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.546471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.546492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.546510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.546531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.548117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.548139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.548158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.549717] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.549738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.551611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.554914] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.554995] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.555028] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.555134] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.571773] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.571826] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.571898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.572211] [drm:drm_mode_addfb2] [FB:79]
>[ 1231.572414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.588449] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.588498] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.588571] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.606985] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.607022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.607144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.607191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.607246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.607289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.607334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.607381] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.607435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.607486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.607536] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.607585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.607625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.607668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.607754] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.607819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.607881] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.607931] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.608202] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.608221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.608297] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.608319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.608342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.608366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.608386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.608407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.608429] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.608449] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.608474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.608498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.608523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.608528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.608553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.608558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.608584] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.608606] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.608632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.608657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.608682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.608707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.608732] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.608757] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.608782] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.608809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.608837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.608897] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.608918] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.608940] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.608979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.609005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.609030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.609089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.609123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.609154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.609189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.609223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.609257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.609284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.609315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.609348] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.609379] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.611438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.611459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.611478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.611497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.613077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.613098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.613118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.614684] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.614706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.616587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.619926] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.620022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.620112] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.620186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.636799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.636852] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.636924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.637372] [drm:drm_mode_addfb2] [FB:77]
>[ 1231.637504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.653539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.653585] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.653653] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.671980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.672022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.672146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.672194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.672249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.672292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.672338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.672383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.672437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.672486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.672535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.672587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.672626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.672654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.672709] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.672751] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.672792] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.672823] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.672982] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.672996] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.673125] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.673161] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.673197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.673236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.673267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.673301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.673336] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.673368] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.673400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.673430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.673460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.673468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.673496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.673504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.673533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.673563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.673589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.673618] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.673650] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.673679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.673706] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.673736] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.673765] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.673799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.673834] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.673909] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.673941] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.673971] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.674023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.674078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.674109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.674141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.674172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.674204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.674239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.674272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.674305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.674335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.674366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.674402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.674434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.676520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.676545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.676570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.676596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.678158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.678178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.678197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.679744] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.679765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.681636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.684894] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.684955] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.684989] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.685018] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.701730] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.701778] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.701841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.702279] [drm:drm_mode_addfb2] [FB:78]
>[ 1231.702395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.718426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.718475] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.718562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.735574] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.735616] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.735662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.735703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.735747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.735787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.735827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.735866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.735917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.735952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.735983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.736012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.736038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.736130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.736208] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.736270] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.736330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.736377] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.736547] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.736563] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.736642] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.736672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.736707] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.736748] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.736783] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.736820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.736856] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.736892] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.736933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.736959] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.736981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.736988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.737009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.737014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.737088] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.737119] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.737150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.737180] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.737214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.737244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.737275] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.737305] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.737335] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.737370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.737407] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.737494] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.737529] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.737564] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.737624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.737660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.737695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.737729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.737763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.737792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.737817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.737840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.737869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.737902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.737934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.737956] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.737977] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.740056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.740092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.740115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.740139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.741711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.741732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.741750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.743326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.743348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.745217] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.748562] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.748650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.748681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.748721] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.765430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.765481] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.765547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.765759] [drm:drm_mode_addfb2] [FB:79]
>[ 1231.765884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.782105] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.782153] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.782242] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.799256] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.799294] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.799334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.799368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.799403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.799434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.799463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.799495] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.799531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.799564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.799596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.799628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.799656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.799683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.799740] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.799787] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.799837] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.799873] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.800133] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.800164] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.800310] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.800358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.800407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.800459] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.800503] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.800549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.800595] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.800639] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.800683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.800724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.800765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.800776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.800815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.800825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.800866] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.800907] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.800947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.800987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.801032] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.801117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.801156] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.801210] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.801247] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.801286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.801327] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.801413] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.801448] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.801483] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.801542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.801578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.801612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.801646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.801677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.801712] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.801750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.801788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.801826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.801859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.801892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.801931] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.801967] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.804076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.804099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.804122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.804146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.805729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.805751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.805770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.807326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.807350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.809214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.812496] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.812530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.812549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.812575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.829326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.829379] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.829451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.829668] [drm:drm_mode_addfb2] [FB:77]
>[ 1231.829803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.846036] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.846116] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.846207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.863191] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.863229] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.863269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.863303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.863338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.863368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.863398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.863429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.863464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.863505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.863548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.863590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.863630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.863669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.863727] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.863774] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.863825] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.863861] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.864119] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.864150] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.864298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.864352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.864407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.864474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.864517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.864564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.864612] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.864655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.864699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.864742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.864782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.864793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.864832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.864842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.864883] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.864924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.864966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.865008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.865093] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.865132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.865176] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.865219] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.865262] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.865310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.865360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.865496] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.865532] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.865567] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.865625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.865662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.865698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.865732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.865766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.865802] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.865841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.865878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.865915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.865948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.865981] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.866020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.866086] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.868168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.868189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.868207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.868231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.869796] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.869817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.869835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.871387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.871408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.873284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.876589] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.876671] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.876713] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.876750] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.893452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.893503] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.893569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.893784] [drm:drm_mode_addfb2] [FB:78]
>[ 1231.893914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.910148] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.910197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.910272] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.927280] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.927317] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.927358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.927392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.927434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.927474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.927527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.927567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.927612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.927654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.927697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.927739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.927778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.927817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.927882] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.927918] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.927949] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.927978] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.928164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.928183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.928272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.928306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.928340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.928377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.928408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.928441] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.928474] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.928505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.928537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.928567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.928596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.928603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.928631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.928638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.928667] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.928698] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.928728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.928757] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.928790] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.928819] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.928849] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.928876] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.928905] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.928939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.928973] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.929087] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.929120] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.929151] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.929203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.929236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.929268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.929299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.929330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.929362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.929397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.929429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.929462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.929493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.929521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.929556] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.929587] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.931657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.931677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.931695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.931714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.933291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.933311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.933329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.934878] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.934899] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1231.936772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1231.940094] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1231.940146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1231.940171] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1231.940205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1231.956917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.956965] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.957029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.957419] [drm:drm_mode_addfb2] [FB:79]
>[ 1231.957555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.973613] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1231.973662] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1231.973751] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1231.990759] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1231.990796] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1231.990836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.990870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.990905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.990935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.990965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.990997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1231.991032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.991149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.991204] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.991249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.991276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.991305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.991361] [drm:intel_power_well_disable [i915]] disabling display
>[ 1231.991403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1231.991443] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1231.991475] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1231.991641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1231.991665] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1231.991720] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1231.991742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1231.991764] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1231.991790] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1231.991813] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1231.991838] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1231.991861] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1231.991884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1231.991908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1231.991929] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1231.991952] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1231.991956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.991979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1231.991983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1231.992006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1231.992097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1231.992133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1231.992166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1231.992202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1231.992234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1231.992265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1231.992297] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1231.992329] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1231.992364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1231.992400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1231.992763] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1231.992792] [drm:intel_power_well_enable [i915]] enabling display
>[ 1231.992820] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1231.992870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1231.992900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1231.992930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1231.992958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1231.992985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1231.993015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1231.993087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1231.993124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1231.993158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1231.993188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1231.993219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1231.993254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1231.993485] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1231.995539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1231.995561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1231.995579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.995598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1231.997295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1231.997317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1231.997336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1231.998885] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1231.998907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.000780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.004116] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.004215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.004247] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.004290] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.020991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.021043] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.021203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.021400] [drm:drm_mode_addfb2] [FB:77]
>[ 1232.021518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.037716] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.037785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.037919] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.055872] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.055910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.055951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.055985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.056020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.056141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.056191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.056242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.056299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.056352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.056399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.056432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.056471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.056511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.056562] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.056590] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.056620] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.056640] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.056762] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.056776] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.056835] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.056857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.056880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.056909] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.056934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.056961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.056988] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.057016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.057075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.057104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.057133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.057141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.057168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.057175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.057203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.057230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.057257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.057285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.057315] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.057342] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.057369] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.057396] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.057422] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.057453] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.057485] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.057562] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.057593] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.057623] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.057676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.057708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.057739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.057769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.057798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.057830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.057862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.057885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.057905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.057924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.057942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.057966] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.057992] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.060065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.060086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.060105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.060123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.061693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.061714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.061735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.063298] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.063319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.065188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.068466] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.068519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.068552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.068594] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.085301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.085352] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.085418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.085615] [drm:drm_mode_addfb2] [FB:78]
>[ 1232.085750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.102012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.102094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.102167] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.119156] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.119194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.119234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.119275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.119320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.119360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.119400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.119440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.119485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.119527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.119569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.119611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.119650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.119689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.119747] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.119793] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.119844] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.119880] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.120109] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.120130] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.120228] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.120263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.120299] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.120337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.120368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.120401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.120434] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.120466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.120497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.120528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.120557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.120565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.120593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.120601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.120630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.120661] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.120690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.120719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.120752] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.120781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.120810] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.120838] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.120867] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.120903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.120937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.121013] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.121073] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.121102] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.121156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.121189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.121220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.121253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.121283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.121315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.121350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.121384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.121417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.121446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.121477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.121512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.121544] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.123638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.123660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.123679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.123698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.125275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.125296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.125314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.126870] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.126891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.128758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.132099] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.132176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.132196] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.132221] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.148973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.149027] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.149192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.149435] [drm:drm_mode_addfb2] [FB:79]
>[ 1232.149562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.165649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.165698] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.165770] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.183963] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.184001] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.184125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.184173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.184228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.184281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.184325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.184367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.184418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.184466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.184514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.184560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.184598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.184638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.184717] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.184780] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.184839] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.184885] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.185152] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.185180] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.185311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.185335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.185359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.185392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.185411] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.185431] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.185451] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.185478] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.185506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.185525] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.185547] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.185552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.185575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.185580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.185603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.185625] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.185648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.185672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.185696] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.185718] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.185742] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.185765] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.185789] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.185814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.185839] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.185890] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.185910] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.185930] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.185966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.185990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.186014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.186089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.186122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.186157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.186194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.186229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.186263] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.186295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.186326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.186362] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.186395] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.188470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.188492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.188513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.188537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.190145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.190167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.190186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.191727] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.191759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.193628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.196913] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.197010] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.197107] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.197170] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.213790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.213840] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.213905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.214237] [drm:drm_mode_addfb2] [FB:77]
>[ 1232.214379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.230469] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.230517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.230588] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.247588] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.247625] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.247666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.247700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.247735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.247765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.247794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.247825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.247859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.247891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.247923] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.247954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.247982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.248010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.248143] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.248211] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.248277] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.248327] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.248569] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.248588] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.248675] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.248708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.248743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.248780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.248811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.248844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.248877] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.248910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.248941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.248972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.249001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.249032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.249065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.249073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.249102] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.249133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.249164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.249195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.249229] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.249259] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.249291] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.249321] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.249351] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.249386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.249421] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.249495] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.249526] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.249556] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.249608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.249639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.249669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.249699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.249729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.249760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.249793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.249826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.249858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.249887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.249915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.249949] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.249980] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.252068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.252089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.252111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.252135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.253718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.253742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.253765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.255326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.255348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.257217] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.260529] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.260612] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.260651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.260703] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.277385] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.277436] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.277502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.277715] [drm:drm_mode_addfb2] [FB:78]
>[ 1232.277847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.294105] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.294154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.294227] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.311217] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.311255] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.311295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.311330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.311365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.311396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.311425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.311457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.311492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.311524] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.311556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.311587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.311615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.311643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.311696] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.311737] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.311779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.311819] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.311981] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.312057] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.312231] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.312275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.312321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.312359] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.312386] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.312414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.312442] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.312467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.312492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.312515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.312539] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.312545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.312568] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.312574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.312598] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.312620] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.312643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.312665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.312692] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.312714] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.312736] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.312758] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.312780] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.312807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.312842] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.312899] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.312924] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.312948] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.312991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.313047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.313080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.313112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.313143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.313175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.313210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.313244] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.313278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.313307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.313336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.313372] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.313403] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.315500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.315521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.315539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.315558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.317151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.317174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.317193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.318755] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.318777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.320651] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.323964] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.324107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.324153] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.324214] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.340816] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.340868] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.340940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.341274] [drm:drm_mode_addfb2] [FB:79]
>[ 1232.341390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.357490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.357538] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.357611] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.375839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.375877] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.375918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.375952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.375987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.376102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.376151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.376203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.376264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.376317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.376369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.376419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.376464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.376510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.376591] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.376656] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.376719] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.376770] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.376987] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.377050] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.377174] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.377206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.377240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.377268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.377287] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.377307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.377328] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.377347] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.377365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.377382] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.377399] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.377403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.377420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.377424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.377441] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.377477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.377495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.377514] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.377543] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.377560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.377576] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.377593] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.377609] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.377629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.377650] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.377697] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.377714] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.377730] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.377762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.377780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.377798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.377820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.377844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.377868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.377893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.377918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.377943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.377966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.377989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.378064] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.378099] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.380171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.380192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.380212] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.380231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.381803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.381823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.381841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.383408] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.383428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.385303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.388589] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.388681] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.388710] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.388747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.405472] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.405522] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.405587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.405801] [drm:drm_mode_addfb2] [FB:77]
>[ 1232.405915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.422163] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.422212] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.422288] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.440921] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.440958] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.440999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.441113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.441171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.441215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.441261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.441306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.441360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.441410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.441442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.441474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.441501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.441530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.441584] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.441626] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.441666] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.441698] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.441861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.441872] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.441928] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.441950] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.441972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.442005] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.442082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.442118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.442152] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.442186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.442218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.442251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.442282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.442292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.442321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.442330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.442360] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.442389] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.442420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.442448] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.442481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.442511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.442542] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.442571] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.442601] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.442635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.442670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.442764] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.442805] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.442836] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.442888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.442920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.442952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.442983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.443011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.443068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.443102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.443136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.443171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.443202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.443232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.443268] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.443299] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.445369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.445390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.445408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.445427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.447007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.447046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.447064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.448636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.448660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.450551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.453788] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.453868] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.453891] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.453922] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.470669] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.470719] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.470785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.470985] [drm:drm_mode_addfb2] [FB:78]
>[ 1232.471249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.487364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.487412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.487488] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.505808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.505846] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.505886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.505920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.505963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.506003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.506118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.506167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.506225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.506278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.506329] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.506379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.506421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.506464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.506549] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.506613] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.506675] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.506727] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.506885] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.506908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.506963] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.506985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.507073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.507111] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.507144] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.507179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.507213] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.507246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.507279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.507311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.507341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.507351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.507380] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.507388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.507419] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.507449] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.507476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.507506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.507539] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.507568] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.507595] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.507623] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.507653] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.507687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.507722] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.507797] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.507828] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.507858] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.507910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.507942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.507973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.508003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.508056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.508089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.508124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.508158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.508192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.508222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.508252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.508288] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.508320] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.510390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.510416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.510438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.510463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.512054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.512074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.512093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.513662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.513684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.515547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.518892] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.518983] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.519085] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.519133] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.535749] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.535797] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.535860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.536270] [drm:drm_mode_addfb2] [FB:79]
>[ 1232.536458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.552477] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.552525] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.552613] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.570942] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.570980] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.571106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.571164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.571220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.571270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.571318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.571368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.571425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.571478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.571529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.571580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.571627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.571669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.571755] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.571821] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.571884] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.571934] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.572176] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.572188] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.572245] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.572267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.572298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.572321] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.572339] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.572359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.572378] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.572397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.572415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.572432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.572448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.572453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.572469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.572473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.572490] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.572506] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.572522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.572538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.572557] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.572574] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.572590] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.572606] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.572622] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.572642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.572663] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.572718] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.572735] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.572751] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.572782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.572801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.572818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.572835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.572851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.572869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.572893] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.572918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.572943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.572966] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.572990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.573063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.573095] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.575172] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.575193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.575211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.575230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.576790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.576810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.576828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.578389] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.578410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.580279] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.583513] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.583547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.583570] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.583601] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.600340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.600391] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.600457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.600667] [drm:drm_mode_addfb2] [FB:77]
>[ 1232.600797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.617018] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.617114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.617184] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.634170] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.634208] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.634249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.634289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.634334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.634374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.634414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.634454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.634498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.634541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.634583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.634625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.634664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.634703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.634761] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.634807] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.634858] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.634894] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.635164] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.635195] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.635344] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.635398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.635452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.635495] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.635516] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.635538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.635560] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.635580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.635600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.635619] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.635638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.635643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.635661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.635665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.635684] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.635702] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.635720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.635738] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.635760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.635778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.635797] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.635814] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.635833] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.635854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.635878] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.635942] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.635962] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.635980] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.636052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.636081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.636109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.636137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.636164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.636192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.636224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.636254] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.636284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.636310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.636336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.636367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.636397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.638484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.638505] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.638524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.638543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.640121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.640141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.640160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.641723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.641747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.643623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.646912] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.647000] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.647098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.647159] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.663785] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.663836] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.663902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.664237] [drm:drm_mode_addfb2] [FB:78]
>[ 1232.664411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.680501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.680548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.680625] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.698931] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.698969] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.699010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.699133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.699194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.699243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.699290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.699341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.699398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.699450] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.699501] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.699552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.699597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.699642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.699727] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.699792] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.699858] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.699891] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.700090] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.700110] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.700180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.700203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.700236] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.700262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.700285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.700309] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.700343] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.700364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.700394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.700411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.700427] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.700432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.700448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.700452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.700468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.700485] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.700501] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.700517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.700536] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.700553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.700569] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.700585] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.700601] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.700620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.700642] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.700701] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.700718] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.700734] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.700766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.700785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.700802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.700819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.700842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.700865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.700890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.700916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.700941] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.700964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.700987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.701073] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.701104] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.703179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.703204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.703227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.703251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.704817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.704839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.704857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.706420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.706441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.708311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.711623] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.711695] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.711728] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.711771] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.728473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.728524] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.728592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.728807] [drm:drm_mode_addfb2] [FB:79]
>[ 1232.728927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.745178] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.745224] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.745294] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.762296] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.762338] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.762383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.762424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.762469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.762509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.762549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.762588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.762633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.762676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.762718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.762761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.762815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.762867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.762923] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.762964] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.763087] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.763145] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.763349] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.763370] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.763467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.763498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.763532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.763568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.763596] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.763628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.763658] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.763688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.763716] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.763746] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.763772] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.763779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.763805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.763812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.763841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.763867] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.763895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.763921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.763952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.763978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.764069] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.764096] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.764126] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.764161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.764196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.764286] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.764316] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.764346] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.764396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.764427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.764454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.764483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.764510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.764539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.764571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.764603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.764635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.764661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.764688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.764718] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.764748] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.766816] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.766838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.766856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.766875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.768439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.768459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.768477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.770052] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.770073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.771933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.775235] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.775317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.775349] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.775391] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.792096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.792148] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.792213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.792427] [drm:drm_mode_addfb2] [FB:77]
>[ 1232.792554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.808808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.808856] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.808928] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.827254] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.827292] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.827332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.827366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.827402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.827433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.827462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.827494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.827529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.827561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.827601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.827630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.827656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.827683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.827733] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.827772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.827811] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.827841] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.828081] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.828111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.828253] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.828303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.828356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.828411] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.828443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.828481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.828519] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.828557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.828604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.828635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.828661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.828669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.828694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.828701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.828733] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.828767] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.828802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.828836] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.828871] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.828904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.828938] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.828972] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.829047] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.829091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.829135] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.829236] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.829333] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.829373] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.829446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.829490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.829533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.829573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.829609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.829633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.829659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.829681] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.829705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.829725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.829753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.829783] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.829810] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.831874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.831896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.831915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.831934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.833533] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.833553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.833575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.835197] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.835219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.837079] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.840408] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.840462] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.840494] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.840536] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.857239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.857291] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.857356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.857570] [drm:drm_mode_addfb2] [FB:78]
>[ 1232.857698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.873957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.874086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.874199] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.892945] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.892982] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.893106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.893163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.893221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.893271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.893318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.893369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.893426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.893478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.893530] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.893581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.893626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.893672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.893758] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.893825] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.893888] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.893938] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.894187] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.894204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.894286] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.894316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.894347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.894379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.894406] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.894434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.894463] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.894495] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.894530] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.894560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.894593] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.894599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.894632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.894638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.894671] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.894700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.894745] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.894778] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.894813] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.894845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.894879] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.894911] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.894945] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.894980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.895083] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.895178] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.895209] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.895243] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.895287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.895311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.895338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.895366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.895395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.895424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.895454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.895485] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.895514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.895542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.895570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.895599] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.895627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.897705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.897727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.897747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.897771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.899339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.899360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.899383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.900940] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.900964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.902877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.906234] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.906299] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.906323] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.906354] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.923091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.923142] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.923207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.923419] [drm:drm_mode_addfb2] [FB:79]
>[ 1232.923549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.939767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1232.939819] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1232.939894] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1232.956907] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1232.956945] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1232.956984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.957106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.957165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.957216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.957265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.957305] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.957351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.957395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.957443] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.957467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.957487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.957506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.957542] [drm:intel_power_well_disable [i915]] disabling display
>[ 1232.957569] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1232.957597] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.957618] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1232.957731] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1232.957744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1232.957800] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1232.957821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1232.957843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1232.957868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1232.957888] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1232.957910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1232.957931] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1232.957957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1232.957987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1232.958047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1232.958074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1232.958083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.958109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1232.958116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1232.958143] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1232.958170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1232.958197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1232.958225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1232.958255] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1232.958281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1232.958307] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1232.958334] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1232.958360] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1232.958390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1232.958422] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1232.958499] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1232.958527] [drm:intel_power_well_enable [i915]] enabling display
>[ 1232.958545] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1232.958580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1232.958600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1232.958620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1232.958637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1232.958656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1232.958675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1232.958696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1232.958717] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1232.958736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.958754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1232.958778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1232.958806] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1232.958832] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1232.960878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1232.960899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1232.960918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.960936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1232.962531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1232.962552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1232.962570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1232.964231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1232.964253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1232.966134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1232.969452] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1232.969518] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1232.969551] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1232.969602] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1232.986297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1232.986347] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1232.986413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1232.986624] [drm:drm_mode_addfb2] [FB:77]
>[ 1232.986755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.003042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.003091] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.003163] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.020125] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.020162] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.020201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.020235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.020269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.020300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.020330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.020361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.020404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.020448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.020490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.020532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.020571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.020610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.020668] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.020714] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.020765] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.020801] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.020953] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.021006] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.021106] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.021141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.021176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.021213] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.021244] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.021277] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.021310] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.021342] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.021373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.021403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.021433] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.021440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.021468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.021476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.021505] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.021534] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.021563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.021592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.021624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.021653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.021682] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.021712] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.021742] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.021787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.021823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.021899] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.021931] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.021962] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.022041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.022073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.022106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.022137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.022169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.022201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.022237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.022272] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.022305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.022335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.022366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.022402] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.022435] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.024512] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.024536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.024559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.024583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.026156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.026177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.026200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.027758] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.027780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.029658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.032973] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.033078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.033098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.033124] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.049871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.049922] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.049988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.050322] [drm:drm_mode_addfb2] [FB:78]
>[ 1233.050444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.066570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.066616] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.066686] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.084926] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.084963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.085089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.085140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.085199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.085234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.085264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.085296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.085333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.085366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.085399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.085430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.085459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.085487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.085541] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.085583] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.085626] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.085657] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.085840] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.085868] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.085981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.086080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.086132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.086180] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.086208] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.086239] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.086269] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.086298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.086327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.086355] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.086385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.086392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.086419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.086428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.086456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.086486] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.086515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.086543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.086576] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.086605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.086634] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.086663] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.086692] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.086719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.086743] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.086793] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.086812] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.086833] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.086872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.086898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.086925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.086951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.086979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.087035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.087070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.087102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.087133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.087205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.087235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.087270] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.087302] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.089366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.089387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.089405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.089424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.090984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.091020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.091038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.092593] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.092617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.094519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.097860] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.097954] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.097988] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.098114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.114727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.114778] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.114845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.115163] [drm:drm_mode_addfb2] [FB:79]
>[ 1233.115358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.131447] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.131493] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.131561] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.149919] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.149957] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.150077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.150126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.150180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.150224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.150269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.150313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.150369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.150420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.150474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.150506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.150531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.150559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.150613] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.150663] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.150701] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.150732] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.150893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.150905] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.150973] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.151055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.151093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.151132] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.151164] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.151200] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.151235] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.151269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.151302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.151332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.151364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.151373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.151402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.151410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.151442] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.151471] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.151501] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.151531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.151561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.151590] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.151620] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.151649] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.151675] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.151708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.151743] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.151822] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.151853] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.151883] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.151934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.151966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.152015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.152047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.152076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.152108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.152143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.152178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.152211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.152241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.152271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.152306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.152339] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.154414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.154438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.154459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.154479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.156084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.156105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.156128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.157688] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.157710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.159582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.162810] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.162857] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.162878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.162915] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.179645] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.179696] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.179764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.180046] [drm:drm_mode_addfb2] [FB:77]
>[ 1233.180245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.196321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.196369] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.196441] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.213461] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.213499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.213539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.213573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.213608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.213639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.213669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.213700] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.213735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.213767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.213799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.213829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.213857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.213884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.213938] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.214049] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.214110] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.214157] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.214397] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.214425] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.214560] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.214597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.214635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.214675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.214707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.214741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.214774] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.214808] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.214828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.214847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.214865] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.214870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.214888] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.214892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.214910] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.214929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.214947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.214964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.215016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.215044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.215072] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.215098] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.215125] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.215157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.215189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.215279] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.215310] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.215341] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.215395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.215427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.215457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.215477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.215496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.215517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.215539] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.215566] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.215594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.215625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.215651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.215674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.215699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.217761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.217783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.217806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.217830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.219409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.219430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.219449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.221028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.221052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.222939] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.226254] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.226316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.226344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.226379] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.243102] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.243151] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.243215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.243425] [drm:drm_mode_addfb2] [FB:78]
>[ 1233.243551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.259779] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.259827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.259898] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.278604] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.278642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.278686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.278727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.278772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.278812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.278851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.278892] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.278936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.278979] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.279106] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.279156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.279186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.279217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.279274] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.279317] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.279359] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.279390] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.279565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.279584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.279681] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.279708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.279739] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.279772] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.279798] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.279828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.279855] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.279883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.279909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.279935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.279959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.280003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.280031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.280040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.280069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.280097] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.280126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.280152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.280185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.280212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.280241] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.280268] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.280298] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.280332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.280367] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.280455] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.280485] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.280514] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.280564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.280595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.280622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.280650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.280677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.280706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.280739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.280771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.280803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.280829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.280856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.280887] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.280917] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.283028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.283049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.283068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.283087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.284662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.284683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.284702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.286255] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.286276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.288140] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.291424] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.291457] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.291476] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.291502] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.308245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.308294] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.308356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.308569] [drm:drm_mode_addfb2] [FB:79]
>[ 1233.308696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.324925] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.324970] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.325148] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.343924] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.343962] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.344086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.344140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.344198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.344247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.344287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.344322] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.344359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.344392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.344425] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.344456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.344486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.344514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.344570] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.344614] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.344642] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.344662] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.344775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.344788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.344844] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.344864] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.344888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.344925] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.344947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.344977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.345038] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.345067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.345096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.345123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.345149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.345157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.345183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.345191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.345218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.345244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.345271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.345297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.345327] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.345353] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.345379] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.345407] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.345436] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.345466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.345498] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.345574] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.345605] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.345636] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.345689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.345720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.345751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.345781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.345811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.345836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.345858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.345879] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.345900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.345918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.345936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.345959] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.346011] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.348076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.348097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.348115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.348134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.349693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.349713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.349731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.351292] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.351314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.353183] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.356499] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.356567] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.356600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.356642] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.373347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.373401] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.373472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.373688] [drm:drm_mode_addfb2] [FB:77]
>[ 1233.373807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.390021] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.390069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.390158] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.407173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.407212] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.407252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.407286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.407322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.407353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.407382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.407414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.407449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.407481] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.407512] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.407543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.407570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.407597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.407651] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.407692] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.407733] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.407765] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.407940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.408022] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.408150] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.408196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.408244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.408293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.408334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.408378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.408408] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.408436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.408462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.408488] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.408512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.408519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.408543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.408548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.408574] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.408597] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.408620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.408643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.408671] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.408695] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.408728] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.408763] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.408798] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.408834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.408881] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.408953] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.409007] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.409036] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.409095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.409129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.409160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.409191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.409221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.409253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.409288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.409321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.409358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.409389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.409418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.409453] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.409488] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.411709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.411730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.411749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.411768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.413346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.413366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.413384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.414973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.415016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.416888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.420165] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.420206] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.420230] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.420261] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.437032] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.437083] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.437149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.437365] [drm:drm_mode_addfb2] [FB:78]
>[ 1233.437480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.453678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.453727] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.453816] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.470810] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.470848] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.470888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.470922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.470956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.471069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.471117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.471168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.471223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.471275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.471326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.471377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.471417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.471460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.471544] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.471608] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.471670] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.471719] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.471944] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.472021] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.472145] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.472178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.472211] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.472247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.472267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.472287] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.472308] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.472327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.472346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.472363] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.472380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.472384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.472401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.472405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.472422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.472438] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.472455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.472471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.472490] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.472506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.472523] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.472539] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.472555] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.472575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.472596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.472645] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.472662] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.472679] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.472710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.472729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.472746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.472769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.472792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.472815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.472841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.472866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.472891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.472914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.472937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.472961] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.473036] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.475131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.475153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.475172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.475191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.476751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.476772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.476794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.478359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.478381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.480253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.483546] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.483631] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.483659] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.483695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.500417] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.500470] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.500542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.500755] [drm:drm_mode_addfb2] [FB:79]
>[ 1233.500888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.517133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.517181] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.517270] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.534259] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.534296] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.534336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.534376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.534421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.534461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.534501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.534541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.534586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.534629] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.534671] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.534713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.534752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.534791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.534849] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.534896] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.534946] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.535042] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.535302] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.535321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.535389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.535412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.535436] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.535461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.535481] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.535503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.535525] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.535546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.535566] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.535585] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.535603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.535608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.535626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.535630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.535650] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.535668] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.535686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.535703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.535725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.535743] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.535761] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.535778] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.535797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.535818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.535842] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.535892] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.535911] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.535929] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.536006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.536035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.536063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.536090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.536117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.536147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.536178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.536209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.536239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.536266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.536292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.536324] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.536352] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.538423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.538444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.538462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.538481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.540079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.540100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.540118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.541676] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.541697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.543573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.546885] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.546959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.547072] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.547146] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.563733] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.563783] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.563849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.564285] [drm:drm_mode_addfb2] [FB:77]
>[ 1233.564432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.580453] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.580502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.580574] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.598901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.598943] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.599070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.599119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.599175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.599219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.599268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.599313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.599367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.599418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.599468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.599519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.599559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.599603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.599689] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.599744] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.599796] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.599838] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.600074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.600119] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.600245] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.600290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.600337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.600386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.600428] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.600471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.600515] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.600558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.600599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.600638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.600684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.600694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.600736] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.600746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.600791] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.600834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.600872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.600914] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.600961] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.601060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.601106] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.601151] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.601195] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.601246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.601299] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.601409] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.601455] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.601501] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.601575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.601621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.601666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.601708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.601739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.601769] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.601803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.601835] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.601867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.601897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.601926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.601960] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.602015] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.604087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.604108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.604127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.604145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.605722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.605745] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.605764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.607319] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.607340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.609211] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.612503] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.612598] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.612638] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.612690] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.629374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.629426] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.629492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.629707] [drm:drm_mode_addfb2] [FB:78]
>[ 1233.629837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.646052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.646104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.646181] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.663197] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.663235] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.663276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.663310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.663345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.663375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.663405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.663436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.663472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.663504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.663535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.663566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.663593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.663621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.663674] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.663720] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.663771] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.663807] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.664078] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.664105] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.664232] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.664278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.664325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.664375] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.664419] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.664464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.664508] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.664550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.664591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.664631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.664670] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.664680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.664717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.664726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.664765] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.664804] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.664843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.664881] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.664923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.664962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.665033] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.665083] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.665111] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.665147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.665182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.665280] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.665312] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.665342] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.665395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.665427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.665459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.665490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.665519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.665551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.665585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.665618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.665651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.665680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.665710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.665744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.665776] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.667848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.667871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.667894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.667919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.669543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.669565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.669585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.671145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.671167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.673029] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.676378] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.676457] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.676485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.676520] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.693241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.693291] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.693356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.693568] [drm:drm_mode_addfb2] [FB:79]
>[ 1233.693700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.709938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.710015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.710084] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.727071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.727114] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.727159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.727200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.727244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.727284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.727324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.727364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.727415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.727455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.727495] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.727534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.727571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.727608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.727662] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.727706] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.727754] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.727788] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.728012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.728041] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.728183] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.728235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.728287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.728342] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.728387] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.728441] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.728484] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.728526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.728568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.728608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.728646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.728656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.728694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.728703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.728743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.728782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.728821] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.728859] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.728901] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.728941] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.729018] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.729058] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.729095] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.729140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.729184] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.729307] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.729348] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.729388] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.729461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.729496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.729531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.729563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.729596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.729630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.729667] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.729703] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.729739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.729771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.729802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.729839] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.729873] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.732014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.732036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.732055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.732074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.733648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.733668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.733686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.735237] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.735258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.737127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.740422] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.740513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.740553] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.740604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.757290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.757343] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.757415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.757630] [drm:drm_mode_addfb2] [FB:77]
>[ 1233.757751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.773964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.774059] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.774131] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.791115] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.791153] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.791192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.791226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.791261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.791292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.791322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.791353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.791388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.791420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.791451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.791481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.791508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.791536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.791589] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.791630] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.791671] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.791707] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.791857] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.791869] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.791926] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.791961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.792033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.792072] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.792105] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.792140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.792174] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.792206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.792238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.792270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.792300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.792309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.792338] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.792346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.792378] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.792408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.792439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.792467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.792501] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.792532] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.792561] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.792591] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.792620] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.792653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.792687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.792785] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.792817] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.792847] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.792899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.792930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.792984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.793015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.793046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.793078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.793113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.793146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.793180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.793210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.793240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.793271] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.793304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.795375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.795396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.795414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.795433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.797017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.797039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.797062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.798625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.798646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.800521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.803856] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.803940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.804023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.804056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.820737] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.820789] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.820861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.821186] [drm:drm_mode_addfb2] [FB:78]
>[ 1233.821319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.837423] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.837469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.837559] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.854581] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.854619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.854659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.854692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.854728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.854758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.854787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.854819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.854854] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.854887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.854918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.854950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.855051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.855087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.855160] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.855219] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.855275] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.855320] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.855504] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.855520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.855594] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.855623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.855653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.855686] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.855713] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.855741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.855769] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.855795] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.855821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.855845] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.855869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.855875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.855899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.855905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.855929] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.855993] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.856035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.856064] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.856097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.856126] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.856157] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.856186] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.856214] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.856247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.856282] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.856380] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.856414] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.856447] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.856505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.856539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.856573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.856606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.856630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.856652] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.856676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.856705] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.856734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.856762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.856791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.856821] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.856848] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.858895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.858916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.858935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.859002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.860648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.860668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.860690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.862255] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.862276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.864148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.867410] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.867474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.867501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.867536] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.884262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.884313] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.884378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.884615] [drm:drm_mode_addfb2] [FB:79]
>[ 1233.884789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.901005] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.901052] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.901142] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.918136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.918173] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.918213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.918247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.918283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.918314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.918343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.918374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.918410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.918443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.918474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.918505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.918534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.918570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.918643] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.918684] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.918726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.918757] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.919025] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.919059] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.919214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.919261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.919310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.919362] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.919405] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.919451] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.919497] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.919542] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.919585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.919626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.919666] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.919676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.919715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.919725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.919765] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.919806] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.919846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.919886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.919932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.920011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.920051] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.920094] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.920136] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.920185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.920242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.920350] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.920385] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.920420] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.920479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.920515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.920550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.920585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.920619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.920655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.920693] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.920732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.920769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.920802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.920834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.920873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.920908] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.923017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.923039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.923058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.923077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.924634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.924658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.924681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.926243] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.926264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.928129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.931449] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.931495] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.931514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.931539] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1233.948284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.948333] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.948397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.948640] [drm:drm_mode_addfb2] [FB:77]
>[ 1233.948780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.965028] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1233.965079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1233.965151] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1233.982155] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1233.982192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1233.982233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.982266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.982301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.982331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.982360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.982391] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1233.982426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.982458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.982489] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.982519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.982547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.982574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.982632] [drm:intel_power_well_disable [i915]] disabling display
>[ 1233.982658] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1233.982683] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1233.982702] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1233.982836] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1233.982849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1233.982905] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1233.982928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1233.983021] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1233.983058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1233.983088] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1233.983120] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1233.983151] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1233.983180] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1233.983210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1233.983238] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1233.983265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1233.983273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.983302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1233.983310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1233.983339] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1233.983367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1233.983394] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1233.983423] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1233.983456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1233.983485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1233.983514] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1233.983543] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1233.983572] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1233.983605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1233.983640] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1233.983722] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1233.983747] [drm:intel_power_well_enable [i915]] enabling display
>[ 1233.983765] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1233.983801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1233.983821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1233.983840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1233.983859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1233.983877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1233.983897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1233.983919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1233.983940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1233.983998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1233.984028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1233.984055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1233.984088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1233.984116] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1233.986199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1233.986224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1233.986247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.986271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1233.987838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1233.987859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1233.987878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1233.989463] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1233.989485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1233.991388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1233.994738] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1233.994823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1233.994872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1233.994900] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.011600] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.011650] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.011715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.011995] [drm:drm_mode_addfb2] [FB:78]
>[ 1234.012201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.028288] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.028336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.028409] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.046881] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.046923] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.047054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.047110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.047167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.047216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.047265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.047315] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.047372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.047425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.047477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.047528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.047573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.047619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.047704] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.047770] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.047833] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.047883] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.048139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.048153] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.048223] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.048245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.048267] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.048293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.048316] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.048340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.048364] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1234.048388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.048412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.048435] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.048458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.048462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.048485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.048490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.048513] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.048537] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.048560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.048583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.048607] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.048630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.048653] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1234.048676] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1234.048699] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1234.048724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.048749] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1234.048808] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.048828] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.048848] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.048884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.048908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.048932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.049016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.049047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.049077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.049111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.049143] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.049175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.049202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.049230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.049262] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1234.049292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.051371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.051394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.051426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.051450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.053147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.053169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.053188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.054738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.054760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.056635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.059922] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1234.060019] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.060052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1234.060094] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.076790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.076841] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.076910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.077257] [drm:drm_mode_addfb2] [FB:79]
>[ 1234.077374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.093453] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.093502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.093575] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.110907] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.110945] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.111076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.111129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.111186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.111235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.111282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.111333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.111389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.111442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.111497] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.111529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.111558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.111587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.111643] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.111686] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.111728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.111768] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.111917] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.111960] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.112059] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.112095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.112131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.112169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.112201] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.112231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.112254] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1234.112279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.112305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.112329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.112354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.112359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.112384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.112388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.112414] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.112439] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.112465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.112489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.112515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.112549] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.112575] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1234.112601] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1234.112626] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1234.112653] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.112681] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1234.112745] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.112767] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.112789] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.112828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.112854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.112880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.112905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.112931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.112989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.113023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.113055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.113086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.113114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.113141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.113174] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1234.113203] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.115272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.115293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.115312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.115331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.116936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.116972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.116991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.118549] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.118571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.120466] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.123774] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1234.123842] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.123868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1234.123903] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.140634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.140684] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.140749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.141043] [drm:drm_mode_addfb2] [FB:77]
>[ 1234.141236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.157328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.157381] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.157461] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.175877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.175915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.176040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.176088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.176144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.176188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.176234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.176278] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.176333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.176383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.176433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.176482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.176523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.176566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.176650] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.176714] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.176776] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.176824] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.177020] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.177040] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.177137] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.177171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.177206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.177252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.177281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.177312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.177342] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1234.177372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.177401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.177428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.177453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.177460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.177487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.177493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.177521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.177548] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.177575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.177599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.177628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.177656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.177680] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1234.177708] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1234.177732] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1234.177762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.177793] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1234.177868] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.177897] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.177925] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.178017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.178052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.178085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.178116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.178148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.178180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.178215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.178251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.178285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.178314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.178345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.178380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1234.178412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.180509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.180532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.180555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.180579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.182181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.182204] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.182223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.183784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.183806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.185678] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.189021] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1234.189098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.189122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1234.189153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.205893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.205943] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.206105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.206360] [drm:drm_mode_addfb2] [FB:78]
>[ 1234.206485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.222567] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.222615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.222686] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.240872] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.240909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.241032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.241085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.241143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.241187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.241235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.241285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.241341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.241393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.241444] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.241494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.241539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.241585] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.241670] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.241735] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.241798] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.241848] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.242113] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.242141] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.242218] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.242249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.242281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.242325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.242366] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.242410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.242454] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1234.242497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.242535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.242561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.242585] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.242591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.242614] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.242620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.242644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.242676] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.242709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.242742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.242776] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.242809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.242842] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1234.242875] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1234.242909] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1234.242944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.243049] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1234.243178] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.243210] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.243240] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.243298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.243333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.243365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.243396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.243426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.243452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.243475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.243496] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.243517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.243542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.243568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.243595] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1234.243621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.245674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.245696] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.245715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.245734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.247322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.247345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.247364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.248937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.248976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.250849] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.254201] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1234.254284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.254316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1234.254366] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.271042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.271087] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.271156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.271373] [drm:drm_mode_addfb2] [FB:79]
>[ 1234.271506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.287740] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.287790] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.287865] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.304880] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.304918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.305053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.305106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.305162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.305210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.305258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.305307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.305364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.305416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.305468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.305501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.305530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.305559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.305615] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.305658] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.305707] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.305738] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.305897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.305911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.306049] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.306085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.306121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.306159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.306190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.306224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.306252] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1234.306274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.306300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.306323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.306349] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.306354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.306379] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.306384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.306410] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.306435] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.306460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.306485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.306511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.306536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.306561] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1234.306587] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1234.306612] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1234.306640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.306667] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1234.306740] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.306772] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.306796] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.306833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.306856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.306876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.306895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.306914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.306966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.306997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.307029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.307060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.307089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.307116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.307148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1234.307177] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.309248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.309269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.309288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.309307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.310877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.310901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.310930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.312542] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.312564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.314474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.317758] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1234.317791] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.317811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1234.317836] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.334587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.334639] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.334705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.335134] [drm:drm_mode_addfb2] [FB:77]
>[ 1234.335282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.351256] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.351305] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.351377] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.370125] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.370163] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.370203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.370237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.370272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.370303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.370332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.370363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.370398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.370430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.370461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.370492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.370520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.370547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.370601] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.370642] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.370684] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.370715] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.370908] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.370967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.371290] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.371326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.371361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.371401] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.371433] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.371469] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.371503] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1234.371538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.371572] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.371606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.371639] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.371647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.371679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.371686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.371720] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.371754] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.371787] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.371821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.371860] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.371886] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.371910] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1234.371968] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1234.371999] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1234.372035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.372082] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1234.372371] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.372392] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.372412] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.372453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.372477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.372501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.372522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.372544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.372570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.372601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.372632] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.372663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.372690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.372719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.372748] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1234.372777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.374826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.374847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.374866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.374885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.376507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.376531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.376555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.378148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.378171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.380034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.383333] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1234.383412] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.383440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1234.383476] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.400197] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.400248] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.400314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.400525] [drm:drm_mode_addfb2] [FB:78]
>[ 1234.400639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.416872] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.416920] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.417107] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.435878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.435916] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.436041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.436090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.436146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.436195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.436244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.436294] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.436351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.436384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.436417] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.436450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.436479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.436508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.436564] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.436607] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.436647] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.436679] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.436858] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.436871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.436946] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.437011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.437045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.437084] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.437115] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.437150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.437184] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1234.437217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1234.437249] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.437279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.437308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.437316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.437345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.437353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.437381] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.437401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.437419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.437436] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.437458] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.437476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.437494] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1234.437512] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1234.437530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1234.437552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.437575] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1234.437639] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.437671] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.437691] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.437726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.437747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.437772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.437798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.437824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.437849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.437878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.437907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.437961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.437992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.438020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.438053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1234.438083] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.440154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.440175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.440193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.440212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.441775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.441805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.441828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.443385] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.443405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.445299] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.448606] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1234.448666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.448686] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1234.448711] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.465461] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.465512] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.465580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.465779] [drm:drm_mode_addfb2] [FB:79]
>[ 1234.465904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.482179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1234.482230] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.482306] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1234.500863] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1234.500905] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.501040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.501094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.501150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.501199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.501247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.501312] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.501370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.501424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.501475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.501526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.501572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.501619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.501696] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.501738] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.501779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1234.501811] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.502172] [drm:drm_mode_addfb2] [FB:77]
>[ 1234.502202] [drm:drm_mode_addfb2] [FB:78]
>[ 1234.531781] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1234.531884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1234.532041] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.532162] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.532175] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.532238] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.532262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.532289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.532318] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.532343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.532369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.532395] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1234.532420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.532446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.532471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.532496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.532501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.532526] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.532531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.532557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.532582] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.532607] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.532632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.532658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.532683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.532708] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1234.532730] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1234.532750] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1234.532774] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.532798] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1234.536111] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.536133] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.536151] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.536189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.536211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.536232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.536252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.536271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.536291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.536313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.536333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.536353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.536371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.536395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.536440] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1234.536471] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.538552] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.538575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.538594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.538613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.540189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.540210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.540229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.541787] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.541808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.543679] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.546975] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1234.547058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.547087] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1234.547125] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.563849] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.563902] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.564069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.580547] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.580573] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.597344] [drm:drm_mode_addfb2] [FB:79]
>[ 1234.597484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.613917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1234.613998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.614073] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1234.632862] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1234.632900] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.633024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.633230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.633269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.633302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.633333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.633365] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.633401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.633435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.633475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.633494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.633512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.633528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.633560] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.633586] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.633612] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.633631] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.633784] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.633796] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.633853] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.633876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.633900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.633996] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.634030] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.634066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.634100] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1234.634133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.634166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.634197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.634228] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.634238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.634267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.634275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.634305] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.634335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.634365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.634393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.634427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.634456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.634485] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1234.634514] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1234.634542] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1234.634575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.634610] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1234.634707] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.634739] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.634769] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.634820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.634852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.634883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.634914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.634969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.634999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.635034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.635069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.635102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.635132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.635163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.635198] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1234.635230] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.637300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.637320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.637338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.637357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.638958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.638980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.639002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.640571] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.640592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.642468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.645750] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1234.645785] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.645809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1234.645840] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.662580] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.662631] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.662698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.663133] [drm:drm_mode_addfb2] [FB:77]
>[ 1234.663285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.679258] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1234.679307] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.679379] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1234.696399] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1234.696436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.696476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.696509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.696553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.696593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.696633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.696673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.696727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.696764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.696797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.696835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.696872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.696909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.697046] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.697113] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.697170] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.697210] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.697358] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.697376] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.697460] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.697492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.697527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.697564] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.697599] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.697639] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.697677] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1234.697716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.697756] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.697782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.697804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.697810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.697832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.697837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.697860] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.697883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.697911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.697963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.698000] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.698033] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.698065] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1234.698097] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1234.698129] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1234.698166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.698204] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1234.698294] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.698327] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.698363] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.698408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.698432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.698455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.698477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.698498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.698521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.698546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.698570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.698593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.698615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.698636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.698664] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1234.698688] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.700741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.700762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.700780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.700799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.702372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.702392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.702410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.703967] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.703988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.705861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.709175] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1234.709230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.709250] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1234.709276] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.726025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.726076] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.726143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.726351] [drm:drm_mode_addfb2] [FB:78]
>[ 1234.726466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.742701] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1234.742750] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.742823] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1234.759847] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1234.759884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.759924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.760047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.760106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.760157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.760206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.760257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.760302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.760336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.760369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.760401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.760430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.760458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.760512] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.760581] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.760627] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.760659] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.760824] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.760842] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.760994] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.761051] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.761083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.761118] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.761146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.761176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.761205] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1234.761234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.761263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.761291] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.761316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.761325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.761350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.761358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.761385] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.761414] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.761443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.761470] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.761502] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.761531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.761560] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1234.761589] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1234.761617] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1234.761650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.761684] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1234.761761] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.761791] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.761811] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.761846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.761867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.761886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.761906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.761956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.761985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.762017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.762048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.762078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.762105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.762131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.762164] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1234.762195] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.764260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.764281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.764299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.764318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.765899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.765931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.765950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.767527] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.767548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.769458] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.772778] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1234.772844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.772884] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1234.773005] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.789622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.789676] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.789748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.790050] [drm:drm_mode_addfb2] [FB:79]
>[ 1234.790253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.806297] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1234.806345] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.806420] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1234.823462] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1234.823499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.823539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.823573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.823607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.823637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.823666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.823698] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.823733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.823765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.823796] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.823827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.823854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.823881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.824009] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.824074] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.824139] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.824191] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.824412] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.824430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.824517] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.824546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.824579] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.824615] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.824643] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.824674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.824704] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1234.824734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.824762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.824790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.824815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.824823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.824849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.824855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.824884] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.824910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.824962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.824989] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.825022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.825049] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.825078] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1234.825105] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1234.825134] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1234.825168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.825203] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1234.825292] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.825322] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.825352] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.825402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.825432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.825459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.825488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.825514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.825543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.825575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.825607] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.825639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.825665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.825692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.825722] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1234.825752] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.827811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.827832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.827851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.827870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.829478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.829498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.829517] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.831108] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.831130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.832983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.836317] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1234.836419] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.836452] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1234.836495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.853198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.853249] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.853315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.853570] [drm:drm_mode_addfb2] [FB:77]
>[ 1234.853700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.869874] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1234.869995] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.870110] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1234.887092] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1234.887130] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.887169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.887203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.887238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.887268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.887298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.887330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.887365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.887407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.887457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.887491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.887520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.887548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.887602] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.887642] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.887688] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.887714] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.887884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.887947] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.888073] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.888119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.888165] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.888215] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.888255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.888299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.888343] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1234.888385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.888427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.888467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.888506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.888516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.888554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.888564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.888603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.888643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.888690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.888726] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.888765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.888799] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.888834] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1234.888870] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1234.888904] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1234.888975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.889018] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1234.889110] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.889147] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.889184] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.889245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.889283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.889320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.889355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.889391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.889424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.889464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.889503] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.889543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.889579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.889610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.889650] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1234.889695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.891785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.891807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.891826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.891845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.893443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.893464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.893482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.895112] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.895133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.896992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.900336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1234.900428] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.900460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1234.900503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.917207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.917259] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.917325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.917539] [drm:drm_mode_addfb2] [FB:78]
>[ 1234.917670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.933898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1234.933976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.934065] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1234.951047] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1234.951084] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1234.951123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.951164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.951209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.951249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.951289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.951328] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.951373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.951416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.951459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.951501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.951540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.951580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.951637] [drm:intel_power_well_disable [i915]] disabling display
>[ 1234.951684] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1234.951734] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.951770] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1234.952036] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1234.952062] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1234.952188] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1234.952233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1234.952280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1234.952330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1234.952371] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1234.952417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1234.952460] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1234.952501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1234.952543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1234.952583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1234.952621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1234.952631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.952667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1234.952677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1234.952716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1234.952755] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1234.952794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1234.952832] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1234.952874] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1234.952912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1234.952986] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1234.953031] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1234.953063] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1234.953098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.953134] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1234.953210] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1234.953242] [drm:intel_power_well_enable [i915]] enabling display
>[ 1234.953274] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1234.953326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1234.953357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1234.953388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1234.953415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1234.953444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1234.953475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1234.953509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1234.953543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1234.953575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.953604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1234.953633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1234.953667] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1234.953698] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1234.955774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1234.955796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1234.955815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.955835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1234.957442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1234.957462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1234.957481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1234.959113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1234.959134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1234.960993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1234.964271] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1234.964309] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1234.964332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1234.964363] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1234.981107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1234.981159] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1234.981225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1234.981438] [drm:drm_mode_addfb2] [FB:79]
>[ 1234.981570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1234.997779] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1234.997827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1234.997916] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.014999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.015036] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.015076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.015109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.015144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.015175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.015203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.015235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.015270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.015303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.015340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.015367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.015392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.015416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.015463] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.015500] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.015537] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.015565] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.015741] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.015759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.015843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.015877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.015913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.016009] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.016057] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.016108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.016155] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.016202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.016247] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.016290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.016331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.016353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.016398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.016410] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.016457] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.016504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.016551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.016597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.016649] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.016696] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.016744] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.016790] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.016838] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.016892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.016966] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.017090] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.017139] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.017186] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.017266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.017316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.017372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.017402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.017432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.017463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.017494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.017526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.017558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.017587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.017613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.017647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.017678] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.019762] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.019784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.019803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.019822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.021394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.021415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.021433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.023012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.023033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.024896] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.028245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.028347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.028379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.028422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.045127] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.045178] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.045245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.045501] [drm:drm_mode_addfb2] [FB:77]
>[ 1235.045614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.061802] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.061851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.062006] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.078985] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.079024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.079064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.079098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.079133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.079164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.079193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.079224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.079267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.079318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.079351] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.079383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.079411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.079438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.079493] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.079534] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.079576] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.079609] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.079737] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.079750] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.079807] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.079830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.079853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.079882] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.079974] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.080008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.080043] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.080077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.080109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.080140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.080170] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.080179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.080208] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.080216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.080246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.080276] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.080307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.080336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.080371] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.080401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.080431] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.080460] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.080491] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.080525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.080560] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.080640] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.080671] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.080702] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.080755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.080786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.080817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.080847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.080877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.080934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.080967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.081001] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.081034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.081064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.081095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.081130] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.081162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.083237] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.083258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.083277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.083300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.084900] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.084937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.084959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.086533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.086556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.088446] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.090926] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.091004] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.091023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.091049] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.107800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.107851] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.107999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.108250] [drm:drm_mode_addfb2] [FB:78]
>[ 1235.108383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.124490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.124536] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.124604] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.142819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.142856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.142895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.143012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.143071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.143121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.143168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.143217] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.143255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.143291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.143322] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.143365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.143405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.143446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.143504] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.143551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.143602] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.143638] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.143809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.143828] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.143984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.144035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.144077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.144122] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.144158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.144198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.144236] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.144272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.144308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.144343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.144377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.144388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.144421] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.144430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.144468] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.144505] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.144556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.144592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.144633] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.144669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.144706] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.144742] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.144779] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.144822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.144865] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.144998] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.145031] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.145063] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.145114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.145137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.145158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.145178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.145197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.145218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.145242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.145263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.145284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.145303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.145322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.145345] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.145371] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.147423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.147447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.147470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.147494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.149074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.149095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.149114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.150659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.150680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.152553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.155866] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.155993] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.156040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.156106] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.172710] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.172762] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.172835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.173180] [drm:drm_mode_addfb2] [FB:79]
>[ 1235.173334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.189387] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.189436] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.189506] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.208002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.208039] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.208083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.208124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.208169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.208209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.208249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.208289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.208334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.208377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.208424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.208447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.208465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.208482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.208515] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.208540] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.208567] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.208585] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.208719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.208731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.208787] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.208813] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.208838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.208867] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.208902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.208975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.209011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.209045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.209077] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.209109] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.209140] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.209149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.209179] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.209187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.209218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.209249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.209280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.209310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.209344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.209375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.209406] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.209445] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.209478] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.209514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.209553] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.209649] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.209683] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.209716] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.209771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.209805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.209838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.209870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.209967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.210001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.210038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.210074] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.210109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.210140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.210170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.210206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.210241] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.212315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.212336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.212356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.212381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.213951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.213973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.213996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.215559] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.215582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.217458] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.220730] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.220774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.220793] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.220819] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.237568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.237620] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.237687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.238102] [drm:drm_mode_addfb2] [FB:77]
>[ 1235.238237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.254262] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.254308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.254378] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.271419] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.271457] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.271496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.271530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.271565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.271595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.271624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.271656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.271692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.271725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.271764] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.271802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.271840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.271877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.272013] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.272080] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.272146] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.272195] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.272393] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.272411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.272493] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.272527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.272561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.272598] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.272628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.272660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.272692] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.272728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.272764] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.272784] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.272803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.272808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.272827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.272831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.272850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.272868] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.272887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.272938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.272969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.272997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.273026] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.273052] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.273079] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.273112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.273144] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.273230] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.273262] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.273293] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.273345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.273376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.273407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.273437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.273467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.273497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.273532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.273564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.273592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.273611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.273635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.273662] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.273688] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.275731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.275752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.275771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.275790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.277363] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.277383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.277401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.278984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.279006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.280877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.284161] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.284204] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.284224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.284250] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.301000] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.301052] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.301118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.301327] [drm:drm_mode_addfb2] [FB:78]
>[ 1235.301458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.317678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.317730] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.317806] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.334818] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.334856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.334896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.335019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.335078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.335128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.335176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.335220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.335267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.335312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.335354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.335398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.335437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.335478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.335537] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.335585] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.335635] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.335672] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.335846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.335865] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.336063] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.336114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.336156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.336199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.336224] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.336252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.336279] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.336304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.336329] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.336352] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.336374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.336381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.336402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.336408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.336430] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.336463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.336485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.336507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.336534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.336556] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.336578] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.336600] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.336631] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.336664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.336698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.336762] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.336789] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.336816] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.336864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.336897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.336968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.337006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.337043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.337088] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.337121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.337151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.337182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.337209] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.337236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.337269] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.337298] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.339387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.339411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.339434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.339458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.341121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.341143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.341161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.342704] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.342735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.344607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.347952] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.348043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.348076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.348118] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.364814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.364866] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.365147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.365355] [drm:drm_mode_addfb2] [FB:79]
>[ 1235.365468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.381497] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.381546] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.381618] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.399829] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.399867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.399992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.400040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.400094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.400137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.400183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.400228] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.400282] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.400338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.400369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.400401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.400426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.400454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.400506] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.400548] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.400589] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.400621] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.400780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.400802] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.400860] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.400894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.400961] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.401001] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.401033] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.401069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.401105] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.401138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.401172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.401203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.401235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.401243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.401272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.401279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.401309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.401340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.401370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.401400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.401431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.401460] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.401488] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.401515] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.401544] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.401574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.401609] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.401684] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.401715] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.401745] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.401797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.401828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.401859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.401888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.401978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.402009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.402045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.402077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.402109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.402138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.402166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.402201] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.402232] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.404307] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.404329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.404348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.404367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.405932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.405952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.405970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.407533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.407555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.409422] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.412710] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.412800] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.412828] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.412864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.429576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.429625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.429689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.429954] [drm:drm_mode_addfb2] [FB:77]
>[ 1235.430150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.446272] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.446318] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.446387] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.463430] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.463468] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.463507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.463541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.463584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.463624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.463664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.463712] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.463749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.463782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.463812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.463841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.463867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.463961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.464043] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.464110] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.464173] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.464223] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.464409] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.464427] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.464509] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.464541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.464575] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.464612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.464643] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.464674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.464706] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.464736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.464757] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.464776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.464794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.464799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.464817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.464821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.464840] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.464859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.464886] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.464944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.464974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.465002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.465029] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.465056] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.465082] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.465113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.465146] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.465221] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.465252] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.465283] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.465337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.465370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.465400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.465431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.465461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.465492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.465519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.465540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.465561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.465578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.465597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.465620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.465640] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.467681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.467706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.467739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.467760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.469323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.469343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.469361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.470928] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.470949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.472810] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.476080] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.476126] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.476145] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.476170] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.492968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.493020] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.493091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.493307] [drm:drm_mode_addfb2] [FB:78]
>[ 1235.493436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.509597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.509641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.509712] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.526729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.526771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.526815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.526857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.526985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.527043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.527094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.527146] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.527192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.527228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.527249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.527270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.527289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.527313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.527351] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.527382] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.527415] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.527439] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.527552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.527565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.527623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.527650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.527677] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.527707] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.527732] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.527758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.527784] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.527810] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.527836] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.527861] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.527931] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.527940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.527970] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.527978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.528007] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.528035] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.528063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.528090] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.528121] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.528148] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.528176] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.528202] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.528229] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.528260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.528293] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.528368] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.528397] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.528429] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.528482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.528515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.528546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.528577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.528606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.528638] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.528671] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.528704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.528737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.528765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.528789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.528824] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.528847] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.530938] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.530960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.530978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.530998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.532570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.532590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.532609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.534170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.534191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.536068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.539402] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.539485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.539504] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.539530] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.556291] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.556342] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.556408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.556617] [drm:drm_mode_addfb2] [FB:79]
>[ 1235.556746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.573000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.573059] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.573147] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.590112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.590149] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.590188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.590222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.590257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.590289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.590319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.590350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.590386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.590419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.590451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.590482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.590511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.590539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.590602] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.590628] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.590658] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.590679] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.590819] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.590831] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.590968] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.591004] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.591041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.591079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.591110] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.591146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.591179] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.591211] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.591243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.591273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.591302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.591310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.591339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.591347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.591376] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.591406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.591436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.591465] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.591498] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.591526] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.591556] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.591585] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.591613] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.591646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.591681] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.591760] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.591791] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.591821] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.591873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.591930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.591960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.591992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.592023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.592057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.592092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.592125] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.592159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.592189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.592216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.592253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.592284] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.594398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.594421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.594440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.594459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.596029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.596053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.596076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.597630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.597652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.599527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.602873] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.602945] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.602965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.602991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.619739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.619791] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.619857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.620196] [drm:drm_mode_addfb2] [FB:77]
>[ 1235.620338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.636481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.636527] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.636595] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.654816] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.654854] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.654980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.655017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.655056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.655087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.655118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.655151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.655188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.655223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.655255] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.655288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.655317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.655346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.655419] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.655474] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.655518] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.655549] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.655760] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.655788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.655884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.655935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.655967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.656003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.656032] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.656064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.656094] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.656123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.656151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.656179] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.656205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.656213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.656241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.656248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.656276] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.656303] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.656330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.656356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.656389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.656418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.656447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.656476] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.656505] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.656538] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.656573] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.656651] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.656674] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.656692] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.656727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.656748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.656767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.656786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.656804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.656824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.656845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.656866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.656922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.656951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.656977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.657009] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.657037] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.659104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.659125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.659144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.659162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.660734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.660755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.660773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.662339] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.662359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.664227] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.667559] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.667612] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.667645] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.667687] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.684392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.684443] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.684509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.684721] [drm:drm_mode_addfb2] [FB:78]
>[ 1235.684845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.701106] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.701154] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.701226] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.720075] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.720113] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.720153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.720187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.720223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.720253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.720282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.720314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.720349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.720382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.720413] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.720444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.720473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.720500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.720553] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.720594] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.720635] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.720666] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.720846] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.720934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.721088] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.721141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.721198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.721262] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.721307] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.721357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.721405] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.721452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.721499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.721543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.721586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.721597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.721638] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.721649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.721692] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.721735] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.721778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.721820] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.721869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.721957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.722002] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.722048] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.722092] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.722144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.722197] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.722299] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.722335] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.722372] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.722434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.722472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.722508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.722545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.722582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.722619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.722660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.722699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.722738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.722773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.722807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.722848] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.722913] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.725006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.725028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.725047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.725068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.726640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.726661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.726680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.728241] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.728262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.730134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.733488] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.733563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.733587] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.733618] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.750348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.750400] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.750466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.750678] [drm:drm_mode_addfb2] [FB:79]
>[ 1235.750794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.767025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.767073] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.767145] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.785592] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.785630] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.785670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.785710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.785754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.785794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.785834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.785873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.785981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.786034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.786088] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.786138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.786185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.786231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.786315] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.786386] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.786452] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.786502] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.786668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.786681] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.786738] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.786760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.786783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.786808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.786828] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.786850] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.786918] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.786947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.786976] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.787003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.787030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.787038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.787065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.787072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.787099] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.787126] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.787153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.787179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.787212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.787240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.787268] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.787297] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.787326] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.787359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.787393] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.787469] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.787501] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.787532] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.787567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.787588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.787607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.787626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.787651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.787677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.787705] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.787733] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.787761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.787787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.787813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.787839] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.787867] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.789960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.789982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.790001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.790020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.791594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.791617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.791636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.793196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.793217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.795089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.798398] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.798476] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.798515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.798566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.815260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.815311] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.815378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.815595] [drm:drm_mode_addfb2] [FB:77]
>[ 1235.815724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.831924] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.831969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.832039] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.849052] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.849089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.849129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.849162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.849198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.849228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.849257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.849289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.849324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.849356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.849387] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.849418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.849445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.849472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.849525] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.849566] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.849608] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.849639] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.849812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.849829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.849997] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.850039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.850087] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.850137] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.850178] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.850223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.850267] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.850310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.850349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.850377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.850400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.850408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.850431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.850437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.850462] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.850486] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.850511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.850533] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.850562] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.850585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.850609] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.850632] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.850655] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.850682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.850713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.850780] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.850812] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.850831] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.850900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.850932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.850962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.850991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.851019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.851049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.851084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.851117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.851150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.851178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.851207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.851242] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.851274] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.853374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.853395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.853414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.853437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.855027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.855049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.855067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.856627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.856650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.858540] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.861858] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.861986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.862006] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.862032] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.878762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.878814] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.878967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.879246] [drm:drm_mode_addfb2] [FB:78]
>[ 1235.879375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.895427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.895471] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.895541] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.913805] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.913843] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.913976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.914029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.914085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.914135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.914183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.914233] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.914289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.914342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.914394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.914444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.914490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.914536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.914621] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.914687] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.914750] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.914800] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.915085] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.915104] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.915199] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.915231] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.915263] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.915293] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.915311] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.915332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.915352] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.915370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.915389] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.915405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.915422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.915426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.915448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.915453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.915477] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.915500] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.915524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.915546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.915570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.915593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.915617] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.915640] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.915664] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.915688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.915714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.915761] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.915781] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.915801] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.915837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.915861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.915933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.915970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.915999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.916032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.916068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.916102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.916138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.916165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.916195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.916231] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.916260] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.918348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.918371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.918394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.918418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.919988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.920009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.920027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.921599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.921622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.923496] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.926762] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.926827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.926859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.926977] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1235.943607] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.943661] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.943734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.944045] [drm:drm_mode_addfb2] [FB:79]
>[ 1235.944247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.960303] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1235.960351] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1235.960440] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1235.978838] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1235.978909] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1235.978949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.978983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.979018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.979049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.979077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.979108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1235.979143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.979175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.979207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.979237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.979265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.979299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.979332] [drm:intel_power_well_disable [i915]] disabling display
>[ 1235.979357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1235.979382] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1235.979400] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1235.979540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1235.979552] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1235.979609] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1235.979633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1235.979656] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1235.979681] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1235.979700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1235.979722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1235.979744] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1235.979768] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1235.979793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1235.979815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1235.979839] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1235.979843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.979929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1235.979938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1235.979968] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1235.979997] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1235.980025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1235.980052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1235.980083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1235.980109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1235.980136] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1235.980163] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1235.980189] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1235.980221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1235.980253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1235.980347] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1235.980379] [drm:intel_power_well_enable [i915]] enabling display
>[ 1235.980406] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1235.980455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1235.980495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1235.980521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1235.980541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1235.980559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1235.980584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1235.980612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1235.980640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1235.980667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1235.980692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1235.980719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1235.980746] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1235.980772] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1235.982820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1235.982842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1235.982921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.982958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1235.984519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1235.984541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1235.984560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1235.986104] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1235.986125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1235.987998] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1235.991294] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1235.991380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1235.991412] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1235.991454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.008157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.008210] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.008282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.008519] [drm:drm_mode_addfb2] [FB:77]
>[ 1236.008666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.024859] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.024946] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.025035] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.043436] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.043473] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.043513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.043547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.043582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.043612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.043641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.043673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.043708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.043741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.043772] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.043803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.043831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.043858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.043991] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.044059] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.044122] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.044173] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.044399] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.044429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.044575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.044625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.044683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.044719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.044748] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.044780] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.044810] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.044841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.044909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.044941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.044970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.044978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.045006] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.045014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.045045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.045073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.045103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.045129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.045162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.045188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.045218] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.045244] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.045272] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.045304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.045338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.045431] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.045462] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.045492] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.045543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.045575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.045602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.045631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.045657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.045687] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.045719] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.045751] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.045782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.045808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.045835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.045898] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.045927] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.047998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.048020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.048039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.048058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.049628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.049648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.049666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.051219] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.051240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.053108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.056446] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.056544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.056577] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.056619] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.073324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.073375] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.073442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.073698] [drm:drm_mode_addfb2] [FB:78]
>[ 1236.073822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.090023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.090069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.090158] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.107154] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.107192] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.107236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.107277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.107321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.107361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.107401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.107441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.107485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.107528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.107571] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.107612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.107652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.107691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.107748] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.107795] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.107845] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.107957] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.108215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.108242] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.108365] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.108410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.108457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.108506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.108549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.108593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.108637] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.108679] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.108720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.108759] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.108797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.108807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.108844] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.108898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.108941] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.108980] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.109020] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.109060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.109104] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.109150] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.109184] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.109216] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.109245] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.109283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.109321] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.109426] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.109460] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.109493] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.109552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.109589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.109623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.109656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.109688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.109722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.109759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.109794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.109830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.109862] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.109916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.109956] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.109990] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.112068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.112089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.112107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.112131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.113699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.113727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.113745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.115323] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.115346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.117219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.120544] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.120595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.120623] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.120659] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.137357] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.137408] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.137480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.137721] [drm:drm_mode_addfb2] [FB:79]
>[ 1236.137861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.154096] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.154144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.154233] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.171223] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.171261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.171301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.171335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.171370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.171401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.171430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.171462] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.171497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.171530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.171562] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.171593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.171621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.171649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.171702] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.171743] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.171785] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.171816] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.172109] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.172137] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.172264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.172300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.172341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.172385] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.172425] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.172467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.172512] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.172537] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.172563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.172589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.172615] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.172621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.172646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.172650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.172676] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.172702] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.172728] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.172753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.172781] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.172805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.172832] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.172886] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.172918] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.172950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.172984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.173074] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.173105] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.173136] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.173191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.173224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.173256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.173287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.173313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.173334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.173357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.173378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.173400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.173418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.173437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.173459] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.173481] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.175690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.175711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.175730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.175749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.177322] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.177342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.177360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.178946] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.178967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.180842] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.184146] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.184235] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.184268] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.184310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.200997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.201046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.201110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.201319] [drm:drm_mode_addfb2] [FB:77]
>[ 1236.201444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.217693] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.217741] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.217831] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.234870] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.234940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.234981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.235021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.235066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.235107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.235147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.235186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.235231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.235274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.235316] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.235359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.235398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.235438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.235495] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.235542] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.235592] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.235627] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.235827] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.235904] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.236039] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.236088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.236138] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.236191] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.236235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.236281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.236319] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.236356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.236392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.236428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.236463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.236471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.236505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.236512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.236548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.236583] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.236619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.236655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.236691] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.236727] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.236762] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.236799] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.236834] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.236915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.236955] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.237042] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.237077] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.237113] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.237175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.237213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.237248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.237283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.237317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.237351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.237377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.237401] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.237425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.237447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.237468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.237494] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.237517] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.239577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.239598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.239617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.239636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.241223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.241243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.241261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.242849] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.242886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.244758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.248050] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.248141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.248177] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.248202] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.264902] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.264950] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.265027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.265234] [drm:drm_mode_addfb2] [FB:78]
>[ 1236.265360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.281639] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.281687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.281777] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.298737] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.298775] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.298815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.298856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.298986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.299026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.299057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.299090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.299127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.299160] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.299192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.299232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.299282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.299303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.299339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.299366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.299395] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.299415] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.299555] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.299574] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.299636] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.299662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.299688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.299717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.299742] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.299769] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.299795] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.299822] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.299854] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.299912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.299940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.299949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.299976] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.299984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.300012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.300039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.300067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.300093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.300124] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.300151] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.300178] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.300204] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.300231] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.300263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.300295] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.300372] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.300404] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.300434] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.300486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.300519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.300549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.300579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.300609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.300640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.300674] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.300700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.300722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.300741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.300759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.300782] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.300803] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.302894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.302915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.302933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.302952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.304530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.304550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.304569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.306135] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.306157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.308028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.311373] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.311465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.311503] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.311529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.328242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.328296] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.328389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.328600] [drm:drm_mode_addfb2] [FB:79]
>[ 1236.328728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.344961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.345009] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.345099] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.362084] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.362122] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.362168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.362220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.362257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.362289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.362318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.362350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.362386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.362419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.362451] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.362482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.362511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.362538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.362592] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.362617] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.362643] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.362661] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.362800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.362813] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.362947] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.362982] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.363017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.363055] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.363086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.363120] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.363153] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.363185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.363216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.363247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.363276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.363284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.363313] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.363320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.363349] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.363379] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.363408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.363437] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.363469] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.363498] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.363527] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.363556] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.363585] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.363618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.363653] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.363750] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.363781] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.363812] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.363890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.363924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.363956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.363988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.364021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.364053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.364089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.364123] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.364157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.364187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.364218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.364253] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.364285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.366359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.366388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.366408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.366432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.368012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.368034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.368052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.369607] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.369628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.371502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.374827] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.374921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.374944] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.374976] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.391713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.391766] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.391839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.392245] [drm:drm_mode_addfb2] [FB:77]
>[ 1236.392359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.408434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.408503] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.408596] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.425578] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.425617] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.425656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.425690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.425726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.425757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.425787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.425819] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.425927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.425985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.426030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.426075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.426114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.426155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.426227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.426282] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.426320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.426348] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.426477] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.426492] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.426569] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.426603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.426639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.426677] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.426710] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.426744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.426777] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.426812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.426855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.426936] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.426983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.426993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.427023] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.427031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.427061] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.427091] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.427121] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.427150] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.427184] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.427213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.427241] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.427273] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.427304] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.427338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.427375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.427503] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.427537] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.427569] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.427629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.427664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.427688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.427709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.427729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.427751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.427781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.427812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.427843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.427903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.427933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.427969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.428008] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.430077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.430099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.430117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.430136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.431707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.431730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.431753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.433316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.433337] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.435238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.437588] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.437658] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.437696] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.437744] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.454448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.454499] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.454565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.454795] [drm:drm_mode_addfb2] [FB:78]
>[ 1236.455043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.471137] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.471188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.471268] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.488279] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.488321] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.488366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.488407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.488451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.488491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.488531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.488570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.488615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.488658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.488701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.488743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.488790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.488842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.488994] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.489060] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.489128] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.489180] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.489423] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.489461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.489568] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.489609] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.489648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.489693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.489729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.489770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.489807] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.489846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.489913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.489947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.489985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.489995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.490031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.490041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.490078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.490112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.490149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.490182] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.490224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.490258] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.490294] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.490330] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.490365] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.490405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.490449] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.490547] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.490577] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.490607] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.490657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.490686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.490715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.490742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.490770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.490798] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.490830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.490885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.490919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.490946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.490976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.491011] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.491040] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.493108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.493128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.493147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.493166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.494729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.494750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.494768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.496327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.496348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.498302] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.501616] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.501691] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.501710] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.501736] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.518475] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.518527] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.518593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.518811] [drm:drm_mode_addfb2] [FB:79]
>[ 1236.519210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.535166] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.535215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.535291] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.552295] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.552341] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.552397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.552431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.552466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.552496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.552525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.552556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.552591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.552624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.552655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.552686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.552714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.552742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.552798] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.552824] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.552925] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.552959] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.553121] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.553139] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.553226] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.553259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.553293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.553330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.553360] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.553393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.553426] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.553458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.553490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.553520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.553549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.553557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.553585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.553593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.553622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.553652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.553682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.553711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.553743] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.553772] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.553802] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.553828] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.553883] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.553915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.553951] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.554043] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.554074] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.554106] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.554157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.554189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.554221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.554253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.554283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.554314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.554348] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.554381] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.554414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.554444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.554474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.554507] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.554538] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.556605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.556625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.556643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.556662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.558238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.558258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.558276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.559819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.559852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.561695] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.564707] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.564760] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.564785] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.564819] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.581568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.581622] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.581696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.582164] [drm:drm_mode_addfb2] [FB:77]
>[ 1236.582297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.598259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.598308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.598384] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.615389] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.615427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.615467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.615500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.615535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.615566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.615595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.615626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.615661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.615694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.615725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.615755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.615783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.615810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.615958] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.616026] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.616090] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.616143] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.616325] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.616345] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.616435] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.616459] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.616485] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.616514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.616538] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.616565] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.616590] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.616616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.616641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.616663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.616688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.616693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.616718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.616723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.616748] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.616774] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.616799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.616823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.616897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.616929] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.616960] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.616989] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.617016] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.617047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.617080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.617158] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.617191] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.617222] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.617275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.617307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.617339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.617369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.617399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.617421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.617443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.617463] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.617484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.617523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.617550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.617573] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.617594] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.619653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.619677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.619701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.619725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.621311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.621333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.621352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.622949] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.622971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.624833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.628183] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.628283] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.628316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.628359] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.645060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.645112] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.645179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.645391] [drm:drm_mode_addfb2] [FB:78]
>[ 1236.645522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.661775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.661827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.661995] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.680797] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.680836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.680953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.681001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.681058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.681102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.681147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.681192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.681246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.681296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.681345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.681394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.681435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.681475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.681528] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.681572] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.681614] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.681645] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.681845] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.681862] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.681938] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.681981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.682014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.682050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.682079] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.682104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.682125] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.682144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.682162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.682184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.682208] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.682212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.682235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.682239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.682263] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.682287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.682310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.682333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.682356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.682379] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.682403] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.682426] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.682449] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.682474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.682500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.682560] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.682580] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.682600] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.682637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.682661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.682684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.682708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.682731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.682754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.682780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.682804] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.682829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.682903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.682936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.682974] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.683007] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.685130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.685161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.685179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.685198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.686773] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.686794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.686813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.688410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.688432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.690324] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.693675] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.693753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.693773] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.693799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.710512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.710561] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.710625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.710907] [drm:drm_mode_addfb2] [FB:79]
>[ 1236.711044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.727213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.727261] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.727341] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.745762] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.745800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.745843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.745967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.746013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.746046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.746077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.746109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.746153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.746197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.746240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.746284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.746324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.746376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.746444] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.746486] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.746535] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.746572] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.746727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.746746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.746845] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.746936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.746970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.747005] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.747034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.747065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.747095] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.747125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.747154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.747185] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.747214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.747222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.747251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.747258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.747283] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.747309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.747335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.747359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.747385] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.747411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.747436] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.747463] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.747488] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.747516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.747543] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.747595] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.747617] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.747639] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.747678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.747705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.747731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.747758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.747784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.747809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.747866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.747900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.747932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.747960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.747987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.748020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.748049] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.750117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.750138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.750156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.750176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.751746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.751767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.751786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.753363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.753384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.755372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.758695] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.758756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.758789] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.758832] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.775544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.775595] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.775661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.775970] [drm:drm_mode_addfb2] [FB:77]
>[ 1236.776144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.792238] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.792286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.792377] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.809437] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.809475] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.809514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.809548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.809582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.809612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.809640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.809671] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.809707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.809739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.809771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.809802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.809830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.809933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.810018] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.810087] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.810147] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.810199] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.810510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.810529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.810622] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.810644] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.810666] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.810689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.810707] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.810728] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.810747] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.810766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.810784] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.810802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.810818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.810869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.810898] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.810906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.810934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.810961] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.810988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.811014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.811044] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.811071] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.811099] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.811125] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.811152] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.811182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.811217] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.811480] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.811499] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.811518] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.811554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.811576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.811601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.811627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.811653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.811679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.811708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.811736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.811764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.811789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.811816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.811874] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.811905] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.814085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.814109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.814129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.814150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.815713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.815734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.815753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.817306] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.817329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.819235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.822504] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.822556] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.822577] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.822611] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.839346] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.839397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.839464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.839673] [drm:drm_mode_addfb2] [FB:78]
>[ 1236.839800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.856023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.856072] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.856144] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.873159] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.873197] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.873236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.873269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.873304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.873334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.873362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.873393] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.873428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.873461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.873492] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.873532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.873559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.873584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.873635] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.873674] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.873713] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.873742] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.873963] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.873991] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.874131] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.874178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.874230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.874282] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.874323] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.874370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.874414] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.874458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.874499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.874544] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.874570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.874578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.874604] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.874610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.874639] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.874665] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.874693] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.874718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.874749] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.874774] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.874802] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.874859] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.874888] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.874917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.874951] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.875027] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.875058] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.875087] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.875137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.875167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.875194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.875223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.875249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.875278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.875311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.875342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.875373] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.875399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.875437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.875472] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.875500] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.877591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.877613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.877632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.877652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.879227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.879248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.879268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.880824] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.880862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.882732] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.886014] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.886059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.886088] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.886125] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.902884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.902935] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.903001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.903210] [drm:drm_mode_addfb2] [FB:79]
>[ 1236.903338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.919560] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.919608] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.919681] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1236.936707] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1236.936745] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1236.936784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.936818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.936949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.937001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.937050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.937100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.937156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.937207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.937258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.937324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.937369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.937417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.937503] [drm:intel_power_well_disable [i915]] disabling display
>[ 1236.937569] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1236.937631] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.937682] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1236.937936] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1236.937951] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1236.938015] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1236.938039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1236.938072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1236.938095] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1236.938114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1236.938134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1236.938154] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1236.938172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1236.938190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1236.938208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1236.938224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1236.938228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.938245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1236.938248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1236.938265] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1236.938282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1236.938298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1236.938314] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1236.938333] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1236.938349] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1236.938365] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1236.938382] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1236.938404] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1236.938429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.938455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1236.938516] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1236.938536] [drm:intel_power_well_enable [i915]] enabling display
>[ 1236.938556] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1236.938592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1236.938616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1236.938640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1236.938664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1236.938687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1236.938721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1236.938745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1236.938768] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1236.938795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.938818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1236.938897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1236.938930] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1236.938959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1236.941030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1236.941052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1236.941070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.941089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1236.942665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1236.942688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1236.942706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1236.944274] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1236.944295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1236.946165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1236.949488] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1236.949551] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1236.949590] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1236.949642] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1236.966325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1236.966377] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1236.966443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1236.966653] [drm:drm_mode_addfb2] [FB:77]
>[ 1236.966783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1236.983045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1236.983094] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1236.983166] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.000152] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.000190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.000234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.000275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.000319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.000360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.000400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.000439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.000484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.000527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.000569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.000611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.000651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.000689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.000747] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.000794] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.000925] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.000979] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.001219] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.001240] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.001329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.001359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.001392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.001428] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.001456] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.001489] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.001518] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.001549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.001577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.001605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.001630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.001638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.001664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.001670] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.001699] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.001725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.001752] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.001777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.001809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.001860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.001890] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.001919] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.001948] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.001982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.002017] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.002106] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.002136] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.002166] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.002216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.002247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.002274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.002303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.002329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.002357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.002389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.002421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.002452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.002478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.002505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.002535] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.002565] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.004643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.004666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.004685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.004703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.006283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.006316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.006336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.007938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.007960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.009834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.013205] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.013295] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.013328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.013370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.030049] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.030096] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.030160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.030367] [drm:drm_mode_addfb2] [FB:78]
>[ 1237.030494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.046788] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.046916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.047025] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.065755] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.065792] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.065912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.065962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.066019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.066063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.066111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.066156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.066210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.066261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.066311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.066360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.066400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.066443] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.066526] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.066590] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.066654] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.066683] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.066862] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.066882] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.066981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.067015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.067051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.067097] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.067126] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.067158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.067189] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.067218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.067248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.067276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.067300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.067307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.067334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.067340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.067368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.067395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.067423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.067450] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.067477] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.067515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.067542] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.067580] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.067607] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.067635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.067667] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.067755] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.067783] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.067812] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.067906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.067940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.067973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.068004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.068036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.068068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.068104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.068138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.068171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.068202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.068233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.068269] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.068301] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.070410] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.070432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.070451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.070470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.072072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.072095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.072114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.073663] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.073684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.075555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.078897] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.078973] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.078993] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.079019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.095770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.095822] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.095993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.096253] [drm:drm_mode_addfb2] [FB:79]
>[ 1237.096367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.112442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.112490] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.112561] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.129593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.129631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.129670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.129705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.129740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.129771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.129801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.129916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.129974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.130029] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.130058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.130085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.130110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.130135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.130181] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.130217] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.130254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.130281] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.130436] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.130460] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.130573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.130603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.130634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.130666] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.130692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.130721] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.130749] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.130782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.130823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.130900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.130937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.130949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.130984] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.130994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.131039] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.131068] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.131098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.131126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.131159] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.131187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.131216] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.131244] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.131273] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.131307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.131342] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.131423] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.131456] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.131489] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.131546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.131580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.131613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.131645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.131677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.131711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.131740] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.131763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.131785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.131806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.131863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.131899] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.131930] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.134005] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.134026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.134044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.134063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.135630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.135650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.135668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.137217] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.137238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.139109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.142372] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.142431] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.142451] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.142476] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.159226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.159277] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.159344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.159555] [drm:drm_mode_addfb2] [FB:77]
>[ 1237.159683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.175905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.175954] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.176025] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.193049] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.193086] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.193126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.193161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.193197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.193227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.193258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.193290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.193325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.193358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.193389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.193420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.193449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.193477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.193530] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.193571] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.193612] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.193644] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.193897] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.193930] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.194077] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.194205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.194255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.194296] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.194324] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.194356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.194387] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.194417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.194444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.194473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.194498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.194506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.194531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.194536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.194573] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.194609] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.194645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.194680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.194717] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.194752] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.194789] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.194869] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.194911] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.194957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.195003] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.195131] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.195175] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.195220] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.195282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.195319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.195357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.195392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.195417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.195440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.195467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.195490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.195512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.195533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.195561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.195592] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.195622] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.197698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.197720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.197739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.197758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.199359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.199379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.199398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.201018] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.201042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.202905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.206237] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.206289] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.206322] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.206364] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.223068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.223120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.223187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.223395] [drm:drm_mode_addfb2] [FB:78]
>[ 1237.223524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.239785] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.239866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.239944] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.256928] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.256965] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.257004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.257044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.257089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.257129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.257169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.257209] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.257253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.257297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.257339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.257381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.257434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.257473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.257540] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.257575] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.257613] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.257639] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.257837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.257861] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.258192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.258225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.258259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.258296] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.258327] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.258361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.258394] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.258427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.258460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.258493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.258524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.258531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.258567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.258573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.258598] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.258623] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.258645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.258667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.258692] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.258713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.258742] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.258771] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.258801] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.258875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.258914] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.259202] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.259224] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.259245] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.259287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.259311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.259334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.259363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.259393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.259440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.259474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.259500] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.259523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.259546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.259572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.259596] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.259616] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.261663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.261687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.261710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.261735] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.263332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.263353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.263371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.265024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.265047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.266910] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.270215] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.270293] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.270326] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.270368] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.287072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.287125] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.287198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.287417] [drm:drm_mode_addfb2] [FB:79]
>[ 1237.287551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.303790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.303871] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.303943] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.320936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.320973] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.321013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.321047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.321090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.321130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.321170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.321210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.321254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.321297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.321339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.321381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.321421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.321460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.321517] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.321563] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.321614] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.321650] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.321914] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.321942] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.322055] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.322087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.322121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.322159] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.322195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.322233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.322269] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.322306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.322342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.322378] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.322413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.322421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.322455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.322462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.322497] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.322533] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.322570] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.322605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.322642] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.322677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.322712] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.322755] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.322803] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.322896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.322936] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.323042] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.323069] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.323090] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.323132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.323156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.323179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.323200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.323221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.323244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.323270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.323294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.323317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.323346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.323375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.323405] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.323434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.325629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.325651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.325670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.325689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.327264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.327285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.327303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.328849] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.328872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.330723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.334072] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.334152] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.334171] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.334197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.350920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.350969] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.351034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.351243] [drm:drm_mode_addfb2] [FB:77]
>[ 1237.351373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.367648] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.367697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.367770] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.384759] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.384797] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.384931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.384985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.385042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.385090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.385139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.385189] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.385247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.385305] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.385338] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.385371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.385400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.385429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.385485] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.385528] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.385577] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.385607] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.385770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.385784] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.385923] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.385959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.385995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.386034] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.386065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.386088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.386111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.386131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.386151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.386170] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.386188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.386193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.386211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.386215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.386233] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.386251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.386268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.386286] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.386307] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.386325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.386343] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.386360] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.386378] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.386399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.386422] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.386488] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.386507] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.386524] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.386559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.386579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.386598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.386617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.386635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.386654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.386675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.386695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.386715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.386739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.386764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.386791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.386848] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.388933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.388955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.388973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.388992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.390562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.390583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.390602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.392164] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.392186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.394054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.397351] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.397438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.397477] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.397503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.414218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.414270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.414337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.414549] [drm:drm_mode_addfb2] [FB:78]
>[ 1237.414664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.430893] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.430941] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.431012] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.448036] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.448074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.448114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.448147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.448182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.448212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.448241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.448272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.448307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.448340] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.448371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.448402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.448430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.448457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.448511] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.448552] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.448588] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.448606] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.448732] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.448746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.448864] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.448896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.448930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.448966] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.448994] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.449027] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.449057] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.449087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.449118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.449148] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.449176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.449184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.449211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.449218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.449249] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.449279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.449307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.449336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.449370] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.449400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.449429] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.449458] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.449488] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.449517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.449545] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.449614] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.449636] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.449659] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.449698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.449724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.449751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.449777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.449806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.449866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.449899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.449932] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.449962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.449989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.450016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.450049] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.450079] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.452143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.452164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.452186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.452210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.453800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.453838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.453857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.455407] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.455430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.457319] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.460646] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.460701] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.460733] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.460779] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.477481] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.477536] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.477608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.477898] [drm:drm_mode_addfb2] [FB:79]
>[ 1237.478090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.494157] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.494210] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.494286] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.512753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.512792] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.512922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.512977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.513034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.513081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.513129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.513180] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.513236] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.513290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.513341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.513393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.513439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.513484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.513570] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.513636] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.513698] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.513749] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.513992] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.514008] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.514083] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.514111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.514141] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.514178] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.514211] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.514245] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.514279] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.514312] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.514346] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.514375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.514407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.514413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.514446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.514451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.514485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.514515] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.514548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.514581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.514614] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.514647] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.514680] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.514713] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.514746] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.514781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.514934] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.515036] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.515067] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.515098] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.515151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.515185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.515217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.515248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.515278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.515310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.515344] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.515378] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.515411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.515440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.515470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.515502] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.515533] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.517607] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.517629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.517648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.517667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.519241] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.519261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.519279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.520840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.520862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.522734] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.526057] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.526116] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.526155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.526207] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.542905] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.542957] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.543023] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.543263] [drm:drm_mode_addfb2] [FB:77]
>[ 1237.543407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.559602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.559651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.559723] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.576742] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.576780] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.576914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.576967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.577025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.577074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.577122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.577174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.577231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.577284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.577336] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.577388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.577417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.577446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.577502] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.577545] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.577585] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.577624] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.577805] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.577826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.577922] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.577947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.577972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.577997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.578017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.578039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.578060] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.578085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.578111] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.578134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.578159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.578164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.578195] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.578202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.578231] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.578252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.578270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.578289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.578311] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.578329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.578348] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.578365] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.578383] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.578404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.578427] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.578490] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.578509] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.578527] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.578566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.578592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.578618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.578643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.578669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.578694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.578721] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.578748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.578776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.578833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.578863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.578897] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.578926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.580995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.581016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.581035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.581054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.582614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.582634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.582656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.584209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.584231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.586103] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.589445] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.589538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.589571] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.589609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.606316] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.606368] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.606433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.606639] [drm:drm_mode_addfb2] [FB:78]
>[ 1237.606769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.623032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.623080] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.623152] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.641731] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.641769] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.641893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.641953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.642011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.642060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.642108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.642158] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.642215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.642267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.642318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.642369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.642414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.642459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.642545] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.642615] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.642656] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.642695] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.642863] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.642877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.642942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.642965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.642988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.643022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.643040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.643060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.643081] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.643099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.643118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.643135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.643152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.643157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.643173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.643177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.643194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.643217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.643240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.643264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.643287] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.643310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.643334] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.643357] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.643381] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.643405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.643431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.643973] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.644006] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.644034] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.644096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.644127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.644157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.644186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.644215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.644244] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.644277] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.644307] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.644338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.644365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.644391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.644424] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.644453] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.646543] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.646565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.646588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.646612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.648179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.648199] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.648221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.649780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.649820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.651672] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.654961] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.655040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.655061] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.655086] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.671873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.671925] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.671992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.672205] [drm:drm_mode_addfb2] [FB:79]
>[ 1237.672336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.688510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.688562] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.688637] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.705658] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.705700] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.705745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.705786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.705917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.705971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.706022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.706074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.706133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.706181] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.706217] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.706249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.706280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.706308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.706363] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.706405] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.706448] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.706480] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.706651] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.706670] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.706756] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.706798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.706896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.706959] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.706994] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.707033] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.707070] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.707108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.707144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.707177] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.707210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.707222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.707254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.707264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.707300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.707335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.707369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.707402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.707444] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.707479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.707510] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.707532] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.707556] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.707582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.707612] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.707674] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.707699] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.707721] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.707763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.707789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.707851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.707886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.707920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.707955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.707994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.708038] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.708070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.708099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.708126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.708162] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.708194] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.710281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.710303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.710321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.710339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.711903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.711926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.711948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.713496] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.713518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.715389] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.718679] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.718773] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.718919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.718986] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.735549] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.735600] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.735670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.735991] [drm:drm_mode_addfb2] [FB:77]
>[ 1237.736163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.752227] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.752276] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.752365] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.770804] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.770874] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.770913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.770947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.770983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.771013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.771041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.771073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.771108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.771140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.771180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.771224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.771264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.771303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.771361] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.771407] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.771458] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.771494] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.771648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.771661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.771717] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.771740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.771763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.771868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.771902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.771937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.771971] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.772015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.772048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.772080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.772110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.772119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.772148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.772155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.772185] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.772214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.772244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.772273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.772306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.772335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.772365] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.772395] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.772424] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.772458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.772492] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.772565] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.772597] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.772628] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.772680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.772711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.772741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.772772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.772824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.772853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.772890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.772922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.772956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.772986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.773017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.773053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.773085] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.775161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.775185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.775208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.775232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.776820] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.776841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.776858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.778421] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.778444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.780336] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.783639] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.783721] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.783754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.783779] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.800489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.800539] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.800603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.800878] [drm:drm_mode_addfb2] [FB:78]
>[ 1237.801055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.817171] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.817216] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.817305] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.834319] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.834357] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.834397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.834432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.834467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.834498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.834528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.834560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.834594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.834635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.834678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.834720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.834760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.834799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.834931] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.834977] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.835024] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.835058] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.835191] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.835202] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.835259] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.835281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.835305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.835330] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.835350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.835376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.835402] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.835427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.835454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.835480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.835506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.835510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.835535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.835540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.835567] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.835590] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.835616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.835641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.835668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.835693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.835719] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.835744] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.835771] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.835830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.835866] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.835938] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.835966] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.835997] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.836050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.836081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.836113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.836143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.836174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.836206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.836240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.836273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.836305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.836335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.836364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.836393] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.836414] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.838452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.838473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.838492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.838511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.840073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.840102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.840120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.841669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.841690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.843553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.846860] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.846936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.846968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.847010] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.863708] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.863756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.863916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.864176] [drm:drm_mode_addfb2] [FB:79]
>[ 1237.864299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.880403] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.880453] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.880544] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.897541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.897578] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.897618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.897652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.897687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.897718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.897747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.897778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.897898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.897951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.898003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.898055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.898101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.898149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.898198] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.898226] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.898254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.898274] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.898384] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.898397] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.898451] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.898472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.898495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.898525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.898550] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.898577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.898603] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.898629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.898655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.898681] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.898706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.898713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.898737] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.898742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.898770] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.898835] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.898865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.898894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.898925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.898953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.898980] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.899008] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.899035] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.899066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.899098] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.899174] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.899203] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.899235] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.899289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.899321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.899352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.899382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.899412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.899443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.899478] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.899510] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.899538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.899557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.899583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.899610] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.899637] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.901677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.901700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.901723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.901747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.903346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.903377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.903395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.904968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.904989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.906849] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.910164] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.910236] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.910277] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.910328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.927011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.927062] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.927129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.927338] [drm:drm_mode_addfb2] [FB:77]
>[ 1237.927466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.943733] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1237.943781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1237.943944] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1237.962745] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1237.962783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1237.962905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.962945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.962982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.963013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.963042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.963074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.963111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.963144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.963178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.963210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.963239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.963267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.963321] [drm:intel_power_well_disable [i915]] disabling display
>[ 1237.963363] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1237.963405] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.963437] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1237.963577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1237.963590] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1237.963646] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1237.963667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1237.963690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1237.963715] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1237.963735] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1237.963757] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1237.963787] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1237.963847] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1237.963875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1237.963903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1237.963929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1237.963938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.963964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1237.963971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1237.963999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1237.964025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1237.964052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1237.964078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1237.964108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1237.964134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1237.964161] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1237.964189] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1237.964215] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1237.964248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1237.964282] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1237.964347] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1237.964365] [drm:intel_power_well_enable [i915]] enabling display
>[ 1237.964383] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1237.964417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1237.964438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1237.964457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1237.964476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1237.964494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1237.964514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1237.964535] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1237.964555] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1237.964575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.964593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1237.964612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1237.964640] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1237.964671] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1237.966725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1237.966754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1237.966773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.966840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1237.968413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1237.968433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1237.968456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1237.970022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1237.970044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1237.971914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1237.975279] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1237.975351] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1237.975391] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1237.975443] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1237.992129] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1237.992178] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1237.992242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1237.992452] [drm:drm_mode_addfb2] [FB:78]
>[ 1237.992578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.008844] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.008890] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.008958] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.025956] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.025995] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.026034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.026069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.026104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.026134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.026164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.026195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.026230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.026263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.026294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.026325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.026353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.026380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.026434] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.026475] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.026516] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.026547] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.026759] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.026826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.026983] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.027034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.027087] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.027141] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.027186] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.027236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.027284] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.027331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.027377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.027421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.027464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.027475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.027516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.027526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.027570] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.027613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.027656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.027698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.027746] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.027788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.027871] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.027916] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.027960] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.028019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.028061] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.028154] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.028192] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.028228] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.028288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.028325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.028362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.028400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.028432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.028469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.028509] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.028548] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.028586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.028621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.028652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.028692] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.028729] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.030842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.030862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.030881] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.030900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.032478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.032500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.032520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.034084] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.034105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.035976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.039279] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.039344] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.039363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.039389] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.056139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.056191] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.056257] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.056468] [drm:drm_mode_addfb2] [FB:79]
>[ 1238.056600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.072882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.072930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.073004] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.089986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.090024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.090064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.090098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.090133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.090164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.090194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.090226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.090261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.090293] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.090325] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.090355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.090383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.090409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.090463] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.090489] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.090514] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.090532] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.090661] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.090673] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.090730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.090753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.090845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.090886] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.090919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.090954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.090989] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.091022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.091055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.091086] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.091117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.091126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.091155] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.091163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.091193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.091223] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.091253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.091284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.091317] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.091346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.091376] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.091405] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.091432] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.091465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.091500] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.091597] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.091629] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.091660] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.091711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.091743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.091774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.091829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.091860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.091892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.091928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.091962] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.091997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.092027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.092057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.092092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.092126] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.094214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.094237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.094256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.094275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.095893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.095914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.095933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.097491] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.097512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.099385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.102700] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.102751] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.102770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.102855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.119545] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.119596] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.119662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.120076] [drm:drm_mode_addfb2] [FB:77]
>[ 1238.120191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.136266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.136313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.136402] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.154791] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.154857] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.154897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.154931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.154967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.154997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.155026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.155058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.155094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.155127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.155159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.155190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.155218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.155256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.155314] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.155361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.155411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.155447] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.155648] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.155667] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.155761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.155891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.155951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.156011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.156061] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.156118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.156171] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.156223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.156272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.156321] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.156368] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.156382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.156425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.156436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.156482] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.156529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.156577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.156623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.156675] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.156720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.156769] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.156844] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.156889] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.156937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.156991] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.157131] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.157171] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.157209] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.157273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.157314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.157353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.157393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.157430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.157465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.157507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.157547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.157588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.157625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.157661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.157703] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.157743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.159857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.159877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.159896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.159915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.161473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.161493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.161511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.163059] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.163080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.164932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.168248] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.168311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.168330] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.168356] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.185094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.185145] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.185212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.185429] [drm:drm_mode_addfb2] [FB:78]
>[ 1238.185558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.201826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.201879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.201959] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.218976] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.219018] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.219063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.219104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.219148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.219188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.219228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.219267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.219312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.219355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.219397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.219433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.219453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.219475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.219510] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.219539] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.219569] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.219591] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.219726] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.219740] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.219913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.219948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.219984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.220022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.220054] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.220080] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.220103] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.220125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.220145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.220165] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.220183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.220189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.220207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.220211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.220231] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.220249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.220274] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.220300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.220326] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.220351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.220378] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.220404] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.220430] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.220457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.220486] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.220539] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.220560] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.220583] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.220623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.220649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.220675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.220701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.220727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.220753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.220806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.220840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.220872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.220899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.220927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.220959] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.220989] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.223062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.223083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.223102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.223121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.224680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.224701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.224719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.226290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.226312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.228187] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.231520] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.231625] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.231658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.231688] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.248401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.248452] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.248519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.248733] [drm:drm_mode_addfb2] [FB:79]
>[ 1238.248970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.265077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.265125] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.265216] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.282224] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.282261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.282302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.282342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.282387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.282427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.282467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.282506] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.282551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.282594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.282636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.282678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.282717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.282757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.282876] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.282921] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.282967] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.283001] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.283164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.283177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.283235] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.283258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.283282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.283307] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.283331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.283358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.283384] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.283410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.283436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.283463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.283485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.283490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.283515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.283519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.283546] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.283569] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.283595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.283621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.283648] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.283673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.283699] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.283724] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.283752] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.283817] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.283854] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.283928] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.283955] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.283986] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.284039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.284070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.284101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.284132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.284162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.284193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.284227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.284261] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.284293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.284323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.284353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.284386] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.284408] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.286454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.286475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.286493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.286512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.288086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.288106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.288123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.289671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.289692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.291564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.294879] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.294952] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.294972] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.294998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.311727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.311779] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.311940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.312190] [drm:drm_mode_addfb2] [FB:77]
>[ 1238.312318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.328403] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.328451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.328541] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.345560] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.345598] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.345638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.345671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.345707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.345737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.345766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.345880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.345937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.345991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.346042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.346093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.346137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.346166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.346221] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.346263] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.346304] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.346335] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.346511] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.346522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.346578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.346600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.346621] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.346645] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.346663] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.346683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.346703] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.346722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.346740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.346768] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.346833] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.346841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.346870] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.346879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.346911] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.346941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.346972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.347002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.347036] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.347066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.347098] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.347128] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.347157] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.347187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.347223] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.347298] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.347329] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.347359] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.347411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.347442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.347469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.347499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.347528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.347559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.347593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.347625] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.347657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.347688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.347717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.347751] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.347804] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.349880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.349903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.349922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.349941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.351501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.351521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.351542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.353107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.353128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.355000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.358315] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.358390] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.358417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.358453] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.375165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.375219] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.375292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.375510] [drm:drm_mode_addfb2] [FB:78]
>[ 1238.375647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.391881] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.391929] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.392018] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.409011] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.409048] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.409088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.409122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.409157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.409188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.409217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.409249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.409285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.409317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.409349] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.409381] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.409409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.409441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.409523] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.409591] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.409641] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.409670] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.409869] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.409889] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.409984] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.410015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.410049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.410086] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.410114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.410146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.410176] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.410207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.410235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.410263] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.410291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.410298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.410325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.410331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.410361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.410387] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.410415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.410445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.410476] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.410506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.410533] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.410562] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.410589] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.410621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.410656] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.410736] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.410799] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.410829] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.410882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.410913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.410940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.410969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.410995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.411024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.411058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.411091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.411122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.411148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.411175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.411205] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.411235] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.413333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.413355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.413373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.413393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.414967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.414991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.415014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.416573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.416595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.418468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.421759] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.421840] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.421860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.421886] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.438632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.438684] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.438750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.439107] [drm:drm_mode_addfb2] [FB:79]
>[ 1238.439220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.455349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.455398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.455488] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.472537] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.472575] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.472615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.472650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.472693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.472733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.472774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.472889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.472958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.473006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.473053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.473100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.473141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.473182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.473236] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.473274] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.473314] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.473342] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.473478] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.473495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.473572] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.473602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.473634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.473667] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.473695] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.473723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.473759] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.473841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.473881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.473920] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.473963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.473973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.474002] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.474011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.474042] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.474072] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.474102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.474131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.474165] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.474195] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.474225] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.474254] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.474284] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.474322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.474360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.474446] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.474482] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.474516] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.474576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.474612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.474647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.474681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.474715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.474750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.474820] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.474856] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.474891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.474921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.474960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.474994] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.475023] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.477092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.477112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.477130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.477149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.478749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.478784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.478807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.480378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.480399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.482290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.485607] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.485691] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.485733] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.485859] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.502452] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.502504] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.502584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.502893] [drm:drm_mode_addfb2] [FB:77]
>[ 1238.503089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.519130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.519177] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.519266] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.536307] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.536345] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.536391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.536441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.536478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.536508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.536538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.536569] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.536612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.536656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.536698] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.536740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.536847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.536894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.536980] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.537049] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.537117] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.537170] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.537323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.537335] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.537392] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.537415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.537438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.537468] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.537493] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.537520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.537546] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.537572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.537598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.537624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.537649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.537654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.537679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.537684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.537711] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.537733] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.537801] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.537832] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.537865] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.537894] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.537923] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.537951] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.537979] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.538010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.538043] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.538120] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.538147] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.538178] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.538234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.538266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.538297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.538326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.538356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.538387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.538421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.538455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.538478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.538516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.538542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.538565] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.538586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.540634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.540655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.540673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.540693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.542273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.542293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.542311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.543864] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.543884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.545752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.549109] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.549199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.549232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.549282] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.565974] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.566027] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.566098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.566311] [drm:drm_mode_addfb2] [FB:78]
>[ 1238.566440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.582652] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.582697] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.582847] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.599855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.599897] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.599942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.599983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.600027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.600068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.600108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.600148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.600192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.600235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.600278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.600320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.600359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.600398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.600455] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.600502] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.600551] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.600584] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.600775] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.600795] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.600888] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.600912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.600937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.600963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.600984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.601006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.601028] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.601049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.601069] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.601088] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.601106] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.601112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.601130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.601134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.601154] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.601171] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.601189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.601214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.601240] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.601266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.601292] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.601318] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.601343] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.601371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.601400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.601465] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.601488] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.601509] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.601550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.601576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.601601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.601627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.601654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.601680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.601709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.601737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.601797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.601827] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.601856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.601891] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.601920] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.603989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.604010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.604028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.604047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.605622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.605642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.605660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.607229] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.607249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.609155] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.612508] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.612590] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.612623] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.612666] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.629383] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.629448] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.629513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.629959] [drm:drm_mode_addfb2] [FB:79]
>[ 1238.630123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.646075] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.646123] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.646194] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.663202] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.663249] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.663305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.663339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.663374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.663405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.663433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.663465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.663500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.663533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.663564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.663596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.663624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.663651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.663704] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.663745] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.663865] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.663900] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.664061] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.664079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.664165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.664195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.664229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.664264] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.664292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.664324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.664353] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.664383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.664411] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.664440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.664465] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.664472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.664499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.664505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.664534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.664559] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.664587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.664612] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.664643] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.664669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.664697] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.664723] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.664751] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.664808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.664844] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.664930] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.664961] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.664991] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.665041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.665071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.665099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.665128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.665154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.665184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.665216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.665249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.665280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.665306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.665334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.665365] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.665396] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.667481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.667506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.667529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.667553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.669130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.669151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.669170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.670753] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.670792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.672663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.676000] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.676097] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.676117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.676143] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.692876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.692928] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.692994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.693203] [drm:drm_mode_addfb2] [FB:77]
>[ 1238.693331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.709554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.709602] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.709674] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.726684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.726726] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.726856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.726914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.726971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.727019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.727068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.727118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.727173] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.727207] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.727240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.727273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.727303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.727332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.727387] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.727430] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.727471] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.727503] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.727664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.727676] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.727743] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.727821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.727856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.727892] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.727921] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.727953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.727984] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.728014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.728043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.728074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.728103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.728112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.728142] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.728149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.728179] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.728209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.728239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.728267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.728300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.728329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.728352] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.728370] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.728389] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.728410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.728435] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.728521] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.728543] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.728561] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.728597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.728618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.728637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.728656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.728675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.728695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.728716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.728736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.728788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.728818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.728845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.728877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.728906] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.730979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.731000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.731019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.731038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.732600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.732623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.732645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.734199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.734220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.736089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.739386] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.739456] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.739475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.739501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.756251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.756303] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.756369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.756578] [drm:drm_mode_addfb2] [FB:78]
>[ 1238.756693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.772972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.773020] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.773094] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.790080] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.790118] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.790158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.790191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.790235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.790275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.790315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.790354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.790399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.790441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.790484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.790527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.790555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.790581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.790626] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.790661] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.790698] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.790724] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.790962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.790986] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.791101] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.791144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.791190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.791238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.791280] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.791323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.791366] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.791408] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.791449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.791488] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.791530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.791538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.791566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.791573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.791602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.791631] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.791662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.791691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.791723] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.791778] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.791809] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.791840] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.791871] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.791906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.791941] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.792032] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.792063] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.792093] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.792144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.792175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.792203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.792233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.792263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.792294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.792327] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.792360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.792392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.792422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.792451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.792484] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.792516] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.794590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.794614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.794637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.794661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.796267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.796291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.796314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.797865] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.797888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.799746] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.803084] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.803141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.803172] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.803213] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.819924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.819976] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.820042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.820253] [drm:drm_mode_addfb2] [FB:79]
>[ 1238.820366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.836639] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.836687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.836838] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.853832] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.853869] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.853909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.853942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.853977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.854008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.854037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.854068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.854103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.854136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.854167] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.854198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.854226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.854254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.854308] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.854348] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.854390] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.854421] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.854629] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.854649] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.854744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.854853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.854906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.854962] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.855007] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.855061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.855111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.855157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.855203] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.855245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.855286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.855299] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.855340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.855351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.855400] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.855445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.855487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.855528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.855580] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.855625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.855672] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.855716] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.855761] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.855856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.855911] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.856019] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.856057] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.856097] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.856163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.856200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.856239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.856274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.856312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.856352] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.856394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.856435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.856472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.856497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.856519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.856547] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.856573] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.858638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.858660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.858679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.858698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.860272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.860293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.860311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.861872] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.861892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.863752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.867105] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.867190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.867210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.867235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.883985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.884037] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.884110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.884328] [drm:drm_mode_addfb2] [FB:77]
>[ 1238.884463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.900703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.900751] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.900930] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.919695] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.919733] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.919854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.919911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.919970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.920021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.920071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.920121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.920179] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.920231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.920282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.920328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.920357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.920386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.920441] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.920484] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.920524] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.920557] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.920722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.920771] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.920866] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.920890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.920914] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.920947] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.920965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.920985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.921005] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.921024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.921043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.921060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.921082] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.921087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.921110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.921114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.921138] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.921160] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.921183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.921206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.921230] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.921253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.921276] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.921300] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.921323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.921347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.921372] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.921421] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.921441] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.921461] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.921497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.921521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.921544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.921568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.921591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.921614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.921640] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.921665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.921690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.921713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.921736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.921811] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.921843] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.923917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.923940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.923959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.923978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.925540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.925561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.925579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.927130] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.927152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.929021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.932355] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.932459] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.932502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.932531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1238.949235] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.949289] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.949361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.949577] [drm:drm_mode_addfb2] [FB:78]
>[ 1238.949712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.965951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1238.965999] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1238.966071] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1238.983061] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1238.983098] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1238.983138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.983172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.983207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.983238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.983267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.983299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1238.983335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.983367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.983399] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.983430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.983458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.983486] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.983540] [drm:intel_power_well_disable [i915]] disabling display
>[ 1238.983582] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1238.983625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1238.983644] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1238.983836] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1238.983856] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1238.983940] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1238.983967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1238.983994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1238.984024] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1238.984049] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1238.984076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1238.984102] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1238.984128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1238.984154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1238.984180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1238.984205] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1238.984211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.984236] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1238.984241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1238.984266] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1238.984292] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1238.984318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1238.984341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1238.984367] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1238.984392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1238.984418] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1238.984444] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1238.984471] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1238.984497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1238.984525] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1238.984591] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1238.984613] [drm:intel_power_well_enable [i915]] enabling display
>[ 1238.984635] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1238.984675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1238.984702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1238.984728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1238.984786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1238.984818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1238.984849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1238.984882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1238.984914] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1238.984944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1238.984971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1238.984997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1238.985029] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1238.985059] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1238.987145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1238.987167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1238.987186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.987205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1238.988794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1238.988818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1238.988841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1238.990412] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1238.990434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1238.992308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1238.995460] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1238.995539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1238.995572] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1238.995613] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.012314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.012365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.012430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.012641] [drm:drm_mode_addfb2] [FB:79]
>[ 1239.012858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.028992] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.029040] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.029112] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.046691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.046728] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.046857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.046912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.046969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.047019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.047067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.047118] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.047174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.047227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.047278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.047329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.047374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.047420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.047506] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.047571] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.047634] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.047685] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.047920] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.047932] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.047990] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.048020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.048041] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.048064] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.048082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.048106] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.048130] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.048153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.048177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.048197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.048220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.048225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.048248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.048252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.048275] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.048296] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.048319] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.048343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.048366] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.048389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.048413] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.048436] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.048459] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.048484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.048509] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.048557] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.048577] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.048597] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.048633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.048657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.048680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.048704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.048727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.048813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.048851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.048887] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.048921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.048952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.048983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.049020] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.049053] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.051125] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.051148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.051172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.051198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.052779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.052800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.052819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.054378] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.054400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.056273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.059566] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.059660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.059700] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.059821] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.076437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.076489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.076555] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.076857] [drm:drm_mode_addfb2] [FB:77]
>[ 1239.077049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.093154] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.093201] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.093276] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.110265] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.110302] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.110342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.110382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.110426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.110467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.110506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.110546] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.110591] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.110634] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.110676] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.110718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.110813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.110871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.110953] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.111020] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.111085] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.111135] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.111368] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.111388] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.111491] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.111523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.111555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.111590] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.111618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.111649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.111679] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.111709] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.111749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.111810] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.111841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.111850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.111880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.111887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.111916] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.111948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.111978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.112008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.112038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.112066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.112096] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.112125] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.112151] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.112183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.112218] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.112295] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.112326] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.112357] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.112408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.112439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.112479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.112510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.112539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.112570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.112604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.112636] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.112668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.112697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.112726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.112793] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.112826] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.114901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.114923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.114942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.114961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.116530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.116551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.116569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.118132] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.118153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.120025] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.123356] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.123410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.123443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.123484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.140186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.140237] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.140304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.140514] [drm:drm_mode_addfb2] [FB:78]
>[ 1239.140628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.156918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.156967] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.157039] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.174013] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.174055] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.174100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.174141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.174185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.174224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.174265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.174304] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.174349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.174391] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.174433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.174475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.174514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.174553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.174611] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.174657] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.174707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.174811] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.174953] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.174971] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.175060] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.175093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.175118] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.175144] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.175164] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.175187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.175209] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.175230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.175250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.175269] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.175288] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.175293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.175312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.175316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.175335] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.175354] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.175372] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.175390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.175411] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.175429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.175447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.175465] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.175482] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.175504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.175527] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.175588] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.175606] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.175625] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.175659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.175684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.175714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.175767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.175797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.175826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.175858] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.175888] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.175919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.175946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.175972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.176005] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.176034] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.178098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.178120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.178138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.178157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.179724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.179761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.179780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.181335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.181356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.183243] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.186532] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.186625] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.186658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.186700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.203406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.203457] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.203524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.203815] [drm:drm_mode_addfb2] [FB:79]
>[ 1239.204010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.220121] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.220170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.220244] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.237261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.237299] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.237339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.237372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.237407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.237438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.237467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.237498] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.237534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.237567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.237598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.237629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.237658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.237685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.237820] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.237892] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.237957] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.238008] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.238205] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.238225] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.238320] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.238353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.238386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.238422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.238450] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.238482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.238512] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.238543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.238571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.238600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.238626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.238634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.238661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.238667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.238696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.238722] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.238781] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.238808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.238841] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.238869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.238899] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.238926] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.238955] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.238989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.239024] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.239101] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.239133] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.239165] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.239220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.239252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.239284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.239315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.239342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.239373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.239408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.239440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.239473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.239499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.239527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.239557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.239588] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.241672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.241698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.241723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.241794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.243367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.243391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.243414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.244985] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.245007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.246868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.250174] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.250252] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.250285] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.250329] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.267030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.267082] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.267148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.267364] [drm:drm_mode_addfb2] [FB:77]
>[ 1239.267494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.283722] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.283814] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.283884] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.300860] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.300900] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.300945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.300986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.301031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.301071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.301112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.301151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.301195] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.301238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.301281] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.301323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.301366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.301387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.301420] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.301446] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.301473] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.301492] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.301627] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.301639] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.301696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.301730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.301793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.301830] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.301859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.301892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.301922] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.301951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.301980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.302007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.302033] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.302042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.302068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.302075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.302102] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.302132] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.302160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.302186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.302217] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.302243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.302274] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.302304] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.302333] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.302365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.302400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.302479] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.302511] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.302542] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.302588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.302610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.302630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.302650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.302679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.302707] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.302756] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.302787] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.302818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.302845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.302872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.302904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.302933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.304998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.305019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.305037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.305058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.306621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.306641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.306663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.308268] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.308291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.310204] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.313536] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.313591] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.313631] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.313674] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.330364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.330415] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.330482] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.330691] [drm:drm_mode_addfb2] [FB:78]
>[ 1239.331087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.347058] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.347104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.347173] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.364190] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.364227] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.364267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.364302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.364337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.364368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.364397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.364429] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.364464] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.364496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.364528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.364559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.364586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.364613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.364666] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.364708] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.364827] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.364877] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.365042] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.365062] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.365151] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.365183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.365217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.365254] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.365285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.365319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.365352] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.365383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.365414] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.365444] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.365474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.365481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.365510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.365517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.365547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.365578] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.365609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.365637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.365670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.365699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.365751] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.365783] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.365810] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.365845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.365880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.365971] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.366003] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.366034] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.366086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.366117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.366147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.366177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.366206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.366234] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.366268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.366300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.366332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.366361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.366390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.366424] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.366456] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.368518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.368538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.368557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.368575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.370147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.370167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.370185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.371830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.371851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.373721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.377046] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.377103] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.377122] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.377148] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.393901] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.393953] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.394020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.394233] [drm:drm_mode_addfb2] [FB:79]
>[ 1239.394363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.410574] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.410622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.410695] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.427801] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.427838] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.427881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.427922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.427967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.428007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.428047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.428086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.428131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.428174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.428216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.428258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.428297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.428346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.428379] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.428405] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.428434] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.428452] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.428588] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.428600] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.428658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.428683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.428719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.428799] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.428830] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.428864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.428895] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.428925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.428954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.428982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.429009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.429018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.429044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.429051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.429078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.429108] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.429137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.429163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.429194] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.429220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.429251] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.429280] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.429309] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.429343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.429378] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.429475] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.429507] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.429538] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.429591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.429613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.429633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.429652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.429670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.429691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.429714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.429771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.429801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.429828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.429855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.429887] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.429916] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.431983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.432004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.432022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.432042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.433605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.433629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.433652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.435207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.435228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.437119] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.440486] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.440555] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.440574] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.440600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.457332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.457383] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.457450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.457668] [drm:drm_mode_addfb2] [FB:77]
>[ 1239.457887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.474031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.474082] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.474162] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.492657] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.492709] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.492842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.492896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.492954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.493003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.493051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.493101] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.493158] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.493211] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.493263] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.493314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.493360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.493405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.493492] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.493558] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.493621] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.493671] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.493882] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.493908] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.493992] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.494023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.494051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.494075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.494094] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.494114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.494133] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.494152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.494170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.494187] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.494203] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.494208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.494230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.494234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.494258] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.494280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.494303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.494326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.494350] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.494373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.494397] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.494420] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.494443] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.494468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.494494] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.494551] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.494571] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.494590] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.494627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.494651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.494674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.494698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.494770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.494804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.494841] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.494878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.494912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.494942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.494973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.495009] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.495042] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.497118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.497143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.497167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.497193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.498774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.498795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.498813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.500372] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.500395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.502274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.505592] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.505659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.505692] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.505808] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.522438] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.522489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.522556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.522829] [drm:drm_mode_addfb2] [FB:78]
>[ 1239.523026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.539097] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.539142] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.539229] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.556261] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.556299] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.556339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.556374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.556410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.556441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.556471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.556509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.556554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.556597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.556639] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.556681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.556721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.556833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.556917] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.556982] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.557040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.557071] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.557230] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.557249] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.557336] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.557366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.557399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.557435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.557463] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.557495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.557525] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.557555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.557582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.557611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.557636] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.557644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.557670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.557677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.557706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.557763] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.557789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.557819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.557848] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.557879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.557906] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.557935] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.557961] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.557995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.558030] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.558106] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.558136] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.558166] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.558216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.558247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.558274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.558302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.558329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.558358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.558390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.558422] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.558454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.558480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.558508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.558538] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.558568] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.560638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.560668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.560686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.560705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.562305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.562326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.562348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.563904] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.563926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.565794] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.569139] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.569226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.569246] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.569271] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.586006] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.586054] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.586118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.586332] [drm:drm_mode_addfb2] [FB:79]
>[ 1239.586482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.602703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.602791] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.602863] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.619868] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.619906] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.619946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.619980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.620015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.620046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.620075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.620107] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.620142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.620175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.620206] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.620236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.620264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.620291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.620344] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.620394] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.620419] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.620438] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.620572] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.620584] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.620640] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.620663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.620686] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.620779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.620809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.620840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.620871] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.620901] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.620929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.620957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.620984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.620992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.621019] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.621026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.621053] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.621080] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.621107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.621133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.621163] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.621192] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.621221] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.621247] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.621274] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.621307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.621335] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.621398] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.621417] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.621435] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.621469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.621490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.621509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.621528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.621546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.621571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.621599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.621628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.621656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.621681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.621707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.621765] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.621795] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.623865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.623886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.623905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.623924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.625489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.625509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.625527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.627094] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.627115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.628993] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.632363] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.632427] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.632460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.632502] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.649208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.649260] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.649327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.649525] [drm:drm_mode_addfb2] [FB:77]
>[ 1239.649658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.665886] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.665934] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.666006] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.683024] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.683062] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.683102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.683137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.683172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.683211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.683252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.683292] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.683337] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.683379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.683421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.683464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.683503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.683542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.683600] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.683647] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.683697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.683797] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.683958] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.683977] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.684065] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.684090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.684117] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.684146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.684171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.684198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.684224] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.684251] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.684277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.684302] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.684328] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.684334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.684358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.684363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.684389] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.684415] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.684440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.684465] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.684491] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.684515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.684540] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.684566] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.684592] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.684618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.684647] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.684699] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.684757] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.684785] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.684839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.684870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.684899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.684928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.684956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.684984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.685017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.685048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.685081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.685111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.685138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.685170] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.685202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.687296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.687317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.687336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.687355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.688946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.688967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.688985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.690526] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.690549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.692416] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.695762] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.695850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.695883] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.695925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.712631] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.712684] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.712845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.713122] [drm:drm_mode_addfb2] [FB:78]
>[ 1239.713252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.729307] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.729355] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.729427] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.747641] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.747678] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.747718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.747837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.747895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.747945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.747993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.748042] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.748082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.748117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.748149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.748182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.748210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.748245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.748281] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.748308] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.748336] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.748357] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.748472] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.748485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.748541] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.748566] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.748597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.748624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.748644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.748665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.748687] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.748760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.748789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.748817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.748844] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.748853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.748879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.748886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.748913] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.748940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.748966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.748992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.749022] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.749048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.749074] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.749100] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.749127] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.749157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.749189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.749261] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.749292] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.749323] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.749376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.749407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.749438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.749468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.749497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.749528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.749562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.749595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.749620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.749639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.749656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.749678] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.749699] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.751790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.751811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.751830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.751849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.753431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.753453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.753471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.755047] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.755070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.756944] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.760264] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.760328] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.760361] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.760401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.777106] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.777158] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.777223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.777420] [drm:drm_mode_addfb2] [FB:79]
>[ 1239.777540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.793783] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.793831] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.793903] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.810884] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.810906] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.810930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.810950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.810970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.810988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.811005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.811023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.811044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.811063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.811082] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.811101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.811117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.811133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.811166] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.811192] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.811217] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.811235] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.811357] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.811369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.811424] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.811445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.811475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.811499] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.811517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.811538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.811560] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.811583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.811608] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.811630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.811654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.811659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.811682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.811750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.811784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.811815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.811843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.811871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.811902] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.811930] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.811958] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.811986] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.812014] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.812046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.812078] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.812155] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.812185] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.812217] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.812265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.812287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.812306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.812327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.812345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.812366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.812394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.812421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.812449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.812474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.812500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.812527] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.812553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.814598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.814619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.814638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.814658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.816223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.816245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.816264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.817829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.817849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.819704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.823059] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.823157] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.823190] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.823233] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.839934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.839986] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.840053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.840260] [drm:drm_mode_addfb2] [FB:77]
>[ 1239.840373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.856604] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.856651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.856802] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.873790] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.873828] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.873869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.873902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.873938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.873969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.873998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.874030] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.874065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.874098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.874129] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.874161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.874188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.874216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.874270] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.874311] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.874352] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.874383] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.874589] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.874609] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.874703] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.874812] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.874873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.874932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.874977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.875031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.875079] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.875129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.875177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.875223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.875265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.875279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.875325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.875337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.875384] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.875426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.875471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.875515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.875567] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.875608] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.875652] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.875692] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.875758] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.875807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.875860] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.875988] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.876026] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.876066] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.876132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.876174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.876210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.876248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.876283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.876323] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.876366] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.876408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.876449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.876483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.876519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.876559] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.876599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.878733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.878755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.878776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.878801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.880389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.880412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.880431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.882005] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.882027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.883898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.887226] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.887265] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.887285] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.887310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.904061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.904112] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.904179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.904373] [drm:drm_mode_addfb2] [FB:78]
>[ 1239.904507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.920781] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.920827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.920895] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1239.937888] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1239.937925] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1239.937964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.937998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.938032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.938062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.938091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.938130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.938175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.938218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.938260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.938303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.938348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.938376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.938422] [drm:intel_power_well_disable [i915]] disabling display
>[ 1239.938457] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1239.938494] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.938520] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1239.938719] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1239.938747] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1239.938874] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1239.938921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1239.938968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1239.939019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1239.939060] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1239.939102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1239.939132] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1239.939160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1239.939186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1239.939212] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1239.939236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1239.939244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.939268] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1239.939274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1239.939300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1239.939323] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1239.939358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1239.939379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1239.939406] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1239.939434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1239.939466] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1239.939497] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1239.939528] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1239.939561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.939595] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1239.939675] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1239.939733] [drm:intel_power_well_enable [i915]] enabling display
>[ 1239.939767] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1239.939831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1239.939868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1239.939903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1239.939936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1239.939969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1239.940004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1239.940042] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1239.940078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1239.940118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.940165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1239.940198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1239.940240] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1239.940279] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1239.942373] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1239.942397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1239.942417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.942438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1239.943998] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1239.944018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1239.944036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1239.945595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1239.945616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1239.947489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1239.950753] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1239.950816] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1239.950837] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1239.950875] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1239.967602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1239.967653] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1239.967803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1239.968078] [drm:drm_mode_addfb2] [FB:79]
>[ 1239.968206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1239.984279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1239.984332] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1239.984408] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.002633] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.002670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.002793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.002854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.002910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.002958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.003006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.003056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.003112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.003165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.003216] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.003266] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.003309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.003353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.003439] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.003505] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.003568] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.003601] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.003791] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.003819] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.003906] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.003937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.003981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.004018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.004053] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.004083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.004111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.004139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.004165] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.004192] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.004216] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.004223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.004248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.004254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.004280] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.004305] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.004331] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.004355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.004384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.004408] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.004434] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.004458] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.004483] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.004513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.004544] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.004617] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.004645] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.004672] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.004761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.004791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.004824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.004852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.004882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.004912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.004945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.004978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.005012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.005039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.005068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.005103] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.005132] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.007206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.007227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.007246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.007265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.008859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.008882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.008905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.010475] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.010496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.012361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.015678] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.015797] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.015831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.015857] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.032575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.032628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.032694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.033059] [drm:drm_mode_addfb2] [FB:77]
>[ 1240.033198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.049264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.049314] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.049382] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.067703] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.067775] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.067815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.067850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.067886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.067916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.067946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.067978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.068015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.068047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.068079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.068110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.068138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.068165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.068219] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.068265] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.068316] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.068352] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.068569] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.068589] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.068683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.068796] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.068851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.068913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.068963] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.069019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.069071] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.069123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.069173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.069223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.069270] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.069283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.069329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.069342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.069389] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.069436] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.069484] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.069529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.069580] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.069627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.069675] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.069762] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.069805] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.069856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.069912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.070028] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.070062] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.070100] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.070169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.070206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.070244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.070281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.070319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.070358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.070401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.070444] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.070484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.070520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.070556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.070599] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.070640] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.072756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.072776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.072795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.072814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.074387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.074407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.074425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.075982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.076003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.077895] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.081181] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.081264] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.081283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.081309] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.098053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.098102] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.098166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.098364] [drm:drm_mode_addfb2] [FB:78]
>[ 1240.098497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.114756] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.114802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.114871] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.131881] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.131918] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.131958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.131991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.132026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.132057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.132087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.132119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.132162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.132205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.132247] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.132289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.132328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.132368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.132425] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.132471] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.132522] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.132558] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.132828] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.132857] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.133005] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.133067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.133115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.133161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.133198] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.133242] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.133282] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.133324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.133362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.133400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.133434] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.133443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.133478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.133487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.133525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.133559] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.133595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.133628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.133669] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.133745] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.133781] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.133820] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.133855] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.133899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.133945] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.134075] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.134110] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.134143] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.134200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.134236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.134270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.134302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.134332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.134362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.134398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.134434] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.134468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.134496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.134526] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.134560] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.134592] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.136677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.136714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.136733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.136756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.138347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.138368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.138387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.139957] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.139979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.141854] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.145190] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.145291] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.145311] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.145337] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.162066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.162118] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.162193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.162421] [drm:drm_mode_addfb2] [FB:79]
>[ 1240.162532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.178747] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.178800] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.178876] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.195889] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.195926] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.195966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.195999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.196034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.196064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.196102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.196150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.196187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.196220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.196252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.196283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.196311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.196339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.196389] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.196418] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.196448] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.196470] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.196599] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.196611] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.196668] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.196764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.196800] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.196835] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.196864] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.196897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.196928] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.196957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.196985] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.197016] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.197045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.197055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.197084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.197091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.197121] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.197151] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.197181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.197210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.197243] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.197273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.197303] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.197332] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.197351] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.197373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.197398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.197465] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.197484] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.197503] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.197538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.197559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.197577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.197603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.197629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.197655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.197685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.197740] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.197774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.197801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.197828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.197861] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.197890] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.199978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.200000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.200018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.200038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.201607] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.201628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.201646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.203244] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.203265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.205164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.208484] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.208548] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.208580] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.208632] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.225329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.225380] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.225446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.225734] [drm:drm_mode_addfb2] [FB:77]
>[ 1240.225933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.242045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.242093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.242166] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.260631] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.260669] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.260802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.260856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.260912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.260961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.261008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.261058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.261115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.261167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.261219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.261269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.261315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.261361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.261446] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.261512] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.261574] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.261625] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.261859] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.261876] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.261955] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.261977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.261998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.262021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.262039] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.262059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.262079] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.262098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.262116] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.262133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.262149] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.262154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.262170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.262173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.262190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.262206] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.262222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.262238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.262257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.262273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.262290] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.262305] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.262321] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.262341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.262362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.262417] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.262434] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.262450] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.262482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.262500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.262516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.262533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.262549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.262567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.262586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.262604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.262622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.262638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.262653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.262674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.262743] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.264819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.264840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.264858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.264878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.266446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.266466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.266484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.268044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.268065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.269934] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.273195] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.273259] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.273286] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.273322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.290048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.290099] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.290165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.290378] [drm:drm_mode_addfb2] [FB:78]
>[ 1240.290506] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.306791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.306839] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.306913] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.323902] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.323940] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.323980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.324020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.324064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.324104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.324144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.324184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.324228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.324271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.324313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.324355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.324395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.324434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.324491] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.324538] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.324588] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.324624] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.325157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.325176] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.325273] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.325305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.325337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.325372] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.325402] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.325432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.325463] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.325493] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.325523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.325551] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.325579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.325585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.325612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.325618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.325646] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.325673] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.325739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.325773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.325805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.325836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.325866] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.325899] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.325929] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.325964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.325999] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.326323] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.326354] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.326384] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.326445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.326475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.326503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.326531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.326559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.326587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.326619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.326649] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.326690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.326748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.326782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.326819] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.326851] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.328918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.328939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.328961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.328985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.330557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.330578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.330597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.332157] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.332178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.334082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.337362] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.337400] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.337424] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.337455] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.354195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.354247] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.354315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.354534] [drm:drm_mode_addfb2] [FB:79]
>[ 1240.354682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.370911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.370960] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.371033] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.388021] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.388059] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.388099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.388133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.388168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.388199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.388228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.388260] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.388296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.388329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.388369] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.388412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.388452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.388478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.388524] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.388558] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.388594] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.388621] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.389157] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.389182] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.389301] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.389344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.389390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.389439] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.389488] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.389518] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.389549] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.389578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.389607] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.389635] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.389662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.389708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.389738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.389748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.389780] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.389811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.389842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.389872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.389908] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.389938] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.389970] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.390000] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.390030] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.390062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.390098] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.390399] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.390418] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.390436] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.390472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.390494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.390522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.390540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.390557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.390579] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.390605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.390629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.390654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.390677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.390750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.390788] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.390822] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.393073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.393094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.393117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.393141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.394823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.394844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.394862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.396409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.396431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.398302] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.401600] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.401686] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.401781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.401838] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.418463] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.418514] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.418580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.419020] [drm:drm_mode_addfb2] [FB:77]
>[ 1240.419150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.435139] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.435186] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.435258] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.453110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.453148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.453188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.453222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.453256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.453287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.453316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.453347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.453383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.453416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.453448] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.453480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.453518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.453557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.453615] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.453662] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.453803] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.453862] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.454057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.454078] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.454174] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.454205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.454239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.454275] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.454303] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.454335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.454365] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.454396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.454424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.454453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.454479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.454486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.454513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.454519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.454550] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.454576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.454604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.454630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.454661] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.454718] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.454749] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.454777] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.454806] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.454840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.454875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.454967] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.454997] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.455027] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.455077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.455109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.455137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.455166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.455192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.455221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.455254] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.455285] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.455316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.455342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.455369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.455403] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.455431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.457498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.457520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.457539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.457563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.459129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.459149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.459167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.460723] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.460744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.462614] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.465948] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.466045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.466064] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.466090] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.482829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.482882] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.482955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.483170] [drm:drm_mode_addfb2] [FB:78]
>[ 1240.483291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.499505] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.499554] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.499626] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.516652] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.516725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.516764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.516798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.516833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.516863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.516891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.516922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.516957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.516990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.517030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.517078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.517104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.517129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.517174] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.517209] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.517245] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.517271] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.517440] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.517456] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.517536] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.517568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.517601] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.517636] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.517664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.517762] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.517804] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.517842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.517880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.517916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.517951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.517962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.517996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.518006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.518042] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.518086] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.518124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.518160] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.518202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.518239] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.518277] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.518313] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.518350] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.518397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.518444] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.518574] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.518617] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.518659] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.518766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.518812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.518856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.518898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.518941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.518980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.519025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.519068] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.519114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.519144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.519178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.519214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.519246] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.521351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.521377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.521402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.521428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.522999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.523020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.523039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.524588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.524610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.526482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.529803] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.529864] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.529896] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.529937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.546645] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.546782] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.546883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.547085] [drm:drm_mode_addfb2] [FB:79]
>[ 1240.547215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.563361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.563409] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.563481] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.581612] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.581649] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.581777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.581835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.581892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.581940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.581988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.582039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.582095] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.582148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.582200] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.582251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.582297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.582342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.582411] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.582454] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.582494] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.582527] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.582763] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.582783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.582853] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.582876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.582902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.582938] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.582960] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.582981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.583002] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.583025] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.583049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.583070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.583093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.583098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.583120] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.583125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.583148] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.583169] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.583192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.583215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.583239] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.583262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.583285] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.583309] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.583332] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.583357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.583382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.583441] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.583462] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.583481] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.583518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.583542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.583566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.583589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.583612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.583636] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.583661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.583739] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.583774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.583803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.583831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.583867] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.583896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.585968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.585990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.586008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.586027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.587589] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.587609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.587628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.589198] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.589219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.591212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.594505] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.594605] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.594632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.594672] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.611376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.611427] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.611493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.611940] [drm:drm_mode_addfb2] [FB:77]
>[ 1240.612072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.628053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.628101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.628172] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.645206] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.645249] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.645294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.645335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.645379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.645420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.645460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.645499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.645544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.645595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.645630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.645662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.645773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.645818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.645898] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.645957] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.646016] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.646061] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.646278] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.646304] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.646425] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.646470] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.646518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.646569] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.646618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.646648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.646720] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.646752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.646786] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.646818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.646848] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.646857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.646887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.646895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.646925] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.646956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.646986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.647016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.647047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.647077] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.647107] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.647136] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.647162] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.647194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.647229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.647316] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.647347] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.647377] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.647428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.647460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.647491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.647521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.647550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.647581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.647614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.647646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.647704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.647734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.647764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.647801] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.647832] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.649894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.649915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.649934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.649953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.651522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.651542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.651561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.653121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.653142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.655014] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.658332] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.658400] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.658440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.658492] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.675175] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.675226] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.675292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.675513] [drm:drm_mode_addfb2] [FB:78]
>[ 1240.675643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.691854] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.691902] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.691974] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.708999] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.709037] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.709077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.709111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.709146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.709177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.709207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.709239] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.709274] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.709307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.709339] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.709371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.709399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.709426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.709480] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.709521] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.709562] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.709593] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.710144] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.710171] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.710255] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.710287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.710319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.710354] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.710382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.710413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.710444] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.710473] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.710502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.710530] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.710558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.710565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.710591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.710597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.710625] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.710652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.710717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.710749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.710782] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.710812] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.710842] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.710872] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.710902] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.710937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.710973] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.711303] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.711335] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.711365] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.711426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.711456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.711486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.711514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.711541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.711570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.711601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.711630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.711671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.711729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.711761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.711797] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.711829] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.713894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.713914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.713933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.713951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.715502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.715532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.715554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.717118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.717139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.719009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.722327] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.722388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.722407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.722433] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.739171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.739222] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.739289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.739498] [drm:drm_mode_addfb2] [FB:79]
>[ 1240.739629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.755849] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.755898] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.755970] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.772982] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.773020] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.773059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.773093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.773128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.773159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.773188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.773220] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.773255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.773288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.773319] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.773350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.773378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.773415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.773473] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.773511] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.773537] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.773556] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.773770] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.773789] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.773853] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.773877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.773902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.773927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.773946] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.773969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.773994] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.774021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.774047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.774073] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.774098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.774104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.774129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.774133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.774159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.774185] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.774211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.774234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.774261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.774286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.774312] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.774337] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.774364] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.774391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.774418] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.774481] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.774503] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.774525] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.774565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.774591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.774636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.774671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.774721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.774751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.774784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.774816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.774847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.774874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.774901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.774933] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.774962] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.777045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.777069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.777092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.777116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.778699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.778722] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.778742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.780305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.780327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.782207] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.785537] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.785593] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.785633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.785741] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.802367] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.802419] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.802484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.802959] [drm:drm_mode_addfb2] [FB:77]
>[ 1240.803076] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.819076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.819124] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.819197] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.837605] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.837642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.837770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.837823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.837882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.837930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.837977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.838027] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.838083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.838136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.838187] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.838238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.838283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.838328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.838414] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.838479] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.838542] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.838594] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.838884] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.838902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.838981] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.839002] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.839024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.839047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.839065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.839085] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.839105] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.839124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.839147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.839169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.839192] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.839197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.839220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.839224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.839248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.839269] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.839292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.839315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.839338] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.839361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.839385] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.839408] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.839432] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.839456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.839482] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.839530] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.839550] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.839570] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.839606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.839630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.839654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.839737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.839771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.839806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.839842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.839877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.839911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.839943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.839974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.840010] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.840042] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.842104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.842126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.842154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.842173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.843769] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.843789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.843807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.845359] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.845380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.847244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.850562] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.850627] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.850660] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.850788] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.867411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.867464] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.867537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.867951] [drm:drm_mode_addfb2] [FB:78]
>[ 1240.868093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.884125] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.884173] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.884245] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.901232] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.901270] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.901311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.901345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.901380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.901411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.901441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.901473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.901508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.901541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.901582] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.901624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.901664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.901776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.901860] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.901925] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.901992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.902042] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.902268] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.902287] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.902375] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.902405] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.902438] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.902474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.902501] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.902534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.902564] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.902594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.902621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.902650] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.902707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.902715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.902744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.902753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.902783] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.902810] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.902840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.902867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.902899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.902926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.902956] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.902986] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.903013] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.903047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.903080] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.903169] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.903200] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.903229] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.903280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.903310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.903338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.903367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.903393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.903423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.903455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.903487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.903518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.903544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.903571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.903602] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.903632] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.905719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.905743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.905765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.905790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.907372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.907395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.907413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.908982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.909004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.910898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.914234] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.914336] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.914376] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.914432] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.931109] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.931160] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.931231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.931447] [drm:drm_mode_addfb2] [FB:79]
>[ 1240.931579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.947787] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1240.947835] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1240.947906] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1240.964931] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1240.964968] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1240.965008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.965042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.965077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.965107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.965136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.965168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.965203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.965235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.965267] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.965298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.965326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.965353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.965406] [drm:intel_power_well_disable [i915]] disabling display
>[ 1240.965448] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1240.965488] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.965520] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1240.965722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1240.965742] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1240.965841] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1240.965876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1240.965913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1240.965951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1240.965978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1240.966002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1240.966028] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1240.966054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1240.966080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1240.966106] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1240.966132] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1240.966138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.966163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1240.966168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1240.966194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1240.966219] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1240.966246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1240.966271] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1240.966298] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1240.966324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1240.966350] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1240.966375] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1240.966400] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1240.966427] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1240.966455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1240.966521] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1240.966543] [drm:intel_power_well_enable [i915]] enabling display
>[ 1240.966565] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1240.966609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1240.966644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1240.966702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1240.966732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1240.966761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1240.966790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1240.966823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1240.966854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1240.966885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.966912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1240.966938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1240.966970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1240.967000] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1240.969084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1240.969108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1240.969131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.969155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1240.970760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1240.970786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1240.970818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1240.972377] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1240.972399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1240.974271] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1240.977589] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1240.977654] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1240.977754] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1240.977829] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1240.994433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1240.994485] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1240.994552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1240.994992] [drm:drm_mode_addfb2] [FB:77]
>[ 1240.995122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.011110] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.011158] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.011230] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.029596] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.029634] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.029764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.029817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.029874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.029923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.029979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.030024] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.030075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.030122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.030168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.030213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.030253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.030293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.030370] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.030433] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.030487] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.030532] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.030778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.030805] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.030893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.030926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.030959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.030994] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.031027] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.031054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.031084] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.031114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.031145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.031171] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.031200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.031206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.031235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.031240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.031271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.031297] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.031327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.031357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.031387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.031416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.031446] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.031476] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.031506] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.031537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.031569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.031645] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.031733] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.031767] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.031831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.031869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.031903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.031937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.031973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.032010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.032054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.032087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.032121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.032150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.032180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.032214] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.032247] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.034320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.034341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.034360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.034378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.035957] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.035976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.035999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.037565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.037589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.039464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.042786] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.042846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.042879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.042921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.059629] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.059707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.059774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.059991] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.060122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.076308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.076357] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.076428] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.093441] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.093478] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.093518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.093552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.093587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.093616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.093644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.093770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.093829] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.093883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.093934] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.093986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.094033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.094079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.094159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.094225] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.094287] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.094338] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.094500] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.094522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.094578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.094599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.094621] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.094655] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.094721] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.094755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.094788] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.094817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.094849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.094877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.094906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.094915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.094944] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.094952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.094983] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.095010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.095038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.095065] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.095097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.095122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.095150] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.095176] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.095203] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.095232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.095279] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.095357] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.095388] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.095418] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.095469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.095499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.095526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.095554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.095580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.095610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.095643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.095701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.095734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.095761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.095790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.095825] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.095855] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.097926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.097950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.097973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.097997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.099568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.099589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.099607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.101183] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.101204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.103078] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.106411] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.106513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.106545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.106586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.123289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.123341] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.123408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.123616] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.123882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.139965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.140013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.140085] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.157072] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.157109] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.157149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.157183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.157217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.157248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.157278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.157310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.157345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.157378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.157409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.157440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.157468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.157495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.157549] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.157590] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.157631] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.157748] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.157895] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.157913] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.158001] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.158033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.158067] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.158104] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.158135] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.158168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.158201] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.158232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.158265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.158294] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.158324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.158332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.158360] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.158368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.158397] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.158427] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.158458] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.158487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.158521] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.158550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.158580] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.158609] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.158635] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.158694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.158732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.158821] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.158851] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.158883] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.158935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.158967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.158999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.159030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.159060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.159091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.159125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.159158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.159191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.159221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.159250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.159284] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.159316] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.161405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.161428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.161447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.161466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.163042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.163063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.163081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.164638] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.164670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.166539] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.169920] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.169956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.169976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.170001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.186753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.186804] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.186871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.187081] [drm:drm_mode_addfb2] [FB:77]
>[ 1241.187196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.203469] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.203517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.203590] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.220564] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.220602] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.220642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.220770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.220830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.220879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.220928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.220977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.221034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.221087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.221144] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.221178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.221207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.221238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.221294] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.221339] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.221379] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.221411] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.221571] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.221585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.221656] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.221721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.221758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.221793] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.221823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.221857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.221890] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.221923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.221954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.221984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.222014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.222022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.222051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.222059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.222086] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.222104] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.222124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.222141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.222164] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.222181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.222200] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.222218] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.222236] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.222257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.222282] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.222334] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.222353] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.222371] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.222406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.222427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.222451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.222477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.222504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.222529] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.222558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.222585] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.222613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.222639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.222689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.222722] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.222753] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.224826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.224848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.224866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.224886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.226457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.226480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.226503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.228058] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.228080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.229948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.233245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.233331] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.233364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.233405] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.250111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.250163] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.250229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.250443] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.250571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.266786] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.266834] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.266907] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.283905] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.283942] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.283981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.284015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.284050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.284081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.284110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.284142] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.284177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.284209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.284241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.284272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.284301] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.284328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.284382] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.284423] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.284465] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.284496] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.284716] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.284736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.284833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.284868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.284906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.284944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.284970] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.284994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.285017] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.285038] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.285063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.285087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.285113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.285119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.285144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.285149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.285175] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.285200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.285226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.285251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.285278] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.285303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.285330] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.285356] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.285387] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.285421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.285447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.285500] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.285518] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.285537] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.285573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.285594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.285613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.285632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.285688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.285720] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.285752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.285782] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.285813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.285840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.285866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.285900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.285928] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.288013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.288035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.288054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.288073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.289645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.289682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.289701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.291271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.291294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.293175] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.296471] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.296559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.296592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.296634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.313343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.313394] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.313461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.313753] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.313952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.330036] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.330084] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.330160] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.348582] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.348619] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.348742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.348789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.348846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.348889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.348935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.348979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.349033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.349084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.349134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.349183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.349224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.349267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.349351] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.349416] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.349479] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.349528] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.349800] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.349830] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.349958] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.349987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.350010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.350033] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.350051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.350071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.350090] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.350113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.350137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.350159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.350181] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.350186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.350209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.350213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.350237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.350258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.350281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.350304] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.350327] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.350350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.350374] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.350397] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.350420] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.350445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.350470] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.350517] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.350537] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.350556] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.350593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.350617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.350651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.350713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.350743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.350774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.350808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.350840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.350870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.350897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.350924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.350957] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.350987] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.353050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.353070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.353088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.353107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.354691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.354714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.354733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.356308] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.356331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.358200] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.361523] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.361583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.361615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.361745] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.378356] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.378405] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.378470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.378751] [drm:drm_mode_addfb2] [FB:77]
>[ 1241.378950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.395073] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.395121] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.395195] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.412186] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.412225] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.412265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.412300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.412335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.412365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.412395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.412426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.412461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.412494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.412526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.412557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.412586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.412613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.412748] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.412818] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.412884] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.412937] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.413167] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.413194] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.413252] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.413274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.413297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.413322] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.413342] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.413363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.413385] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.413405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.413425] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.413450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.413476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.413482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.413507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.413512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.413538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.413563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.413589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.413615] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.413670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.413702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.413731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.413759] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.413788] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.413820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.413853] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.413928] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.413957] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.413988] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.414042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.414074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.414105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.414135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.414165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.414196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.414224] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.414245] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.414267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.414285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.414305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.414327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.414348] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.416407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.416431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.416452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.416473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.418040] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.418079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.418110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.419691] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.419713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.421574] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.424895] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.424955] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.424987] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.425029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.441737] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.441789] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.441855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.442064] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.442196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.458415] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.458465] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.458537] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.475559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.475597] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.475637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.475758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.475816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.475864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.475912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.475961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.476018] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.476070] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.476120] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.476171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.476216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.476261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.476347] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.476420] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.476460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.476493] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.476701] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.476731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.476808] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.476832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.476856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.476889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.476908] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.476928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.476948] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.476967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.476986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.477003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.477019] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.477024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.477040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.477044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.477061] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.477077] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.477093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.477110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.477129] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.477146] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.477162] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.477178] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.477194] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.477213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.477234] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.477281] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.477298] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.477315] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.477346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.477365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.477382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.477399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.477415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.477433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.477453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.477471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.477489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.477505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.477521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.477541] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.477560] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.479626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.479666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.479685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.479707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.481289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.481311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.481330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.482890] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.482912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.484795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.488158] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.488229] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.488263] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.488305] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.505033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.505086] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.505151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.505394] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.505520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.521716] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.521764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.521856] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.538890] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.538927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.538967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.539001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.539036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.539075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.539115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.539155] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.539200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.539242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.539284] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.539326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.539366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.539405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.539462] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.539509] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.539559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.539594] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.539841] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.539860] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.539950] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.539980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.540014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.540050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.540078] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.540110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.540140] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.540171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.540199] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.540228] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.540254] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.540261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.540288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.540295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.540325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.540351] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.540379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.540405] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.540436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.540461] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.540489] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.540515] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.540542] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.540571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.540604] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.540700] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.540732] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.540763] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.540814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.540843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.540873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.540901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.540929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.540957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.540991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.541023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.541054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.541080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.541109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.541142] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.541171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.543262] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.543284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.543303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.543322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.544898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.544918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.544937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.546476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.546499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.548364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.551741] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.551799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.551832] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.551873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.568576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.568627] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.568805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.569054] [drm:drm_mode_addfb2] [FB:77]
>[ 1241.569179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.585286] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.585331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.585400] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.602394] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.602431] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.602471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.602505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.602541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.602580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.602621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.602744] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.602805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.602859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.602910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.602961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.603006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.603052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.603115] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.603158] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.603199] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.603231] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.603374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.603387] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.603458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.603479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.603501] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.603525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.603543] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.603563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.603584] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.603603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.603632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.603689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.603716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.603726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.603753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.603760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.603788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.603815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.603842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.603869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.603899] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.603926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.603953] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.603979] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.604006] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.604038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.604070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.604148] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.604180] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.604211] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.604265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.604297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.604327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.604357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.604387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.604418] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.604443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.604464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.604484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.604503] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.604521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.604543] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.604564] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.606609] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.606642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.606665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.606689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.608249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.608271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.608291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.609847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.609869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.611723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.615068] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.615161] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.615201] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.615253] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.631942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.631995] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.632061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.632277] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.632405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.648629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.648719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.648812] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.665819] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.665857] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.665897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.665931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.665966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.665996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.666026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.666057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.666093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.666125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.666156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.666196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.666236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.666275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.666332] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.666379] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.666429] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.666461] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.666596] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.666657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.666755] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.666789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.666825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.666862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.666894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.666927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.666960] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.666992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.667025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.667056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.667085] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.667092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.667120] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.667128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.667157] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.667187] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.667216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.667244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.667277] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.667305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.667334] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.667364] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.667393] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.667426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.667461] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.667538] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.667569] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.667600] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.667680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.667711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.667744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.667776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.667807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.667839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.667875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.667910] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.667944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.667974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.668005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.668042] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.668074] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.670144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.670165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.670184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.670203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.671771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.671793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.671822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.673380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.673401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.675273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.678594] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.678712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.678750] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.678795] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.695436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.695489] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.695562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.695911] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.696041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.712111] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.712162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.712238] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.729253] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.729291] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.729331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.729364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.729400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.729430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.729459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.729490] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.729525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.729558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.729589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.729621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.729739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.729788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.729856] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.729899] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.729940] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.729973] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.730134] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.730153] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.730249] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.730279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.730311] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.730345] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.730373] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.730403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.730434] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.730463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.730492] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.730519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.730546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.730553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.730579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.730585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.730613] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.730678] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.730712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.730739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.730772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.730802] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.730834] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.730863] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.730889] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.730921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.730958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.731045] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.731077] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.731107] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.731158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.731190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.731221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.731248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.731277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.731308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.731342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.731375] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.731407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.731436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.731464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.731498] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.731529] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.733594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.733616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.733684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.733719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.735280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.735300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.735318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.736879] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.736900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.738777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.742071] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.742145] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.742165] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.742191] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.758942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.758993] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.759060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.759269] [drm:drm_mode_addfb2] [FB:77]
>[ 1241.759400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.775617] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.775711] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.775781] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.792767] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.792805] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.792845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.792879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.792915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.792945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.792975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.793007] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.793050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.793093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.793135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.793178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.793217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.793256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.793314] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.793361] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.793411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.793447] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.793708] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.793741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.793880] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.793918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.793956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.793995] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.794034] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.794076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.794107] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.794136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.794193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.794230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.794256] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.794262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.794288] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.794294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.794321] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.794346] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.794371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.794397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.794427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.794462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.794499] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.794536] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.794571] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.794610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.794691] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.794798] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.794837] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.794881] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.794937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.794967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.794995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.795022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.795058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.795081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.795106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.795130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.795154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.795175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.795196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.795222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.795245] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.797305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.797326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.797344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.797363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.798950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.798972] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.798991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.800550] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.800571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.802436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.805771] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.805871] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.805904] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.805954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.822680] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.822731] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.822801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.823017] [drm:drm_mode_addfb2] [FB:78]
>[ 1241.823137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.839322] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.839369] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.839441] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.857720] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.857758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.857797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.857837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.857882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.857923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.857962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.858002] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.858046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.858089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.858132] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.858174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.858213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.858253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.858310] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.858357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.858407] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.858443] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.858657] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.858686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.858809] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.858842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.858874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.858907] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.858933] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.858964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.858992] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.859021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.859047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.859073] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.859097] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.859104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.859128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.859133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.859159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.859183] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.859208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.859231] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.859260] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.859283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.859308] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.859340] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.859375] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.859411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.859449] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.859533] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.859570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.859592] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.859673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.859707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.859739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.859769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.859799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.859830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.859866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.859900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.859934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.859963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.859992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.860027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.860059] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.862147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.862171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.862191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.862212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.863787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.863808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.863827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.865381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.865402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.867282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.870307] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.870363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.870396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.870438] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.887143] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.887195] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.887261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.887484] [drm:drm_mode_addfb2] [FB:79]
>[ 1241.887621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.903817] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.903865] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.903937] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.922559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.922597] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.922729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.922782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.922839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.922887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.922935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.922985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.923041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.923094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.923145] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.923196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.923242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.923287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.923373] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.923438] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.923501] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.923553] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.923812] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.923841] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.923972] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.924016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.924063] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.924100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.924125] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.924159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.924192] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.924226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.924260] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.924290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.924322] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.924328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.924361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.924366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.924400] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.924429] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.924462] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.924495] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.924528] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.924561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.924594] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.924689] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.924735] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.924783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.924831] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.924928] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.924959] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.924990] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.925042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.925074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.925105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.925133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.925162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.925193] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.925227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.925260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.925293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.925322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.925351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.925383] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.925414] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.927482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.927506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.927529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.927553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.929133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.929154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.929177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.930732] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.930754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.932617] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.935963] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.936063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.936103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.936139] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1241.952836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.952888] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.952959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.953172] [drm:drm_mode_addfb2] [FB:77]
>[ 1241.953301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.969513] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1241.969558] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1241.969710] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1241.986720] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1241.986758] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1241.986798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.986832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.986866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.986896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.986925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.986956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1241.986991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.987023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.987054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.987085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.987112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.987139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.987192] [drm:intel_power_well_disable [i915]] disabling display
>[ 1241.987229] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1241.987254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1241.987273] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1241.987404] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1241.987416] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1241.987472] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1241.987495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1241.987518] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1241.987543] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1241.987563] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1241.987584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1241.987616] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1241.987688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1241.987720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1241.987751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1241.987781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1241.987790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.987819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1241.987828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1241.987858] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1241.987888] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1241.987919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1241.987949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1241.987983] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1241.988012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1241.988043] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1241.988074] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1241.988105] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1241.988140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1241.988175] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1241.988251] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1241.988281] [drm:intel_power_well_enable [i915]] enabling display
>[ 1241.988312] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1241.988362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1241.988394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1241.988424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1241.988454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1241.988481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1241.988511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1241.988545] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1241.988578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1241.988611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1241.988664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1241.988692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1241.988728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1241.988760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1241.990843] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1241.990865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1241.990884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.990903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1241.992474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1241.992494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1241.992512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1241.994073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1241.994094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1241.995965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1241.999273] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1241.999346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1241.999378] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1241.999420] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.016125] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.016176] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.016243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.016469] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.016598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.032844] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.032893] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.032965] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.049965] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.050003] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.050043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.050077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.050113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.050143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.050173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.050205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.050240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.050273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.050305] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.050336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.050364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.050392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.050445] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.050486] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.050528] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.050561] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.050744] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.050763] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.050852] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.050884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.050919] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.050957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.050988] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.051021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.051054] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.051086] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.051117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.051147] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.051177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.051185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.051213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.051220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.051250] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.051280] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.051310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.051339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.051369] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.051399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.051429] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.051460] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.051491] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.051524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.051559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.051672] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.051704] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.051735] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.051789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.051821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.051851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.051882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.051910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.051941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.051975] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.052007] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.052039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.052068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.052097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.052131] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.052162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.054230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.054251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.054273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.054297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.055879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.055900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.055918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.057477] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.057498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.059360] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.062707] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.062794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.062817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.062848] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.079574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.079625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.079910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.080118] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.080246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.096251] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.096298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.096370] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.114551] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.114589] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.114722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.114776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.114833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.114882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.114930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.114988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.115039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.115085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.115131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.115177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.115219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.115260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.115336] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.115395] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.115450] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.115495] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.115736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.115764] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.115867] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.115900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.115933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.115967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.116002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.116027] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.116053] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.116078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.116101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.116123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.116144] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.116150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.116171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.116175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.116197] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.116218] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.116239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.116268] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.116299] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.116329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.116359] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.116389] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.116419] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.116450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.116483] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.116545] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.116570] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.116596] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.116712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.116748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.116784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.116817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.116850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.116884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.116923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.116963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.117008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.117035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.117061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.117094] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.117119] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.119204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.119225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.119244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.119264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.120859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.120882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.120904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.122464] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.122486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.124359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.127676] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.127742] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.127775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.127816] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.144524] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.144575] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.144735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.145008] [drm:drm_mode_addfb2] [FB:77]
>[ 1242.145140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.161199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.161247] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.161319] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.179541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.179579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.179703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.179763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.179822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.179871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.179919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.179969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.180026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.180078] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.180130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.180181] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.180228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.180268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.180323] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.180366] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.180407] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.180440] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.180620] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.180641] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.180736] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.180760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.180784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.180817] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.180835] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.180859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.180883] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.180907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.180930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.180951] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.180981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.180988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.181014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.181018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.181037] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.181054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.181071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.181093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.181117] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.181141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.181164] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.181188] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.181211] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.181236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.181280] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.181341] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.181358] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.181374] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.181408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.181432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.181456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.181479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.181503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.181526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.181551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.181576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.181601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.181673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.181704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.181737] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.181767] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.183830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.183850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.183868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.183887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.185451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.185471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.185489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.187047] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.187067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.188939] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.192247] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.192327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.192366] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.192418] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.209100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.209152] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.209219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.209442] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.209559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.225802] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.225850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.225925] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.242936] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.242973] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.243013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.243046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.243082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.243112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.243142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.243173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.243209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.243242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.243273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.243305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.243334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.243361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.243415] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.243456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.243498] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.243529] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.243728] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.243747] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.243834] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.243867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.243902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.243938] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.243969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.244002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.244035] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.244066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.244097] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.244127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.244156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.244163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.244191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.244198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.244229] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.244258] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.244289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.244318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.244348] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.244378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.244408] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.244437] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.244468] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.244500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.244535] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.244644] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.244677] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.244705] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.244757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.244790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.244822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.244853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.244883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.244916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.244951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.244985] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.245017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.245047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.245078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.245111] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.245143] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.247230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.247252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.247271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.247290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.248870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.248891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.248909] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.250459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.250480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.252343] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.255689] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.255781] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.255822] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.255873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.272555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.272609] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.272780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.273066] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.273204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.289253] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.289300] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.289390] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.306396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.306434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.306473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.306507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.306542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.306572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.306601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.306722] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.306781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.306834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.306885] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.306937] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.306984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.307031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.307084] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.307111] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.307139] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.307159] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.307272] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.307284] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.307339] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.307360] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.307383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.307412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.307437] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.307464] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.307490] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.307516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.307560] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.307583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.307643] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.307651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.307680] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.307687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.307716] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.307743] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.307770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.307796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.307828] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.307854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.307881] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.307908] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.307934] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.307964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.307997] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.308074] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.308101] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.308121] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.308159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.308185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.308212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.308239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.308265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.308291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.308319] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.308347] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.308375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.308401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.308426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.308454] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.308479] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.310558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.310580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.310659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.310693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.312253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.312273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.312291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.313853] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.313874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.315741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.319079] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.319175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.319208] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.319250] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.335954] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.336006] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.336072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.336307] [drm:drm_mode_addfb2] [FB:77]
>[ 1242.336449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.352690] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.352743] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.352836] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.369829] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.369867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.369907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.369941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.369975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.370006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.370036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.370068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.370103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.370136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.370168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.370200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.370228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.370256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.370310] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.370351] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.370400] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.370419] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.370552] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.370566] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.370694] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.370872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.370908] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.370945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.370973] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.371006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.371036] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.371066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.371096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.371126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.371153] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.371160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.371187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.371193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.371222] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.371248] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.371277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.371303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.371334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.371359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.371388] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.371413] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.371441] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.371471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.371504] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.371596] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.371651] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.371682] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.371734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.371764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.371796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.371824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.371855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.371883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.371918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.371951] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.371984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.372011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.372379] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.372411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.372438] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.374531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.374554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.374577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.374646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.376227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.376250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.376273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.377834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.377856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.379717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.382979] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.383045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.383074] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.383111] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.399829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.399880] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.399946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.400183] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.400340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.416527] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.416574] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.416752] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.433746] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.433783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.433824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.433857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.433900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.433941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.433981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.434021] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.434065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.434108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.434151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.434193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.434232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.434271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.434329] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.434376] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.434426] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.434462] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.434742] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.434768] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.434892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.434937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.434984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.435034] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.435075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.435118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.435162] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.435204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.435245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.435284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.435323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.435333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.435371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.435380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.435419] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.435458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.435497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.435534] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.435577] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.435654] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.435692] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.435742] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.435777] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.435815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.435855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.435938] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.435972] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.436006] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.436063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.436097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.436130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.436163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.436197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.436230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.436268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.436303] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.436339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.436371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.436402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.436439] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.436473] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.438550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.438571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.438589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.438659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.440240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.440266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.440291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.441847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.441870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.443731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.447002] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.447046] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.447069] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.447101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.463843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.463893] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.463960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.464197] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.464344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.480561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.480686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.480783] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.497774] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.497812] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.497852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.497886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.497921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.497951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.497981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.498012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.498047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.498079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.498110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.498148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.498173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.498197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.498244] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.498281] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.498318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.498346] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.498538] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.498555] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.498744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.498793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.498842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.498895] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.498937] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.498984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.499030] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.499076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.499121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.499162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.499203] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.499214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.499253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.499263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.499306] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.499347] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.499388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.499428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.499473] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.499513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.499552] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.499593] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.499670] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.499715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.499765] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.499896] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.499939] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.499982] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.500052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.500097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.500140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.500181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.500210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.500241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.500276] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.500309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.500342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.500371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.500398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.500431] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.500463] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.502538] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.502559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.502577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.502646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.504236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.504260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.504283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.505847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.505871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.507741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.511049] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.511129] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.511169] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.511220] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.527904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.527955] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.528021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.528233] [drm:drm_mode_addfb2] [FB:77]
>[ 1242.528348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.544649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.544701] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.544794] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.561787] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.561825] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.561864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.561898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.561933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.561972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.562012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.562053] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.562097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.562140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.562182] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.562225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.562264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.562304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.562361] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.562408] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.562458] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.562494] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.562881] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.562902] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.562998] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.563030] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.563064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.563100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.563129] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.563161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.563192] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.563223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.563251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.563280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.563306] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.563313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.563339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.563346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.563375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.563401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.563429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.563455] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.563486] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.563512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.563540] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.563566] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.563620] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.563652] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.563689] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.564041] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.564070] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.564098] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.564146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.564175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.564201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.564228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.564253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.564280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.564311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.564340] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.564369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.564393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.564419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.564450] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.564477] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.566550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.566571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.566633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.566668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.568377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.568399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.568419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.569984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.570006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.571876] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.575211] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.575314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.575353] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.575404] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.592098] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.592163] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.592229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.592441] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.592564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.608764] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.608813] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.608901] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.625917] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.625955] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.625994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.626028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.626063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.626093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.626121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.626153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.626187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.626219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.626250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.626281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.626308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.626335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.626389] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.626429] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.626471] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.626502] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.626736] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.626767] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.626882] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.626906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.626930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.626957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.626982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.627009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.627035] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.627060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.627086] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.627108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.627132] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.627138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.627162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.627167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.627192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.627214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.627240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.627265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.627291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.627316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.627341] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.627366] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.627392] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.627418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.627446] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.627512] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.627534] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.627556] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.627645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.627676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.627706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.627734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.627761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.627790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.627822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.627853] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.627883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.627909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.627935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.627967] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.627998] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.630084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.630107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.630127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.630147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.631722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.631743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.631761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.633306] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.633327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.635191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.638508] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.638574] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.638687] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.638758] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.655348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.655397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.655461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.655819] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.655953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.672049] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.672098] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.672170] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.690529] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.690566] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.690692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.690730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.690769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.690800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.690831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.690863] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.690900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.690934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.690966] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.690998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.691036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.691076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.691136] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.691192] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.691221] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.691242] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.691377] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.691408] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.691478] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.691500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.691524] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.691550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.691572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.691634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.691664] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.691694] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.691723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.691751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.691777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.691786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.691812] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.691819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.691846] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.691873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.691899] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.691924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.691955] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.691981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.692007] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.692033] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.692059] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.692089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.692122] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.692198] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.692230] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.692260] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.692313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.692345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.692376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.692407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.692436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.692468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.692502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.692527] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.692549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.692567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.692615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.692648] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.692679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.694742] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.694763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.694781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.694800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.696372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.696394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.696417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.697979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.698001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.699870] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.703163] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.703254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.703285] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.703327] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.720034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.720088] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.720160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.720374] [drm:drm_mode_addfb2] [FB:77]
>[ 1242.720510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.736751] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.736798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.736870] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.755511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.755550] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.755590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.755709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.755764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.755809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.755855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.755899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.755953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.756004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.756054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.756103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.756144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.756187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.756270] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.756334] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.756396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.756446] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.756653] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.756667] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.756733] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.756757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.756783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.756812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.756842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.756885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.756908] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.756937] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.756955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.756971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.756988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.756992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.757009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.757013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.757029] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.757046] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.757068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.757091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.757115] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.757138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.757161] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.757185] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.757209] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.757233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.757259] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.757307] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.757327] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.757346] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.757383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.757407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.757431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.757454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.757478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.757501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.757526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.757551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.757576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.757661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.757696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.757734] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.757767] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.759857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.759879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.759898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.759917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.761480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.761500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.761519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.763107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.763138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.765027] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.768348] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.768413] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.768454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.768505] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.785198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.785250] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.785316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.785532] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.785756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.801894] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.801942] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.802034] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.819059] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.819097] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.819137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.819170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.819204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.819234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.819263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.819295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.819329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.819362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.819393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.819423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.819451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.819478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.819531] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.819573] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.819692] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.819738] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.819952] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.819970] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.820060] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.820088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.820113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.820139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.820159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.820181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.820207] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.820236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.820257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.820276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.820295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.820300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.820317] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.820321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.820340] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.820358] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.820377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.820394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.820416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.820434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.820453] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.820470] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.820488] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.820510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.820537] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.820628] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.820655] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.820682] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.820735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.820765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.820793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.820821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.820848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.820876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.820908] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.820938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.820971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.821000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.821027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.821062] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.821093] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.823168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.823189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.823208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.823227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.824808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.824828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.824850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.826402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.826425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.828311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.831653] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.831746] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.831779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.831821] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.848527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.848578] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.848756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.849004] [drm:drm_mode_addfb2] [FB:79]
>[ 1242.849124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.865222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.865271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.865364] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.883662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.883700] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.883740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.883774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.883809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.883839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.883868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.883899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.883934] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.883967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.883998] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.884029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.884058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.884085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.884139] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.884180] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.884221] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.884252] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.884405] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.884417] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.884474] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.884497] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.884522] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.884550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.884585] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.884655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.884686] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.884717] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.884745] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.884773] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.884799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.884808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.884834] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.884842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.884869] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.884895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.884922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.884948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.884978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.885005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.885031] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.885061] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.885089] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.885120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.885152] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.885230] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.885261] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.885291] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.885345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.885377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.885409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.885439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.885468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.885500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.885525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.885546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.885567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.885617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.885645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.885677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.885706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.887772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.887793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.887812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.887831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.889390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.889411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.889429] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.890994] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.891015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.892887] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.895512] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.895547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.895570] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.895656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.912340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.912391] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.912458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.912757] [drm:drm_mode_addfb2] [FB:77]
>[ 1242.912932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.929056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.929108] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.929184] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1242.946516] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1242.946554] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1242.946679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.946727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.946785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.946829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.946874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.946919] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.946972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.947023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.947072] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.947121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.947162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.947205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.947289] [drm:intel_power_well_disable [i915]] disabling display
>[ 1242.947354] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1242.947416] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.947465] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1242.947727] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1242.947746] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1242.947843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1242.947875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1242.947907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1242.947932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1242.947951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1242.947972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1242.947992] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1242.948011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1242.948029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1242.948046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1242.948063] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1242.948067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.948084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1242.948088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1242.948104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1242.948121] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1242.948137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1242.948153] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1242.948173] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1242.948189] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1242.948206] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1242.948222] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1242.948238] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1242.948257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.948278] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1242.948324] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1242.948341] [drm:intel_power_well_enable [i915]] enabling display
>[ 1242.948357] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1242.948388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1242.948411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1242.948435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1242.948459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1242.948482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1242.948505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1242.948531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1242.948556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1242.948626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.948662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1242.948691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1242.948727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1242.948757] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1242.950839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1242.950863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1242.950886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.950910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1242.952471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1242.952492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1242.952511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1242.954089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1242.954110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1242.955989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1242.959310] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1242.959371] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1242.959402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1242.959442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1242.976153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1242.976203] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1242.976269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1242.976482] [drm:drm_mode_addfb2] [FB:78]
>[ 1242.976704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1242.992827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1242.992876] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1242.992949] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.011506] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.011548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.011669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.011724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.011782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.011833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.011873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.011908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.011945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.011980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.012012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.012044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.012081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.012100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.012136] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.012163] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.012191] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.012212] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.012323] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.012336] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.012395] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.012421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.012448] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.012478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.012502] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.012529] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.012556] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.012619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.012651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.012679] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.012706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.012715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.012741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.012748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.012776] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.012803] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.012840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.012866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.012897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.012924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.012950] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.012976] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.013002] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.013035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.013067] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.013143] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.013174] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.013204] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.013257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.013289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.013320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.013350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.013380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.013412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.013446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.013479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.013512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.013531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.013549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.013600] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.013630] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.015695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.015716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.015735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.015754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.017312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.017332] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.017355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.018909] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.018930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.020790] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.024154] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.024223] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.024256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.024304] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.040988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.041037] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.041101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.041309] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.041432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.057677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.057723] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.057814] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.076510] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.076547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.076673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.076712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.076751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.076798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.076841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.076875] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.076912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.076945] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.076978] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.077018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.077060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.077100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.077159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.077207] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.077258] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.077294] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.077462] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.077481] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.077542] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.077573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.077636] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.077673] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.077702] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.077734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.077765] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.077795] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.077827] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.077857] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.077885] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.077892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.077919] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.077927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.077958] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.077988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.078018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.078047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.078080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.078109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.078139] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.078169] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.078191] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.078212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.078237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.078289] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.078308] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.078327] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.078361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.078381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.078406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.078432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.078458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.078483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.078512] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.078540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.078570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.078623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.078653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.078687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.078716] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.080777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.080801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.080824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.080848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.082418] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.082439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.082457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.084012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.084033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.085902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.089207] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.089286] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.089318] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.089359] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.106066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.106118] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.106184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.106392] [drm:drm_mode_addfb2] [FB:77]
>[ 1243.106522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.122745] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.122792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.122863] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.139878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.139916] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.139956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.139989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.140024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.140054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.140083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.140114] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.140149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.140182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.140214] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.140245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.140282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.140321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.140379] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.140425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.140476] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.140512] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.140809] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.140827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.140916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.140951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.140977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.141003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.141023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.141046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.141068] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.141088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.141109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.141128] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.141147] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.141152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.141171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.141175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.141194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.141212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.141230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.141248] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.141269] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.141288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.141306] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.141325] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.141342] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.141364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.141387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.141446] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.141464] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.141485] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.141525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.141551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.141604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.141634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.141662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.141691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.141723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.141753] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.141784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.141810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.141836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.141868] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.141897] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.143960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.143981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.143999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.144018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.145603] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.145624] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.145642] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.147208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.147230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.149101] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.152396] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.152484] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.152517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.152558] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.169264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.169315] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.169382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.169667] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.169876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.185983] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.186032] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.186104] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.203110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.203147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.203186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.203220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.203255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.203285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.203313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.203345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.203380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.203422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.203464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.203507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.203546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.203653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.203740] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.203811] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.203882] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.203934] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.204124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.204136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.204194] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.204216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.204239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.204264] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.204285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.204307] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.204329] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.204349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.204369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.204388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.204407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.204412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.204430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.204435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.204453] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.204472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.204490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.204508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.204529] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.204547] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.204597] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.204624] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.204651] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.204683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.204716] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.204804] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.204832] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.204864] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.204919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.204951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.204981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.205011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.205041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.205073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.205100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.205121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.205142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.205160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.205186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.205213] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.205239] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.207291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.207312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.207331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.207351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.208922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.208943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.208961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.210558] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.210594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.212456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.215835] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.215891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.215932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.215983] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.232665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.232716] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.232782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.233019] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.233143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.249365] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.249414] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.249485] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.266487] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.266524] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.266564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.266689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.266747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.266796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.266843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.266893] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.266949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.267000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.267050] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.267100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.267145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.267190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.267274] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.267359] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.267396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.267427] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.267604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.267625] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.267710] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.267734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.267758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.267783] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.267812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.267832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.267852] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.267871] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.267890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.267907] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.267924] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.267928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.267951] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.267955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.267979] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.268001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.268024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.268047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.268071] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.268094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.268118] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.268141] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.268164] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.268189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.268214] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.268265] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.268285] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.268304] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.268341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.268372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.268394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.268414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.268432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.268456] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.268483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.268509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.268535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.268559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.268631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.268708] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.268737] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.270809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.270831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.270850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.270869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.272429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.272449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.272467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.274029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.274050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.275921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.279257] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.279356] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.279389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.279431] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.296126] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.296177] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.296243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.296458] [drm:drm_mode_addfb2] [FB:77]
>[ 1243.296670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.312851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.312899] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.312971] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.329961] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.329998] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.330041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.330082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.330127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.330167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.330207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.330246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.330291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.330334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.330376] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.330418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.330457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.330497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.330554] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.330689] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.330756] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.330791] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.330949] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.330968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.331055] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.331088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.331124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.331161] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.331192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.331226] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.331259] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.331292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.331323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.331354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.331384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.331392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.331421] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.331428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.331458] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.331487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.331517] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.331545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.331600] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.331631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.331660] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.331691] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.331718] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.331752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.331787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.331879] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.331910] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.331940] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.331993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.332025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.332057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.332087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.332116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.332147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.332180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.332212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.332245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.332274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.332302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.332336] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.332367] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.334431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.334451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.334470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.334489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.336041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.336063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.336083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.337664] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.337686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.339548] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.342892] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.342986] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.343007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.343033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.359771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.359822] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.359889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.360121] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.360252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.376495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.376544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.376712] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.393697] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.393734] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.393779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.393820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.393864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.393904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.393944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.393983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.394036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.394073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.394105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.394136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.394162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.394188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.394239] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.394280] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.394327] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.394361] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.394603] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.394636] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.394778] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.394829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.394882] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.394938] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.394984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.395029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.395069] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.395097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.395124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.395149] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.395173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.395180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.395203] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.395208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.395233] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.395257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.395282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.395319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.395360] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.395384] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.395408] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.395431] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.395454] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.395482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.395512] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.395629] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.395666] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.395701] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.395771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.395813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.395850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.395891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.395931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.395971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.396015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.396066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.396099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.396129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.396158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.396181] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.396202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.398268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.398290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.398309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.398328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.399904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.399925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.399944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.401493] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.401516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.403377] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.406714] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.406811] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.406844] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.406887] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.423619] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.423670] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.423737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.423949] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.424078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.440260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.440309] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.440380] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.458825] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.458867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.458912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.458953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.458997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.459037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.459077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.459116] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.459161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.459204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.459246] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.459288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.459327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.459366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.459410] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.459436] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.459464] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.459483] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.459645] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.459666] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.459763] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.459798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.459833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.459872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.459895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.459919] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.459941] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.459962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.459982] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.460002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.460020] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.460026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.460043] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.460047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.460067] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.460085] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.460103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.460120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.460143] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.460160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.460180] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.460197] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.460215] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.460236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.460260] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.460313] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.460331] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.460351] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.460385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.460405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.460425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.460443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.460462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.460482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.460504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.460524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.460546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.460612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.460639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.460671] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.460701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.462785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.462808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.462829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.462859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.464423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.464444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.464462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.466018] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.466039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.467911] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.471273] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.471346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.471380] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.471422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.488144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.488196] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.488261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.488456] [drm:drm_mode_addfb2] [FB:77]
>[ 1243.488690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.504800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.504848] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.504920] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.523487] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.523525] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.523649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.523710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.523767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.523815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.523862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.523920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.523972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.524019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.524065] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.524112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.524154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.524196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.524272] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.524330] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.524386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.524431] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.524671] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.524693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.524780] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.524812] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.524844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.524883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.524922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.524949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.524975] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.524999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.525023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.525052] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.525081] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.525087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.525117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.525122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.525152] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.525179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.525209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.525239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.525270] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.525299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.525329] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.525359] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.525389] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.525421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.525453] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.525515] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.525541] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.525628] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.525693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.525730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.525764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.525797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.525829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.525864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.525914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.525947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.525980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.526003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.526022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.526045] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.526066] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.528155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.528178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.528199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.528219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.529780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.529802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.529826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.531379] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.531400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.533269] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.536621] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.536707] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.536748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.536799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.553491] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.553546] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.553726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.553958] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.554077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.570199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.570251] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.570326] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.587499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.587538] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.587669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.587722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.587779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.587826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.587874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.587924] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.587980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.588033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.588084] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.588134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.588180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.588226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.588309] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.588353] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.588395] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.588427] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.588632] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.588653] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.588730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.588753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.588785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.588808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.588826] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.588846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.588866] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.588885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.588904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.588921] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.588937] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.588941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.588957] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.588961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.588978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.588994] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.589011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.589027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.589047] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.589063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.589080] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.589096] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.589112] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.589131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.589152] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.589211] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.589228] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.589244] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.589276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.589295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.589332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.589351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.589369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.589396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.589416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.589435] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.589453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.589469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.589491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.589516] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.589540] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.591655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.591680] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.591703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.591727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.593299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.593320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.593339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.594892] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.594913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.596785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.600128] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.600220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.600253] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.600296] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.616995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.617046] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.617113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.617307] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.617438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.633694] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.633740] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.633808] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.650798] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.650836] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.650876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.650909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.650945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.650975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.651005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.651037] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.651071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.651104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.651135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.651167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.651194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.651222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.651275] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.651316] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.651358] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.651389] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.651652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.651679] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.651812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.651861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.651910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.651963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.652005] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.652039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.652070] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.652098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.652127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.652153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.652187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.652196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.652230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.652237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.652273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.652309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.652342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.652377] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.652414] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.652449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.652484] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.652520] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.652563] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.652650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.652691] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.652798] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.652833] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.652869] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.652931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.652968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.653005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.653040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.653066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.653089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.653116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.653140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.653163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.653192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.653221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.653251] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.653281] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.655331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.655352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.655371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.655390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.656968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.656987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.657005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.658582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.658603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.660475] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.663803] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.663853] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.663877] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.663908] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.680647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.680697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.680761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.681000] [drm:drm_mode_addfb2] [FB:77]
>[ 1243.681133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.697345] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.697394] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.697467] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.714473] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.714516] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.714642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.714697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.714755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.714805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.714839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.714871] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.714909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.714944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.714975] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.715008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.715046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.715065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.715100] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.715127] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.715155] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.715175] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.715285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.715298] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.715354] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.715380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.715407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.715436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.715461] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.715487] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.715514] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.715546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.715611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.715642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.715670] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.715679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.715706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.715713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.715741] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.715769] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.715795] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.715821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.715852] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.715879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.715906] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.715933] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.715960] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.715992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.716025] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.716101] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.716133] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.716164] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.716217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.716249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.716280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.716311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.716341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.716372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.716406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.716437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.716459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.716477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.716496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.716519] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.716542] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.718640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.718665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.718688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.718712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.720279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.720301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.720320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.721886] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.721907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.723776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.727121] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.727220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.727240] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.727270] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.743988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.744039] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.744105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.744314] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.744442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.760665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.760713] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.760785] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.777772] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.777810] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.777850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.777884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.777920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.777951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.777979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.778010] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.778045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.778077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.778108] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.778139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.778167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.778194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.778248] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.778288] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.778330] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.778361] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.778564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.778585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.778683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.778718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.778754] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.778792] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.778823] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.778857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.778881] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.778902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.778921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.778941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.778958] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.778965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.778982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.778986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.779006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.779023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.779049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.779075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.779101] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.779127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.779153] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.779179] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.779204] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.779232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.779261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.779330] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.779352] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.779370] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.779408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.779430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.779451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.779470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.779489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.779510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.779531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.779588] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.779618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.779644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.779672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.779705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.779734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.781805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.781826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.781844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.781863] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.783435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.783459] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.783487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.785071] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.785095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.786985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.790323] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.790422] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.790462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.790514] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.807195] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.807246] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.807313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.807589] [drm:drm_mode_addfb2] [FB:79]
>[ 1243.807793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.823873] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.823922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.823993] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.842478] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.842515] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.842644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.842698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.842756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.842805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.842859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.842908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.842961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.843011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.843059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.843108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.843152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.843196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.843277] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.843343] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.843399] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.843447] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.843721] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.843748] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.843870] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.843902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.843927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.843951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.843969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.843990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.844013] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.844036] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.844060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.844081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.844104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.844109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.844132] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.844136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.844159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.844180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.844204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.844227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.844250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.844273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.844297] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.844320] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.844344] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.844368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.844394] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.844441] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.844461] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.844481] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.844517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.844590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.844623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.844658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.844690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.844724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.844760] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.844794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.844828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.844858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.844888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.844924] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.844958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.847032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.847056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.847078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.847102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.848678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.848699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.848721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.850279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.850301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.852163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.855443] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.855493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.855530] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.855651] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.872276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.872327] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.872394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.872712] [drm:drm_mode_addfb2] [FB:77]
>[ 1243.872865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.888953] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.889001] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.889072] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.907470] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.907507] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.907546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.907671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.907730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.907781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.907829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.907878] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.907935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.907988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.908039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.908089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.908135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.908180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.908266] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.908327] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.908368] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.908401] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.908594] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.908625] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.908701] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.908727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.908761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.908788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.908811] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.908835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.908859] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.908902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.908925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.908954] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.908972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.908976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.908993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.908997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.909014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.909031] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.909047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.909063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.909083] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.909100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.909117] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.909134] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.909150] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.909170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.909191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.909248] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.909265] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.909282] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.909313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.909332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.909349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.909366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.909383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.909400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.909420] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.909438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.909456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.909473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.909489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.909509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.909528] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.911641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.911664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.911686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.911711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.913285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.913306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.913324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.914876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.914897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.916767] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.920083] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.920148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.920181] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.920232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1243.936930] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.936983] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.937055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.937269] [drm:drm_mode_addfb2] [FB:78]
>[ 1243.937388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.953605] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1243.953654] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1243.953725] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1243.970743] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1243.970781] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1243.970820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.970854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.970889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.970920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.970949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.970981] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1243.971016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.971048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.971089] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.971131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.971171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.971210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.971268] [drm:intel_power_well_disable [i915]] disabling display
>[ 1243.971315] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1243.971365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1243.971402] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1243.971666] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1243.971702] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1243.971830] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1243.971876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1243.971924] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1243.971974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1243.972010] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1243.972042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1243.972072] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1243.972099] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1243.972127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1243.972152] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1243.972176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1243.972182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.972206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1243.972212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1243.972236] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1243.972259] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1243.972295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1243.972332] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1243.972363] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1243.972386] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1243.972411] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1243.972434] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1243.972458] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1243.972486] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1243.972518] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1243.972673] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1243.972717] [drm:intel_power_well_enable [i915]] enabling display
>[ 1243.972751] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1243.972811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1243.972846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1243.972880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1243.972913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1243.972947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1243.972980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1243.973006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1243.973028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1243.973056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1243.973085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1243.973112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1243.973142] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1243.973171] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1243.975243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1243.975265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1243.975283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.975303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1243.976879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1243.976900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1243.976919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1243.978508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1243.978578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1243.980424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1243.983728] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1243.983808] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1243.983840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1243.983887] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.000588] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.000641] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.000713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.000932] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.001065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.017262] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.017310] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.017381] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.034393] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.034431] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.034471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.034504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.034626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.034676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.034724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.034774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.034832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.034883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.034918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.034950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.034980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.035007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.035055] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.035083] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.035110] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.035131] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.035243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.035256] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.035311] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.035331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.035354] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.035379] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.035403] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.035430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.035457] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.035482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.035511] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.035576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.035606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.035615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.035642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.035650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.035678] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.035705] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.035732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.035758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.035788] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.035814] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.035842] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.035868] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.035895] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.035925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.035958] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.036034] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.036062] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.036093] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.036146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.036177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.036207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.036238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.036267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.036298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.036332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.036366] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.036399] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.036428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.036452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.036477] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.036497] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.038582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.038603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.038621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.038640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.040211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.040236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.040262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.041814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.041836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.043713] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.047090] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.047146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.047186] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.047211] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.063917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.063969] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.064040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.064257] [drm:drm_mode_addfb2] [FB:77]
>[ 1244.064389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.080605] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.080654] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.080726] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.097714] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.097751] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.097791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.097825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.097861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.097892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.097921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.097953] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.097988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.098021] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.098053] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.098084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.098112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.098139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.098193] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.098234] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.098277] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.098295] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.098431] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.098444] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.098501] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.098536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.098609] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.098649] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.098681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.098717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.098751] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.098784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.098817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.098849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.098879] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.098888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.098916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.098923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.098952] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.098983] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.099014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.099043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.099077] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.099106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.099136] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.099165] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.099194] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.099227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.099261] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.099348] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.099379] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.099410] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.099461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.099493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.099524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.099579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.099610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.099643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.099678] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.099711] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.099744] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.099774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.099805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.099841] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.099874] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.101964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.101986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.102005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.102024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.103636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.103657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.103675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.105243] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.105268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.107139] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.110459] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.110522] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.110621] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.110666] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.127307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.127358] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.127428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.127856] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.127988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.143975] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.144028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.144108] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.162516] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.162588] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.162629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.162663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.162698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.162729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.162758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.162790] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.162832] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.162875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.162918] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.162960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.162999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.163038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.163096] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.163143] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.163193] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.163229] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.163442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.163461] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.163648] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.163699] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.163752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.163810] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.163854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.163908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.163959] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.164004] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.164054] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.164100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.164146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.164157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.164202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.164213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.164259] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.164304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.164350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.164395] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.164442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.164472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.164501] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.164577] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.164618] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.164683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.164739] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.164817] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.164849] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.164880] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.164934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.164965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.164996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.165017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.165036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.165056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.165079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.165100] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.165121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.165139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.165158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.165181] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.165202] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.167252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.167273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.167292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.167311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.168883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.168903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.168922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.170515] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.170552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.172421] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.175729] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.175805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.175837] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.175880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.192582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.192633] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.192700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.192913] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.193046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.209285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.209352] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.209453] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.226407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.226444] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.226485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.226519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.226640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.226686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.226736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.226781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.226838] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.226889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.226940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.226972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.226998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.227026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.227080] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.227122] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.227163] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.227196] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.227329] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.227343] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.227407] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.227431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.227457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.227486] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.227511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.227583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.227618] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.227653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.227686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.227718] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.227749] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.227758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.227787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.227795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.227825] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.227854] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.227885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.227915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.227946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.227975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.228005] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.228033] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.228061] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.228093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.228129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.228206] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.228247] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.228278] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.228330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.228362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.228392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.228422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.228452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.228484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.228518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.228576] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.228611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.228641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.228671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.228707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.228739] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.230829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.230851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.230870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.230890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.232454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.232475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.232497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.234099] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.234121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.236007] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.239287] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.239324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.239343] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.239368] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.256117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.256169] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.256240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.256455] [drm:drm_mode_addfb2] [FB:77]
>[ 1244.256672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.272832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.272881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.272956] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.291924] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.291963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.292003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.292038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.292073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.292104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.292133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.292165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.292201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.292233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.292274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.292316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.292356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.292395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.292453] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.292500] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.292639] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.292687] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.292908] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.292936] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.293056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.293090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.293131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.293177] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.293221] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.293246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.293269] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.293290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.293310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.293328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.293346] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.293351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.293368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.293373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.293391] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.293410] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.293435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.293460] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.293486] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.293511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.293571] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.293601] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.293629] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.293662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.293695] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.293787] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.293818] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.293849] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.293902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.293935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.293966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.293997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.294027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.294055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.294077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.294105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.294133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.294158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.294184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.294211] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.294238] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.296287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.296311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.296334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.296358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.297923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.297944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.297962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.299519] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.299553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.301426] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.304771] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.304855] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.304884] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.304921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.321639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.321690] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.321756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.321970] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.322098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.338297] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.338343] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.338412] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.355429] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.355466] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.355506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.355624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.355682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.355726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.355772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.355825] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.355880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.355931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.355981] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.356031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.356071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.356115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.356199] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.356264] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.356326] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.356375] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.356591] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.356611] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.356690] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.356716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.356743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.356781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.356802] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.356824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.356845] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.356864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.356883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.356906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.356929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.356933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.356956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.356960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.356984] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.357005] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.357028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.357051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.357075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.357098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.357131] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.357154] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.357184] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.357206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.357228] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.357287] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.357304] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.357320] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.357353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.357372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.357390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.357407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.357423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.357441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.357466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.357491] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.357516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.357586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.357617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.357650] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.357679] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.359758] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.359781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.359800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.359819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.361391] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.361411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.361430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.362982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.363004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.364875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.368227] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.368311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.368344] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.368386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.385077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.385125] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.385190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.385440] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.385674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.401760] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.401809] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.401882] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.420604] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.420642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.420680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.420714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.420749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.420779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.420808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.420840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.420875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.420907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.420938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.420969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.420997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.421024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.421077] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.421119] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.421160] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.421191] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.421401] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.421420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.421514] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.421625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.421684] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.421740] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.421785] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.421836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.421882] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.421928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.421973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.422014] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.422056] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.422069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.422113] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.422125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.422169] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.422211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.422253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.422293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.422344] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.422390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.422436] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.422481] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.422526] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.422676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.422731] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.422881] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.422921] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.422958] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.423030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.423074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.423115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.423150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.423176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.423204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.423233] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.423259] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.423294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.423329] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.423362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.423399] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.423433] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.425493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.425532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.425551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.425573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.427147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.427168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.427187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.428749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.428770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.430632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.433949] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.434017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.434055] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.434081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.450795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.450846] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.450912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.451119] [drm:drm_mode_addfb2] [FB:77]
>[ 1244.451251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.467469] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.467518] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.467694] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.484691] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.484729] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.484768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.484802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.484838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.484868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.484897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.484929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.484964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.484997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.485028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.485060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.485088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.485115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.485170] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.485195] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.485220] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.485239] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.485374] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.485386] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.485458] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.485484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.485514] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.485588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.485617] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.485651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.485682] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.485711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.485740] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.485771] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.486042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.486048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.486068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.486073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.486093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.486114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.486132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.486150] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.486172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.486191] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.486209] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.486227] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.486245] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.486267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.486290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.486353] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.486372] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.486390] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.486425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.486445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.486464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.486482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.486500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.486555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.486587] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.486618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.486649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.486675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.486702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.486735] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.486763] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.489013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.489034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.489053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.489072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.490727] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.490747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.490765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.492318] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.492341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.494212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.497473] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.497587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.497624] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.497670] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.514332] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.514384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.514450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.514778] [drm:drm_mode_addfb2] [FB:78]
>[ 1244.514918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.531032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.531081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.531172] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.548158] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.548195] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.548235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.548275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.548319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.548359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.548399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.548439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.548483] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.548597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.548652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.548706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.548750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.548793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.548867] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.548910] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.548954] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.548985] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.549264] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1244.549291] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1244.549415] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.549453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.549478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.549512] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.549571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.549603] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.549637] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1244.549666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1244.549695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.549726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.549756] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.549763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.549792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.549799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.549830] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.549855] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.549875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.549892] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1244.549915] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.549933] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.549953] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1244.549970] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1244.549989] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1244.550010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.550033] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1244.550085] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.550104] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.550122] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.550156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.550177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.550196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.550215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.550234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.550253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.550275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.550296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.550316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.550341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.550366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.550393] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1244.550419] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.552465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.552486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.552555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.552588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.554151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.554171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.554189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.555756] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.555779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.557643] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.560788] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1244.560859] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.560878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1244.560904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.577656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.577707] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.577774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.577987] [drm:drm_mode_addfb2] [FB:79]
>[ 1244.578100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.594328] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1244.594380] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1244.594457] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1244.612604] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1244.612642] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1244.612682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.612716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.612751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.612782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.612811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.612843] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.612877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.612909] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.612940] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.612972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.613000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.613027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.613081] [drm:intel_power_well_disable [i915]] disabling display
>[ 1244.613122] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1244.613163] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1244.613194] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1244.615440] [IGT] kms_flip: exiting, ret=0
>[ 1244.635380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1244.635415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1244.635451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1244.635491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1244.635574] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1244.635608] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1244.635640] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1244.635670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1244.635700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1244.635727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1244.635754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1244.635761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.635787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1244.635792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.635819] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1244.635845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1244.635871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1244.635896] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1244.635928] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1244.635954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1244.635979] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1244.636005] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1244.636030] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1244.636062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1244.636097] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1244.636217] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1244.636235] [drm:intel_power_well_enable [i915]] enabling display
>[ 1244.636251] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1244.636284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1244.636302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1244.636319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1244.636335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1244.636350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1244.636367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1244.636386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1244.636404] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1244.636421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.636437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1244.636452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1244.636472] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1244.636502] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1244.638612] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1244.638633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1244.638650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.638669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1244.640251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1244.640269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1244.640286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1244.641855] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1244.641874] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1244.643759] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1244.647227] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1244.647292] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1244.647330] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1244.647383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1244.647467] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1244.647492] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1244.664083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1244.664132] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1244.664201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1244.664439] Console: switching to colour frame buffer device 240x75
>[ 1244.771631] Console: switching to colour dummy device 80x25
>[ 1244.771752] [IGT] kms_flip: executing
>[ 1244.783406] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1244.783452] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1244.784582] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1244.784616] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1244.786603] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1244.786614] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1244.788592] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1244.788634] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1244.790594] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1244.790605] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1244.790613] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1244.790643] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1244.790685] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1244.791793] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1244.792736] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1244.792757] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1244.792776] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1244.792794] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1244.793808] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1244.793828] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1244.794936] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1244.794939] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1244.795039] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1244.795042] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1244.795047] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1244.795049] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1244.795054] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1244.795056] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1244.795067] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1244.795070] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.795073] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.795076] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.795079] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1244.795082] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1244.795085] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1244.795088] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1244.795091] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.795094] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.795097] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1244.795100] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1244.795103] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1244.795106] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1244.795109] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1244.795112] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1244.795115] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1244.795118] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1244.795121] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1244.795124] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1244.795126] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1244.795129] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1244.795132] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1244.795135] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1244.795138] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1244.795141] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1244.795144] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1244.795147] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1244.795150] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1244.795153] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1244.795156] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1244.795193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1244.795216] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1244.796562] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1244.796583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1244.798604] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1244.798615] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1244.800590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1244.800628] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1244.802594] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1244.802605] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1244.802612] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1244.803010] [IGT] kms_flip: starting subtest 2x-flip-vs-expired-vblank
>[ 1244.806066] [IGT] kms_flip: exiting, ret=77
>[ 1244.831027] Console: switching to colour frame buffer device 240x75
>[ 1244.938261] Console: switching to colour dummy device 80x25
>[ 1244.938379] [IGT] kms_flip: executing
>[ 1244.949379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1244.949431] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1244.950598] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1244.950641] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1244.952583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1244.952594] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1244.954597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1244.954635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1244.956597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1244.956608] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1244.956616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1244.956646] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1244.956688] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1244.957777] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1244.958695] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1244.958716] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1244.958735] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1244.958752] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1244.959768] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1244.959787] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1244.960903] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1244.960906] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1244.961007] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1244.961010] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1244.961015] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1244.961017] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1244.961023] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1244.961025] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1244.961034] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1244.961038] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1244.961041] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.961044] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.961047] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1244.961050] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1244.961053] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1244.961056] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1244.961059] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.961062] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1244.961065] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1244.961068] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1244.961070] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1244.961073] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1244.961076] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1244.961079] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1244.961082] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1244.961085] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1244.961088] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1244.961091] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1244.961094] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1244.961097] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1244.961100] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1244.961103] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1244.961106] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1244.961109] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1244.961112] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1244.961115] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1244.961118] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1244.961121] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1244.961124] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1244.961160] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1244.961183] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1244.962542] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1244.962564] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1244.964608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1244.964618] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1244.966583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1244.966622] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1244.968583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1244.968593] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1244.968601] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1244.968994] [IGT] kms_flip: starting subtest plain-flip-fb-recreate
>[ 1244.969869] [drm:drm_mode_addfb2] [FB:77]
>[ 1244.969896] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.022961] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.023024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.031039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1245.031088] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1245.031165] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1245.049428] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1245.049472] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1245.049590] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1245.049649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.049702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.049758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.049792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.049822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.049854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.049891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.049924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.049957] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.049988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.050018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.050046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.050101] [drm:intel_power_well_disable [i915]] disabling display
>[ 1245.050142] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1245.050186] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.050220] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1245.050309] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1245.050437] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1245.050567] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1245.050586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1245.050678] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1245.050709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1245.050741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1245.050771] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1245.050790] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1245.050810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1245.050830] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1245.050849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1245.050866] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1245.050883] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1245.050899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1245.050903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.050919] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1245.050923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1245.050940] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1245.050956] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1245.050972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1245.050988] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1245.051007] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1245.051023] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1245.051039] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1245.051056] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1245.051071] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1245.051091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1245.051112] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1245.054492] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1245.054536] [drm:intel_power_well_enable [i915]] enabling display
>[ 1245.054554] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1245.054597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1245.054618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1245.054641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1245.054664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1245.054688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1245.054711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1245.054736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1245.054761] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1245.054786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.054809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1245.054832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1245.054857] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1245.054880] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1245.056932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1245.056952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1245.056971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.056990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1245.058595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1245.058615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1245.058632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1245.060185] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1245.060206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1245.062075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1245.065390] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1245.065458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1245.065491] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1245.065619] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1245.065742] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1245.065772] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1245.082249] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1245.082300] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1245.082372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1245.382521] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.399172] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.415864] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.432542] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.449218] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.465899] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.482579] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.499259] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.515936] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.532618] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.549297] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.565979] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.582657] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.599337] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.616016] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.632697] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.649376] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.666056] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.682735] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.699416] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.716094] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.732774] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.749483] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.766136] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.782814] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.799528] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.816175] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.832855] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.849535] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.866215] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.882895] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.899575] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.916253] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.932934] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.949613] [drm:drm_mode_addfb2] [FB:77]
>[ 1245.966294] [drm:drm_mode_addfb2] [FB:79]
>[ 1245.982974] [drm:drm_mode_addfb2] [FB:78]
>[ 1245.999655] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.016337] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.033014] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.049692] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.066373] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.083053] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.099734] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.116412] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.133092] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.149772] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.166481] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.183133] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.199812] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.216522] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.233173] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.249851] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.266531] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.283212] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.299890] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.316571] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.333251] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.349930] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.366611] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.383290] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.399971] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.416650] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.433330] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.450009] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.466698] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.483374] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.500051] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.516730] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.533440] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.550090] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.566771] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.583479] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.600130] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.616809] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.633491] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.650169] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.666850] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.683530] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.700210] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.716888] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.733569] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.750248] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.766930] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.783609] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.800290] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.816968] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.833648] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.850328] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.867008] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.883688] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.900369] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.917046] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.933728] [drm:drm_mode_addfb2] [FB:78]
>[ 1246.950436] [drm:drm_mode_addfb2] [FB:77]
>[ 1246.967088] [drm:drm_mode_addfb2] [FB:79]
>[ 1246.983767] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.000478] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.017128] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.033807] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.050487] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.067167] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.083847] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.100527] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.117206] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.133887] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.150566] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.167246] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.183925] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.200606] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.217286] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.233965] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.250643] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.267325] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.284005] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.300685] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.317362] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.334045] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.350724] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.367446] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.384085] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.400764] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.417472] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.434123] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.450803] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.467483] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.484164] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.500842] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.517522] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.534202] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.550883] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.567563] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.584243] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.600923] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.617602] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.634282] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.650960] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.667642] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.684321] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.701001] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.717680] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.734390] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.751040] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.767721] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.784428] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.801079] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.817761] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.834464] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.851119] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.867800] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.884480] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.901161] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.917839] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.934520] [drm:drm_mode_addfb2] [FB:78]
>[ 1247.951199] [drm:drm_mode_addfb2] [FB:77]
>[ 1247.967880] [drm:drm_mode_addfb2] [FB:79]
>[ 1247.984559] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.001240] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.017921] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.034598] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.051273] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.067961] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.084640] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.101321] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.118019] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.134695] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.151418] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.168058] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.184739] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.201461] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.218099] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.234777] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.251461] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.268138] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.284817] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.301497] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.318177] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.334857] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.351692] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.368216] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.384896] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.401577] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.418256] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.434936] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.451615] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.468296] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.484975] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.501656] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.518372] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.535014] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.551696] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.568416] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.585053] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.601736] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.618456] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.635092] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.651775] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.668456] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.685102] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.701776] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.718455] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.735133] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.751819] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.768495] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.785173] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.801857] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.818536] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.835192] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.851896] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.868576] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.885274] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.901932] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.918615] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.935349] [drm:drm_mode_addfb2] [FB:78]
>[ 1248.951974] [drm:drm_mode_addfb2] [FB:77]
>[ 1248.968654] [drm:drm_mode_addfb2] [FB:79]
>[ 1248.985373] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.002011] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.018695] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.035401] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.052053] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.068733] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.085414] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.102090] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.118772] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.135453] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.152133] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.168813] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.185508] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.202170] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.218852] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.235533] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.252213] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.268893] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.285572] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.302252] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.318966] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.335643] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.352364] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.369005] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.385683] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.402399] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.419047] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.435722] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.452406] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.469083] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.485762] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.502442] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.519123] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.535802] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.552483] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.569164] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.585841] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.602520] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.619203] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.635881] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.652562] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.669243] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.685922] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.702601] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.719310] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.735962] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.752642] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.769362] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.785998] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.802680] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.819398] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.836041] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.852720] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.869402] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.886080] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.902758] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.919439] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.936118] [drm:drm_mode_addfb2] [FB:78]
>[ 1249.952800] [drm:drm_mode_addfb2] [FB:77]
>[ 1249.969479] [drm:drm_mode_addfb2] [FB:79]
>[ 1249.986160] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.002837] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.019520] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.036200] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.052879] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.069560] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.086238] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.102883] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.119565] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.136245] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.152926] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.169605] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.186312] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.202964] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.219646] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.236352] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.253007] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.269684] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.286366] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.303042] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.319723] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.336403] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.353085] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.369763] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.386443] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.403121] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.419806] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.436484] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.453164] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.469844] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.486524] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.503202] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.519916] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.536594] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.553312] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.569955] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.586635] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.603350] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.619995] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.636674] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.653356] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.670035] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.686714] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.703393] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.720075] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.736755] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.753434] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.770115] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.786793] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.803470] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.820154] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.836833] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.853512] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.870193] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.886873] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.903551] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.920260] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.936913] [drm:drm_mode_addfb2] [FB:78]
>[ 1250.953591] [drm:drm_mode_addfb2] [FB:77]
>[ 1250.970311] [drm:drm_mode_addfb2] [FB:79]
>[ 1250.986953] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.003630] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.020351] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.036991] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.053672] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.070352] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.087032] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.103709] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.120390] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.137072] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.153750] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.170430] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.187111] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.203788] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.220471] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.237151] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.253829] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.270510] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.287191] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.303834] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.320517] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.337196] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.353878] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.370557] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.387264] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.403913] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.420600] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.437304] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.453958] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.470636] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.487317] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.503993] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.520705] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.537354] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.554036] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.570714] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.587394] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.604073] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.620755] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.637435] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.654116] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.670795] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.687475] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.704153] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.720867] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.737549] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.754267] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.770909] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.787587] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.804302] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.820947] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.837626] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.854309] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.870986] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.887666] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.904345] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.921026] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.937706] [drm:drm_mode_addfb2] [FB:78]
>[ 1251.954386] [drm:drm_mode_addfb2] [FB:77]
>[ 1251.971064] [drm:drm_mode_addfb2] [FB:79]
>[ 1251.987745] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.004422] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.021105] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.037785] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.054465] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.071147] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.087791] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.104469] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.121152] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.137833] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.154512] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.171218] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.187872] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.204549] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.221259] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.237914] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.254592] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.271272] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.287951] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.304629] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.321312] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.337991] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.354671] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.371350] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.388030] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.404708] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.421392] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.438069] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.454751] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.471429] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.488109] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.504787] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.521469] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.538149] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.554829] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.571510] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.588219] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.604866] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.621548] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.638255] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.654909] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.671587] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.688269] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.704946] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.721627] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.738307] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.754990] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.771667] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.788347] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.805025] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.821707] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.838387] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.855067] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.871746] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.888427] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.905104] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.921787] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.938466] [drm:drm_mode_addfb2] [FB:78]
>[ 1252.955165] [drm:drm_mode_addfb2] [FB:77]
>[ 1252.971825] [drm:drm_mode_addfb2] [FB:79]
>[ 1252.988506] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.005212] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.021865] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.038546] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.055227] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.071905] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.088585] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.105262] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.121946] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.138625] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.155305] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.171984] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.188665] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.205341] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.222024] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.238705] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.255385] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.272063] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.288743] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.305421] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.322103] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.338814] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.355495] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.372215] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.388854] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.405532] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.422251] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.438896] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.455575] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.472255] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.488934] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.505613] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.522294] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.538973] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.555653] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.572334] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.589013] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.605691] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.622373] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.639053] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.655733] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.672414] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.689092] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.705772] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.722454] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.739167] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.755812] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.772493] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.789212] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.805849] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.822532] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.839246] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.855892] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.872572] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.889252] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.905930] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.922612] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.939291] [drm:drm_mode_addfb2] [FB:78]
>[ 1253.955971] [drm:drm_mode_addfb2] [FB:77]
>[ 1253.972644] [drm:drm_mode_addfb2] [FB:79]
>[ 1253.989330] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.006010] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.022691] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.039370] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.056050] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.072728] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.089409] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.106084] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.122769] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.139450] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.156168] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.172806] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.189489] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.206203] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.222849] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.239528] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.256211] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.272885] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.289569] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.306245] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.322929] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.339607] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.356288] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.372966] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.389648] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.406325] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.423007] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.439691] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.456367] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.473017] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.489696] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.506371] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.523055] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.539767] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.556445] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.573168] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.589800] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.606468] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.623179] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.639832] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.656511] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.673188] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.689871] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.706546] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.723231] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.739910] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.756589] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.773270] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.789951] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.806628] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.823311] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.839990] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.856669] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.873349] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.890029] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.906724] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.923402] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.940119] [drm:drm_mode_addfb2] [FB:78]
>[ 1254.956760] [drm:drm_mode_addfb2] [FB:77]
>[ 1254.973439] [drm:drm_mode_addfb2] [FB:79]
>[ 1254.990158] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.006800] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.023480] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.040192] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.056839] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.073520] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.090199] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.106879] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.123558] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.140239] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.156919] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.173597] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.190278] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.206958] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.223639] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.240319] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.256997] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.273678] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.290356] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.307040] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.323718] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.340396] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.357116] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.373757] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.390552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.407070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1255.407148] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1255.407222] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1255.425812] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1255.425856] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1255.425889] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1255.425927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.425961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.425997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.426028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.426057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.426164] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.426219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.426272] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.426320] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.426372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.426420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.426466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.426551] [drm:intel_power_well_disable [i915]] disabling display
>[ 1255.426597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1255.426642] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1255.426678] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1255.426974] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.427005] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.456234] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1255.456339] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.456415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1255.456487] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1255.456498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1255.456556] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1255.456578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1255.456603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1255.456630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1255.456653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1255.456678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1255.456702] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1255.456725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1255.456749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1255.456772] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1255.456795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1255.456800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.456823] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1255.456827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1255.456851] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1255.456874] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1255.456897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1255.456919] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1255.456943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1255.456967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1255.456990] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1255.457014] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1255.457037] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1255.457122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1255.457161] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1255.460612] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1255.460634] [drm:intel_power_well_enable [i915]] enabling display
>[ 1255.460654] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1255.460693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1255.460718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1255.460743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1255.460768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1255.460792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1255.460816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1255.460843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1255.460869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1255.460895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.460919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1255.460942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1255.460968] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1255.460993] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1255.463105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1255.463127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1255.463149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.463173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1255.464751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1255.464773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1255.464792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1255.466351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1255.466375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1255.468254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1255.471601] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1255.471689] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1255.471722] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1255.471775] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1255.488465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1255.488516] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1255.488582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1255.788696] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.805384] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.822115] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.838752] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.855432] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.872111] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.888792] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.905471] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.922152] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.938829] [drm:drm_mode_addfb2] [FB:79]
>[ 1255.955511] [drm:drm_mode_addfb2] [FB:77]
>[ 1255.972190] [drm:drm_mode_addfb2] [FB:78]
>[ 1255.988872] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.005551] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.022227] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.038961] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.055591] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.072273] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.088951] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.105631] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.122310] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.138989] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.155700] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.172381] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.189100] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.205739] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.222421] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.239138] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.255780] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.272459] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.289141] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.305822] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.322500] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.339180] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.355860] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.372539] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.389219] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.405899] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.422579] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.439258] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.455940] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.472619] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.489299] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.505978] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.522659] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.539337] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.556051] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.572697] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.589378] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.606095] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.622739] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.639418] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.656102] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.672777] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.689457] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.706137] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.722817] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.739497] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.756176] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.772856] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.789536] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.806216] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.822896] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.839575] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.856255] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.872935] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.889616] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.906294] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.922975] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.939654] [drm:drm_mode_addfb2] [FB:79]
>[ 1256.956334] [drm:drm_mode_addfb2] [FB:77]
>[ 1256.973054] [drm:drm_mode_addfb2] [FB:78]
>[ 1256.989694] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.006375] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.023093] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.039734] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.056413] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.073097] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.089773] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.106452] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.123132] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.139812] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.156493] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.173172] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.189851] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.206531] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.223213] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.239892] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.256573] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.273251] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.289933] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.306614] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.323292] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.340002] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.356573] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.373321] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.390028] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.406676] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.423356] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.440060] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.456716] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.473395] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.490210] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.506755] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.523434] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.540116] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.556794] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.573475] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.590155] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.606833] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.623514] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.640195] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.656875] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.673553] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.690368] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.706914] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.723610] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.740300] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.757049] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.773649] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.790329] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.807048] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.823687] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.840367] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.857082] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.873726] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.890406] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.907086] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.923769] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.940446] [drm:drm_mode_addfb2] [FB:79]
>[ 1257.957127] [drm:drm_mode_addfb2] [FB:77]
>[ 1257.973806] [drm:drm_mode_addfb2] [FB:78]
>[ 1257.990488] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.007167] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.023848] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.040526] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.057206] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.073885] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.090568] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.107248] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.123927] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.140607] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.157286] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.174006] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.190646] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.207326] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.224049] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.240686] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.257363] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.274048] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.290726] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.307405] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.324085] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.340764] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.357442] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.374152] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.390815] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.407477] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.424168] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.440846] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.457536] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.474205] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.490886] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.507564] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.524245] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.540956] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.557604] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.574283] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.591007] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.607643] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.624324] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.641042] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.657682] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.674363] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.691043] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.707719] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.724402] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.741080] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.757761] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.774441] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.791122] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.807802] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.824481] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.841160] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.857840] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.874522] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.891201] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.907882] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.924562] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.941241] [drm:drm_mode_addfb2] [FB:79]
>[ 1258.957960] [drm:drm_mode_addfb2] [FB:77]
>[ 1258.974601] [drm:drm_mode_addfb2] [FB:78]
>[ 1258.991281] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.008001] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.024641] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.041320] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.058003] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.074680] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.091359] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.108039] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.124718] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.141398] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.158079] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.174758] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.191448] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.208119] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.224797] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.241476] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.258157] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.274837] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.291515] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.308199] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.324877] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.341557] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.358236] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.374958] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.391595] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.408275] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.424997] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.441636] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.458316] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.474999] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.491676] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.508356] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.525036] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.541715] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.558395] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.575077] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.591756] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.608433] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.625107] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.641780] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.658459] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.675140] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.691820] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.708498] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.725178] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.741859] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.758539] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.775219] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.791927] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.808580] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.825258] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.841962] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.858618] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.875298] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.891977] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.908657] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.925337] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.942017] [drm:drm_mode_addfb2] [FB:79]
>[ 1259.958697] [drm:drm_mode_addfb2] [FB:77]
>[ 1259.975382] [drm:drm_mode_addfb2] [FB:78]
>[ 1259.992059] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.008745] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.025418] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.042097] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.058776] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.075461] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.092149] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.108816] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.125497] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.142177] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.158886] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.175537] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.192215] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.208933] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.225575] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.242255] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.258936] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.275617] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.292294] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.308975] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.325654] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.342335] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.359013] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.375695] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.392374] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.409051] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.425733] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.442414] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.459094] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.475774] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.492453] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.509134] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.525813] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.542493] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.559173] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.575884] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.592532] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.609212] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.625918] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.642572] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.659252] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.675934] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.692609] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.709292] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.725972] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.742651] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.759331] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.776012] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.792691] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.809369] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.826052] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.842730] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.859411] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.876092] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.892770] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.909449] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.926131] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.942810] [drm:drm_mode_addfb2] [FB:79]
>[ 1260.959491] [drm:drm_mode_addfb2] [FB:77]
>[ 1260.976171] [drm:drm_mode_addfb2] [FB:78]
>[ 1260.992878] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.009524] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.026211] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.042914] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.059570] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.076250] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.092929] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.109609] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.126289] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.142967] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.159648] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.176329] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.193008] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.209687] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.226369] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.243049] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.259729] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.276405] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.293088] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.309767] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.326447] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.343131] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.359834] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.376487] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.393168] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.409866] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.426526] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.443206] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.459887] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.476567] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.493246] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.509926] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.526605] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.543285] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.559965] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.576646] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.593326] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.610006] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.626685] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.643364] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.660044] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.676724] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.693404] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.710085] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.726764] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.743444] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.760125] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.776834] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.793485] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.810165] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.826871] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.843523] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.860203] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.876884] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.893563] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.910242] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.926922] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.943602] [drm:drm_mode_addfb2] [FB:79]
>[ 1261.960283] [drm:drm_mode_addfb2] [FB:77]
>[ 1261.976963] [drm:drm_mode_addfb2] [FB:78]
>[ 1261.993642] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.010337] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.027005] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.043682] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.060363] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.077042] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.093723] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.110401] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.127082] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.143761] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.160441] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.177122] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.193831] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.210465] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.227160] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.243856] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.260522] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.277200] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.293880] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.310560] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.327240] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.343920] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.360603] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.377281] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.393959] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.410640] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.427319] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.444000] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.460679] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.477359] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.494038] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.510718] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.527398] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.544079] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.560789] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.577439] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.594119] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.610829] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.627479] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.644159] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.660838] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.677518] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.694197] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.710877] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.727557] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.744238] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.760916] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.777598] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.794278] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.810957] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.827636] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.844317] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.860996] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.877676] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.894356] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.911036] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.927717] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.944395] [drm:drm_mode_addfb2] [FB:79]
>[ 1262.961075] [drm:drm_mode_addfb2] [FB:77]
>[ 1262.977784] [drm:drm_mode_addfb2] [FB:78]
>[ 1262.994436] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.011115] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.027823] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.044475] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.061155] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.077836] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.094515] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.111195] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.127874] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.144553] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.161234] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.177914] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.194594] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.211283] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.227962] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.244634] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.261310] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.277995] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.294674] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.311353] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.328033] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.344714] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.361410] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.378073] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.394785] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.411432] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.428113] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.444816] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.461474] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.478153] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.494831] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.511511] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.528190] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.544872] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.561552] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.578232] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.594911] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.611591] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.628271] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.644951] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.661630] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.678312] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.694990] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.711670] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.728349] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.745029] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.761736] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.778391] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.795068] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.811779] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.828423] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.845108] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.861789] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.878468] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.895148] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.911829] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.928508] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.945188] [drm:drm_mode_addfb2] [FB:79]
>[ 1263.961868] [drm:drm_mode_addfb2] [FB:77]
>[ 1263.978548] [drm:drm_mode_addfb2] [FB:78]
>[ 1263.995229] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.011908] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.028587] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.045267] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.061951] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.078628] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.095310] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.111988] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.128667] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.145346] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.162027] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.178736] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.195387] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.212063] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.228774] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.245428] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.262108] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.278787] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.295466] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.312146] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.328825] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.345505] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.362185] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.378867] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.395545] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.412225] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.428906] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.445585] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.462264] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.478945] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.495626] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.512306] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.528985] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.545699] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.562348] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.579024] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.595731] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.612382] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.629063] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.645745] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.662422] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.679103] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.695783] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.712464] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.729143] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.745824] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.762503] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.779184] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.795864] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.812543] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.829222] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.845901] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.862581] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.879262] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.895942] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.912625] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.929301] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.945981] [drm:drm_mode_addfb2] [FB:79]
>[ 1264.962692] [drm:drm_mode_addfb2] [FB:77]
>[ 1264.979343] [drm:drm_mode_addfb2] [FB:78]
>[ 1264.996023] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.012730] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.029381] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.046060] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.062741] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.079421] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.096100] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.112780] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.129459] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.146140] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.162819] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.179498] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.196179] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.212859] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.229537] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.246219] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.262898] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.279577] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.296259] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.312939] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.329616] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.346298] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.362978] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.379685] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.396339] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.413018] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.429722] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.446378] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.463058] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.479736] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.496415] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.513097] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.529775] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.546457] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.563137] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.579815] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.596496] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.613174] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.629857] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.646537] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.663216] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.679895] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.696576] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.713256] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.729933] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.746615] [drm:drm_mode_addfb2] [FB:79]
>[ 1265.763295] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.779969] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.796803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.796890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1265.796937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1265.797028] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1265.814035] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1265.814073] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1265.814113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.814147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.814183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.814214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.814243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.814275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.814310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.814342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.814381] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.814410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.814436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.814461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.814512] [drm:intel_power_well_disable [i915]] disabling display
>[ 1265.814551] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1265.814590] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1265.814619] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1265.815103] [drm:drm_mode_addfb2] [FB:77]
>[ 1265.815148] [drm:drm_mode_addfb2] [FB:78]
>[ 1265.844052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1265.844156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1265.844229] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.844296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1265.844308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1265.844366] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1265.844388] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1265.844410] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1265.844434] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1265.844452] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1265.844473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1265.844493] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1265.844512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1265.844531] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1265.844548] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1265.844565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1265.844569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.844586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1265.844589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1265.844607] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1265.844682] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1265.844712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1265.844741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1265.844774] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1265.844804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1265.844835] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1265.844864] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1265.844896] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1265.844931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1265.844968] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1265.848297] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1265.848318] [drm:intel_power_well_enable [i915]] enabling display
>[ 1265.848337] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1265.848375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1265.848397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1265.848418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1265.848437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1265.848456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1265.848476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1265.848498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1265.848518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1265.848540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1265.848565] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1265.848589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1265.848615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1265.848695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1265.850780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1265.850802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1265.850821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.850841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1265.852412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1265.852435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1265.852458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1265.854024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1265.854045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1265.855916] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1265.859236] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1265.859284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1265.859308] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1265.859339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1265.876077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1265.876128] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1265.876195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1266.176303] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.193015] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.209699] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.226379] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.243059] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.259748] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.276413] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.293098] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.309778] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.326454] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.343138] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.359818] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.376494] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.393177] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.409857] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.426533] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.443219] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.459898] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.476572] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.493256] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.509935] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.526641] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.543298] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.559976] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.576679] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.593334] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.610016] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.626691] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.643377] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.660054] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.676704] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.693401] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.710115] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.726786] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.743467] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.760145] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.776825] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.793506] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.810176] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.826865] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.843546] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.860225] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.876906] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.893623] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.910263] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.926945] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.943663] [drm:drm_mode_addfb2] [FB:77]
>[ 1266.960303] [drm:drm_mode_addfb2] [FB:78]
>[ 1266.976984] [drm:drm_mode_addfb2] [FB:79]
>[ 1266.993697] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.010344] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.027024] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.043703] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.060383] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.077063] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.093743] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.110422] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.127102] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.143783] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.160463] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.177143] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.193821] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.210505] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.227180] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.243863] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.260542] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.277223] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.293901] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.310622] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.327262] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.343942] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.360660] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.377304] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.393981] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.410662] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.427341] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.444021] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.460700] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.477380] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.494060] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.510742] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.527420] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.544100] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.560779] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.577460] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.594139] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.610819] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.627499] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.644154] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.660859] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.677574] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.694220] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.710900] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.727619] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.744257] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.760940] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.777655] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.794299] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.810979] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.827659] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.844338] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.861018] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.877698] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.894378] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.911058] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.927737] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.944418] [drm:drm_mode_addfb2] [FB:77]
>[ 1267.961097] [drm:drm_mode_addfb2] [FB:78]
>[ 1267.977776] [drm:drm_mode_addfb2] [FB:79]
>[ 1267.994458] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.011137] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.027817] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.044497] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.061151] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.077856] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.094581] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.111217] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.127895] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.144616] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.161256] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.177935] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.194649] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.211294] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.227975] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.244656] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.261334] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.278016] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.294696] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.311372] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.328054] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.344734] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.361413] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.378094] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.394775] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.411454] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.428134] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.444813] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.461494] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.478174] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.494853] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.511575] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.528213] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.544893] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.561609] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.578252] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.594932] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.611615] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.628291] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.644974] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.661652] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.678348] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.695018] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.711691] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.728371] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.745052] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.761734] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.778412] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.795091] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.811772] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.828450] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.845131] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.861810] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.878524] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.895171] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.911850] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.928569] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.945211] [drm:drm_mode_addfb2] [FB:77]
>[ 1268.961890] [drm:drm_mode_addfb2] [FB:78]
>[ 1268.978607] [drm:drm_mode_addfb2] [FB:79]
>[ 1268.995251] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.011931] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.028611] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.045290] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.061970] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.078650] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.095330] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.112009] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.128689] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.145370] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.162050] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.178728] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.195408] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.212090] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.228768] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.245448] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.262129] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.278808] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.295527] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.312168] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.328847] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.345567] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.362208] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.378887] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.395600] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.412246] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.428926] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.445606] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.462286] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.478965] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.495645] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.512326] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.529007] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.545686] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.562364] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.579045] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.595725] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.612405] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.629087] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.645765] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.662445] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.679125] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.695804] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.712524] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.729165] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.745844] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.762562] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.779204] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.795885] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.812566] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.829243] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.845923] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.862603] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.879284] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.895963] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.912644] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.929322] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.946002] [drm:drm_mode_addfb2] [FB:77]
>[ 1269.962683] [drm:drm_mode_addfb2] [FB:78]
>[ 1269.979364] [drm:drm_mode_addfb2] [FB:79]
>[ 1269.996019] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.012723] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.029403] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.046085] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.062763] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.079478] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.096122] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.112802] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.129520] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.146163] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.162841] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.179559] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.196200] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.212881] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.229563] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.246241] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.262921] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.279600] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.296280] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.312961] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.329639] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.346321] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.362999] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.379678] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.396359] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.413040] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.429720] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.446400] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.463079] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.479759] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.496480] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.513118] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.529799] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.546519] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.563159] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.579838] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.596552] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.613199] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.629878] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.646558] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.663238] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.679918] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.696597] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.713278] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.729956] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.746638] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.763318] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.780012] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.796675] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.813357] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.830036] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.846716] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.863396] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.880076] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.896755] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.913478] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.930116] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.946796] [drm:drm_mode_addfb2] [FB:77]
>[ 1270.963511] [drm:drm_mode_addfb2] [FB:78]
>[ 1270.980155] [drm:drm_mode_addfb2] [FB:79]
>[ 1270.996835] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.013517] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.030194] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.046876] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.063555] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.080236] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.096916] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.113595] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.130276] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.146954] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.163633] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.180314] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.196994] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.213674] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.230354] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.247034] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.263716] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.280429] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.297073] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.313758] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.330472] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.347114] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.363792] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.380504] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.397151] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.413832] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.430513] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.447192] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.463872] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.480552] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.497230] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.513910] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.530590] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.547271] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.563951] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.580630] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.597311] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.613991] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.630670] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.647351] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.664003] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.680709] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.697427] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.714069] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.730750] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.747470] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.764110] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.780787] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.797503] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.814151] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.830829] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.847510] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.864188] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.880870] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.897548] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.914229] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.930908] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.947587] [drm:drm_mode_addfb2] [FB:77]
>[ 1271.964268] [drm:drm_mode_addfb2] [FB:78]
>[ 1271.980947] [drm:drm_mode_addfb2] [FB:79]
>[ 1271.997629] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.014309] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.030989] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.047668] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.064348] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.081026] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.097708] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.114427] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.131067] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.147747] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.164465] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.181107] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.197786] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.214467] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.231146] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.247826] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.264506] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.281186] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.297865] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.314544] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.331225] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.347905] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.364585] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.381265] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.397944] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.414625] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.431304] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.447986] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.464664] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.481377] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.498025] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.514705] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.531424] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.548064] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.564745] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.581461] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.598103] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.614785] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.631465] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.648144] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.664824] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.681504] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.698185] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.714864] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.731543] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.748225] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.764903] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.781583] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.798263] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.814943] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.831622] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.848302] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.864984] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.881662] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.898378] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.915022] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.931701] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.948419] [drm:drm_mode_addfb2] [FB:77]
>[ 1272.965062] [drm:drm_mode_addfb2] [FB:78]
>[ 1272.981741] [drm:drm_mode_addfb2] [FB:79]
>[ 1272.998448] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.015102] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.031781] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.048462] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.065141] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.081821] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.098501] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.115180] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.131861] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.148540] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.165234] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.181900] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.198583] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.215259] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.231938] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.248619] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.265297] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.281977] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.298657] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.315378] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.332018] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.348698] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.365417] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.382058] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.398738] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.415419] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.432096] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.448778] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.465457] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.482138] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.498817] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.515498] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.532176] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.548860] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.565538] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.582218] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.598896] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.615580] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.632256] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.648909] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.665616] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.682331] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.698975] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.715657] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.732375] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.749017] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.765695] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.782414] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.799055] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.815734] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.832417] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.849096] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.865775] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.882455] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.899133] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.915815] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.932495] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.949174] [drm:drm_mode_addfb2] [FB:77]
>[ 1273.965854] [drm:drm_mode_addfb2] [FB:78]
>[ 1273.982533] [drm:drm_mode_addfb2] [FB:79]
>[ 1273.999214] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.015895] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.032575] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.049254] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.065913] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.082614] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.099330] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.115973] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.132653] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.149373] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.166011] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.182692] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.199397] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.216053] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.232733] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.249412] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.266091] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.282772] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.299451] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.316132] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.332811] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.349491] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.366171] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.382850] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.399531] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.416211] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.432890] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.449572] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.466250] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.482930] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.499610] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.516327] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.532971] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.549651] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.566370] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.583009] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.599689] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.616371] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.633049] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.649730] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.666410] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.683090] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.699770] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.716449] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.733129] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.749810] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.766490] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.783170] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.799850] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.816529] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.833209] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.849888] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.866569] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.883282] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.899927] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.916607] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.933326] [drm:drm_mode_addfb2] [FB:79]
>[ 1274.949967] [drm:drm_mode_addfb2] [FB:77]
>[ 1274.966646] [drm:drm_mode_addfb2] [FB:78]
>[ 1274.983363] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.000008] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.016687] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.033368] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.050047] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.066727] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.083406] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.100087] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.116765] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.133445] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.150125] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.166805] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.183485] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.200165] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.216846] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.233526] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.250206] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.266884] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.283564] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.300287] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.316925] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.333604] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.350322] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.366963] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.383644] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.400349] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.417003] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.433683] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.450364] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.467043] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.483722] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.500403] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.517083] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.533762] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.550443] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.567124] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.583804] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.600482] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.617162] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.633842] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.650523] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.667202] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.683882] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.700562] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.717279] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.733921] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.750601] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.767323] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.783962] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.800686] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.817327] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.834001] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.850680] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.867361] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.884041] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.900720] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.917401] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.934079] [drm:drm_mode_addfb2] [FB:79]
>[ 1275.950759] [drm:drm_mode_addfb2] [FB:77]
>[ 1275.967439] [drm:drm_mode_addfb2] [FB:78]
>[ 1275.984120] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.000800] [drm:drm_mode_addfb2] [FB:77]
>[ 1276.017479] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.034160] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.050840] [drm:drm_mode_addfb2] [FB:77]
>[ 1276.067519] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.084235] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.100879] [drm:drm_mode_addfb2] [FB:77]
>[ 1276.117558] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.134281] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.150918] [drm:drm_mode_addfb2] [FB:77]
>[ 1276.167597] [drm:drm_mode_addfb2] [FB:78]
>[ 1276.184430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1276.184513] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1276.184555] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1276.184644] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1276.201662] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1276.201700] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1276.201745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1276.201786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1276.201830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1276.201870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1276.201910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1276.201950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1276.201994] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1276.202037] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1276.202079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1276.202121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1276.202160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1276.202200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1276.202354] [drm:intel_power_well_disable [i915]] disabling display
>[ 1276.202425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1276.202478] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1276.202511] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1276.205557] [IGT] kms_flip: exiting, ret=0
>[ 1276.226127] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1276.226167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1276.226206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1276.226290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1276.226324] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1276.226359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1276.226395] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1276.226427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1276.226464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1276.226492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1276.226525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1276.226532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1276.226565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1276.226570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1276.226604] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1276.226637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1276.226671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1276.226703] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1276.226738] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1276.226770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1276.226804] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1276.226838] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1276.226871] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1276.226907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1276.226944] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1276.227036] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1276.227066] [drm:intel_power_well_enable [i915]] enabling display
>[ 1276.227094] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1276.227147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1276.227181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1276.227232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1276.227265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1276.227299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1276.227333] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1276.227370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1276.227406] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1276.227442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1276.227481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1276.227506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1276.227534] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1276.227558] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1276.229624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1276.229643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1276.229663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1276.229687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1276.231292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1276.231311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1276.231328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1276.232892] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1276.232910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1276.234803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1276.238319] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1276.238389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1276.238419] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1276.238462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1276.238564] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1276.238612] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1276.255184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1276.255271] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1276.255347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1276.255651] Console: switching to colour frame buffer device 240x75
>[ 1276.364084] Console: switching to colour dummy device 80x25
>[ 1276.364260] [IGT] kms_flip: executing
>[ 1276.376095] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1276.376148] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1276.377307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1276.377351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1276.379289] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1276.379302] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1276.381285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1276.381327] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1276.383288] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1276.383299] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1276.383307] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1276.383338] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1276.383380] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1276.384519] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1276.385454] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1276.385475] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1276.385494] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1276.385512] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1276.386530] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1276.386550] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1276.387664] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1276.387668] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1276.387772] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1276.387774] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1276.387779] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1276.387782] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1276.387786] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1276.387789] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1276.387799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1276.387802] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1276.387805] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1276.387808] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1276.387811] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1276.387814] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1276.387817] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1276.387820] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1276.387823] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1276.387826] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1276.387829] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1276.387832] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1276.387835] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1276.387837] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1276.387840] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1276.387843] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1276.387846] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1276.387849] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1276.387852] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1276.387855] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1276.387858] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1276.387861] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1276.387864] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1276.387867] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1276.387870] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1276.387873] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1276.387876] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1276.387879] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1276.387882] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1276.387884] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1276.387887] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1276.387926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1276.387949] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1276.389252] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1276.389276] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1276.391373] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1276.391384] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1276.393502] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1276.393540] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1276.395654] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1276.395665] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1276.395672] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1276.396042] [IGT] kms_flip: starting subtest wf_vblank
>[ 1276.397027] [drm:drm_mode_addfb2] [FB:58]
>[ 1276.397056] [drm:drm_mode_addfb2] [FB:79]
>[ 1276.450081] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1276.450145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1276.455324] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1276.455371] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1276.455444] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1276.472469] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1276.472514] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1276.472547] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1276.472586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1276.472619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1276.472654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1276.472685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1276.472714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1276.472746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1276.472781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1276.472814] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1276.472846] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1276.472877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1276.472914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1276.472954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1276.473013] [drm:intel_power_well_disable [i915]] disabling display
>[ 1276.473058] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1276.473111] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1276.473149] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1276.473351] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1276.473576] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1276.473696] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1276.473715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1276.473799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1276.473830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1276.473863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1276.473900] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1276.473928] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1276.473960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1276.473990] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1276.474020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1276.474049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1276.474078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1276.474104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1276.474111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1276.474138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1276.474144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1276.474174] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1276.474227] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1276.474253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1276.474283] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1276.474314] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1276.474344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1276.474371] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1276.474401] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1276.474432] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1276.474466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1276.474501] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1276.477769] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1276.477788] [drm:intel_power_well_enable [i915]] enabling display
>[ 1276.477805] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1276.477839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1276.477859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1276.477882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1276.477905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1276.477929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1276.477952] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1276.477978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1276.478002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1276.478027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1276.478051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1276.478074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1276.478099] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1276.478122] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1276.480242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1276.480263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1276.480282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1276.480301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1276.481878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1276.481898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1276.481916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1276.483479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1276.483500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1276.485371] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1276.488701] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1276.488754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1276.488793] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1276.488841] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1276.488904] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1276.488930] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1276.505536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1276.505586] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1276.505650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1286.530448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1286.546847] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1286.546902] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1286.546982] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1286.563973] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1286.564018] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1286.564050] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1286.564090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1286.564124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1286.564160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1286.564190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1286.564220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1286.564252] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1286.564288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1286.564321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1286.564352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1286.564383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1286.564412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1286.564449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1286.564508] [drm:intel_power_well_disable [i915]] disabling display
>[ 1286.564556] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1286.564607] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1286.564647] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1286.565144] [drm:drm_mode_addfb2] [FB:58]
>[ 1286.565227] [drm:drm_mode_addfb2] [FB:78]
>[ 1286.594678] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1286.594868] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1286.595000] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1286.595077] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1286.595089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1286.595149] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1286.595171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1286.595194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1286.595218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1286.595236] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1286.595257] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1286.595277] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1286.595296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1286.595315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1286.595338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1286.595362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1286.595367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1286.595390] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1286.595394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1286.595418] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1286.595442] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1286.595465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1286.595488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1286.595512] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1286.595535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1286.595558] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1286.595581] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1286.595605] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1286.595630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1286.595655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1286.598938] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1286.598959] [drm:intel_power_well_enable [i915]] enabling display
>[ 1286.598978] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1286.599016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1286.599041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1286.599066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1286.599091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1286.599115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1286.599140] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1286.599167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1286.599193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1286.599219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1286.599243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1286.599267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1286.599293] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1286.599318] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1286.601403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1286.601426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1286.601445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1286.601464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1286.603064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1286.603086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1286.603105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1286.604657] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1286.604679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1286.606551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1286.609899] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1286.609987] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1286.610020] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1286.610062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1286.626767] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1286.626853] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1286.626925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1296.651515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1296.651611] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1296.651659] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1296.651734] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1296.668958] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1296.668996] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1296.669037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1296.669071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1296.669107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1296.669138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1296.669168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1296.669200] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1296.669235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1296.669268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1296.669300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1296.669331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1296.669437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1296.669480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1296.669569] [drm:intel_power_well_disable [i915]] disabling display
>[ 1296.669639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1296.669699] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1296.669733] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1296.669953] [drm:drm_mode_addfb2] [FB:58]
>[ 1296.669983] [drm:drm_mode_addfb2] [FB:78]
>[ 1296.699105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1296.699218] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1296.699300] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1296.699432] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1296.699450] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1296.699516] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1296.699540] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1296.699566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1296.699593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1296.699613] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1296.699640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1296.699667] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1296.699693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1296.699720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1296.699745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1296.699771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1296.699776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1296.699801] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1296.699806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1296.699833] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1296.699859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1296.699885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1296.699910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1296.699937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1296.699962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1296.699988] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1296.700014] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1296.700040] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1296.700067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1296.700096] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1296.703481] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1296.703502] [drm:intel_power_well_enable [i915]] enabling display
>[ 1296.703520] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1296.703558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1296.703584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1296.703608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1296.703633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1296.703657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1296.703682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1296.703708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1296.703734] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1296.703760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1296.703784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1296.703808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1296.703834] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1296.703858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1296.705965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1296.705986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1296.706005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1296.706024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1296.707614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1296.707638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1296.707661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1296.709226] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1296.709248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1296.711124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1296.714476] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1296.714565] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1296.714585] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1296.714611] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1296.731340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1296.731498] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1296.731564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1306.756350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1306.756533] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1306.756625] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1306.756766] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1306.774030] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1306.774069] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1306.774110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1306.774144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1306.774180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1306.774211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1306.774241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1306.774272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1306.774307] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1306.774349] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1306.774392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1306.774434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1306.774473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1306.774513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1306.774572] [drm:intel_power_well_disable [i915]] disabling display
>[ 1306.774618] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1306.774670] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1306.774706] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1306.778178] [IGT] kms_flip: exiting, ret=0
>[ 1306.800860] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1306.800903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1306.800945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1306.801016] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1306.801056] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1306.801097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1306.801137] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1306.801177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1306.801217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1306.801256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1306.801295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1306.801303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1306.801342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1306.801348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1306.801388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1306.801428] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1306.801467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1306.801506] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1306.801547] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1306.801585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1306.801635] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1306.801666] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1306.801697] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1306.801731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1306.801767] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1306.801853] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1306.801881] [drm:intel_power_well_enable [i915]] enabling display
>[ 1306.801908] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1306.801985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1306.802018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1306.802050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1306.802082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1306.802114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1306.802145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1306.802180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1306.802213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1306.802247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1306.802278] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1306.802309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1306.802342] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1306.802374] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1306.804455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1306.804476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1306.804498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1306.804522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1306.806106] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1306.806126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1306.806144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1306.807706] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1306.807725] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1306.809604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1306.813072] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1306.813125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1306.813148] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1306.813181] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1306.813247] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1306.813268] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1306.829929] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1306.830016] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1306.830087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1306.830330] Console: switching to colour frame buffer device 240x75
>[ 1306.939536] Console: switching to colour dummy device 80x25
>[ 1306.939651] [IGT] kms_flip: executing
>[ 1306.955797] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1306.955842] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1306.957043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1306.957084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1306.959026] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1306.959039] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1306.961022] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1306.961064] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1306.963021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1306.963033] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1306.963041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1306.963073] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1306.963115] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1306.964225] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1306.965159] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1306.965181] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1306.965200] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1306.965217] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1306.966237] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1306.966257] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1306.967368] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1306.967372] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1306.967477] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1306.967480] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1306.967485] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1306.967487] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1306.967492] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1306.967494] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1306.967504] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1306.967508] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1306.967511] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1306.967513] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1306.967516] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1306.967520] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1306.967522] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1306.967525] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1306.967528] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1306.967531] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1306.967534] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1306.967537] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1306.967540] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1306.967543] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1306.967546] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1306.967549] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1306.967552] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1306.967555] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1306.967558] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1306.967561] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1306.967564] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1306.967567] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1306.967570] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1306.967572] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1306.967575] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1306.967578] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1306.967581] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1306.967584] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1306.967587] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1306.967590] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1306.967593] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1306.967633] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1306.967656] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1306.968990] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1306.969015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1306.971001] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1306.971008] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1306.973122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1306.973161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1306.975276] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1306.975286] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1306.975294] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1306.975684] [IGT] kms_flip: starting subtest plain-flip-ts-check
>[ 1306.976581] [drm:drm_mode_addfb2] [FB:77]
>[ 1306.976618] [drm:drm_mode_addfb2] [FB:79]
>[ 1307.030166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1307.030230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1307.046754] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1307.046802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1307.046874] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1307.063896] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1307.064024] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1307.064076] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1307.064135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1307.064188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1307.064226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1307.064258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1307.064287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1307.064319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1307.064355] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1307.064387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1307.064408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1307.064428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1307.064446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1307.064464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1307.064500] [drm:intel_power_well_disable [i915]] disabling display
>[ 1307.064527] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1307.064556] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1307.064578] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1307.064641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1307.064735] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1307.064812] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1307.064824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1307.064876] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1307.064901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1307.064954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1307.064992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1307.065020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1307.065052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1307.065083] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1307.065111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1307.065140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1307.065167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1307.065193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1307.065202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1307.065228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1307.065236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1307.065263] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1307.065289] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1307.065315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1307.065341] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1307.065371] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1307.065397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1307.065423] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1307.065450] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1307.065475] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1307.065508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1307.065542] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1307.068848] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1307.068867] [drm:intel_power_well_enable [i915]] enabling display
>[ 1307.068888] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1307.068927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1307.068984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1307.069015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1307.069043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1307.069070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1307.069102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1307.069137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1307.069170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1307.069204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1307.069233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1307.069260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1307.069283] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1307.069304] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1307.071332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1307.071355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1307.071375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1307.071395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1307.072970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1307.072993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1307.073013] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1307.074572] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1307.074605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1307.076507] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1307.079750] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1307.079826] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1307.079846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1307.079873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1307.079994] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1307.080027] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1307.096633] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1307.096683] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1307.096747] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1317.404928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1317.421473] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1317.421553] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1317.421630] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1317.438669] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1317.438714] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1317.438746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1317.438784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1317.438824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1317.438868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1317.438909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1317.438949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1317.438988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1317.439033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1317.439075] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1317.439118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1317.439160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1317.439199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1317.439238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1317.439296] [drm:intel_power_well_disable [i915]] disabling display
>[ 1317.439344] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1317.439394] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1317.439433] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1317.439887] [drm:drm_mode_addfb2] [FB:77]
>[ 1317.439919] [drm:drm_mode_addfb2] [FB:78]
>[ 1317.469193] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1317.469299] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1317.469372] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1317.469441] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1317.469453] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1317.469574] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1317.469612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1317.469649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1317.469689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1317.469720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1317.469755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1317.469790] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1317.469821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1317.469850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1317.469880] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1317.469906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1317.469914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1317.469943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1317.469950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1317.469980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1317.470009] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1317.470039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1317.470067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1317.470100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1317.470130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1317.470157] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1317.470186] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1317.470215] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1317.470248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1317.470283] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1317.473585] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1317.473605] [drm:intel_power_well_enable [i915]] enabling display
>[ 1317.473626] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1317.473663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1317.473687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1317.473711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1317.473735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1317.473758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1317.473781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1317.473807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1317.473831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1317.473856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1317.473879] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1317.473902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1317.473927] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1317.473950] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1317.476009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1317.476030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1317.476049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1317.476068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1317.477733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1317.477755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1317.477774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1317.479329] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1317.479351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1317.481232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1317.484588] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1317.484650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1317.484670] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1317.484696] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1317.501454] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1317.501506] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1317.501672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1327.809750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1327.809837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1327.809884] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1327.809958] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1327.827002] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1327.827040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1327.827167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1327.827226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1327.827284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1327.827333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1327.827381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1327.827431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1327.827489] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1327.827542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1327.827594] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1327.827645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1327.827690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1327.827736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1327.827805] [drm:intel_power_well_disable [i915]] disabling display
>[ 1327.827848] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1327.827889] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1327.827921] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1327.828258] [drm:drm_mode_addfb2] [FB:77]
>[ 1327.828308] [drm:drm_mode_addfb2] [FB:78]
>[ 1327.857580] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1327.857688] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1327.857766] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1327.857839] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1327.857851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1327.857914] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1327.857938] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1327.857963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1327.857989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1327.858010] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1327.858032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1327.858054] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1327.858133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1327.858167] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1327.858201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1327.858232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1327.858241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1327.858270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1327.858278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1327.858309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1327.858339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1327.858370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1327.858402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1327.858436] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1327.858466] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1327.858497] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1327.858526] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1327.858555] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1327.858590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1327.858626] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1327.862023] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1327.862042] [drm:intel_power_well_enable [i915]] enabling display
>[ 1327.862114] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1327.862170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1327.862201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1327.862231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1327.862259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1327.862289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1327.862318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1327.862350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1327.862382] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1327.862413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1327.862440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1327.862467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1327.862501] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1327.862529] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1327.864601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1327.864621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1327.864640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1327.864659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1327.866233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1327.866253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1327.866271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1327.867833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1327.867853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1327.869721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1327.873041] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1327.873161] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1327.873200] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1327.873252] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1327.889940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1327.889991] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1327.890058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.198222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.198309] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1338.198356] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1338.198430] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1338.215463] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1338.215500] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1338.215541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.215575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.215619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.215744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.215796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.215847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.215906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.215959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.216011] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.216049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.216079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.216107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.216167] [drm:intel_power_well_disable [i915]] disabling display
>[ 1338.216195] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1338.216224] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1338.216244] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1338.218981] [IGT] kms_flip: exiting, ret=0
>[ 1338.238543] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1338.238579] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1338.238624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1338.238686] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1338.238711] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1338.238739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1338.238767] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1338.238793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1338.238818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1338.238841] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1338.238864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1338.238870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.238892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1338.238897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.238920] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1338.238943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1338.238965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1338.238986] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1338.239014] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1338.239036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1338.239058] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1338.239080] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1338.239102] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1338.239129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.239159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1338.239258] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1338.239283] [drm:intel_power_well_enable [i915]] enabling display
>[ 1338.239306] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1338.239351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.239376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.239400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.239423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.239444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.239468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.239503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.239538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.239572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.239604] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.239651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.239698] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1338.239720] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1338.241777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1338.241796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1338.241814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.241832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1338.243408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1338.243426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1338.243443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.245003] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1338.245021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1338.246894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1338.249975] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1338.250007] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1338.250029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1338.250061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1338.250125] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1338.250145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1338.266815] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.266863] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.266933] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.267182] Console: switching to colour frame buffer device 240x75
>[ 1338.379463] Console: switching to colour dummy device 80x25
>[ 1338.379578] [IGT] kms_flip: executing
>[ 1338.393550] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1338.393602] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1338.395742] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1338.395778] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1338.397894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1338.397906] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1338.400024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1338.400063] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1338.402180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1338.402191] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1338.402199] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1338.402229] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1338.402271] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1338.403369] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1338.404289] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1338.404311] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1338.404330] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1338.404348] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1338.405378] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1338.405401] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1338.406517] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1338.406521] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1338.406669] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1338.406675] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1338.406684] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1338.406689] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1338.406699] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1338.406703] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1338.406719] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1338.406726] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.406732] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.406739] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.406745] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1338.406751] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1338.406758] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1338.406765] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1338.406771] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.406777] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.406783] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1338.406790] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1338.406796] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1338.406803] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1338.406809] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1338.406815] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1338.406822] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1338.406829] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1338.406835] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1338.406841] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1338.406846] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1338.406853] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1338.406860] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1338.406867] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1338.406873] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1338.406878] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1338.406885] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1338.406892] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1338.406898] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1338.406904] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1338.406910] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1338.406979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1338.407017] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1338.408863] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1338.408902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1338.410720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1338.410731] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1338.412731] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1338.412769] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1338.414719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1338.414730] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1338.414737] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1338.415108] [IGT] kms_flip: starting subtest nonblocking-read
>[ 1338.418229] [IGT] kms_flip: exiting, ret=0
>[ 1338.450440] Console: switching to colour frame buffer device 240x75
>[ 1338.558771] Console: switching to colour dummy device 80x25
>[ 1338.558890] [IGT] kms_flip: executing
>[ 1338.570515] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1338.570568] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1338.572718] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1338.572758] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1338.574854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1338.574864] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1338.576961] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1338.576999] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1338.579113] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1338.579125] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1338.579132] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1338.579163] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1338.579205] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1338.580328] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1338.581277] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1338.581299] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1338.581322] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1338.581345] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1338.582372] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1338.582394] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1338.583521] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1338.583524] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1338.583695] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1338.583698] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1338.583704] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1338.583706] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1338.583712] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1338.583715] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1338.583726] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1338.583730] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.583733] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.583737] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.583741] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1338.583744] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1338.583747] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1338.583750] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1338.583754] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.583758] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1338.583761] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1338.583764] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1338.583767] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1338.583770] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1338.583774] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1338.583778] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1338.583781] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1338.583785] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1338.583788] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1338.583791] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1338.583794] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1338.583799] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1338.583802] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1338.583805] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1338.583808] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1338.583812] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1338.583815] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1338.583819] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1338.583822] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1338.583825] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1338.583828] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1338.583869] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1338.583894] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1338.585689] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1338.585719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1338.587715] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1338.587726] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1338.589714] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1338.589750] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1338.591714] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1338.591725] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1338.591732] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1338.592124] [IGT] kms_flip: starting subtest flip-vs-rmfb
>[ 1338.593006] [drm:drm_mode_addfb2] [FB:77]
>[ 1338.593051] [drm:drm_mode_addfb2] [FB:79]
>[ 1338.646059] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1338.646122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.650442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1338.650492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1338.650570] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1338.667586] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1338.667631] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1338.667756] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1338.667816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.667869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.667925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.667964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.667991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.668020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.668052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.668083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.668111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.668147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.668183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.668219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.668272] [drm:intel_power_well_disable [i915]] disabling display
>[ 1338.668314] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1338.668360] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.668396] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1338.668467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1338.668598] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1338.668826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1338.668851] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1338.668975] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1338.668997] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1338.669019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1338.669042] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1338.669060] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1338.669080] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1338.669100] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1338.669119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1338.669137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1338.669154] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1338.669171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1338.669175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.669192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1338.669196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.669213] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1338.669235] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1338.669259] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1338.669282] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1338.669305] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1338.669329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1338.669352] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1338.669376] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1338.669399] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1338.669424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.669449] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1338.672735] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1338.672756] [drm:intel_power_well_enable [i915]] enabling display
>[ 1338.672774] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1338.672810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.672833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.672854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.672875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.672900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.672924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.672951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.672976] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.673002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.673036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.673061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.673088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1338.673112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1338.675214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1338.675255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1338.675275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.675295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1338.676882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1338.676904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1338.676923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.678482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1338.678504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1338.680377] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1338.683729] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1338.683812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1338.683844] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1338.683887] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1338.683969] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1338.684009] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1338.700596] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.700680] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.700746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.717290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1338.717310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1338.734089] [drm:drm_mode_addfb2] [FB:78]
>[ 1338.734229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.767313] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1338.767361] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1338.767452] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1338.784455] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1338.784499] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1338.784531] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1338.784569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.784603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.784722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.784767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.784816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.784862] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.784919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.784969] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.785018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.785067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.785107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.785150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.785234] [drm:intel_power_well_disable [i915]] disabling display
>[ 1338.785297] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1338.785358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.785411] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1338.785704] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1338.785725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1338.785805] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1338.785828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1338.785859] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1338.785883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1338.785901] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1338.785921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1338.785942] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1338.785965] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1338.785989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1338.786012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1338.786035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1338.786040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.786063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1338.786067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.786091] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1338.786112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1338.786135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1338.786156] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1338.786180] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1338.786203] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1338.786226] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1338.786250] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1338.786272] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1338.786296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.786322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1338.786378] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1338.786399] [drm:intel_power_well_enable [i915]] enabling display
>[ 1338.786418] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1338.786454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.786478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.786502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.786525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.786549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.786572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.786597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.786675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.786710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.786739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.786767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.786801] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1338.786831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1338.788897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1338.788919] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1338.788938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.788957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1338.790526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1338.790547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1338.790565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.792151] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1338.792174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1338.794148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1338.797443] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1338.797534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1338.797574] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1338.797626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1338.797804] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1338.797856] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1338.816350] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.816397] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.816460] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.816756] [drm:drm_mode_addfb2] [FB:77]
>[ 1338.816962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.847679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1338.847728] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1338.847817] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1338.864815] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1338.864860] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1338.864893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1338.864932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.864966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.865001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.865033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.865062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.865093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.865128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.865161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.865193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.865233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.865272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.865312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.865370] [drm:intel_power_well_disable [i915]] disabling display
>[ 1338.865417] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1338.865477] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.865498] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1338.865664] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1338.865687] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1338.865784] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1338.865816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1338.865850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1338.865886] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1338.865914] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1338.865947] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1338.865976] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1338.866008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1338.866037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1338.866066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1338.866092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1338.866099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.866125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1338.866132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.866162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1338.866190] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1338.866217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1338.866243] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1338.866273] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1338.866299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1338.866327] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1338.866352] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1338.866380] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1338.866409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.866442] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1338.866519] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1338.866550] [drm:intel_power_well_enable [i915]] enabling display
>[ 1338.866579] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1338.866659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.866689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.866720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.866748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.866777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.866806] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.866840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.866873] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.866906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.866935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.866964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.866999] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1338.867029] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1338.869121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1338.869142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1338.869161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.869184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1338.870782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1338.870805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1338.870824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.872382] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1338.872403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1338.874274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1338.876842] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1338.876883] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1338.876903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1338.876929] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1338.876990] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1338.877011] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1338.893690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.893742] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.893813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.894004] [drm:drm_mode_addfb2] [FB:79]
>[ 1338.894131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.927065] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1338.927119] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1338.927197] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1338.944220] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1338.944264] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1338.944297] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1338.944335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.944369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.944404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.944435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.944474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.944513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.944558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.944600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.944728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.944784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.944829] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.944872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.944958] [drm:intel_power_well_disable [i915]] disabling display
>[ 1338.945028] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1338.945094] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.945151] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1338.945312] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1338.945332] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1338.945420] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1338.945446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1338.945473] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1338.945502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1338.945528] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1338.945554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1338.945580] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1338.945614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1338.945674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1338.945703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1338.945731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1338.945740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.945767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1338.945774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1338.945802] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1338.945832] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1338.945861] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1338.945888] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1338.945922] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1338.945951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1338.945980] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1338.946011] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1338.946040] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1338.946074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1338.946108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1338.946160] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1338.946180] [drm:intel_power_well_enable [i915]] enabling display
>[ 1338.946201] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1338.946240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1338.946266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1338.946292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1338.946318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1338.946345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1338.946371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1338.946399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1338.946427] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1338.946454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.946480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1338.946506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1338.946533] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1338.946559] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1338.948611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1338.948655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1338.948674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.948693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1338.950287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1338.950310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1338.950329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1338.951896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1338.951917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1338.953789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1338.957119] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1338.957172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1338.957204] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1338.957246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1338.957341] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1338.957391] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1338.973956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1338.974007] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1338.974072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1338.974297] [drm:drm_mode_addfb2] [FB:78]
>[ 1338.974426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.007298] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.007346] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.007435] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.024448] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.024491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.024524] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.024563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.024596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.024725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.024777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.024828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.024879] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.024937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.024990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.025041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.025091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.025137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.025183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.025269] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.025335] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.025398] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.025433] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.025620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.025640] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.025706] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.025729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.025755] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.025784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.025809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.025835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.025860] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.025891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.025911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.025929] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.025946] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.025950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.025967] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.025971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.025987] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.026004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.026027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.026050] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.026074] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.026097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.026120] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.026144] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.026167] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.026191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.026216] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.026266] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.026287] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.026307] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.026342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.026366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.026389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.026413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.026436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.026459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.026484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.026509] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.026534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.026557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.026580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.026604] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.026676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.028753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.028775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.028794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.028813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.030393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.030418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.030441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.032009] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.032031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.033900] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.037246] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.037339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.037379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.037430] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.037529] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.037581] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.054117] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.054169] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.054240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.054467] [drm:drm_mode_addfb2] [FB:77]
>[ 1339.054610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.087461] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.087509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.087599] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.104704] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.104749] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.104781] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.104819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.104852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.104887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.104917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.104945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.104977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.105012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.105053] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.105096] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.105138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.105177] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.105217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.105275] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.105322] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.105351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.105373] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.105500] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.105513] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.105571] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.105605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.105675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.105715] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.105748] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.105784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.105818] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.105851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.105884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.105915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.105945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.105955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.105984] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.105992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.106022] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.106054] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.106085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.106114] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.106149] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.106179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.106210] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.106240] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.106269] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.106302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.106338] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.106416] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.106448] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.106479] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.106529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.106560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.106592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.106644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.106673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.106702] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.106736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.106770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.106804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.106834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.106864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.106900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.106933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.109013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.109037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.109060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.109084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.110652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.110672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.110691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.112247] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.112268] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.114129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.117448] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.117512] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.117545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.117587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.117900] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.117928] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.134296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.134345] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.134410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.134707] [drm:drm_mode_addfb2] [FB:79]
>[ 1339.134909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.167675] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.167739] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.167837] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.184866] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.184910] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.184942] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.184981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.185021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.185065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.185105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.185145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.185184] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.185229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.185280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.185318] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.185355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.185390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.185425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.185477] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.185519] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.185564] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.185599] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.185864] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.185890] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.186014] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.186057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.186104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.186153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.186192] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.186236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.186277] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.186320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.186348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.186376] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.186402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.186409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.186436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.186443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.186472] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.186498] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.186525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.186550] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.186581] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.186632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.186662] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.186689] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.186717] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.186752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.186786] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.186874] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.186905] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.186933] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.186983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.187015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.187046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.187073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.187101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.187128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.187159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.187190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.187222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.187247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.187275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.187306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.187336] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.189404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.189425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.189443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.189462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.191024] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.191044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.191062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.192632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.192653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.194520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.197846] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.197899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.197929] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.197968] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.198040] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.198070] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.214688] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.214740] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.214810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.215038] [drm:drm_mode_addfb2] [FB:78]
>[ 1339.215185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.248029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.248077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.248150] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.265184] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.265228] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.265260] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.265298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.265332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.265367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.265399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.265428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.265460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.265495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.265528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.265568] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.265678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.265724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.265771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.265857] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.265921] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.265984] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.266037] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.266206] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.266226] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.266326] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.266358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.266391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.266425] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.266454] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.266485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.266516] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.266545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.266574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.266657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.266685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.266694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.266723] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.266731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.266762] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.266792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.266823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.266853] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.266883] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.266913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.266944] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.266973] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.266999] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.267031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.267066] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.267142] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.267175] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.267205] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.267255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.267286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.267317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.267347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.267376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.267407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.267441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.267473] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.267505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.267535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.267564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.267598] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.267655] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.269729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.269751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.269770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.269789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.271359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.271383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.271406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.272957] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.272980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.274850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.278204] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.278269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.278289] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.278314] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.278375] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.278396] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.295066] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.295115] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.295180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.295405] [drm:drm_mode_addfb2] [FB:77]
>[ 1339.295552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.328409] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.328461] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.328537] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.345558] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.345602] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.345721] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.345779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.345827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.345879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.345922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.345970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.346015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.346067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.346099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.346131] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.346162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.346188] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.346216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.346270] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.346321] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.346358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.346389] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.346529] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.346542] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.346670] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.346706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.346743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.346781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.346812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.346847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.346880] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.346912] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.346940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.346971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.346997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.347005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.347034] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.347041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.347072] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.347103] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.347132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.347161] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.347193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.347223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.347252] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.347282] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.347311] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.347344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.347379] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.347458] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.347489] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.347519] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.347570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.347623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.347653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.347685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.347715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.347747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.347781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.347814] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.347847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.347877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.347908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.347943] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.347975] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.350041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.350064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.350087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.350111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.351693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.351716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.351735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.353285] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.353306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.355169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.358442] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.358494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.358521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.358556] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.358700] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.358743] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.375276] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.375324] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.375387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.375633] [drm:drm_mode_addfb2] [FB:79]
>[ 1339.375811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.408655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.408706] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.408782] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.425827] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.425871] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.425904] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.425942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.425976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.426011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.426042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.426071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.426103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.426139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.426172] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.426203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.426234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.426262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.426289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.426343] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.426384] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.426427] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.426461] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.426683] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.426716] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.426866] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.426921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.426966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.427014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.427051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.427093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.427132] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.427173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.427210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.427248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.427282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.427291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.427326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.427335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.427373] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.427407] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.427443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.427477] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.427518] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.427552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.427590] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.427665] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.427700] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.427744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.427790] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.427889] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.427931] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.427960] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.428009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.428037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.428067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.428093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.428121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.428149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.428180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.428212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.428244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.428269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.428297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.428327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.428358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.430446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.430470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.430493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.430517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.432118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.432140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.432159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.433726] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.433748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.435637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.438982] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.439071] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.439103] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.439129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.439189] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.439211] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.455826] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.455871] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.455935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.456114] [drm:drm_mode_addfb2] [FB:78]
>[ 1339.456239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.489195] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.489240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.489310] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.506380] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.506423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.506455] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.506494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.506528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.506571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.506691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.506742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.506797] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.506847] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.506892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.506936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.506977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.507002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.507026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.507072] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.507108] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.507144] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.507173] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.507304] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.507320] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.507393] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.507421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.507451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.507484] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.507511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.507538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.507566] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.507649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.507687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.507724] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.507760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.507772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.507808] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.507815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.507843] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.507869] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.507896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.507924] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.507954] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.507981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.508007] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.508034] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.508060] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.508091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.508123] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.508200] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.508233] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.508263] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.508315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.508347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.508377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.508408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.508438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.508469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.508501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.508523] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.508544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.508563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.508611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.508643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.508672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.510735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.510756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.510774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.510793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.512362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.512382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.512400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.513952] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.513973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.515833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.519138] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.519201] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.519221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.519247] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.519307] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.519328] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.536000] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.536049] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.536114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.536313] [drm:drm_mode_addfb2] [FB:77]
>[ 1339.536441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.569343] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.569392] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.569464] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.586487] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.586531] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.586563] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.586692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.586745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.586803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.586852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.586894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.586928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.586965] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.586999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.587031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.587062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.587091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.587119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.587175] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.587217] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.587259] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.587294] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.587451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.587469] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.587555] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.587660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.587710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.587745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.587773] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.587804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.587834] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.587864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.587894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.587921] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.587947] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.587956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.587981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.587989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.588015] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.588042] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.588067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.588096] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.588128] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.588156] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.588185] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.588206] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.588224] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.588246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.588273] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.588327] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.588350] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.588371] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.588410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.588436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.588463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.588489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.588516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.588542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.588567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.588623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.588657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.588686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.588715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.588748] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.588777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.590850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.590871] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.590890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.590909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.592470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.592490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.592511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.594100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.594121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.595994] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.599327] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.599428] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.599459] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.599499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.599571] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.599669] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.616210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.616260] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.616325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.616523] [drm:drm_mode_addfb2] [FB:79]
>[ 1339.616770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.649555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.649638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.649710] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.666717] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.666761] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.666793] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.666831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.666865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.666900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.666931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.666959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.666991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.667026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.667067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.667110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.667152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.667191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.667231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.667289] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.667335] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.667386] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.667424] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.667668] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.667700] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.667850] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.667894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.667941] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.667992] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.668032] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.668076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.668118] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.668159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.668198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.668238] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.668273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.668284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.668321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.668330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.668371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.668407] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.668445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.668481] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.668523] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.668558] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.668630] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.668657] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.668687] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.668716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.668751] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.668829] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.668862] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.668892] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.668942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.668972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.669000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.669030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.669057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.669087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.669120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.669151] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.669182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.669208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.669235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.669266] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.669296] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.671387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.671409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.671428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.671448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.673025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.673046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.673064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.674622] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.674644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.676502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.679852] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.679929] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.679956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.679990] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.680053] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.680080] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.696719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.696768] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.696833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.697052] [drm:drm_mode_addfb2] [FB:78]
>[ 1339.697183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.730062] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.730111] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.730183] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.747208] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.747252] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.747285] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.747323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.747356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.747391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.747422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.747451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.747482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.747519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.747552] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.747666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.747715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.747757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.747798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.747882] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.747954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.748020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.748077] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.748237] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.748255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.748342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.748376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.748412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.748451] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.748482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.748503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.748525] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.748545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.748570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.748637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.748664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.748672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.748700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.748708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.748735] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.748762] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.748789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.748818] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.748850] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.748877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.748907] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.748936] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.748964] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.748998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.749032] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.749105] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.749137] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.749158] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.749192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.749213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.749233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.749252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.749271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.749291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.749313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.749333] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.749354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.749372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.749390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.749413] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.749434] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.751474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.751495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.751513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.751532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.753133] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.753157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.753180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.754738] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.754760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.756627] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.759887] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.759944] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.759963] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.759988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.760049] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.760070] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.776714] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.776761] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.776824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.777024] [drm:drm_mode_addfb2] [FB:77]
>[ 1339.777135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.810063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.810109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.810179] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.827207] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.827251] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.827283] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.827321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.827355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.827390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.827421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.827451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.827482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.827518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.827551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.827666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.827715] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.827758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.827800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.827883] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.827954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.828019] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.828076] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.828246] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.828266] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.828361] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.828383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.828406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.828430] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.828451] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.828472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.828493] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.828512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.828532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.828557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.828618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.828626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.828653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.828661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.828688] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.828715] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.828742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.828768] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.828798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.828825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.828851] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.828877] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.828903] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.828935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.828970] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.829047] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.829080] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.829111] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.829163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.829195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.829228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.829258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.829278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.829298] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.829320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.829341] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.829362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.829386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.829412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.829440] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.829466] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.831519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.831540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.831558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.831636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.833205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.833225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.833243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.834809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.834830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.836699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.840038] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.840135] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.840167] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.840209] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.840286] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.840319] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.856916] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.856968] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.857038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.857238] [drm:drm_mode_addfb2] [FB:79]
>[ 1339.857371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.890260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.890308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.890380] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.907401] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.907445] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.907477] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.907515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.907548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.907672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.907722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.907771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.907823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.907881] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.907922] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.907954] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.907985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.908014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.908042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.908099] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.908142] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.908185] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.908220] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.908357] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.908369] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.908426] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.908446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.908468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.908497] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.908522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.908550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.908617] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.908647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.908677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.908705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.908731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.908739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.908765] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.908773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.908800] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.908826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.908853] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.908879] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.908910] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.908936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.908963] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.908989] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.909016] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.909047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.909079] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.909156] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.909188] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.909219] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.909270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.909302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.909333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.909363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.909394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.909427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.909458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.909481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.909501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.909520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.909538] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.909563] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.909617] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.911689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.911711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.911729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.911748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.913317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.913338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.913357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.914919] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.914940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.916800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1339.920145] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1339.920238] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1339.920278] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1339.920330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1339.920412] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1339.920452] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1339.937016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.937066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.937130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.937327] [drm:drm_mode_addfb2] [FB:78]
>[ 1339.937455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.970361] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1339.970409] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1339.970481] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1339.989286] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1339.989335] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1339.989375] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1339.989420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.989461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.989505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.989545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.989657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.989707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1339.989766] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.989817] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.989870] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.989922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.989969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.990015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.990102] [drm:intel_power_well_disable [i915]] disabling display
>[ 1339.990160] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1339.990204] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1339.990239] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1339.990371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1339.990383] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1339.990440] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1339.990461] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1339.990487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1339.990516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1339.990541] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1339.990610] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1339.990642] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1339.990671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1339.990699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1339.990727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1339.990754] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1339.990763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.990789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1339.990797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1339.990824] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1339.990851] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1339.990878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1339.990903] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1339.990934] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1339.990963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1339.990992] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1339.991020] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1339.991050] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1339.991084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1339.991118] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1339.991194] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1339.991227] [drm:intel_power_well_enable [i915]] enabling display
>[ 1339.991258] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1339.991304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1339.991326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1339.991345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1339.991365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1339.991383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1339.991404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1339.991426] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1339.991452] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1339.991480] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1339.991506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1339.991532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1339.991560] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1339.991618] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1339.993685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1339.993706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1339.993724] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.993743] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1339.995302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1339.995322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1339.995340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1339.996905] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1339.996926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1339.998796] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.002146] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.002231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.002263] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.002306] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.002383] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.002417] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.019012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.019062] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.019128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.019310] [drm:drm_mode_addfb2] [FB:77]
>[ 1340.019444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.052356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.052404] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.052477] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.069502] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.069546] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.069672] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.069732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.069785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.069840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.069874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.069904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.069937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.069980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.070025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.070069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.070112] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.070152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.070193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.070258] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.070287] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.070318] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.070340] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.070445] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.070457] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.070516] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.070538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.070604] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.070640] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.070669] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.070700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.070730] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.070759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.070789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.070817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.070846] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.070854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.070880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.070888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.070915] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.070941] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.070967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.070993] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.071024] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.071054] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.071083] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.071109] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.071136] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.071170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.071196] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.071247] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.071267] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.071285] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.071318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.071338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.071364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.071390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.071417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.071442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.071470] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.071498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.071522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.071548] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.071599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.071633] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.071663] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.073734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.073755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.073774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.073794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.075365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.075385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.075403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.076964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.076985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.078856] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.082200] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.082291] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.082324] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.082366] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.082444] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.082484] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.099074] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.099125] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.099190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.099388] [drm:drm_mode_addfb2] [FB:79]
>[ 1340.099521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.132416] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.132469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.132544] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.149683] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.149727] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.149760] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.149799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.149833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.149868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.149899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.149928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.149960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.149995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.150028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.150059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.150090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.150119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.150146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.150200] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.150226] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.150251] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.150272] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.150399] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.150411] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.150469] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.150492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.150516] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.150552] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.150633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.150664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.150699] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.150728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.150760] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.150788] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.150819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.150827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.150856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.150864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.150894] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.150921] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.150951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.150977] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.151010] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.151037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.151066] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.151092] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.151119] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.151152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.151187] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.151266] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.151297] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.151328] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.151377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.151406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.151434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.151460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.151488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.151516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.151547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.151606] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.151640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.151667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.151696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.151728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.151760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.153848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.153872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.153895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.153920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.155475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.155498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.155519] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.157090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.157112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.158973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.162313] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.162409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.162442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.162485] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.162547] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.162624] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.179186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.179234] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.179297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.179500] [drm:drm_mode_addfb2] [FB:78]
>[ 1340.179706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.212532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.212613] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.212682] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.229686] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.229730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.229763] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.229801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.229834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.229870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.229900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.229930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.229961] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.229997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.230030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.230061] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.230092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.230120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.230147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.230191] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.230216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.230242] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.230262] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.230380] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.230392] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.230449] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.230472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.230495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.230520] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.230549] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.230622] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.230654] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.230683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.230712] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.230740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.230766] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.230774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.230800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.230808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.230835] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.230861] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.230888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.230914] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.230945] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.230971] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.230998] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.231024] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.231051] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.231082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.231118] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.231196] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.231229] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.231260] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.231313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.231345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.231376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.231406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.231437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.231469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.231502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.231524] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.231551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.231596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.231624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.231656] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.231685] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.233767] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.233789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.233808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.233827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.235398] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.235419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.235440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.237004] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.237025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.238894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.242238] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.242329] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.242363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.242409] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.242470] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.242492] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.259110] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.259159] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.259224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.259427] [drm:drm_mode_addfb2] [FB:77]
>[ 1340.259543] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.292455] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.292504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.292658] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.309645] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.309689] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.309722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.309760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.309793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.309827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.309857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.309887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.309918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.309953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.309986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.310018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.310049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.310082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.310105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.310150] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.310185] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.310220] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.310248] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.310414] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.310430] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.310510] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.310543] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.310628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.310681] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.310720] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.310768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.310809] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.310852] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.310891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.310931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.310966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.310978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.311014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.311025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.311064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.311110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.311151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.311187] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.311232] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.311268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.311306] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.311343] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.311383] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.311429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.311475] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.311616] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.311659] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.311700] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.311768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.311811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.311850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.311890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.311927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.311970] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.312016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.312062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.312116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.312143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.312171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.312202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.312234] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.314305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.314325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.314344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.314363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.315952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.315976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.315999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.317545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.317582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.319442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.322823] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.322875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.322908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.322949] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.323027] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.323060] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.339659] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.339708] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.339778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.339981] [drm:drm_mode_addfb2] [FB:79]
>[ 1340.340115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.373005] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.373054] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.373127] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.390149] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.390193] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.390226] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.390265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.390299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.390334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.390365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.390394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.390425] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.390461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.390493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.390525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.390639] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.390681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.390724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.390810] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.390882] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.390955] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.390992] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.391114] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.391127] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.391184] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.391206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.391229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.391253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.391274] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.391295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.391317] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.391337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.391356] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.391375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.391393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.391398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.391415] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.391420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.391439] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.391458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.391476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.391494] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.391515] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.391537] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.391589] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.391616] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.391643] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.391673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.391706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.391783] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.391815] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.391847] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.391899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.391930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.391961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.391991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.392021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.392052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.392086] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.392119] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.392142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.392161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.392180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.392203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.392224] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.394282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.394303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.394322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.394341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.395904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.395924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.395942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.397539] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.397572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.399440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.402820] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.402873] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.402906] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.402948] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.403025] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.403058] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.419657] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.419707] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.419773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.419953] [drm:drm_mode_addfb2] [FB:78]
>[ 1340.420088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.453000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.453053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.453129] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.470149] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.470194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.470227] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.470265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.470298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.470334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.470365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.470394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.470426] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.470461] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.470494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.470526] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.470645] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.470688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.470729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.470814] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.470881] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.470932] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.470955] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.471062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.471074] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.471132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.471154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.471177] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.471202] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.471222] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.471243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.471268] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.471294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.471320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.471347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.471371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.471377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.471402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.471407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.471433] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.471459] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.471485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.471511] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.471542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.471603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.471633] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.471663] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.471691] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.471723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.471756] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.471832] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.471861] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.471892] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.471930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.471951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.471977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.472003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.472029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.472054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.472083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.472111] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.472139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.472164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.472191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.472218] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.472244] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.474292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.474313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.474332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.474351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.475932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.475952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.475970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.477535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.477567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.479427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.482768] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.482862] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.482895] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.482937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.483015] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.483047] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.499643] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.499695] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.499766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.499968] [drm:drm_mode_addfb2] [FB:77]
>[ 1340.500105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.532987] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.533038] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.533114] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.550135] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.550179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.550211] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.550249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.550283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.550318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.550349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.550378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.550410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.550446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.550479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.550511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.550542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.550654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.550697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.550792] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.550834] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.550875] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.550909] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.551063] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.551083] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.551180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.551214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.551249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.551294] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.551322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.551353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.551383] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.551413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.551443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.551471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.551499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.551506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.551544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.551588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.551620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.551651] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.551682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.551713] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.551747] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.551777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.551805] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.551835] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.551866] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.551900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.551937] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.552014] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.552046] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.552076] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.552126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.552157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.552189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.552218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.552249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.552279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.552313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.552346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.552378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.552407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.552435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.552469] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.552500] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.554594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.554614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.554633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.554652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.556229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.556249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.556267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.557833] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.557854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.559740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.563074] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.563109] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.563133] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.563165] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.563228] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.563254] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.579909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.579959] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.580024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.580227] [drm:drm_mode_addfb2] [FB:79]
>[ 1340.580360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.613250] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.613299] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.613370] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.630386] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.630431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.630463] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.630502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.630535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.630661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.630706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.630738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.630778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.630810] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.630840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.630868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.630896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.630921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.630946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.630994] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.631032] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.631070] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.631101] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.631229] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.631246] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.631325] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.631354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.631386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.631420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.631449] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.631479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.631508] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.631547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.631626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.631667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.631704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.631716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.631752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.631762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.631803] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.631833] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.631864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.631894] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.631929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.631959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.631989] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.632019] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.632049] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.632084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.632120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.632225] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.632258] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.632292] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.632332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.632356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.632378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.632400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.632420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.632443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.632467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.632490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.632512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.632534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.632588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.632625] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.632658] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.634731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.634751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.634769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.634788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.636358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.636378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.636400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.637964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.637985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.639850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.643173] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.643225] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.643251] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.643285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.643348] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.643375] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.660017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.660067] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.660132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.660332] [drm:drm_mode_addfb2] [FB:78]
>[ 1340.660448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.693359] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.693412] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.693488] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.710508] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.710640] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.710693] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.710753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.710803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.710849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.710879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.710907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.710937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.710972] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.711003] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.711035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.711064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.711093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.711119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.711172] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.711212] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.711252] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.711284] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.711420] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.711437] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.711520] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.711606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.711653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.711704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.711746] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.711791] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.711834] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.711874] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.711903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.711930] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.711956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.711965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.711991] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.711998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.712025] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.712052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.712079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.712105] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.712134] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.712161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.712188] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.712216] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.712245] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.712276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.712309] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.712400] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.712433] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.712464] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.712516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.712571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.712603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.712635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.712664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.712695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.712728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.712760] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.712791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.712817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.712844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.712879] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.712908] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.714976] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.714997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.715020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.715044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.716643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.716664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.716685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.718241] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.718262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.720135] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.723454] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.723518] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.723613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.723686] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.723803] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.723855] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.740300] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.740351] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.740416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.740732] [drm:drm_mode_addfb2] [FB:77]
>[ 1340.740872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.773701] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.773778] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.773920] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.790988] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.791032] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.791064] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.791103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.791136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.791171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.791201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.791230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.791262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.791297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.791330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.791361] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.791391] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.791419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.791446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.791501] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.791621] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.791677] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.791710] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.791842] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.791855] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.791913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.791934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.791957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.791982] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.792003] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.792024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.792046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.792066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.792086] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.792104] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.792123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.792128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.792146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.792150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.792169] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.792186] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.792205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.792222] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.792244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.792262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.792281] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.792298] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.792316] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.792337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.792360] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.792409] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.792429] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.792450] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.792490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.792516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.792571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.792601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.792630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.792659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.792691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.792721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.792750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.792777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.792803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.792835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.792865] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.794927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.794947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.794966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.794985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.796567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.796587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.796610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.798175] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.798197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.800064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.803388] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.803451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.803491] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.803542] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.803717] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.803770] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.820223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.820270] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.820333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.820770] [drm:drm_mode_addfb2] [FB:79]
>[ 1340.820939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.853595] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.853641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.853730] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.870897] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.870940] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.870973] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.871010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.871044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.871079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.871109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.871138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.871169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.871204] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.871237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.871268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.871298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.871326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.871353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.871407] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.871448] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.871499] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.871597] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.871782] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.871804] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.871913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.871954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.871996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.872043] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.872082] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.872123] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.872164] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.872203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.872242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.872280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.872316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.872325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.872359] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.872368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.872406] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.872442] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.872478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.872520] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.872585] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.872614] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.872645] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.872677] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.872708] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.872742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.872777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.872867] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.872900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.872930] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.872980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.873013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.873044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.873075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.873105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.873136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.873170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.873202] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.873235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.873264] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.873293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.873327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.873359] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.875424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.875445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.875464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.875483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.877103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.877123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.877141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.878706] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.878727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.880592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.883850] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.883909] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.883929] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.883954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.884016] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.884038] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.900707] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.900759] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.900830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.901014] [drm:drm_mode_addfb2] [FB:78]
>[ 1340.901154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.934054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1340.934102] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1340.934173] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1340.951200] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1340.951244] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1340.951277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1340.951315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.951349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.951385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.951416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.951446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.951478] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.951513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.951630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.951680] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.951732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.951776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.951817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.951903] [drm:intel_power_well_disable [i915]] disabling display
>[ 1340.951974] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1340.952039] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.952081] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1340.952236] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1340.952254] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1340.952346] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1340.952367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1340.952390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1340.952414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1340.952434] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1340.952460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1340.952486] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1340.952515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1340.952570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1340.952600] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1340.952627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1340.952635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.952661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1340.952669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1340.952696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1340.952723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1340.952749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1340.952775] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1340.952806] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1340.952832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1340.952859] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1340.952885] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1340.952912] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1340.952945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1340.953154] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1340.953216] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1340.953236] [drm:intel_power_well_enable [i915]] enabling display
>[ 1340.953254] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1340.953290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1340.953311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1340.953336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1340.953362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1340.953389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1340.953415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1340.953442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1340.953471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1340.953499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.953527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1340.953581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1340.953615] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1340.953646] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1340.955842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1340.955863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1340.955886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.955910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1340.957514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1340.957547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1340.957566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1340.959201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1340.959222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1340.961085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1340.964404] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1340.964468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1340.964509] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1340.964607] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1340.964682] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1340.964715] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1340.981251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1340.981300] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1340.981365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1340.981658] [drm:drm_mode_addfb2] [FB:77]
>[ 1340.981863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.014593] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.014646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.014722] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.031747] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.031791] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.031824] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.031863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.031896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.031932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.031963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.031993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.032025] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.032060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.032094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.032134] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.032161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.032186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.032220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.032272] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.032313] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.032358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.032393] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.032620] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.032648] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.032781] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.032825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.032873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.032923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.032962] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.033007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.033049] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.033091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.033132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.033177] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.033208] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.033217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.033248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.033256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.033292] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.033323] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.033357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.033389] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.033426] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.033456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.033491] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.033522] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.033589] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.033627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.033668] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.033760] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.033797] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.033833] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.033891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.033924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.033959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.033991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.034026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.034058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.034096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.034133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.034176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.034202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.034230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.034264] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.034292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.036364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.036384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.036402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.036421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.038004] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.038026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.038049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.039663] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.039685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.041573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.044918] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.045011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.045051] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.045103] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.045185] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.045222] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.061791] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.061841] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.061906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.062105] [drm:drm_mode_addfb2] [FB:79]
>[ 1341.062222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.095134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.095183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.095256] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.112363] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.112407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.112439] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.112477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.112510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.112635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.112686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.112735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.112787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.112839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.112874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.112907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.112944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.112968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.112994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.113032] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.113064] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.113097] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.113123] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.113220] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.113232] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.113291] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.113313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.113337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.113361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.113382] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.113404] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.113425] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.113451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.113477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.113505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.113554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.113564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.113592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.113600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.113629] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.113657] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.113685] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.113712] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.113742] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.113769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.113795] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.113821] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.113848] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.113880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.113912] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.113988] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.114017] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.114049] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.114100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.114132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.114163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.114193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.114222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.114253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.114287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.114321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.114352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.114372] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.114396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.114423] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.114449] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.116493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.116514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.116589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.116623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.118185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.118206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.118224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.119784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.119806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.121670] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.125018] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.125105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.125141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.125167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.125227] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.125249] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.141881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.141931] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.142001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.142206] [drm:drm_mode_addfb2] [FB:78]
>[ 1341.142335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.175209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.175254] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.175323] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.192378] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.192422] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.192454] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.192492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.192615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.192663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.192694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.192724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.192764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.192797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.192827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.192864] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.192903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.192938] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.192973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.193025] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.193068] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.193112] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.193147] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.193289] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.193306] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.193387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.193418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.193451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.193487] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.193527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.193615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.193658] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.193698] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.193738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.193776] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.193820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.193830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.193860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.193869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.193900] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.193930] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.193961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.193990] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.194027] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.194061] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.194092] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.194126] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.194159] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.194195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.194235] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.194322] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.194359] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.194394] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.194453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.194490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.194547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.194579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.194611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.194643] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.194680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.194715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.194751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.194781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.194818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.194853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.194885] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.196947] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.196968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.196987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.197006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.198620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.198643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.198666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.200226] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.200248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.202120] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.205440] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.205502] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.205615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.205687] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.205976] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.205998] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.222285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.222335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.222400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.222718] [drm:drm_mode_addfb2] [FB:77]
>[ 1341.222873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.255630] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.255678] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.255751] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.272777] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.272821] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.272853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.272892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.272927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.272963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.272994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.273033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.273072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.273118] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.273161] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.273203] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.273245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.273285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.273324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.273382] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.273429] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.273479] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.273526] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.273721] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.273734] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.273793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.273819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.273846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.273875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.273900] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.273927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.273953] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.273979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.274006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.274031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.274057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.274063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.274088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.274093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.274119] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.274144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.274170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.274196] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.274222] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.274247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.274274] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.274299] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.274326] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.274353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.274381] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.274443] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.274466] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.274487] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.274560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.274592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.274621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.274649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.274677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.274706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.274738] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.274769] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.274800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.274826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.274852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.274884] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.274914] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.276994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.277015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.277033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.277053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.278624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.278644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.278666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.280214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.280236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.282099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.285428] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.285481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.285514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.285649] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.285948] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.285976] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.302266] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.302315] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.302382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.302700] [drm:drm_mode_addfb2] [FB:79]
>[ 1341.302885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.335608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.335656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.335729] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.352756] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.352800] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.352833] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.352870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.352904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.352939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.352971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.353001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.353033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.353068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.353101] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.353133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.353165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.353193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.353231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.353289] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.353335] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.353386] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.353431] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.353578] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.353598] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.353695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.353726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.353760] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.353797] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.353825] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.353857] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.353887] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.353917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.353945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.353974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.354000] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.354007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.354033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.354040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.354069] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.354095] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.354123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.354148] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.354179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.354205] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.354234] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.354260] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.354287] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.354317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.354349] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.354429] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.354460] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.354489] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.354576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.354609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.354640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.354670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.354698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.354729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.354764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.354797] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.354832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.354859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.354888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.354923] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.354951] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.357023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.357045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.357063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.357082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.358664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.358684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.358702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.360254] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.360275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.362147] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.365466] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.365605] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.365657] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.365703] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.365778] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.365810] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.382314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.382366] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.382437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.382773] [drm:drm_mode_addfb2] [FB:78]
>[ 1341.382906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.415656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.415705] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.415777] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.432807] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.432852] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.432884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.432922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.432955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.432990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.433021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.433060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.433100] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.433145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.433188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.433230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.433277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.433297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.433316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.433349] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.433374] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.433401] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.433423] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.433577] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.433597] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.433696] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.433727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.433763] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.433799] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.433827] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.433859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.433892] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.433921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.433951] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.433977] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.434005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.434012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.434040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.434047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.434076] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.434104] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.434132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.434157] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.434188] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.434214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.434242] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.434268] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.434295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.434325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.434358] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.434439] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.434470] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.434500] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.434588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.434618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.434650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.434678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.434707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.434736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.434770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.434804] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.434839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.434866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.434895] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.434929] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.434958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.437029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.437050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.437069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.437088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.438669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.438692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.438715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.440275] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.440297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.442173] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.445464] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.445617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.445650] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.445696] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.445768] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.445802] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.462336] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.462386] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.462451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.462772] [drm:drm_mode_addfb2] [FB:77]
>[ 1341.462895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.495684] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.495733] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.495821] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.512839] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.512883] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.512915] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.512953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.512987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.513022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.513053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.513082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.513121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.513166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.513209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.513251] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.513295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.513322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.513348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.513393] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.513428] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.513465] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.513494] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.513720] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.513743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.513860] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.513904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.513940] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.513973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.514001] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.514036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.514070] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.514105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.514139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.514173] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.514206] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.514214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.514246] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.514253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.514295] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.514320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.514343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.514364] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.514389] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.514411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.514431] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.514452] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.514471] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.514494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.514562] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.514661] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.514695] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.514729] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.514786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.514821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.514855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.514887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.514920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.514954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.514980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.515002] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.515024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.515044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.515064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.515092] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.515121] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.517176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.517197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.517216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.517234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.518800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.518820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.518839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.520387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.520409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.522276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.525552] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.525590] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.525609] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.525635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.525694] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.525723] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.542390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.542439] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.542504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.542867] [drm:drm_mode_addfb2] [FB:79]
>[ 1341.542982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.575736] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.575788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.575881] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.592887] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.592931] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.592964] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.593002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.593036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.593072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.593103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.593131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.593163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.593208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.593239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.593269] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.593298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.593324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.593350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.593401] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.593439] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.593479] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.593591] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.593794] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.593820] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.593952] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.593995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.594031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.594069] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.594099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.594131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.594163] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.594193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.594229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.594249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.594267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.594272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.594290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.594294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.594312] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.594330] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.594348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.594366] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.594387] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.594405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.594423] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.594440] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.594458] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.594479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.594534] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.594624] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.594654] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.594686] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.594739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.594771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.594803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.594833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.594862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.594894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.594923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.594944] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.594965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.594983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.595001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.595027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.595054] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.597104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.597125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.597144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.597162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.598741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.598762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.598780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.600327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.600349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.602213] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.605489] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.605584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.605605] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.605638] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.605694] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.605720] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.622374] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.622421] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.622483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.622788] [drm:drm_mode_addfb2] [FB:78]
>[ 1341.622937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.655720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.655766] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.655835] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.673155] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.673226] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.673277] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.673338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.673391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.673459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.673525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.673688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.673765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.673853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.673937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.674013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.674094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.674170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.674243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.674379] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.674469] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.674619] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.674711] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.675055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.675089] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.675228] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.675292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.675359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.675431] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.675494] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.675606] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.675659] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.675704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.675750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.675792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.675834] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.675847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.675887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.675899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.675945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.675987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.676029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.676075] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.676126] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.676171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.676215] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.676260] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.676305] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.676353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.676392] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.676469] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.676544] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.676587] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.676669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.676718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.676766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.676813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.676859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.676907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.676944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.676977] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.677008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.677047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.677069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.677097] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.677124] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.679210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.679232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.679251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.679270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.680845] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.680865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.680883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.682443] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.682465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.684365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.687700] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.687799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.687832] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.687874] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.687952] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.687984] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.704581] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.704631] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.704695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.704877] [drm:drm_mode_addfb2] [FB:77]
>[ 1341.705012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.737925] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.737973] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.738045] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.755072] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.755116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.755155] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.755200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.755241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.755286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.755326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.755366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.755406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.755451] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.755494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.755615] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.755669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.755716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.755764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.755849] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.755895] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.755925] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.755947] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.756055] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.756067] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.756124] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.756146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.756169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.756194] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.756214] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.756236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.756257] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.756278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.756299] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.756317] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.756341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.756347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.756372] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.756377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.756403] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.756429] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.756455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.756483] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.756575] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.756607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.756637] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.756665] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.756693] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.756725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.756757] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.756843] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.756864] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.756882] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.756916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.756936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.756961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.756987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.757012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.757038] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.757067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.757094] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.757122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.757148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.757174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.757200] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.757227] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.759275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.759299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.759322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.759346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.760924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.760945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.760964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.762542] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.762566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.764426] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.767773] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.767863] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.767903] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.767955] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.768037] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.768077] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.784644] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.784694] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.784764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.784968] [drm:drm_mode_addfb2] [FB:79]
>[ 1341.785105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.817986] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.818034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.818107] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.835141] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.835184] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.835217] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.835255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.835288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.835323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.835354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.835383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.835414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.835449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.835482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.835592] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.835641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.835683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.835732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.835788] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.835834] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.835876] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.835913] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.836027] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.836039] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.836098] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.836124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.836151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.836181] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.836206] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.836233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.836259] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.836285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.836311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.836337] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.836362] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.836368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.836393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.836397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.836423] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.836445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.836473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.836537] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.836570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.836600] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.836629] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.836657] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.836685] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.836717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.836749] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.836826] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.836857] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.836888] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.836943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.836976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.837006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.837037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.837066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.837098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.837132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.837162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.837183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.837202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.837220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.837243] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.837264] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.839313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.839334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.839353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.839372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.840945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.840965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.840987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.842544] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.842566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.844434] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.847779] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.847869] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.847911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.847945] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.848008] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.848034] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.864651] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.864701] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.864767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.864966] [drm:drm_mode_addfb2] [FB:78]
>[ 1341.865098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.897994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.898042] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.898114] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.915174] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.915218] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.915250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.915293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.915334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.915379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.915419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.915459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.915499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.915621] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.915683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.915729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.915774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.915814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.915854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.915925] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.915984] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.916039] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.916072] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.916194] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.916209] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.916284] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.916312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.916342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.916374] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.916407] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.916443] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.916481] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.916558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.916599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.916637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.916682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.916690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.916717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.916724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.916752] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.916779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.916806] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.916832] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.916862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.916890] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.916917] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.916943] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.916969] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.917001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.917036] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.917099] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.917119] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.917137] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.917171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.917191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.917210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.917228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.917246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.917266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.917287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.917308] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.917328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.917352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.917378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.917404] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.917431] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.919521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.919542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.919561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.919580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1341.921164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1341.921185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1341.921203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.922765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1341.922786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1341.924659] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1341.927993] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1341.928086] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1341.928112] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1341.928146] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1341.928208] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1341.928234] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1341.944876] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.944926] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.944991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.945188] [drm:drm_mode_addfb2] [FB:77]
>[ 1341.945303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.978221] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1341.978270] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1341.978342] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1341.995375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1341.995418] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1341.995451] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1341.995489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.995611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.995668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.995718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.995766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.995809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1341.995855] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.995898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.995943] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.995986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.996027] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.996067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.996125] [drm:intel_power_well_disable [i915]] disabling display
>[ 1341.996173] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1341.996223] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1341.996263] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1341.996409] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1341.996429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1341.996563] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1341.996594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1341.996628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1341.996663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1341.996692] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1341.996726] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1341.996758] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1341.996787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1341.996819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1341.996849] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1341.996878] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1341.996886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.996915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1341.996922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1341.996951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1341.996981] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1341.997005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1341.997024] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1341.997045] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1341.997070] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1341.997095] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1341.997121] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1341.997147] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1341.997174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1341.997202] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1341.997256] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1341.997279] [drm:intel_power_well_enable [i915]] enabling display
>[ 1341.997302] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1341.997340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1341.997366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1341.997393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1341.997419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1341.997445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1341.997471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1341.997528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1341.997563] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1341.997594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1341.997621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1341.997649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1341.997682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1341.997711] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1341.999781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1341.999802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1341.999821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1341.999841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.001400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.001420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.001439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.003037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.003061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.004940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.008281] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.008378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.008418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.008470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.008834] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.008859] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.025159] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.025208] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.025273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.025544] [drm:drm_mode_addfb2] [FB:79]
>[ 1342.025742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.058530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.058582] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.058660] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.075802] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.075846] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.075878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.075917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.075950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.075985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.076016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.076044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.076076] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.076111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.076144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.076176] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.076207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.076235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.076269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.076302] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.076327] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.076352] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.076372] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.076539] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.076559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.076644] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.076668] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.076692] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.076717] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.076738] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.076760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.076782] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.076803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.076824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.076843] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.076862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.076867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.076886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.076890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.076909] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.076927] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.076946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.076964] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.076986] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.077004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.077023] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.077041] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.077059] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.077081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.077105] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.077156] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.077176] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.077194] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.077228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.077248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.077266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.077285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.077303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.077322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.077343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.077363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.077389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.077415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.077440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.077467] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.077524] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.079595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.079617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.079636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.079654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.081221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.081245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.081270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.082828] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.082850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.084723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.088060] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.088159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.088192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.088235] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.088313] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.088347] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.104941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.104991] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.105057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.105255] [drm:drm_mode_addfb2] [FB:78]
>[ 1342.105385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.138284] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.138332] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.138404] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.155413] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.155458] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.155576] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.155634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.155684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.155736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.155779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.155825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.155872] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.155926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.155981] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.156013] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.156044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.156070] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.156098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.156152] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.156196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.156236] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.156270] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.156429] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.156442] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.156577] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.156606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.156632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.156662] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.156687] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.156713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.156739] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.156765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.156791] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.156817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.156842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.156848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.156873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.156878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.156903] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.156929] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.156955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.156980] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.157007] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.157032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.157058] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.157084] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.157110] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.157137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.157166] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.157220] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.157243] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.157265] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.157304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.157330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.157357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.157384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.157409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.157435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.157463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.157517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.157552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.157581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.157609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.157643] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.157672] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.159745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.159766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.159785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.159804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.161365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.161385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.161403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.162943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.162966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.164826] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.168123] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.168209] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.168234] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.168268] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.168330] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.168359] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.184994] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.185044] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.185109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.185309] [drm:drm_mode_addfb2] [FB:77]
>[ 1342.185439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.218336] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.218384] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.218456] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.235554] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.235598] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.235631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.235674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.235716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.235760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.235801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.235841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.235881] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.235925] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.235968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.236010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.236052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.236092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.236131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.236189] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.236235] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.236286] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.236325] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.236575] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.236601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.236730] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.236776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.236824] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.236874] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.236915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.236954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.236988] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.237022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.237057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.237091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.237124] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.237132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.237165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.237171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.237205] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.237239] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.237273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.237306] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.237341] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.237374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.237409] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.237442] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.237479] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.237562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.237613] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.237699] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.237731] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.237765] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.237824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.237860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.237894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.237928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.237960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.237984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.238009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.238032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.238054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.238074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.238095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.238123] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.238152] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.240206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.240227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.240245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.240264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.241851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.241875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.241898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.243469] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.243507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.245378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.248745] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.248797] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.248820] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.248852] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.248914] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.248939] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.265595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.265645] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.265709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.265908] [drm:drm_mode_addfb2] [FB:79]
>[ 1342.266042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.298938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.298987] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.299061] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.316095] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.316139] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.316171] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.316209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.316242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.316278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.316309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.316339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.316370] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.316421] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.316453] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.316569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.316619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.316661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.316701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.316782] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.316849] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.316910] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.316964] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.317129] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.317148] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.317230] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.317262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.317295] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.317332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.317361] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.317394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.317434] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.317459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.317517] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.317545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.317572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.317581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.317607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.317615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.317642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.317669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.317695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.317721] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.317751] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.317777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.317805] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.317831] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.317860] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.317892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.317927] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.318005] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.318038] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.318069] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.318122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.318152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.318173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.318192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.318210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.318230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.318253] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.318273] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.318294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.318312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.318331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.318354] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.318375] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.320417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.320438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.320461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.320541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.322092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.322114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.322134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.323695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.323717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.325578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.328887] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.328957] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.328991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.329036] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.329106] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.329139] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.345744] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.345794] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.345859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.346053] [drm:drm_mode_addfb2] [FB:78]
>[ 1342.346167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.379088] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.379140] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.379218] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.396283] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.396326] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.396359] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.396397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.396431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.396465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.396579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.396625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.396677] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.396735] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.396787] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.396839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.396889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.396930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.396974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.397058] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.397122] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.397184] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.397237] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.397385] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.397398] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.397467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.397532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.397570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.397608] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.397639] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.397673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.397708] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.397739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.397771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.397802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.397831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.397839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.397868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.397875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.397905] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.397934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.397964] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.397993] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.398026] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.398055] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.398082] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.398112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.398142] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.398175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.398209] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.398286] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.398318] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.398348] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.398399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.398430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.398462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.398512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.398544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.398573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.398608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.398642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.398675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.398705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.398735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.398770] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.398802] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.400873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.400894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.400912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.400931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.402523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.402543] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.402561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.404135] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.404159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.406023] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.409343] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.409411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.409432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.409458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.409581] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.409611] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.426191] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.426240] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.426306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.426601] [drm:drm_mode_addfb2] [FB:77]
>[ 1342.426795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.459533] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.459582] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.459654] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.476686] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.476730] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.476763] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.476802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.476835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.476870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.476901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.476930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.476962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.476998] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.477032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.477063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.477104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.477141] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.477159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.477192] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.477217] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.477243] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.477264] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.477388] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.477402] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.477473] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.477536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.477574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.477612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.477641] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.477675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.477706] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.477738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.477766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.477797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.477824] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.477832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.477859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.477866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.477895] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.477922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.477951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.477977] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.478008] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.478034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.478062] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.478088] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.478115] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.478148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.478182] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.478259] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.478291] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.478320] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.478369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.478398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.478427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.478454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.478506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.478538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.478572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.478605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.478640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.478667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.478696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.478731] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.478760] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.480831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.480852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.480870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.480889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.482459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.482497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.482515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.484081] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.484104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.485989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.489310] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.489366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.489386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.489411] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.489525] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.489555] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.506149] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.506196] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.506259] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.506531] [drm:drm_mode_addfb2] [FB:79]
>[ 1342.506720] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.539524] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.539569] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.539638] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.556648] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.556692] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.556724] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.556763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.556796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.556830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.556860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.556889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.556920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.556954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.556986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.557018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.557049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.557077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.557104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.557156] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.557197] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.557238] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.557277] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.557510] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.557542] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.557690] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.557741] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.557792] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.557848] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.557893] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.557943] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.557993] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.558035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.558074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.558114] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.558150] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.558159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.558196] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.558206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.558246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.558282] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.558321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.558356] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.558399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.558436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.558514] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.558553] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.558596] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.558645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.558694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.558820] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.558863] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.558903] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.558978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.559007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.559037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.559064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.559093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.559122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.559154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.559186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.559217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.559243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.559272] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.559306] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.559334] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.561403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.561423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.561441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.561505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.563067] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.563086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.563104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.564685] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.564708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.566571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.569918] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.570006] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.570038] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.570088] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.570169] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.570191] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.586789] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.586839] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.586904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.587086] [drm:drm_mode_addfb2] [FB:78]
>[ 1342.587220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.620132] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.620180] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.620252] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.637264] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.637308] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.637340] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.637378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.637411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.637447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.637569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.637613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.637665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.637718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.637749] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.637779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.637807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.637832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.637857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.637905] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.637942] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.637980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.638011] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.638151] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.638168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.638245] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.638273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.638304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.638344] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.638379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.638417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.638459] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.638536] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.638577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.638616] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.638661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.638668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.638695] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.638703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.638731] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.638758] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.638785] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.638811] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.638842] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.638869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.638896] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.638922] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.638948] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.638978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.639013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.639094] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.639113] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.639134] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.639173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.639199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.639226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.639252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.639278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.639303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.639332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.639360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.639387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.639413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.639438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.639492] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.639523] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.641593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.641617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.641640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.641664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.643236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.643257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.643276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.644840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.644861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.646733] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.649991] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.650051] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.650070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.650096] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.650157] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.650178] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.666850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.666900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.666965] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.667162] [drm:drm_mode_addfb2] [FB:77]
>[ 1342.667297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.700192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.700240] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.700313] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.717348] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.717392] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.717424] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.717544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.717598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.717654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.717704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.717746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.717780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.717824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.717868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.717912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.717956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.717996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.718036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.718094] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.718141] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.718192] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.718232] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.718395] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.718413] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.718579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.718610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.718644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.718683] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.718712] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.718747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.718771] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.718792] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.718812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.718830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.718848] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.718853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.718871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.718876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.718894] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.718912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.718930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.718947] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.718969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.718986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.719006] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.719023] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.719041] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.719063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.719087] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.719136] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.719155] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.719173] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.719207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.719226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.719245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.719263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.719282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.719301] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.719322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.719342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.719362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.719380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.719397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.719420] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.719444] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.721536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.721557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.721576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.721597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.723160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.723180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.723198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.724749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.724769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.726640] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.729904] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.729956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.729975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.730001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.730062] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.730083] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.746734] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.746779] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.746841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.747034] [drm:drm_mode_addfb2] [FB:79]
>[ 1342.747144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.780155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.780239] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.780358] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.797360] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.797404] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.797444] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.797573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.797627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.797686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.797735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.797770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.797802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.797840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.797875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.797907] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.797939] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.797968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.797996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.798051] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.798092] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.798134] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.798168] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.798309] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.798327] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.798418] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.798444] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.798508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.798543] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.798571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.798602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.798632] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.798661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.798690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.798717] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.798743] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.798751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.798777] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.798786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.798816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.798845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.798872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.798900] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.798925] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.798944] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.798969] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.798994] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.799020] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.799047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.799075] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.799128] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.799151] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.799173] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.799211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.799237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.799264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.799290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.799317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.799343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.799371] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.799398] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.799425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.799477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.799509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.799542] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.799572] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.801645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.801666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.801685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.801707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.803279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.803299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.803318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.804881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.804902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.806765] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.810112] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.810200] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.810232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.810274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.810351] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.810384] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.826982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.827032] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.827098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.827295] [drm:drm_mode_addfb2] [FB:78]
>[ 1342.827411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.860325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.860373] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.860445] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.877570] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.877618] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.877659] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.877703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.877744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.877789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.877829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.877869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.877908] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.877953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.877996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.878038] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.878072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.878095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.878118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.878154] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.878183] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.878213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.878236] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.878363] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.878375] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.878443] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.878515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.878548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.878586] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.878615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.878647] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.878677] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.878707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.878736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.878763] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.878790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.878798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.878827] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.878834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.878864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.878893] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.878920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.878949] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.878981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.879010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.879039] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.879068] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.879097] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.879131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.879165] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.879245] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.879267] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.879285] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.879320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.879341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.879360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.879379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.879397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.879416] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.879438] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.879498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.879529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.879556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.879583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.879616] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.879644] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.881713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.881734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.881752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.881776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.883342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.883363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.883381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.884937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.884958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.886865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.890207] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.890282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.890302] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.890328] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.890390] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.890411] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.907089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.907139] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.907204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.907408] [drm:drm_mode_addfb2] [FB:77]
>[ 1342.907826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.940493] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1342.940542] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1342.940616] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1342.957640] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1342.957683] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1342.957716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1342.957755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.957788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.957824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.957854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.957883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.957915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.957951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.957983] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.958015] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.958046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.958074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.958102] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.958155] [drm:intel_power_well_disable [i915]] disabling display
>[ 1342.958196] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1342.958238] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.958272] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1342.958501] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1342.958533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1342.958683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1342.958732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1342.958793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1342.958844] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1342.958883] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1342.958928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1342.958969] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1342.959012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1342.959051] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1342.959091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1342.959128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1342.959138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.959175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1342.959184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1342.959224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1342.959261] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1342.959300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1342.959336] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1342.959379] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1342.959416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1342.959496] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1342.959535] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1342.959576] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1342.959624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1342.959672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1342.959775] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1342.959817] [drm:intel_power_well_enable [i915]] enabling display
>[ 1342.959846] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1342.959896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1342.959927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1342.959955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1342.959984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1342.960010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1342.960039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1342.960071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1342.960102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1342.960134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.960164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1342.960189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1342.960222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1342.960250] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1342.962328] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1342.962349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1342.962372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.962396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1342.964020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1342.964041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1342.964064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1342.965625] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1342.965647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1342.967515] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1342.970862] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1342.970957] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1342.970981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1342.971012] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1342.971074] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1342.971104] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1342.987732] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1342.987783] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1342.987848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1342.988053] [drm:drm_mode_addfb2] [FB:79]
>[ 1342.988205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.021076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.021129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.021221] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.038230] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.038274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.038307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.038347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.038381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.038416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.038529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.038580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.038626] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.038689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.038722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.038750] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.038777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.038801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.038825] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.038870] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.038905] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.038941] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.038971] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.039105] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.039121] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.039193] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.039220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.039250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.039283] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.039309] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.039337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.039364] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.039391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.039417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.039497] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.039534] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.039545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.039580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.039590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.039625] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.039670] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.039699] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.039728] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.039760] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.039788] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.039817] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.039845] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.039873] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.039907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.039942] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.040026] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.040056] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.040076] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.040112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.040134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.040156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.040176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.040196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.040217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.040240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.040262] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.040284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.040305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.040324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.040349] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.040371] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.042415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.042452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.042471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.042490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.044057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.044077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.044095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.045658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.045679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.047538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.050891] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.050966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.050991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.051025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.051103] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.051143] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.067755] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.067805] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.067871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.068096] [drm:drm_mode_addfb2] [FB:78]
>[ 1343.068239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.101099] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.101152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.101245] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.118310] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.118354] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.118386] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.118429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.118551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.118610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.118660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.118709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.118753] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.118791] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.118825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.118857] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.118889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.118918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.118946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.119000] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.119041] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.119084] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.119118] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.119273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.119291] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.119376] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.119410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.119459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.119535] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.119563] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.119594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.119624] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.119653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.119682] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.119710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.119737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.119745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.119771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.119778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.119808] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.119836] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.119863] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.119889] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.119923] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.119945] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.119964] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.119982] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.120001] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.120022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.120046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.120097] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.120116] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.120134] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.120167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.120187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.120206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.120225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.120243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.120262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.120284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.120304] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.120323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.120341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.120366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.120393] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.120420] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.122511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.122532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.122550] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.122574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.124146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.124166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.124184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.125747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.125768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.127638] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.130868] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.130902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.130921] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.130947] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.131005] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.131034] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.147679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.147725] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.147788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.148006] [drm:drm_mode_addfb2] [FB:77]
>[ 1343.148146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.181083] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.181148] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.181266] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.198343] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.198387] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.198420] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.198545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.198592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.198646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.198689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.198737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.198782] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.198836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.198887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.198936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.198985] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.199026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.199069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.199153] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.199217] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.199279] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.199332] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.199540] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.199560] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.199637] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.199669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.199691] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.199713] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.199732] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.199755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.199779] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.199802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.199826] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.199847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.199870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.199875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.199898] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.199902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.199925] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.199946] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.199969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.199989] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.200013] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.200036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.200060] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.200083] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.200107] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.200132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.200157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.200217] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.200238] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.200258] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.200294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.200317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.200341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.200365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.200388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.200411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.200507] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.200543] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.200576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.200603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.200631] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.200665] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.200695] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.202784] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.202809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.202832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.202856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.204435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.204475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.204493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.206110] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.206133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.207998] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.211317] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.211381] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.211413] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.211526] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.211625] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.211654] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.228165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.228214] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.228279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.228735] [drm:drm_mode_addfb2] [FB:79]
>[ 1343.228853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.261507] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.261556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.261644] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.278707] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.278751] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.278783] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.278821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.278855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.278890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.278920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.278949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.278980] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.279016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.279048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.279080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.279111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.279146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.279169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.279215] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.279249] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.279284] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.279313] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.279503] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.279529] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.279893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.279926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.279957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.279991] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.280018] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.280047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.280076] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.280103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.280137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.280172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.280193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.280200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.280220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.280225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.280248] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.280269] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.280290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.280309] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.280334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.280362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.280392] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.280421] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.280485] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.280524] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.280561] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.280827] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.280850] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.280870] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.280911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.280937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.280960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.280982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.281003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.281026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.281051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.281074] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.281097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.281118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.281138] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.281171] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.281192] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.283239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.283262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.283287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.283313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.284886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.284907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.284930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.286532] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.286554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.288423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.291768] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.291818] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.291849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.291889] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.291980] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.292028] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.308583] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.308630] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.308693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.308915] [drm:drm_mode_addfb2] [FB:78]
>[ 1343.309053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.341946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.341995] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.342084] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.359129] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.359173] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.359206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.359244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.359278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.359313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.359344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.359374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.359406] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.359526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.359581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.359630] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.359684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.359733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.359780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.359866] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.359933] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.359986] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.360009] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.360111] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.360123] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.360179] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.360200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.360227] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.360256] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.360282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.360308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.360334] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.360361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.360387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.360416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.360472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.360481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.360510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.360517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.360547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.360575] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.360603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.360629] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.360660] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.360687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.360714] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.360740] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.360767] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.360799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.360831] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.360908] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.360933] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.360950] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.360985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.361006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.361025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.361044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.361063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.361082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.361104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.361124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.361144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.361162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.361180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.361202] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.361223] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.363268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.363289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.363308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.363327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.364903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.364922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.364940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.366528] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.366550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.368411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.371768] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.371857] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.371890] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.371932] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.372028] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.372079] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.388639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.388689] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.388753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.388981] [drm:drm_mode_addfb2] [FB:77]
>[ 1343.389124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.421982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.422030] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.422119] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.439135] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.439179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.439210] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.439249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.439282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.439318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.439349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.439378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.439410] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.439531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.439585] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.439633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.439685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.439720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.439748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.439802] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.439844] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.439882] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.439904] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.440010] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.440023] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.440078] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.440099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.440122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.440148] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.440174] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.440201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.440227] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.440253] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.440279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.440305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.440330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.440336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.440361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.440366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.440392] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.440423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.440488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.440517] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.440549] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.440578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.440606] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.440633] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.440660] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.440692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.440725] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.440803] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.440835] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.440865] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.440903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.440923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.440943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.440962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.440981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.441000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.441022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.441043] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.441063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.441081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.441099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.441122] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.441142] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.443189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.443210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.443228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.443247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.444812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.444835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.444858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.446422] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.446461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.448329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.451679] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.451765] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.451803] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.451855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.451954] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.452006] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.468545] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.468598] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.468669] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.468897] [drm:drm_mode_addfb2] [FB:79]
>[ 1343.469043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.501888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.501937] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.502027] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.519049] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.519093] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.519125] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.519164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.519198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.519234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.519264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.519294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.519326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.519361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.519394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.519505] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.519554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.519597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.519640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.519726] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.519787] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.519830] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.519866] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.519990] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.520003] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.520059] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.520081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.520106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.520135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.520160] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.520187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.520213] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.520240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.520266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.520291] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.520316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.520322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.520347] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.520352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.520378] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.520406] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.520470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.520500] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.520532] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.520561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.520590] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.520618] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.520644] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.520675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.520708] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.520785] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.520814] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.520844] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.520896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.520928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.520959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.520989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.521020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.521050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.521084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.521117] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.521143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.521162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.521180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.521203] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.521224] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.523266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.523286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.523305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.523324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.524877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.524907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.524925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.526509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.526530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.528404] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.531759] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.531849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.531882] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.531924] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.531999] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.532029] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.548609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.548658] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.548728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.548953] [drm:drm_mode_addfb2] [FB:78]
>[ 1343.549097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.581975] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.582028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.582121] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.599125] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.599170] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.599202] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.599241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.599275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.599310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.599340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.599370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.599402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.599508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.599559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.599612] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.599661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.599703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.599746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.599802] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.599848] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.599890] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.599914] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.600023] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.600036] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.600094] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.600116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.600139] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.600164] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.600184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.600206] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.600226] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.600246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.600265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.600284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.600302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.600307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.600328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.600333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.600359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.600385] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.600416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.600474] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.600505] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.600534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.600561] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.600588] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.600614] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.600646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.600677] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.600755] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.600788] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.600818] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.600871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.600903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.600933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.600964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.600992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.601013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.601036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.601056] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.601077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.601095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.601113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.601136] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.601156] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.603210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.603231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.603250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.603269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.604842] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.604862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.604880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.606458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.606479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.608349] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.611695] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.611787] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.611828] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.611888] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.611950] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.611980] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.628567] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.628617] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.628681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.628886] [drm:drm_mode_addfb2] [FB:77]
>[ 1343.629025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.661909] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.661958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.662046] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.679155] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.679203] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.679243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.679287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.679328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.679372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.679412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.679547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.679601] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.679658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.679709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.679757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.679806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.679848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.679893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.679975] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.680037] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.680096] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.680148] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.680334] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.680353] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.680518] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.680550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.680584] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.680621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.680649] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.680681] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.680717] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.680746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.680772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.680798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.680823] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.680829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.680854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.680860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.680887] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.680911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.680938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.680962] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.680991] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.681014] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.681040] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.681064] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.681090] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.681119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.681151] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.681222] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.681251] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.681278] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.681325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.681351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.681378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.681402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.681467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.681498] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.681532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.681565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.681598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.681625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.681655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.681691] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.681720] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.683807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.683829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.683847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.683867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.685460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.685484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.685507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.687080] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.687102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.688971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.692308] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.692406] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.692514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.692680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.692761] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.692791] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.709187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.709237] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.709302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.709660] [drm:drm_mode_addfb2] [FB:79]
>[ 1343.709800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.742532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.742580] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.742669] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.759689] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.759733] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.759766] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.759804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.759837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.759873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.759903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.759933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.759964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.759999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.760032] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.760064] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.760095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.760123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.760150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.760204] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.760245] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.760286] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.760320] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.760487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.760744] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.760841] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.760873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.760907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.760943] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.760972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.761005] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.761035] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.761065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.761094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.761122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.761148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.761156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.761182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.761189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.761218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.761246] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.761275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.761300] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.761333] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.761359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.761387] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.761452] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.761482] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.761516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.761552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.761874] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.761903] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.761930] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.761977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.762005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.762032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.762058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.762085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.762111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.762141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.762170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.762199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.762223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.762248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.762280] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.762306] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.764399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.764442] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.764465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.764489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.766056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.766078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.766096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.767651] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.767672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.769535] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.772802] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.772853] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.772876] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.772908] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.772972] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.772996] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.789653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.789703] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.789769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.790001] [drm:drm_mode_addfb2] [FB:78]
>[ 1343.790144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.822993] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.823042] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.823113] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.840137] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.840180] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.840212] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.840251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.840284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.840319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.840350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.840379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.840411] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.840534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.840588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.840641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.840691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.840733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.840781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.840865] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.840930] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.840993] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.841047] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.841273] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.841305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.841394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.841471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.841500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.841526] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.841547] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.841570] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.841592] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.841618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.841645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.841671] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.841696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.841702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.841727] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.841732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.841758] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.841784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.841810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.841835] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.841862] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.841887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.841914] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.841939] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.841963] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.841990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.842019] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.842074] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.842098] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.842119] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.842159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.842185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.842212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.842238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.842264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.842290] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.842318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.842346] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.842375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.842402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.842458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.842493] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.842523] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.844599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.844620] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.844639] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.844658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.846229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.846249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.846267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.847821] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.847841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.849714] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.853053] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.853149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.853182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.853224] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.853301] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.853335] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.869931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.869980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.870045] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.870271] [drm:drm_mode_addfb2] [FB:77]
>[ 1343.870415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.903274] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.903322] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.903394] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1343.920490] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1343.920534] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1343.920567] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1343.920605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.920638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.920673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.920704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.920733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.920765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.920800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.920834] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.920866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.920897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.920926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.920954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.921008] [drm:intel_power_well_disable [i915]] disabling display
>[ 1343.921053] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1343.921112] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.921133] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1343.921259] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1343.921271] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1343.921329] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1343.921353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1343.921376] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1343.921465] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1343.921496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1343.921531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1343.921562] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1343.921595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1343.921623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1343.921653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1343.921680] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1343.921690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.921717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1343.921725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1343.921756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1343.921783] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1343.921814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1343.921840] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1343.921873] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1343.921900] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1343.921929] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1343.921955] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1343.921984] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1343.922017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.922051] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1343.922131] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1343.922163] [drm:intel_power_well_enable [i915]] enabling display
>[ 1343.922192] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1343.922241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1343.922272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1343.922303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1343.922330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1343.922358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1343.922386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1343.922440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1343.922474] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1343.922508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.922535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1343.922564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1343.922600] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1343.922629] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1343.924720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1343.924744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1343.924768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.924792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1343.926407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1343.926445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1343.926464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1343.928032] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1343.928053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1343.929948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1343.933272] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1343.933341] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1343.933367] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1343.933401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1343.933686] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1343.933713] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1343.950115] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1343.950165] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1343.950230] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1343.950628] [drm:drm_mode_addfb2] [FB:79]
>[ 1343.950764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1343.983459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1343.983508] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1343.983581] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.000608] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.000652] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.000685] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.000723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.000756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.000791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.000822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.000851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.000883] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.000918] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.000951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.000983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.001022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.001046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.001069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.001114] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.001149] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.001185] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.001213] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.001371] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.001448] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.001578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.001610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.001642] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.001675] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.001700] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.001730] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.001758] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.001787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.001813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.001839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.001863] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.001871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.001894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.001900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.001934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.001968] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.002003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.002046] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.002075] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.002100] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.002126] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.002149] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.002172] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.002199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.002227] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.002290] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.002314] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.002335] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.002375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.002432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.002467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.002500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.002532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.002566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.002604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.002640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.002676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.002707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.002738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.002777] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.002812] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.004892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.004913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.004931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.004950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.006534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.006557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.006576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.008132] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.008154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.010030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.013325] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.013397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.013478] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.013524] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.013726] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.013747] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.030173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.030219] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.030281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.030590] [drm:drm_mode_addfb2] [FB:78]
>[ 1344.030730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.063539] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.063588] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.063661] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.080685] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.080729] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.080761] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.080800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.080833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.080869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.080908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.080948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.080988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.081033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.081076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.081118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.081160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.081199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.081238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.081296] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.081342] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.081392] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.081495] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.081700] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.081728] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.081851] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.081884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.081917] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.081954] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.081981] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.082013] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.082043] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.082073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.082101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.082130] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.082156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.082163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.082189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.082196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.082225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.082251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.082278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.082303] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.082334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.082360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.082389] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.082444] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.082471] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.082505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.082541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.082629] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.082660] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.082690] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.082738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.082767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.082796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.082824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.082852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.082880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.082914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.082947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.082978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.083004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.083032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.083063] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.083094] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.085163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.085187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.085210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.085234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.086809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.086829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.086847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.088397] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.088435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.090303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.093668] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.093737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.093769] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.093812] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.093889] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.093922] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.110520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.110570] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.110635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.110861] [drm:drm_mode_addfb2] [FB:77]
>[ 1344.110989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.143862] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.143911] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.143983] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.160989] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.161033] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.161066] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.161104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.161138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.161173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.161203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.161233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.161264] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.161299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.161332] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.161363] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.161394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.161508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.161550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.161642] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.161680] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.161708] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.161731] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.161837] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.161850] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.161906] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.161927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.161950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.161975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.161996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.162016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.162037] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.162057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.162077] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.162095] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.162113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.162118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.162137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.162141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.162159] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.162177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.162195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.162212] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.162233] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.162251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.162269] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.162287] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.162312] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.162339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.162367] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.162479] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.162509] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.162536] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.162590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.162623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.162652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.162682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.162708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.162729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.162751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.162771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.162792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.162810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.162828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.162850] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.162871] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.164916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.164939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.164962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.164986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.166561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.166582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.166601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.168158] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.168179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.170052] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.173371] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.173488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.173521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.173563] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.173641] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.173674] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.190269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.190321] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.190392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.190760] [drm:drm_mode_addfb2] [FB:79]
>[ 1344.190900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.223611] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.223664] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.223740] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.240764] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.240808] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.240840] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.240878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.240912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.240955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.240995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.241035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.241075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.241120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.241163] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.241205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.241247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.241287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.241326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.241384] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.241515] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.241575] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.241626] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.241813] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.241837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.241917] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.241946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.241977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.242014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.242047] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.242083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.242118] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.242152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.242186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.242221] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.242254] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.242261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.242294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.242300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.242334] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.242368] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.242439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.242485] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.242516] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.242545] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.242574] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.242603] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.242633] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.242665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.242697] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.242787] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.242820] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.242851] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.242904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.242936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.242969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.242998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.243018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.243039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.243062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.243083] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.243103] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.243121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.243139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.243162] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.243183] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.245227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.245247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.245266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.245285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.246857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.246877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.246895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.248492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.248513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.250385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.253735] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.253768] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.253787] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.253813] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.253873] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.253895] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.270568] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.270618] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.270682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.270906] [drm:drm_mode_addfb2] [FB:78]
>[ 1344.271049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.303911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.303964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.304041] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.321053] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.321097] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.321129] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.321167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.321200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.321235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.321274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.321315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.321354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.321400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.321527] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.321584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.321634] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.321682] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.321717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.321771] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.321813] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.321856] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.321891] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.322048] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.322066] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.322153] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.322185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.322221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.322260] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.322292] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.322324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.322367] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.322433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.322463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.322491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.322517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.322526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.322551] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.322559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.322586] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.322613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.322639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.322665] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.322695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.322721] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.322748] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.322775] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.322800] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.322833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.322866] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.322930] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.322950] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.322970] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.323009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.323035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.323061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.323087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.323113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.323139] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.323164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.323192] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.323219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.323245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.323271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.323298] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.323324] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.325392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.325430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.325453] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.325477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.327047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.327071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.327094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.328681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.328704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.330578] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.333912] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.334011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.334041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.334088] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.334166] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.334203] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.350795] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.350846] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.350917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.351143] [drm:drm_mode_addfb2] [FB:77]
>[ 1344.351289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.384140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.384188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.384261] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.401286] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.401330] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.401362] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.401495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.401549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.401605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.401654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.401702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.401752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.401808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.401861] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.401912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.401963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.402009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.402054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.402139] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.402195] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.402235] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.402277] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.402451] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.402471] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.402573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.402602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.402634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.402667] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.402693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.402723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.402750] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.402779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.402805] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.402833] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.402857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.402864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.402889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.402895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.402922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.402947] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.402973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.402996] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.403025] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.403049] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.403075] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.403099] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.403125] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.403155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.403186] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.403257] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.403286] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.403314] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.403360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.403439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.403469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.403500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.403528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.403559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.403594] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.403627] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.403661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.403688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.403719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.403751] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.403782] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.405882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.405906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.405927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.405948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.407514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.407534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.407552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.409113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.409134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.411008] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.414331] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.414373] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.414457] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.414503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.414577] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.414610] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.431174] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.431224] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.431289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.431615] [drm:drm_mode_addfb2] [FB:79]
>[ 1344.431787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.464517] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.464570] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.464645] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.481710] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.481753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.481786] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.481824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.481858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.481893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.481924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.481954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.481986] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.482028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.482072] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.482114] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.482157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.482196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.482236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.482293] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.482340] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.482390] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.482512] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.482708] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.482737] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.482879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.482927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.482965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.483003] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.483024] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.483046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.483067] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.483088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.483108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.483127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.483146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.483151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.483168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.483173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.483192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.483209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.483228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.483246] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.483268] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.483286] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.483305] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.483323] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.483341] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.483362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.483416] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.483489] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.483518] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.483549] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.483599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.483629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.483660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.483690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.483720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.483752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.483786] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.483819] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.483852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.483880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.483898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.483921] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.483942] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.485993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.486013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.486031] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.486050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.487625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.487646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.487664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.489221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.489242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.491114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.494332] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.494436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.494470] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.494516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.494582] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.494614] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.511179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.511231] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.511302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.511633] [drm:drm_mode_addfb2] [FB:78]
>[ 1344.511750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.544522] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.544571] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.544660] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.561679] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.561723] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.561755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.561793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.561826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.561862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.561892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.561921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.561952] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.561987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.562020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.562051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.562082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.562110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.562137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.562190] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.562231] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.562272] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.562305] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.562528] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.562556] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.562695] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.562747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.562802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.562859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.562892] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.562928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.562950] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.562971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.562991] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.563010] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.563028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.563033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.563057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.563061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.563088] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.563113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.563140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.563165] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.563191] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.563217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.563243] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.563269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.563295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.563322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.563350] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.563457] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.563490] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.563520] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.563576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.563609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.563642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.563674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.563704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.563736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.563770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.563793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.563819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.563844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.563871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.563898] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.563924] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.565979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.566000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.566019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.566041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.567628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.567651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.567670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.569235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.569257] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.571136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.574441] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.574514] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.574543] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.574581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.574650] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.574679] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.591308] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.591358] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.591521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.591733] [drm:drm_mode_addfb2] [FB:77]
>[ 1344.591857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.624684] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.624733] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.624807] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.641814] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.641857] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.641890] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.641928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.641961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.641996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.642025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.642054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.642085] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.642120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.642152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.642183] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.642214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.642241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.642268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.642321] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.642363] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.642493] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.642544] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.642758] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.642786] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.642884] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.642907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.642931] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.642957] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.642977] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.643003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.643029] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.643055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.643082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.643108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.643133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.643139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.643164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.643168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.643194] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.643217] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.643243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.643266] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.643291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.643317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.643342] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.643369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.643426] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.643461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.643495] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.643570] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.643602] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.643633] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.643687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.643720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.643751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.643782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.643812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.643833] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.643856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.643878] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.643899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.643917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.643935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.643962] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.643988] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.646037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.646058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.646076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.646095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.647683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.647706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.647725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.649284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.649306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.651180] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.654530] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.654615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.654647] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.654689] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.654786] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.654836] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.671428] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.671478] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.671544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.671745] [drm:drm_mode_addfb2] [FB:79]
>[ 1344.671874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.704739] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.704788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.704876] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.721922] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.721966] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.721999] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.722037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.722070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.722105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.722135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.722164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.722196] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.722231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.722264] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.722296] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.722328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.722356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.722462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.722545] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.722612] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.722683] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.722718] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.722872] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.722892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.722995] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.723027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.723059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.723093] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.723122] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.723153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.723184] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.723213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.723242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.723270] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.723297] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.723303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.723330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.723337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.723376] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.723468] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.723500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.723531] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.723565] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.723595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.723627] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.723657] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.723685] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.723719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.723754] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.723845] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.723879] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.723910] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.723962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.723994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.724026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.724054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.724084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.724115] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.724148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.724181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.724213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.724242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.724268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.724302] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.724333] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.726430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.726454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.726477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.726501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.728088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.728110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.728128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.729695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.729716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.731587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.734932] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.735005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.735025] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.735051] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.735111] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.735140] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.751803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.751853] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.751918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.752115] [drm:drm_mode_addfb2] [FB:78]
>[ 1344.752246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.785149] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.785197] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.785286] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.802280] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.802324] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.802356] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.802481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.802528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.802582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.802633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.802677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.802719] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.802770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.802818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.802865] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.802911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.802950] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.802991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.803072] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.803134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.803192] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.803242] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.803464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.803489] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.803633] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.803675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.803717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.803763] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.803792] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.803819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.803845] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.803868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.803892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.803914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.803936] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.803941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.803969] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.803975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.804005] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.804036] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.804066] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.804095] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.804125] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.804154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.804185] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.804215] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.804244] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.804276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.804308] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.804434] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.804475] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.804513] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.804577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.804619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.804660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.804693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.804723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.804757] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.804792] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.804826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.804859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.804890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.804920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.804954] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.804986] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.807076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.807100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.807123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.807148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.808726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.808747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.808765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.810353] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.810385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.812254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.815626] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.815687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.815721] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.815763] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.815838] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.815867] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.832473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.832522] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.832588] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.832788] [drm:drm_mode_addfb2] [FB:77]
>[ 1344.832921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.865815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.865863] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.865953] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.882965] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.883010] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.883042] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.883081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.883114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.883149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.883180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.883209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.883241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.883275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.883313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.883355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.883475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.883519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.883547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.883602] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.883648] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.883691] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.883727] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.883862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.883874] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.883932] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.883954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.883977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.884002] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.884023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.884044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.884066] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.884087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.884107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.884126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.884144] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.884149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.884168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.884172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.884191] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.884209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.884227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.884245] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.884266] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.884284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.884303] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.884321] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.884338] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.884400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.884433] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.884507] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.884536] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.884566] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.884616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.884646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.884675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.884697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.884716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.884737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.884764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.884792] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.884820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.884845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.884871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.884898] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.884924] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.886980] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.887001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.887020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.887040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.888616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.888639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.888662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.890223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.890245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.892118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.895467] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.895554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.895586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.895628] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.895725] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.895777] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.912333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.912465] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.912567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.912782] [drm:drm_mode_addfb2] [FB:79]
>[ 1344.912896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.945678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1344.945727] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1344.945816] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1344.962835] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1344.962878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1344.962910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1344.962949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.962982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.963018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.963048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.963077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.963108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.963143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.963176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.963207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.963238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.963265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.963292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.963339] [drm:intel_power_well_disable [i915]] disabling display
>[ 1344.963428] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1344.963472] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.963506] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1344.963615] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1344.963627] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1344.963684] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1344.963707] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1344.963730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1344.963754] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1344.963774] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1344.963796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1344.963817] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1344.963837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1344.963857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1344.963876] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1344.963894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1344.963898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.963916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1344.963921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1344.963940] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1344.963957] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1344.963976] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1344.963993] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1344.964016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1344.964034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1344.964053] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1344.964070] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1344.964089] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1344.964110] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1344.964134] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1344.964183] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1344.964202] [drm:intel_power_well_enable [i915]] enabling display
>[ 1344.964219] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1344.964253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1344.964272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1344.964291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1344.964316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1344.964342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1344.964396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1344.964430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1344.964461] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1344.964492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.964521] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1344.964547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1344.964579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1344.964608] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1344.966674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1344.966694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1344.966713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.966734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1344.968309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1344.968330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1344.968348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1344.969946] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1344.969967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1344.971838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1344.975158] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1344.975221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1344.975254] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1344.975296] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1344.975463] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1344.975514] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1344.991998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1344.992046] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1344.992109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1344.992311] [drm:drm_mode_addfb2] [FB:78]
>[ 1344.992549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.025324] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.025455] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.025563] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.042593] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.042637] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.042670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.042708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.042742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.042777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.042808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.042838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.042869] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.042912] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.042955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.042997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.043040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.043079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.043118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.043178] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.043214] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.043254] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.043283] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.043464] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.043490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.043617] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.043663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.043710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.043760] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.043801] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.043837] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.043867] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.043896] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.043922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.043948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.043973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.043980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.044004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.044010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.044036] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.044059] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.044084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.044108] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.044137] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.044161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.044197] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.044223] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.044250] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.044277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.044305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.044405] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.044434] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.044462] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.044515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.044546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.044579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.044609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.044638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.044669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.044704] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.044737] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.044769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.044799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.044828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.044863] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.044895] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.046973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.046997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.047020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.047045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.048631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.048653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.048672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.050225] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.050248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.052130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.055424] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.055496] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.055519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.055551] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.055611] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.055632] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.072288] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.072335] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.072495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.072752] [drm:drm_mode_addfb2] [FB:77]
>[ 1345.072879] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.105678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.105727] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.105801] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.122804] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.122848] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.122880] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.122919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.122953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.122988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.123019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.123049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.123081] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.123117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.123150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.123182] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.123214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.123242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.123269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.123325] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.123453] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.123516] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.123576] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.123797] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.123824] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.123936] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.123971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.124008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.124046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.124078] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.124121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.124143] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.124164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.124183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.124203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.124221] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.124226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.124244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.124248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.124267] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.124285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.124303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.124327] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.124357] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.124409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.124437] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.124467] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.124495] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.124527] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.124560] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.124649] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.124682] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.124712] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.124763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.124796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.124828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.124860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.124886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.124906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.124928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.124949] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.124969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.124987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.125012] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.125039] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.125065] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.127131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.127153] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.127172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.127191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.128766] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.128786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.128804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.130352] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.130398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.132266] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.135532] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.135582] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.135602] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.135627] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.135689] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.135710] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.152413] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.152463] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.152528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.152751] [drm:drm_mode_addfb2] [FB:79]
>[ 1345.152901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.185726] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.185778] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.185855] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.202876] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.202920] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.202953] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.202991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.203025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.203059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.203089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.203119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.203150] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.203185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.203218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.203250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.203290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.203330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.203444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.203531] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.203602] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.203670] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.203728] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.203920] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.203940] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.204028] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.204060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.204083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.204108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.204128] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.204149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.204170] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.204195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.204222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.204247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.204274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.204279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.204304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.204309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.204337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.204393] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.204424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.204452] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.204484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.204512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.204540] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.204567] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.204594] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.204626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.204658] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.204752] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.204785] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.204816] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.204867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.204899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.204932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.204962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.204986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.205007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.205030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.205051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.205071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.205095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.205121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.205148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.205175] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.207234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.207255] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.207274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.207293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.208890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.208910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.208928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.210482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.210503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.212392] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.215742] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.215827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.215860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.215902] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.215979] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.216012] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.232610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.232659] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.232724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.232947] [drm:drm_mode_addfb2] [FB:78]
>[ 1345.233094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.265952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.266000] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.266072] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.283255] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.283299] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.283331] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.283455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.283503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.283557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.283600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.283646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.283690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.283744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.283795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.283843] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.283876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.283902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.283930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.283985] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.284027] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.284066] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.284102] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.284269] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.284281] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.284352] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.284421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.284456] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.284491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.284520] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.284551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.284582] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.284615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.284646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.284674] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.284704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.284712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.284741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.284748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.284777] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.284807] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.284836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.284865] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.284897] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.284916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.284941] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.284968] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.284993] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.285021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.285048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.285103] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.285126] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.285148] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.285187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.285214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.285241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.285267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.285294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.285320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.285375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.285409] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.285442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.285469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.285497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.285530] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.285559] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.287631] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.287653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.287675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.287699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.289266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.289286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.289305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.290920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.290941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.292829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.296101] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.296146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.296166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.296192] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.296253] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.296274] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.312941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.312988] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.313051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.313252] [drm:drm_mode_addfb2] [FB:77]
>[ 1345.313451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.346267] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.346317] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.346479] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.365294] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.365337] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.365461] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.365504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.365539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.365582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.365623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.365665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.365705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.365752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.365795] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.365841] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.365866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.365887] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.365906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.365941] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.365968] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.365997] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.366019] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.366112] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.366126] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.366182] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.366203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.366226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.366250] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.366270] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.366292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.366313] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.366340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.366397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.366425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.366452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.366461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.366487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.366494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.366522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.366548] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.366574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.366600] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.366631] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.366657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.366684] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.366710] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.366737] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.366768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.366800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.366880] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.366906] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.366925] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.366962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.366987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.367013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.367039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.367065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.367091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.367119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.367147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.367175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.367201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.367226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.367254] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.367280] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.369334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.369373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.369398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.369424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.370992] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.371015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.371038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.372594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.372615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.374479] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.377828] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.377914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.377947] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.377989] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.378063] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.378093] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.394697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.394749] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.394820] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.395026] [drm:drm_mode_addfb2] [FB:79]
>[ 1345.395147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.428039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.428092] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.428183] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.445189] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.445233] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.445265] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.445303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.445337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.445460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.445510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.445559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.445610] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.445656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.445679] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.445701] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.445720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.445739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.445757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.445793] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.445821] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.445849] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.445871] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.445974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.445987] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.446047] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.446073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.446100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.446129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.446154] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.446181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.446207] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.446233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.446259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.446280] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.446300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.446305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.446335] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.446368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.446402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.446434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.446463] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.446492] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.446523] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.446551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.446578] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.446606] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.446632] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.446664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.446696] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.446788] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.446817] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.446835] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.446870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.446891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.446911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.446930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.446948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.446968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.446990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.447010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.447031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.447049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.447067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.447090] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.447110] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.449156] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.449177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.449195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.449215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.450778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.450797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.450815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.452393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.452414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.454277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.457623] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.457715] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.457755] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.457809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.457878] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.457906] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.474489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.474536] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.474599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.474801] [drm:drm_mode_addfb2] [FB:78]
>[ 1345.474925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.507816] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.507862] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.507933] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.524962] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.525009] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.525049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.525094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.525135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.525179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.525219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.525258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.525298] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.525342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.525463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.525511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.525553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.525589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.525628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.525679] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.525719] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.525762] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.525796] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.525930] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.525946] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.526022] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.526051] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.526082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.526115] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.526141] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.526170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.526199] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.526225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.526252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.526277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.526301] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.526307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.526341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.526389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.526429] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.526456] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.526485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.526512] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.526542] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.526569] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.526596] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.526622] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.526650] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.526681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.526714] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.526791] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.526814] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.526832] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.526866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.526887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.526906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.526925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.526943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.526963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.526984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.527005] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.527025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.527044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.527061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.527084] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.527104] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.529150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.529173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.529193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.529214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.530782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.530802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.530820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.532375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.532395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.534263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.537618] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.537682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.537702] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.537727] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.537788] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.537809] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.554479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.554532] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.554603] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.554805] [drm:drm_mode_addfb2] [FB:77]
>[ 1345.554940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.587821] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.587870] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.587943] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.604965] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.605008] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.605040] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.605079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.605119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.605164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.605217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.605257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.605297] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.605342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.605465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.605514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.605560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.605600] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.605640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.605714] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.605771] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.605825] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.605871] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.606062] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.606086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.606203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.606246] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.606291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.606341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.606416] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.606452] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.606483] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.606517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.606549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.606582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.606612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.606621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.606650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.606658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.606689] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.606720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.606749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.606776] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.606809] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.606838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.606868] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.606894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.606923] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.606955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.606989] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.607082] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.607114] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.607144] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.607193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.607225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.607256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.607285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.607316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.607369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.607404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.607438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.607471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.607501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.607532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.607567] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.607599] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.609664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.609685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.609703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.609722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.611326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.611362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.611384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.612958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.612981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.614880] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.618201] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.618267] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.618307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.618428] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.618548] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.618600] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.635046] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.635096] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.635161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.635442] [drm:drm_mode_addfb2] [FB:79]
>[ 1345.635645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.668391] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.668443] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.668519] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.685603] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.685647] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.685679] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.685718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.685758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.685803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.685843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.685883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.685922] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.685967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.686010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.686052] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.686094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.686133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.686172] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.686230] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.686276] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.686326] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.686422] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.686574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.686593] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.686683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.686717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.686751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.686789] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.686820] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.686854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.686887] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.686918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.686950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.686980] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.687009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.687017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.687045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.687052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.687082] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.687112] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.687141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.687171] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.687202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.687231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.687261] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.687291] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.687320] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.687380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.687417] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.687509] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.687541] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.687572] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.687623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.687655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.687683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.687713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.687743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.687771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.687804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.687837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.687869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.687900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.687929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.687963] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.687995] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.690060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.690081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.690102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.690126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.691692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.691715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.691738] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.693328] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.693366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.695236] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.698540] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.698624] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.698651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.698687] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.698753] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.698781] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.715405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.715455] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.715520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.715718] [drm:drm_mode_addfb2] [FB:78]
>[ 1345.715849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.748746] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.748794] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.748866] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.765890] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.765934] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.765966] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.766004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.766037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.766072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.766102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.766131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.766162] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.766198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.766230] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.766271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.766314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.766427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.766464] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.766537] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.766597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.766652] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.766701] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.766855] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.766871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.766946] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.766975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.767005] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.767038] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.767065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.767093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.767121] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.767148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.767182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.767216] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.767250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.767257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.767290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.767296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.767333] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.767405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.767435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.767464] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.767495] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.767524] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.767551] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.767579] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.767606] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.767637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.767670] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.767760] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.767792] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.767823] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.767875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.767907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.767938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.767969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.767994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.768016] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.768039] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.768059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.768081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.768099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.768118] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.768140] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.768162] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.770194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.770225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.770243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.770262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.771862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.771882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.771900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.773469] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.773490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.775383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.778706] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.778760] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.778787] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.778823] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.778889] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.778917] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.795548] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.795598] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.795663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.795865] [drm:drm_mode_addfb2] [FB:77]
>[ 1345.795982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.828892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.828941] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.829015] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.846042] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.846085] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.846117] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.846155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.846189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.846224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.846263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.846304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.846419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.846480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.846531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.846583] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.846635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.846683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.846729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.846796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.846838] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.846882] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.846918] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.847060] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.847079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.847166] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.847204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.847228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.847253] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.847273] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.847295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.847324] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.847380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.847409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.847436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.847462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.847471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.847497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.847504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.847531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.847558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.847584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.847611] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.847644] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.847673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.847701] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.847730] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.847759] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.847792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.847826] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.847902] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.847936] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.847965] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.848000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.848021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.848041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.848060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.848078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.848098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.848120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.848140] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.848160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.848179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.848197] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.848222] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.848248] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.850290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.850311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.850387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.850420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.851979] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.851999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.852016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.853579] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.853600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.855471] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.858796] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.858851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.858882] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.858921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.858994] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.859025] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.875639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.875688] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.875754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.875955] [drm:drm_mode_addfb2] [FB:79]
>[ 1345.876082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.908980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.909028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.909101] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1345.926130] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1345.926174] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1345.926206] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1345.926244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.926277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.926312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.926425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.926475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.926521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.926580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.926633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.926685] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.926737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.926784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.926830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.926888] [drm:intel_power_well_disable [i915]] disabling display
>[ 1345.926931] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1345.926975] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.927009] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1345.927146] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1345.927158] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1345.927214] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1345.927235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1345.927258] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1345.927283] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1345.927306] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1345.927363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1345.927393] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1345.927422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1345.927451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1345.927478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1345.927504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1345.927512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.927537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1345.927545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1345.927572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1345.927598] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1345.927624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1345.927650] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1345.927681] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1345.927707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1345.927734] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1345.927764] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1345.927792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1345.927824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.927859] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1345.927940] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1345.927972] [drm:intel_power_well_enable [i915]] enabling display
>[ 1345.928003] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1345.928056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1345.928089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1345.928119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1345.928143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1345.928161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1345.928182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1345.928205] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1345.928225] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1345.928251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.928277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1345.928303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1345.928356] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1345.928386] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1345.930459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1345.930480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1345.930498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.930517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1345.932088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1345.932108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1345.932131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1345.933695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1345.933716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1345.935587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1345.938932] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1345.939023] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1345.939056] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1345.939098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1345.939176] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1345.939209] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1345.955802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1345.955851] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1345.955917] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1345.956114] [drm:drm_mode_addfb2] [FB:78]
>[ 1345.956243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1345.989142] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1345.989190] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1345.989264] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.006289] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.006434] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.006485] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.006543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.006595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.006650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.006699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.006748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.006780] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.006816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.006850] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.006883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.006915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.006945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.006974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.007026] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.007054] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.007083] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.007105] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.007241] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.007255] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.007370] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.007402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.007437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.007473] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.007502] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.007534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.007564] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.007596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.007625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.007653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.007681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.007689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.007718] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.007725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.007754] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.007781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.007808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.007834] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.007868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.007896] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.007926] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.007955] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.007984] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.008017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.008052] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.008131] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.008158] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.008178] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.008212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.008232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.008252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.008270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.008288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.008308] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.008367] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.008400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.008430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.008456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.008483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.008515] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.008543] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.010628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.010650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.010669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.010688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.012261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.012281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.012300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.013901] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.013922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.015808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.019074] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.019124] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.019143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.019169] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.019230] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.019251] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.035931] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.035980] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.036044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.036272] [drm:drm_mode_addfb2] [FB:77]
>[ 1346.036542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.069281] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.069413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.069525] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.088413] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.088459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.088494] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.088535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.088570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.088607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.088639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.088669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.088704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.088741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.088776] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.088809] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.088842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.088881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.088908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.088963] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.089004] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.089046] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.089081] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.089279] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.089372] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.089523] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.089572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.089625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.089681] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.089725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.089775] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.089822] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.089869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.089913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.089958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.090002] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.090013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.090054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.090064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.090110] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.090151] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.090196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.090236] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.090284] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.090329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.090411] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.090454] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.090500] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.090553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.090607] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.090705] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.090737] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.090766] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.090816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.090846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.090874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.090903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.090929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.090959] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.090993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.091025] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.091057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.091083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.091110] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.091141] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.091172] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.093259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.093280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.093298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.093373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.094948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.094968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.094986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.096574] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.096597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.098470] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.101817] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.101889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.101908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.101933] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.101994] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.102016] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.118687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.118737] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.118803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.119000] [drm:drm_mode_addfb2] [FB:79]
>[ 1346.119132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.152030] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.152083] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.152159] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.169166] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.169210] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.169242] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.169281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.169314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.169442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.169492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.169541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.169592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.169657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.169690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.169723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.169755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.169785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.169815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.169870] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.169916] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.169958] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.169993] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.170131] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.170143] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.170199] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.170221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.170243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.170266] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.170285] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.170317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.170377] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.170407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.170437] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.170465] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.170492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.170501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.170527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.170535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.170562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.170589] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.170616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.170642] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.170673] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.170699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.170725] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.170754] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.170782] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.170813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.170848] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.170943] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.170975] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.171006] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.171060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.171092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.171124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.171147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.171166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.171187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.171209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.171230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.171250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.171268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.171286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.171339] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.171369] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.173440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.173462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.173481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.173500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.175060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.175083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.175107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.176671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.176693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.178561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.181890] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.181927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.181946] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.181971] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.182032] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.182057] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.198715] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.198765] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.198835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.199039] [drm:drm_mode_addfb2] [FB:78]
>[ 1346.199159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.232071] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.232124] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.232200] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.249222] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.249266] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.249298] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.249426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.249479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.249535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.249584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.249621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.249653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.249691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.249725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.249756] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.249787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.249815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.249843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.249897] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.249939] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.249981] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.250015] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.250157] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.250175] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.250262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.250299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.250390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.250436] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.250464] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.250495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.250525] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.250554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.250582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.250609] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.250637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.250646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.250672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.250679] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.250707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.250734] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.250761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.250787] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.250817] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.250843] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.250871] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.250899] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.250928] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.250958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.250990] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.251054] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.251074] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.251094] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.251134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.251161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.251188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.251214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.251240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.251266] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.251295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.251354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.251388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.251416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.251444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.251479] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.251507] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.253576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.253599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.253622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.253646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.255208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.255229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.255248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.256841] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.256862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.258732] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.262080] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.262167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.262199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.262241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.262387] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.262440] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.278944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.278991] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.279054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.279253] [drm:drm_mode_addfb2] [FB:77]
>[ 1346.279493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.312292] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.312371] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.312442] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.329444] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.329493] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.329533] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.329578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.329618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.329662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.329702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.329742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.329781] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.329826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.329868] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.329911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.329953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.329992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.330031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.330088] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.330135] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.330195] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.330217] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.330378] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.330398] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.330496] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.330528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.330562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.330599] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.330628] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.330660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.330690] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.330721] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.330749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.330778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.330804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.330811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.330838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.330845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.330875] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.330901] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.330929] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.330954] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.330985] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.331011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.331039] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.331065] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.331093] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.331123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.331157] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.331236] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.331267] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.331298] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.331375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.331405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.331436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.331464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.331493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.331522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.331556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.331589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.331623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.331651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.331679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.331715] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.331744] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.333817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.333837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.333856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.333875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.335461] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.335486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.335509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.337070] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.337093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.338967] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.342287] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.342405] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.342424] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.342450] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.342510] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.342531] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.359166] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.359213] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.359281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.359608] [drm:drm_mode_addfb2] [FB:79]
>[ 1346.359739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.392525] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.392573] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.392646] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.409666] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.409710] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.409743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.409782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.409815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.409851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.409882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.409911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.409943] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.409978] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.410020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.410062] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.410105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.410148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.410167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.410201] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.410226] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.410253] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.410273] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.410470] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.410489] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.410580] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.410613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.410638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.410663] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.410683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.410705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.410727] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.410748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.410768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.410787] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.410805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.410810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.410829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.410833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.410852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.410870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.410888] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.410906] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.410927] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.410944] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.410970] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.410995] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.411022] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.411049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.411077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.411132] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.411155] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.411177] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.411215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.411241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.411268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.411296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.411351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.411383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.411417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.411448] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.411479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.411506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.411532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.411564] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.411594] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.413657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.413678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.413696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.413715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.415293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.415329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.415347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.416903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.416925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.418845] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.422172] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.422229] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.422261] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.422304] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.422444] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.422476] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.439018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.439067] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.439132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.439592] [drm:drm_mode_addfb2] [FB:78]
>[ 1346.439737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.472354] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.472402] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.472491] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.489750] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.489793] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.489833] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.489878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.489919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.489963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.490004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.490043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.490083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.490128] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.490171] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.490213] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.490255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.490295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.490417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.490504] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.490573] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.490643] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.490701] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.490891] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.490910] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.490994] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.491021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.491048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.491077] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.491102] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.491129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.491155] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.491182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.491208] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.491234] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.491259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.491265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.491295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.491331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.491364] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.491394] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.491423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.491451] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.491481] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.491509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.491537] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.491565] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.491591] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.491623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.491655] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.491733] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.491755] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.491773] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.491808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.491833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.491859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.491885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.491911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.491937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.491964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.491992] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.492020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.492046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.492072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.492100] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.492126] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.494189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.494211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.494230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.494249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.495839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.495862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.495885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.497468] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.497491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.499363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.502712] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.502799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.502832] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.502875] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.502970] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.503020] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.519587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.519639] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.519710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.519915] [drm:drm_mode_addfb2] [FB:77]
>[ 1346.520051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.552937] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.552985] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.553076] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.570119] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.570162] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.570194] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.570232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.570265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.570382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.570432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.570476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.570523] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.570581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.570635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.570687] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.570740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.570765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.570784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.570819] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.570847] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.570874] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.570897] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.570999] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.571011] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.571066] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.571087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.571110] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.571135] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.571159] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.571186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.571213] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.571238] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.571264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.571295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.571352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.571360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.571389] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.571396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.571425] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.571452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.571480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.571507] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.571538] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.571564] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.571592] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.571618] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.571644] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.571675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.571707] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.571785] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.571818] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.571849] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.571901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.571933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.571965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.571995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.572026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.572057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.572082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.572102] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.572124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.572142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.572161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.572183] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.572205] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.574249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.574271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.574350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.574384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.575953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.575974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.575992] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.577547] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.577570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.579442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.582772] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.582826] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.582859] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.582900] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.582973] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.582995] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.599609] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.599659] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.599724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.599928] [drm:drm_mode_addfb2] [FB:79]
>[ 1346.600044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.632949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.633002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.633078] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.650101] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.650145] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.650177] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.650215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.650249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.650284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.650404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.650448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.650494] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.650553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.650608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.650652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.650696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.650735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.650760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.650805] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.650842] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.650878] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.650907] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.651028] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.651044] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.651117] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.651145] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.651175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.651209] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.651235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.651262] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.651301] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.651382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.651419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.651455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.651492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.651503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.651539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.651549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.651595] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.651621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.651648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.651674] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.651704] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.651733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.651762] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.651790] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.651819] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.651852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.651886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.651963] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.651995] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.652025] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.652080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.652113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.652134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.652154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.652172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.652192] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.652214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.652235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.652256] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.652273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.652321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.652353] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.652383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.654452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.654473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.654492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.654511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.656070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.656091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.656108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.657661] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.657684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.659548] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.662849] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.662916] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.662936] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.662962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.663022] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.663043] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.679713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.679762] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.679832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.680033] [drm:drm_mode_addfb2] [FB:78]
>[ 1346.680152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.713056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.713104] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.713180] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.730203] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.730247] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.730280] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.730410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.730464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.730520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.730569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.730603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.730637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.730675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.730709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.730742] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.730775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.730803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.730833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.730887] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.730929] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.730970] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.731005] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.731159] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.731177] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.731264] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.731364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.731413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.731448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.731476] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.731506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.731536] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.731565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.731594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.731621] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.731648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.731657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.731683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.731691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.731718] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.731744] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.731770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.731799] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.731831] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.731859] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.731888] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.731909] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.731927] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.731952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.731986] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.732042] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.732062] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.732080] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.732114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.732134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.732154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.732172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.732191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.732210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.732232] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.732252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.732273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.732325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.732352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.732383] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.732412] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.734484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.734506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.734524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.734543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.736114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.736135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.736154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.737706] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.737727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.739597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.742907] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.742976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.743005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.743042] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.743111] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.743141] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.759762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.759812] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.759876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.760076] [drm:drm_mode_addfb2] [FB:77]
>[ 1346.760205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.793104] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.793153] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.793225] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.810255] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.810390] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.810441] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.810499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.810551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.810606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.810655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.810702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.810751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.810807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.810860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.810911] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.810962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.811008] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.811054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.811140] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.811200] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.811249] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.811293] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.811476] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.811494] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.811579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.811608] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.811630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.811654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.811672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.811692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.811715] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.811739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.811763] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.811786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.811809] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.811813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.811836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.811840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.811864] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.811885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.811908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.811928] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.811952] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.811975] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.811998] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.812022] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.812045] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.812070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.812095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.812145] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.812165] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.812185] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.812220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.812245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.812270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.812353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.812384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.812419] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.812455] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.812490] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.812524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.812554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.812584] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.812620] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.812652] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.814723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.814744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.814763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.814783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.816387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.816407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.816425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.817975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.817996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.819869] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.823162] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.823252] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.823284] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.823419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.823493] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.823523] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.840038] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.840090] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.840160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.840598] [drm:drm_mode_addfb2] [FB:79]
>[ 1346.840731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.873376] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.873428] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.873504] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.890587] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.890630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.890662] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.890700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.890733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.890769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.890799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.890828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.890859] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.890895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.890927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.890959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.890990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.891018] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.891046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.891099] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.891143] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.891178] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.891207] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.891392] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.891419] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.891550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.891596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.891643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.891684] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.891712] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.891742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.891771] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.891798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.891824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.891856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.891889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.891897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.891930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.891936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.891971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.892005] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.892039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.892073] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.892108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.892143] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.892166] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.892186] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.892205] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.892228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.892253] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.892358] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.892392] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.892422] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.892475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.892507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.892543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.892580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.892618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.892655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.892688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.892713] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.892735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.892755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.892773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.892798] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.892819] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.894898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.894921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.894943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.894967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.896567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.896590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.896609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.898169] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.898190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.900064] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.903406] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.903491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.903517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.903551] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.903613] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.903640] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1346.920280] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.920364] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.920429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.920628] [drm:drm_mode_addfb2] [FB:78]
>[ 1346.920758] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.953622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1346.953671] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1346.953745] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1346.970813] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1346.970860] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1346.970901] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1346.970945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.970986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.971030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.971070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.971115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.971148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1346.971182] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.971213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.971242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.971271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.971369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.971409] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.971490] [drm:intel_power_well_disable [i915]] disabling display
>[ 1346.971557] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1346.971621] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1346.971675] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1346.971860] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1346.971877] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1346.971960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1346.971992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1346.972026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1346.972063] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1346.972101] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1346.972123] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1346.972144] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1346.972164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1346.972190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1346.972216] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1346.972241] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1346.972247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.972272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1346.972306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1346.972338] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1346.972367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1346.972396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1346.972422] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1346.972452] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1346.972480] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1346.972508] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1346.972534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1346.972562] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1346.972678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1346.972713] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1346.972803] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1346.972837] [drm:intel_power_well_enable [i915]] enabling display
>[ 1346.972863] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1346.972898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1346.972919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1346.972940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1346.972959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1346.972978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1346.973002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1346.973031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1346.973059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1346.973087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1346.973113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1346.973139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1346.973167] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1346.973192] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1346.975231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1346.975252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1346.975271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.975348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1346.976921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1346.976941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1346.976959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1346.978520] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1346.978541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1346.980411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1346.983702] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1346.983790] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1346.983825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1346.983871] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1346.983945] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1346.983981] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.000577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.000627] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.000692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.000892] [drm:drm_mode_addfb2] [FB:77]
>[ 1347.001024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.033918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.033969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.034046] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.051067] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.051111] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.051151] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.051195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.051236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.051280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.051398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.051452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.051499] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.051559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.051612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.051664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.051716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.051760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.051791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.051846] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.051887] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.051931] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.051966] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.052096] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.052109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.052165] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.052186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.052208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.052233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.052255] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.052316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.052346] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.052375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.052404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.052431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.052457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.052466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.052491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.052499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.052526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.052552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.052579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.052605] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.052635] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.052661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.052688] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.052714] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.052741] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.052773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.052807] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.052873] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.052892] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.052910] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.052949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.052975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.053002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.053028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.053054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.053080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.053108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.053136] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.053165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.053190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.053216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.053243] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.053271] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.055365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.055387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.055406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.055426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.056984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.057004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.057022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.058588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.058609] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.060482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.063827] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.063917] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.063949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.063991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.064068] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.064100] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.080697] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.080747] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.080812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.081012] [drm:drm_mode_addfb2] [FB:79]
>[ 1347.081126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.114041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.114090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.114162] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.131350] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.131394] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.131427] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.131465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.131498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.131533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.131564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.131592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.131623] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.131658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.131691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.131723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.131754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.131782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.131810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.131858] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.131884] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.131908] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.131929] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.132046] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.132058] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.132115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.132139] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.132162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.132187] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.132206] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.132228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.132249] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.132328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.132362] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.132390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.132421] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.132429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.132459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.132467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.132497] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.132525] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.132554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.132581] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.132614] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.132641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.132671] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.132698] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.132729] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.132760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.132795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.132874] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.132906] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.132935] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.132986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.133016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.133044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.133073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.133099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.133129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.133162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.133193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.133225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.133251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.133306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.133339] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.133370] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.135462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.135484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.135503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.135523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.137094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.137118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.137141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.138707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.138728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.140599] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.143946] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.144034] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.144071] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.144097] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.144158] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.144179] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.160814] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.160864] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.160928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.161127] [drm:drm_mode_addfb2] [FB:78]
>[ 1347.161257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.194156] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.194205] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.194277] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.211337] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.211381] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.211414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.211452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.211493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.211537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.211577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.211616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.211656] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.211701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.211744] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.211790] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.211821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.211848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.211873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.211919] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.211954] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.211991] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.212020] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.212187] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.212204] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.212362] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.212412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.212464] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.212514] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.212556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.212603] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.212647] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.212691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.212733] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.212775] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.212814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.212827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.212874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.212884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.212922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.212961] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.213000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.213037] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.213080] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.213116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.213155] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.213191] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.213229] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.213270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.213347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.213464] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.213505] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.213542] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.213608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.213645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.213687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.213726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.213765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.213805] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.213857] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.213891] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.213925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.213954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.213980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.214014] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.214046] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.216121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.216142] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.216161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.216180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.217746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.217765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.217783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.219365] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.219385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.221263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.224575] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.224660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.224692] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.224734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.224813] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.224846] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.241448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.241500] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.241572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.241784] [drm:drm_mode_addfb2] [FB:77]
>[ 1347.241919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.274799] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.274847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.274921] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.292136] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.292179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.292212] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.292251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.292381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.292441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.292490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.292538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.292587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.292644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.292696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.292752] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.292785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.292814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.292843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.292899] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.292941] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.292982] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.293017] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.293181] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.293193] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.293262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.293332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.293369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.293407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.293436] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.293471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.293503] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.293535] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.293564] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.293595] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.293622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.293632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.293659] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.293667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.293698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.293725] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.293754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.293780] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.293814] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.293840] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.293868] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.293894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.293922] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.293951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.293984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.294059] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.294090] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.294119] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.294168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.294196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.294225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.294251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.294308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.294336] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.294370] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.294402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.294435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.294462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.294491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.294525] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.294553] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.296626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.296647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.296666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.296685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.298263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.298302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.298321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.299882] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.299903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.301806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.305109] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.305182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.305209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.305243] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.305555] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.305583] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.321971] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.322023] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.322094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.322390] [drm:drm_mode_addfb2] [FB:79]
>[ 1347.322594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.355322] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.355371] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.355444] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.374064] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.374109] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.374141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.374179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.374213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.374248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.374360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.374405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.374457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.374515] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.374568] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.374620] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.374667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.374693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.374721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.374777] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.374819] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.374860] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.374896] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.375052] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.375075] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.375132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.375154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.375176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.375199] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.375218] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.375238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.375329] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.375362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.375395] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.375427] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.375458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.375467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.375496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.375504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.375534] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.375563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.375594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.375624] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.375658] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.375687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.375717] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.375745] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.375771] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.375804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.375839] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.375917] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.375949] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.375980] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.376030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.376062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.376092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.376122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.376152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.376183] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.376217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.376249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.376310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.376337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.376368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.376403] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.376435] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.378508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.378532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.378555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.378579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.380151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.380172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.380194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.381779] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.381801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.383681] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.386980] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.387050] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.387070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.387095] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.387156] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.387178] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.403850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.403900] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.403970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.404200] [drm:drm_mode_addfb2] [FB:78]
>[ 1347.404455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.437189] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.437242] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.437416] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.456210] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.456258] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.456380] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.456439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.456488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.456541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.456584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.456629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.456673] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.456729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.456780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.456829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.456878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.456919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.456962] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.457041] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.457106] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.457167] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.457220] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.457487] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.457507] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.457585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.457616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.457637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.457660] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.457679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.457699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.457719] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.457738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.457758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.457780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.457803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.457808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.457831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.457835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.457859] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.457882] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.457905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.457928] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.457951] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.457974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.457998] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.458021] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.458045] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.458069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.458095] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.458143] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.458163] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.458183] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.458219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.458243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.458314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.458351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.458380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.458414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.458449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.458484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.458517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.458544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.458573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.458609] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.458639] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.460707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.460728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.460747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.460767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.462359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.462379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.462397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.463954] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.463975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.465847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.469138] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.469233] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.469342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.469412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.469700] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.469721] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.486012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.486061] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.486126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.486429] [drm:drm_mode_addfb2] [FB:77]
>[ 1347.486602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.519356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.519405] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.519478] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.538452] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.538496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.538529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.538568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.538601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.538636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.538666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.538696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.538727] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.538763] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.538804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.538847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.538890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.538929] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.538968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.539026] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.539073] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.539123] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.539162] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.539360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.539382] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.539480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.539515] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.539550] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.539587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.539618] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.539651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.539684] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.539716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.539748] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.539778] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.539808] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.539816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.539844] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.539851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.539881] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.539912] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.539942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.539971] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.540003] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.540032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.540062] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.540092] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.540121] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.540154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.540189] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.540292] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.540325] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.540357] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.540411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.540445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.540477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.540508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.540539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.540571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.540606] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.540640] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.540673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.540702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.540734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.540769] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.540801] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.542880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.542902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.542920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.542940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.544513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.544533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.544551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.546098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.546119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.547990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.551339] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.551426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.551459] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.551502] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.551586] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.551613] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.568207] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.568257] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.568422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.568678] [drm:drm_mode_addfb2] [FB:79]
>[ 1347.568814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.601550] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.601599] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.601672] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.618688] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.618732] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.618764] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.618802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.618836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.618872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.618911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.618952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.618991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.619036] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.619079] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.619121] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.619163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.619202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.619242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.619367] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.619410] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.619455] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.619490] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.619640] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.619660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.619758] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.619793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.619828] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.619866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.619897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.619931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.619964] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.619996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.620028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.620058] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.620088] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.620097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.620125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.620132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.620162] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.620192] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.620221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.620250] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.620309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.620341] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.620374] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.620404] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.620435] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.620470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.620506] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.620584] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.620617] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.620647] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.620698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.620730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.620761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.620792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.620822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.620853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.620887] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.620920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.620953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.620982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.621010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.621044] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.621076] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.623145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.623166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.623184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.623202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.624789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.624812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.624831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.626404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.626425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.628292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.631614] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.631669] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.631701] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.631743] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.631810] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.631839] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.648458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.648508] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.648574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.648775] [drm:drm_mode_addfb2] [FB:78]
>[ 1347.648926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.681805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.681854] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.681926] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.700857] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.700900] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.700934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.700972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.701006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.701041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.701071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.701101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.701133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.701168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.701201] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.701240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.701345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.701384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.701426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.701504] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.701564] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.701620] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.701668] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.701866] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.701892] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.702012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.702055] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.702098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.702149] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.702187] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.702231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.702300] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.702332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.702361] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.702392] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.702418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.702427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.702455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.702463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.702493] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.702520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.702550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.702577] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.702608] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.702636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.702665] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.702691] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.702719] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.702751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.702785] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.702860] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.702891] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.702920] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.702969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.702997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.703026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.703052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.703081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.703108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.703141] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.703173] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.703204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.703232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.703282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.703318] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.703347] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.705409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.705430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.705448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.705466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.707036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.707056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.707074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.708636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.708656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.710524] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.713842] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.713905] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.713942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.713991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.714067] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.714105] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.730690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.730740] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.730805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.731025] [drm:drm_mode_addfb2] [FB:77]
>[ 1347.731168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.764032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.764085] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.764161] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.783131] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.783176] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.783208] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.783247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.783367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.783425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.783474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.783523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.783566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.783605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.783639] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.783670] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.783702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.783730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.783757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.783811] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.783853] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.783895] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.783929] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.784083] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.784102] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.784180] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.784200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.784224] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.784304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.784335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.784365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.784396] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.784424] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.784453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.784481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.784507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.784516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.784542] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.784550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.784577] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.784603] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.784630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.784655] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.784686] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.784712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.784739] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.784766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.784792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.784825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.784858] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.784920] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.784940] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.784957] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.784990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.785015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.785042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.785068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.785095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.785121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.785149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.785178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.785205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.785231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.785291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.785327] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.785356] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.787423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.787444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.787467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.787491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.789054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.789074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.789093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.790645] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.790666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.792528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.795873] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.795964] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.795997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.796038] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.796115] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.796154] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.812740] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.812791] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.812861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.813066] [drm:drm_mode_addfb2] [FB:79]
>[ 1347.813199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.846087] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.846132] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.846201] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.863469] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.863514] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.863554] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.863598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.863639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.863684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.863724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.863763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.863803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.863853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.863888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.863919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.863949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.863976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.864002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.864051] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.864090] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.864130] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.864162] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.864366] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.864395] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.864538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.864590] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.864643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.864700] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.864746] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.864783] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.864816] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.864852] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.864872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.864892] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.864910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.864916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.864933] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.864937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.864957] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.864975] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.864994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.865011] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.865037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.865063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.865090] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.865116] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.865142] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.865169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.865198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.865305] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.865334] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.865362] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.865417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.865449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.865481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.865512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.865542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.865573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.865608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.865641] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.865667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.865686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.865704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.865728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.865748] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.867822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.867842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.867860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.867879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.869455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.869476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.869494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.871047] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.871068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.872932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.876193] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.876311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.876345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.876391] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.876467] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.876499] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.893044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.893094] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.893159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.893470] [drm:drm_mode_addfb2] [FB:78]
>[ 1347.893593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.926391] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1347.926439] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1347.926511] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1347.945459] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1347.945504] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1347.945537] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1347.945576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.945610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.945645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.945676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.945706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.945738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.945773] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.945813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.945842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.945881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.945918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.945955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.946010] [drm:intel_power_well_disable [i915]] disabling display
>[ 1347.946054] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1347.946101] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.946138] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1347.946320] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1347.946350] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1347.946490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1347.946536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1347.946588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1347.946641] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1347.946683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1347.946730] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1347.946775] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1347.946823] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1347.946851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1347.946881] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1347.946908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1347.946915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.946942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1347.946949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1347.946978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1347.947004] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1347.947033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1347.947058] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1347.947090] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1347.947116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1347.947144] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1347.947172] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1347.947200] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1347.947230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1347.947304] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1347.947396] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1347.947428] [drm:intel_power_well_enable [i915]] enabling display
>[ 1347.947458] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1347.947507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1347.947535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1347.947565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1347.947592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1347.947620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1347.947648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1347.947680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1347.947712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1347.947743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.947769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1347.947797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1347.947828] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1347.947859] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1347.949932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1347.949955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1347.949978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.950002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1347.951584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1347.951605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1347.951623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1347.953176] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1347.953198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1347.955110] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1347.958453] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1347.958545] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1347.958578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1347.958620] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1347.958715] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1347.958765] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1347.975334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1347.975387] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1347.975457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1347.975666] [drm:drm_mode_addfb2] [FB:77]
>[ 1347.975786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.008684] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.008732] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.008824] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.025835] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.025879] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.025911] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.025949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.025983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.026018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.026048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.026077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.026108] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.026143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.026175] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.026207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.026324] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.026366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.026408] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.026494] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.026564] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.026629] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.026686] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.026823] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.026836] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.026893] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.026914] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.026937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.026963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.026983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.027004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.027025] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.027045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.027065] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.027084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.027102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.027107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.027125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.027130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.027148] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.027166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.027185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.027202] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.027231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.027288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.027315] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.027343] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.027369] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.027400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.027432] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.027511] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.027544] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.027574] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.027626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.027658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.027690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.027720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.027749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.027780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.027804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.027824] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.027845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.027863] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.027882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.027904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.027925] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.029973] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.029994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.030012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.030031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.031618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.031640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.031659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.033235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.033273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.035144] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.038495] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.038578] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.038610] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.038652] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.038728] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.038767] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.055360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.055410] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.055475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.055675] [drm:drm_mode_addfb2] [FB:79]
>[ 1348.055829] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.088702] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.088750] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.088824] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.107711] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.107759] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.107800] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.107844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.107885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.107929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.107969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.108009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.108048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.108093] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.108136] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.108178] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.108220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.108332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.108380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.108468] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.108526] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.108574] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.108609] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.108728] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.108741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.108799] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.108820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.108844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.108869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.108891] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.108917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.108944] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.108970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.108996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.109022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.109047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.109052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.109077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.109082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.109108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.109133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.109160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.109185] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.109212] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.109267] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.109300] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.109329] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.109357] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.109390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.109423] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.109517] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.109542] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.109561] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.109596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.109617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.109637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.109656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.109676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.109696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.109718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.109738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.109765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.109790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.109817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.109844] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.109870] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.111921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.111942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.111964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.111988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.113565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.113588] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.113611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.115170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.115192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.117097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.120435] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.120533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.120566] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.120609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.120686] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.120719] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.137314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.137364] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.137429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.137650] [drm:drm_mode_addfb2] [FB:78]
>[ 1348.137791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.170659] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.170708] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.170781] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.189189] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.189237] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.189350] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.189412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.189465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.189521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.189564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.189595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.189627] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.189665] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.189708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.189752] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.189796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.189836] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.189876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.189935] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.189982] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.190033] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.190072] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.190290] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.190319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.190452] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.190495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.190521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.190550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.190575] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.190601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.190627] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.190652] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.190678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.190703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.190728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.190733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.190758] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.190762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.190788] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.190809] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.190835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.190860] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.190885] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.190910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.190935] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.190960] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.190985] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.191012] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.191039] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.191094] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.191116] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.191138] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.191177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.191203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.191259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.191291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.191321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.191350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.191383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.191415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.191446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.191473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.191500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.191533] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.191562] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.193634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.193655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.193674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.193693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.195278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.195299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.195317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.196880] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.196901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.198768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.202084] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.202148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.202179] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.202219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.202595] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.202628] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.218933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.218984] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.219049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.219340] [drm:drm_mode_addfb2] [FB:77]
>[ 1348.219547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.252299] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.252347] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.252420] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.269431] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.269474] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.269506] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.269544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.269578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.269613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.269644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.269673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.269705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.269741] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.269774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.269806] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.269837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.269875] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.269914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.269972] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.270019] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.270068] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.270108] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.270360] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.270381] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.270490] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.270521] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.270555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.270592] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.270621] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.270653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.270683] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.270713] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.270741] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.270769] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.270795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.270802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.270831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.270838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.270867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.270895] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.270922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.270950] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.270981] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.271006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.271034] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.271060] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.271087] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.271116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.271150] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.271252] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.271285] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.271316] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.271367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.271400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.271429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.271459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.271486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.271516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.271550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.271584] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.271616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.271642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.271671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.271706] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.271734] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.273879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.273901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.273920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.273939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.275515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.275537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.275555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.277113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.277134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.279006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.282324] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.282388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.282421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.282464] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.282540] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.282571] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.299171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.299222] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.299388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.299681] [drm:drm_mode_addfb2] [FB:79]
>[ 1348.299825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.332516] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.332568] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.332645] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.349834] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.349878] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.349910] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.349947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.349981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.350024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.350065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.350105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.350148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.350184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.350215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.350309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.350355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.350394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.350432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.350514] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.350577] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.350636] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.350672] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.350811] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.350829] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.350910] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.350942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.350975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.351012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.351042] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.351073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.351105] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.351148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.351169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.351188] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.351211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.351247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.351274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.351282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.351309] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.351336] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.351363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.351389] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.351420] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.351446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.351473] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.351499] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.351525] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.351556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.351592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.351661] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.351681] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.351699] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.351733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.351753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.351771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.351789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.351807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.351827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.351848] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.351868] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.351888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.351906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.351924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.351946] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.351966] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.354017] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.354038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.354057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.354076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.355657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.355677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.355695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.357271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.357292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.359161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.362496] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.362588] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.362615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.362649] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.362712] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.362738] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.379376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.379426] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.379491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.379715] [drm:drm_mode_addfb2] [FB:78]
>[ 1348.379845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.412721] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.412770] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.412844] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.429894] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.429938] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.429971] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.430009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.430043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.430079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.430110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.430139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.430171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.430206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.430326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.430379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.430428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.430470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.430518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.430578] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.430620] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.430663] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.430697] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.430840] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.430858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.430945] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.430978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.431014] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.431053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.431074] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.431095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.431117] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.431137] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.431156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.431175] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.431193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.431236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.431264] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.431272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.431301] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.431327] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.431355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.431382] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.431412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.431438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.431465] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.431491] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.431518] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.431549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.431580] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.431656] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.431678] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.431696] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.431734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.431760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.431787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.431813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.431840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.431863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.431891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.431919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.431948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.431974] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.432000] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.432027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.432053] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.434107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.434129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.434148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.434168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.435740] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.435761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.435798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.437444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.437469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.439341] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.442691] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.442779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.442819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.442871] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.442971] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.443023] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.459565] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.459614] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.459680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.459866] [drm:drm_mode_addfb2] [FB:77]
>[ 1348.459997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.492916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.492965] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.493055] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.510061] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.510105] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.510138] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.510177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.510211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.510332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.510378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.510427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.510474] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.510528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.510581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.510631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.510681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.510721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.510764] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.510849] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.510913] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.510968] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.511002] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.511162] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.511175] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.511307] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.511343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.511378] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.511416] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.511447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.511477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.511499] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.511519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.511539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.511558] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.511576] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.511581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.511599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.511603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.511628] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.511654] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.511679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.511704] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.511730] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.511754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.511780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.511806] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.511831] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.511858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.511886] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.511951] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.511973] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.511995] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.512034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.512059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.512085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.512111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.512137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.512162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.512189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.512250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.512285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.512313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.512341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.512375] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.512404] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.514468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.514489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.514507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.514526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.516085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.516108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.516131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.517694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.517716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.519621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.522942] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.523006] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.523046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.523098] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.523175] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.523197] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.539787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.539839] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.539911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.540137] [drm:drm_mode_addfb2] [FB:79]
>[ 1348.540388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.573130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.573179] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.573342] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.592160] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.592204] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.592327] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.592383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.592435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.592490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.592539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.592587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.592637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.592694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.592747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.592798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.592852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.592881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.592910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.592965] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.593008] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.593049] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.593090] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.593280] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.593301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.593402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.593427] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.593451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.593476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.593496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.593518] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.593540] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.593560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.593580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.593599] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.593617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.593622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.593640] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.593644] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.593663] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.593689] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.593705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.593721] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.593741] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.593758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.593775] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.593791] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.593814] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.593839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.593865] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.593914] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.593935] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.593955] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.593991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.594015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.594039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.594062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.594086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.594109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.594135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.594159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.594184] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.594208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.594281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.594316] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.594345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.596422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.596444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.596463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.596482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.598053] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.598074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.598092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.599656] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.599677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.601538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.604888] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.604976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.605016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.605068] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.605158] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.605191] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.621758] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.621808] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.621874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.622102] [drm:drm_mode_addfb2] [FB:78]
>[ 1348.622332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.655098] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.655152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.655310] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.672302] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.672346] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.672378] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.672416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.672450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.672485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.672515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.672544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.672575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.672611] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.672644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.672676] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.672706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.672734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.672762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.672807] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.672832] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.672857] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.672878] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.673005] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.673017] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.673075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.673097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.673121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.673147] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.673171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.673206] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.673279] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1348.673309] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1348.673342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.673370] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.673401] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.673409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.673438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.673446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.673476] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.673503] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.673532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.673558] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1348.673591] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.673618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.673648] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1348.673675] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1348.673705] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1348.673741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.673776] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1348.673856] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.673887] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.673917] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.673966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.673995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.674024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.674051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.674079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.674106] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.674138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.674170] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.674202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.674253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.674281] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.674315] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1348.674345] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.676439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.676461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.676484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.676508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.678084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.678105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.678124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.679687] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.679708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.681613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.684949] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1348.685052] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.685079] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1348.685113] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.685192] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1348.685277] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1348.701830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.701880] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.701944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.702172] [drm:drm_mode_addfb2] [FB:77]
>[ 1348.702446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.735173] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1348.735304] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.735413] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1348.754156] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1348.754201] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1348.754337] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.754396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.754447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.754504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.754552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.754601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.754650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.754714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.754748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.754781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.754814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.754843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.754872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.754928] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.754971] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.755020] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1348.755053] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.755382] [drm:drm_mode_addfb2] [FB:77]
>[ 1348.755414] [drm:drm_mode_addfb2] [FB:78]
>[ 1348.784659] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1348.784756] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1348.784821] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1348.784882] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1348.784894] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.784953] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.784975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.784997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.785021] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.785039] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.785060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.785080] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1348.785098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1348.785117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.785134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.785151] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.785155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.785171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.785175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.785203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.785267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.785293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.785320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1348.785351] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.785378] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.785405] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1348.785431] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1348.785457] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1348.785488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.785521] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1348.788828] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.788848] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.788865] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.788901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.788921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.788940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.788958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.788974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.788993] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.789013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.789032] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.789050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.789067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.789083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.789104] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1348.789123] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.791182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.791219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.791238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.791256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.792828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.792848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.792866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.794431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.794452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.796321] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.799625] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1348.799688] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.799708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1348.799734] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.816460] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.816505] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1348.816568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.833228] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1348.833250] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.850010] [drm:drm_mode_addfb2] [FB:79]
>[ 1348.850154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.866542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1348.866591] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.866661] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1348.885320] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1348.885358] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.885402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.885442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.885487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.885527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.885567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.885606] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.885651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.885694] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.885736] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.885778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.885817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.885856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.885914] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.885960] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.886011] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1348.886047] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.886290] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1348.886321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.886475] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.886529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.886585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.886643] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.886694] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.886741] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.886784] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1348.886828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1348.886872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.886913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.886954] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.886965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.887004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.887014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.887055] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.887096] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.887138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.887179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1348.887264] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.887305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.887348] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1348.887391] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1348.887432] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1348.887478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.887528] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1348.887632] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.887682] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.887713] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.887764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.887796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.887826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.887856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.887884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.887914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.887948] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.887980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.888013] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.888042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.888073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.888107] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1348.888138] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.890238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.890259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.890277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.890296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.891883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.891905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.891924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.893487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.893509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.895379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.898710] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1348.898763] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.898797] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1348.898839] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.915541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.915591] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1348.915657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.915860] [drm:drm_mode_addfb2] [FB:77]
>[ 1348.916015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.932280] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1348.932327] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.932397] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1348.949382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1348.949420] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1348.949460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.949494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.949530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.949560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.949590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.949622] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.949656] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.949689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.949721] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.949752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.949780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.949807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.949860] [drm:intel_power_well_disable [i915]] disabling display
>[ 1348.949902] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1348.949942] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1348.949973] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1348.950174] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1348.950230] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1348.950360] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1348.950409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1348.950457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1348.950508] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1348.950546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1348.950591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1348.950632] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1348.950674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1348.950713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1348.950755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1348.950791] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1348.950801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.950837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1348.950846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1348.950886] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1348.950922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1348.950961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1348.950996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1348.951039] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1348.951074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1348.951113] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1348.951157] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1348.951186] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1348.951245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.951281] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1348.951374] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1348.951405] [drm:intel_power_well_enable [i915]] enabling display
>[ 1348.951435] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1348.951488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1348.951519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1348.951546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1348.951575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1348.951601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1348.951631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1348.951664] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1348.951696] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1348.951728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.951754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1348.951782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1348.951813] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1348.951843] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1348.953929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1348.953952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1348.953970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.953992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1348.955570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1348.955591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1348.955610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1348.957192] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1348.957230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1348.959099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1348.962419] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1348.962465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1348.962485] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1348.962515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1348.979261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1348.979312] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1348.979378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1348.979600] [drm:drm_mode_addfb2] [FB:78]
>[ 1348.979746] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1348.995958] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1348.996006] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1348.996077] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.013087] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.013124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.013164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.013197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.013326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.013378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.013428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.013479] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.013536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.013588] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.013646] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.013678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.013707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.013737] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.013792] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.013835] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.013877] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.013908] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.014072] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.014090] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.014158] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.014190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.014264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.014303] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.014332] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.014367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.014398] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.014430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.014460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.014490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.014518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.014527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.014556] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.014564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.014594] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.014623] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.014653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.014683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.014715] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.014744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.014774] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.014803] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.014832] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.014866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.014900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.014992] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.015023] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.015053] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.015104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.015135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.015162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.015192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.015246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.015275] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.015310] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.015343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.015377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.015404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.015433] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.015469] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.015499] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.017568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.017590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.017608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.017627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.019194] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.019233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.019256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.020830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.020853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.022721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.025986] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.026037] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.026056] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.026082] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.042831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.042882] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.042948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.043148] [drm:drm_mode_addfb2] [FB:79]
>[ 1349.043411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.059532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.059580] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.059649] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.076658] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.076694] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.076734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.076768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.076803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.076834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.076877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.076909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.076944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.076977] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.077009] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.077040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.077068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.077095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.077142] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.077168] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.077245] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.077280] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.077445] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.077464] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.077553] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.077583] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.077615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.077652] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.077681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.077713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.077742] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.077772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.077802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.077830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.077855] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.077863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.077889] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.077896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.077925] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.077952] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.077980] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.078006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.078037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.078062] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.078090] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.078116] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.078144] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.078173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.078232] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.078306] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.078337] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.078367] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.078417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.078449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.078477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.078507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.078533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.078563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.078596] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.078629] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.078661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.078687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.078714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.078745] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.078775] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.080854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.080876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.080899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.080923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.082506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.082529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.082548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.084106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.084127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.085998] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.088430] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.088507] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.088526] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.088552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.105301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.105352] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.105420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.105644] [drm:drm_mode_addfb2] [FB:77]
>[ 1349.105788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.121999] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.122045] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.122115] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.139123] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.139160] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.139281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.139331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.139387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.139431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.139475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.139520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.139573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.139624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.139677] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.139710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.139735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.139763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.139819] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.139861] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.139902] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.139935] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.140074] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.140086] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.140141] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.140163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.140249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.140288] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.140322] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.140358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.140393] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.140426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.140460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.140491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.140523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.140532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.140561] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.140568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.140598] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.140630] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.140661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.140691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.140724] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.140755] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.140786] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.140815] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.140844] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.140875] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.140910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.141006] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.141037] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.141067] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.141120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.141152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.141183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.141238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.141266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.141299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.141334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.141367] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.141401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.141431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.141461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.141496] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.141528] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.143601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.143622] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.143641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.143663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.145230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.145250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.145268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.146819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.146840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.148736] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.152041] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.152112] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.152138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.152173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.168898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.168949] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.169014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.169312] [drm:drm_mode_addfb2] [FB:78]
>[ 1349.169511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.185597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.185645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.185715] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.204471] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.204509] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.204549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.204582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.204618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.204656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.204697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.204736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.204781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.204825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.204867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.204909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.204948] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.204987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.205045] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.205091] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.205140] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.205161] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.205337] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.205356] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.205444] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.205474] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.205508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.205544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.205572] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.205604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.205634] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.205665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.205693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.205722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.205748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.205756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.205783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.205789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.205818] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.205846] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.205875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.205900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.205932] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.205958] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.205986] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.206011] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.206042] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.206077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.206112] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.206217] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.206248] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.206279] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.206330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.206358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.206388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.206416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.206445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.206474] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.206506] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.206538] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.206570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.206596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.206625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.206659] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.206687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.208770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.208790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.208808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.208827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.210418] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.210440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.210459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.212013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.212034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.213903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.217259] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.217347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.217373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.217407] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.234124] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.234177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.234360] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.234598] [drm:drm_mode_addfb2] [FB:79]
>[ 1349.234725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.250818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.250868] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.250945] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.267952] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.267990] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.268034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.268076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.268120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.268160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.268292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.268348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.268410] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.268465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.268517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.268569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.268615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.268662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.268729] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.268771] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.268812] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.268845] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.268995] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.269007] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.269062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.269084] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.269106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.269129] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.269147] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.269181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.269250] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.269280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.269313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.269341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.269370] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.269379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.269408] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.269416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.269446] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.269475] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.269505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.269531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.269564] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.269591] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.269619] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.269646] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.269675] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.269708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.269742] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.269820] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.269850] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.269880] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.269931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.269961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.269988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.270016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.270042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.270071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.270104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.270135] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.270167] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.270221] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.270248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.270282] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.270312] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.272384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.272405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.272424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.272443] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.274011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.274031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.274049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.275611] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.275632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.277498] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.280834] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.280915] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.280935] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.280960] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.297713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.297764] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.297830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.298053] [drm:drm_mode_addfb2] [FB:77]
>[ 1349.298273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.314409] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.314457] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.314547] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.331537] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.331579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.331624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.331665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.331710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.331750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.331789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.331829] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.331874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.331917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.331959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.332001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.332041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.332079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.332146] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.332243] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.332289] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.332323] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.332472] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.332490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.332580] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.332610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.332644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.332680] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.332708] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.332740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.332770] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.332800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.332828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.332856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.332881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.332888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.332915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.332921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.332951] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.332977] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.333005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.333030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.333061] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.333086] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.333115] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.333140] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.333169] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.333230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.333266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.333353] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.333383] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.333414] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.333464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.333493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.333522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.333553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.333579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.333610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.333642] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.333675] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.333707] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.333733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.333760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.333791] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.333821] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.335882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.335903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.335921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.335940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.337511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.337531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.337549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.339096] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.339117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.340989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.344303] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.344370] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.344410] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.344444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.361151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.361280] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.361377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.361624] [drm:drm_mode_addfb2] [FB:78]
>[ 1349.361750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.377845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.377892] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.377980] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.396708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.396746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.396786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.396820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.396855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.396886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.396924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.396964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.397010] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.397052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.397095] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.397137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.397176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.397293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.397376] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.397440] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.397506] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.397557] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.397723] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.397743] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.397843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.397877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.397913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.397950] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.397983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.398017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.398050] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.398082] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.398114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.398145] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.398175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.398210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.398239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.398246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.398278] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.398309] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.398339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.398370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.398402] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.398432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.398463] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.398493] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.398521] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.398554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.398589] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.398673] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.398702] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.398729] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.398777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.398806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.398834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.398863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.398890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.398919] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.398950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.398980] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.399010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.399037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.399064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.399095] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.399124] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.401240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.401264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.401288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.401312] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.402874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.402895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.402913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.404474] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.404494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.406357] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.409697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.409792] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.409825] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.409866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.426570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.426622] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.426688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.426912] [drm:drm_mode_addfb2] [FB:79]
>[ 1349.427040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.443266] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.443315] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.443404] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.460398] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.460436] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.460475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.460509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.460544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.460583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.460623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.460663] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.460708] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.460751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.460793] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.460835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.460874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.460913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.460971] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.461017] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.461068] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.461088] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.461258] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.461278] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.461387] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.461421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.461457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.461494] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.461525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.461558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.461591] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.461623] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.461655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.461684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.461714] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.461721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.461749] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.461756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.461785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.461815] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.461844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.461873] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.461905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.461935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.461965] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.461995] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.462025] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.462055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.462089] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.462167] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.462222] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.462254] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.462306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.462340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.462371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.462402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.462432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.462465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.462500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.462534] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.462568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.462597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.462627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.462662] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.462694] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.464771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.464793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.464812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.464831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.466424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.466448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.466471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.468035] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.468057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.469924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.473271] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.473341] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.473360] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.473387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.490145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.490287] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.490389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.490609] [drm:drm_mode_addfb2] [FB:77]
>[ 1349.490736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.506838] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.506887] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.506963] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.524004] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.524042] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.524082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.524116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.524150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.524273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.524327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.524379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.524440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.524484] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.524528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.524571] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.524609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.524648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.524716] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.524772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.524825] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.524868] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.525039] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.525055] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.525132] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.525163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.525257] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.525308] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.525347] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.525392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.525441] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.525477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.525508] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.525542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.525571] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.525581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.525610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.525618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.525650] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.525680] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.525712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.525741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.525775] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.525803] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.525834] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.525861] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.525892] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.525927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.525964] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.526048] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.526080] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.526112] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.526167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.526222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.526257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.526288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.526320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.526351] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.526388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.526426] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.526467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.526493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.526522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.526557] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.526585] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.528677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.528700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.528723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.528747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.530338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.530359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.530378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.531935] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.531956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.533828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.537119] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.537282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.537332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.537399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.553991] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.554044] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.554116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.554439] [drm:drm_mode_addfb2] [FB:78]
>[ 1349.554633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.570646] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.570690] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.570777] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.587816] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.587854] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.587895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.587929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.587965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.587995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.588024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.588056] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.588091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.588123] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.588155] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.588267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.588310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.588358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.588443] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.588508] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.588570] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.588622] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.588854] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.588885] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.589022] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.589054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.589086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.589121] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.589150] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.589236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.589273] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.589305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.589338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.589368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.589400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.589408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.589436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.589444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.589475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.589504] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.589531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.589559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.589592] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.589621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.589648] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.589677] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.589707] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.589741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.589777] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.589852] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.589883] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.589913] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.589965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.589996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.590026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.590056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.590086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.590116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.590149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.590205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.590239] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.590271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.590302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.590337] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.590369] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.592443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.592465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.592484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.592506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.594077] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.594098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.594116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.595694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.595715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.597591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.600932] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.601026] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.601058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.601100] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.617805] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.617856] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.617922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.618119] [drm:drm_mode_addfb2] [FB:79]
>[ 1349.618362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.634481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.634530] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.634618] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.651631] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.651669] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.651708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.651742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.651776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.651806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.651835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.651866] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.651901] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.651933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.651963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.651994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.652022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.652049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.652102] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.652147] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.652254] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.652303] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.652533] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.652550] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.652639] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.652672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.652696] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.652722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.652743] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.652765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.652787] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.652807] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.652827] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.652847] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.652865] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.652870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.652887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.652892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.652911] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.652932] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.652958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.652984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.653011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.653037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.653063] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.653089] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.653114] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.653141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.653212] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.653288] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.653320] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.653350] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.653405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.653439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.653471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.653503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.653535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.653567] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.653600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.653623] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.653643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.653662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.653681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.653704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.653724] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.655778] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.655799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.655818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.655837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.657402] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.657422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.657444] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.659003] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.659026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.660901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.664251] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.664335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.664369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.664411] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.681115] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.681166] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.681330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.681604] [drm:drm_mode_addfb2] [FB:77]
>[ 1349.681735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.697792] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.697840] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.697928] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.714947] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.714985] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.715026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.715059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.715102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.715143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.715272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.715321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.715382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.715434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.715484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.715534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.715575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.715619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.715704] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.715768] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.715830] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.715887] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.716008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.716022] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.716093] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.716114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.716136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.716236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.716271] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.716308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.716342] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.716375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.716408] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.716439] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.716469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.716478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.716506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.716513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.716543] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.716572] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.716599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.716629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.716661] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.716691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.716721] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.716750] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.716780] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.716812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.716847] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.716919] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.716950] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.716981] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.717033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.717065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.717095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.717126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.717156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.717213] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.717246] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.717282] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.717315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.717345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.717376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.717411] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.717443] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.719520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.719542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.719561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.719580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.721163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.721200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.721218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.722784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.722805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.724717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.728052] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.728136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.728155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.728241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.744932] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.744982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.745048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.745361] [drm:drm_mode_addfb2] [FB:78]
>[ 1349.745486] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.761607] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.761655] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.761744] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.778757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.778794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.778834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.778869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.778911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.778952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.778992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.779031] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.779076] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.779119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.779161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.779280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.779312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.779344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.779400] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.779442] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.779483] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.779515] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.779653] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.779673] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.779773] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.779805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.779838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.779872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.779900] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.779931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.779962] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.779991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.780021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.780049] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.780077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.780084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.780110] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.780117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.780154] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.780230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.780262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.780293] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.780327] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.780358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.780389] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.780420] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.780451] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.780482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.780518] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.780595] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.780626] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.780657] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.780708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.780740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.780771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.780802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.780831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.780859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.780894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.780926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.780959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.780988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.781016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.781050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.781082] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.783191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.783212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.783231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.783250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.784831] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.784853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.784871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.786425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.786447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.788319] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.791602] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.791635] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.791654] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.791680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.808432] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.808485] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.808557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.808761] [drm:drm_mode_addfb2] [FB:79]
>[ 1349.808895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.825108] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.825157] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.825319] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.844113] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.844150] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.844273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.844327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.844384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.844434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.844475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.844509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.844546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.844581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.844613] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.844644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.844673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.844701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.844748] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.844776] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.844803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.844823] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.844924] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.844937] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.844993] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.845019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.845046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.845075] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.845100] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.845127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.845158] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.845218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.845248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.845277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.845304] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.845313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.845339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.845347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.845374] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.845401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.845427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.845453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.845484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.845510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.845537] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.845563] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.845590] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.845621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.845654] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.845731] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.845762] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.845792] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.845845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.845878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.845909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.845939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.845968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.846000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.846034] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.846066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.846088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.846107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.846125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.846148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.846200] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.848266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.848287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.848306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.848325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.849882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.849902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.849920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.851471] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.851492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.853354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.856695] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.856789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.856822] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.856864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.873560] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.873611] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.873681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.873884] [drm:drm_mode_addfb2] [FB:77]
>[ 1349.874015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.890240] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.890286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.890377] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.907388] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.907426] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.907467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.907501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.907535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.907566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.907595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.907627] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.907662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.907695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.907727] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.907758] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.907786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.907814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.907866] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.907907] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.907949] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.907980] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.908234] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.908261] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.908394] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.908443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.908493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.908544] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.908587] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.908634] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.908680] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.908724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.908768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.908809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.908850] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.908860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.908899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.908909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.908950] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.908991] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.909032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.909071] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.909118] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.909158] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.909239] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.909270] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.909302] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.909337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.909374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.909451] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.909482] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.909513] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.909564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.909595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.909626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.909653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.909682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.909713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.909747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.909781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.909814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.909843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.909873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.909907] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.909938] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.912008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.912030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.912049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.912068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.913640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.913660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.913679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.915260] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.915281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.917149] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.920472] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.920532] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.920551] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.920577] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1349.937330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.937383] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.937454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.937649] [drm:drm_mode_addfb2] [FB:78]
>[ 1349.937781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.954004] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1349.954053] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1349.954125] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1349.971220] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1349.971257] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1349.971297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.971331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.971366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.971397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.971425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.971457] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1349.971492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.971525] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.971556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.971587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.971625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.971662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.971695] [drm:intel_power_well_disable [i915]] disabling display
>[ 1349.971720] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1349.971750] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1349.971771] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1349.971899] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1349.971911] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1349.971968] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1349.971991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1349.972015] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1349.972040] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1349.972060] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1349.972081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1349.972102] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1349.972122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1349.972152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1349.972209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1349.972236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1349.972244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.972270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1349.972279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1349.972306] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1349.972332] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1349.972359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1349.972385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1349.972416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1349.972443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1349.972471] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1349.972497] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1349.972524] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1349.972555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1349.972587] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1349.972666] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1349.972694] [drm:intel_power_well_enable [i915]] enabling display
>[ 1349.972726] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1349.972779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1349.972811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1349.972842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1349.972872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1349.972902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1349.972933] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1349.972968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1349.973000] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1349.973033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1349.973059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1349.973079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1349.973102] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1349.973123] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1349.975226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1349.975248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1349.975267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.975287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1349.976864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1349.976885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1349.976903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1349.978456] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1349.978477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1349.980346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1349.983692] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1349.983784] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1349.983824] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1349.983881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.000559] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.000610] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.000680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.000880] [drm:drm_mode_addfb2] [FB:79]
>[ 1350.001017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.017238] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.017287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.017360] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.034382] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.034420] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.034460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.034501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.034545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.034585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.034625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.034665] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.034709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.034752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.034794] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.034837] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.034876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.034915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.034973] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.035027] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.035056] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.035076] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.035224] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.035245] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.035342] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.035378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.035414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.035453] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.035479] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.035503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.035526] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.035546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.035566] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.035585] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.035603] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.035608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.035626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.035630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.035649] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.035666] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.035685] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.035702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.035725] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.035742] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.035761] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.035778] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.035797] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.035818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.035841] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.035896] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.035915] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.035933] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.035967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.035987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.036007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.036025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.036044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.036063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.036085] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.036105] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.036125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.036143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.036200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.036233] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.036261] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.038348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.038370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.038388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.038407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.039978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.039999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.040022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.041588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.041610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.043470] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.046814] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.046905] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.046938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.046980] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.063682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.063733] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.063799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.063998] [drm:drm_mode_addfb2] [FB:77]
>[ 1350.064112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.080360] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.080408] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.080480] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.097507] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.097549] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.097595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.097635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.097680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.097720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.097760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.097799] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.097844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.097886] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.097928] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.097970] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.098009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.098049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.098106] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.098153] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.098289] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.098344] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.098555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.098575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.098672] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.098704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.098740] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.098776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.098804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.098836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.098866] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.098897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.098925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.098954] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.098980] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.098987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.099014] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.099020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.099049] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.099075] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.099103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.099128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.099196] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.099224] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.099255] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.099282] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.099311] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.099347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.099382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.099458] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.099489] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.099519] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.099570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.099601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.099629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.099658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.099684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.099714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.099747] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.099779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.099810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.099835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.099864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.099896] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.099926] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.101994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.102016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.102035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.102055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.103625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.103645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.103663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.105256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.105277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.107140] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.110490] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.110590] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.110623] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.110673] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.127368] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.127419] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.127485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.127679] [drm:drm_mode_addfb2] [FB:78]
>[ 1350.127805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.144044] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.144093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.144243] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.161242] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.161279] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.161319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.161353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.161389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.161419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.161448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.161480] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.161514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.161547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.161578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.161610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.161637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.161665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.161718] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.161759] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.161807] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.161843] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.162005] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.162016] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.162074] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.162097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.162120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.162209] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.162238] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.162271] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.162302] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.162331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.162361] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.162388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.162416] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.162424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.162450] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.162458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.162485] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.162512] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.162539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.162565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.162598] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.162627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.162654] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.162680] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.162707] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.162740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.162768] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.162822] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.162842] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.162859] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.162894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.162915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.162934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.162952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.162970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.162989] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.163011] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.163031] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.163051] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.163069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.163087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.163109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.163130] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.165235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.165257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.165275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.165295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.166856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.166880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.166903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.168472] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.168493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.170363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.173707] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.173799] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.173831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.173873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.190577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.190628] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.190694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.190895] [drm:drm_mode_addfb2] [FB:79]
>[ 1350.191024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.207254] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.207303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.207375] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.224395] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.224437] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.224482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.224523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.224568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.224608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.224648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.224687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.224731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.224774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.224816] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.224858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.224897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.224936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.224993] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.225040] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.225090] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.225126] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.225398] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.225417] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.225507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.225542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.225578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.225615] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.225648] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.225681] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.225714] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.225746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.225778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.225809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.225838] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.225845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.225873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.225881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.225909] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.225939] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.225968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.225997] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.226030] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.226060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.226090] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.226120] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.226173] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.226205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.226241] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.226332] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.226363] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.226394] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.226445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.226477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.226508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.226535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.226564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.226595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.226628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.226661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.226693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.226722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.226751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.226785] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.226817] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.228894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.228917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.228936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.228956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.230526] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.230546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.230564] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.232131] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.232168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.234037] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.237392] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.237474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.237506] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.237554] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.254251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.254301] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.254367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.254565] [drm:drm_mode_addfb2] [FB:77]
>[ 1350.254695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.270926] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.270978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.271071] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.288040] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.288077] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.288117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.288236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.288296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.288341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.288387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.288431] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.288485] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.288536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.288586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.288635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.288676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.288721] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.288805] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.288861] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.288907] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.288937] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.289085] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.289099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.289219] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.289256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.289291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.289329] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.289360] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.289394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.289426] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.289455] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.289487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.289518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.289549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.289556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.289585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.289592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.289622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.289652] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.289682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.289708] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.289740] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.289769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.289799] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.289829] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.289855] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.289887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.289922] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.290021] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.290053] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.290083] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.290135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.290188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.290219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.290251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.290282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.290314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.290350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.290384] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.290418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.290448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.290478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.290514] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.290546] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.292641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.292663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.292682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.292701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.294270] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.294291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.294309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.295866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.295886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.297749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.301028] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.301066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.301090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.301121] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.317861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.317912] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.317977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.318238] [drm:drm_mode_addfb2] [FB:78]
>[ 1350.318443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.334537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.334585] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.334674] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.351684] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.351722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.351762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.351796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.351831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.351861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.351891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.351923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.351958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.351990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.352022] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.352053] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.352081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.352108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.352220] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.352265] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.352308] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.352342] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.352480] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.352492] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.352550] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.352572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.352595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.352624] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.352649] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.352676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.352702] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.352728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.352754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.352780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.352805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.352811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.352836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.352841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.352867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.352892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.352917] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.352943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.352969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.352994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.353019] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.353045] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.353071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.353098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.353127] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.353229] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.353257] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.353284] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.353340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.353372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.353402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.353433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.353463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.353494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.353528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.353561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.353594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.353623] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.353653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.353687] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.353711] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.355753] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.355774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.355792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.355811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.357375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.357395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.357413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.358970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.358993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.360857] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.364145] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.364239] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.364271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.364313] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.381013] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.381068] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.381139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.381461] [drm:drm_mode_addfb2] [FB:79]
>[ 1350.381579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.397701] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.397750] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.397840] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.414848] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.414886] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.414926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.414960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.414995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.415025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.415054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.415086] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.415122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.415242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.415294] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.415342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.415383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.415431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.415522] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.415569] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.415605] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.415626] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.415724] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.415736] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.415793] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.415814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.415838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.415862] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.415882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.415904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.415925] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.415945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.415964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.415983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.416001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.416007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.416024] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.416029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.416048] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.416065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.416083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.416101] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.416127] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.416184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.416212] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.416239] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.416266] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.416297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.416329] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.416407] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.416436] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.416467] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.416505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.416526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.416546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.416564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.416582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.416602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.416624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.416644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.416664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.416683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.416701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.416723] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.416744] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.418801] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.418824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.418842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.418862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.420442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.420462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.420480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.422033] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.422054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.423928] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.427281] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.427364] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.427396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.427439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.444141] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.444226] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.444297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.444499] [drm:drm_mode_addfb2] [FB:77]
>[ 1350.444618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.460818] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.460866] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.460955] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.477960] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.477998] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.478038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.478072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.478107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.478215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.478259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.478310] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.478368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.478422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.478473] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.478525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.478561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.478590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.478643] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.478686] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.478728] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.478761] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.478911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.478929] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.479014] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.479052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.479078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.479107] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.479138] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.479196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.479228] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.479257] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.479286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.479313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.479339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.479347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.479373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.479380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.479407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.479437] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.479465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.479492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.479524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.479553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.479582] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.479611] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.479639] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.479672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.479706] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.479774] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.479793] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.479812] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.479846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.479867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.479886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.479904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.479922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.479942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.479963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.479984] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.480003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.480021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.480039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.480062] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.480082] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.482170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.482191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.482209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.482228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.483806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.483827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.483845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.485407] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.485428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.487296] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.490617] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.490675] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.490704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.490742] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.507458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.507509] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.507575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.507757] [drm:drm_mode_addfb2] [FB:78]
>[ 1350.507889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.524134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.524228] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.524318] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.541316] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.541353] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.541397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.541438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.541483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.541523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.541563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.541602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.541647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.541689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.541732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.541774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.541813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.541852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.541910] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.541956] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.542007] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.542043] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.542261] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.542292] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.542417] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.542460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.542503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.542553] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.542577] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.542602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.542625] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.542647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.542672] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.542698] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.542723] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.542729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.542754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.542759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.542785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.542811] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.542837] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.542863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.542889] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.542914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.542939] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.542965] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.542991] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.543018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.543046] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.543102] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.543125] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.543190] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.543245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.543278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.543307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.543335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.543363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.543392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.543424] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.543457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.543489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.543516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.543545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.543580] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.543612] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.545710] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.545731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.545750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.545770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.547371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.547394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.547413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.548973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.548995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.550859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.554179] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.554241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.554274] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.554316] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.571011] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.571059] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.571123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.571433] [drm:drm_mode_addfb2] [FB:79]
>[ 1350.571563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.587700] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.587748] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.587837] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.604847] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.604885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.604926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.604961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.604997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.605028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.605059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.605091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.605126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.605252] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.605306] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.605358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.605404] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.605452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.605538] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.605604] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.605667] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.605718] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.605943] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.605972] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.606096] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.606136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.606208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.606254] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.606296] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.606340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.606383] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.606423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.606462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.606495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.606531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.606541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.606578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.606586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.606624] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.606661] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.606695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.606731] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.606772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.606809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.606846] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.606885] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.606922] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.606960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.607010] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.607101] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.607154] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.607186] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.607239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.607272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.607305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.607336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.607367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.607398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.607434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.607468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.607501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.607531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.607561] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.607595] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.607627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.609722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.609743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.609762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.609781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.611369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.611391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.611410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.612962] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.612983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.614853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.618181] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.618235] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.618267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.618293] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.635012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.635062] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.635128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.635471] [drm:drm_mode_addfb2] [FB:77]
>[ 1350.635606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.651716] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.651764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.651839] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.668848] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.668885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.668924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.668958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.668993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.669023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.669052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.669083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.669119] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.669237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.669290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.669339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.669386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.669432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.669507] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.669553] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.669595] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.669619] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.669727] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.669739] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.669796] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.669817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.669843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.669872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.669897] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.669924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.669950] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.669976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.670002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.670028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.670053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.670059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.670084] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.670089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.670120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.670179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.670212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.670240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.670271] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.670298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.670327] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.670354] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.670381] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.670413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.670447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.670525] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.670551] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.670570] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.670606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.670627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.670646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.670671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.670698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.670724] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.670752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.670780] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.670808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.670834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.670859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.670886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.670912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.672963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.672985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.673004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.673023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.674599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.674619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.674641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.676226] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.676247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.678118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.681437] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.681517] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.681549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.681590] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.698296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.698347] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.698414] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.698639] [drm:drm_mode_addfb2] [FB:78]
>[ 1350.698784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.714994] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.715041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.715131] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.732194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.732233] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.732273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.732307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.732342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.732372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.732401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.732433] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.732468] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.732500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.732531] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.732563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.732591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.732628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.732687] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.732734] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.732784] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.732820] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.732963] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.732975] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.733032] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.733054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.733078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.733102] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.733190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.733222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.733253] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.733284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.733313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.733340] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.733367] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.733375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.733401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.733409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.733436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.733463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.733490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.733516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.733549] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.733578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.733605] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.733632] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.733658] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.733691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.733719] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.733772] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.733791] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.733810] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.733844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.733865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.733884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.733902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.733919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.733940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.733961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.733982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.734002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.734020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.734044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.734071] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.734097] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.736187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.736224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.736253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.736277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.737858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.737880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.737899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.739457] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.739479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.741366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.744713] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.744802] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.744835] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.744877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.761582] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.761632] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.761698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.761919] [drm:drm_mode_addfb2] [FB:79]
>[ 1350.762049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.778279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.778325] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.778416] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.795407] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.795445] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.795485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.795519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.795555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.795586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.795616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.795648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.795683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.795716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.795748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.795779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.795807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.795835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.795888] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.795929] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.795972] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.796003] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.796235] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.796265] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.796411] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.796458] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.796506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.796556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.796592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.796627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.796661] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.796696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.796730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.796764] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.796797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.796805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.796837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.796844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.796877] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.796911] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.796944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.796978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.797013] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.797046] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.797080] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.797114] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.797190] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.797236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.797280] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.797396] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.797427] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.797457] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.797513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.797546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.797576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.797596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.797621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.797647] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.797692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.797725] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.797748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.797767] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.797786] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.797809] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.797831] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.799881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.799902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.799921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.799940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.801509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.801529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.801547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.803105] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.803137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.805018] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.808391] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.808454] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.808487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.808529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.825242] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.825296] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.825368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.825575] [drm:drm_mode_addfb2] [FB:77]
>[ 1350.825707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.841930] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.841978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.842055] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.859063] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.859101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.859235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.859289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.859347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.859397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.859446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.859482] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.859521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.859555] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.859586] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.859618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.859647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.859677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.859730] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.859772] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.859818] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.859838] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.859940] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.859953] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.860008] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.860029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.860053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.860078] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.860099] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.860164] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.860195] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.860223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.860252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.860279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.860305] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.860313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.860339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.860347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.860375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.860402] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.860429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.860455] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.860485] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.860511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.860538] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.860564] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.860591] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.860622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.860654] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.860983] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.861010] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.861027] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.861061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.861081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.861099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.861169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.861197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.861227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.861262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.861360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.861382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.861400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.861418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.861445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.861470] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.863515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.863536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.863555] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.863574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.865166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.865187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.865205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.866771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.866794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.868662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.871957] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.872038] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.872062] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.872093] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.888808] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.888857] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.888920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.889168] [drm:drm_mode_addfb2] [FB:78]
>[ 1350.889368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.905499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.905550] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.905627] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.922646] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.922689] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.922734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.922775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.922819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.922859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.922899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.922939] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.922984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.923026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.923069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.923111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.923243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.923298] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.923372] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.923415] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.923458] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.923491] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.923641] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.923661] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.923761] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.923791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.923822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.923856] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.923882] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.923913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.923940] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.923969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.923995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.924021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.924045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.924052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.924077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.924083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.924123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.924184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.924213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.924241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.924274] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.924301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.924331] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.924358] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.924386] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.924421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.924455] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.924532] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.924561] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.924591] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.924641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.924671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.924699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.924728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.924754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.924783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.924816] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.924847] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.924878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.924904] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.924931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.924961] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.924992] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.927059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.927080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.927098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.927162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.928736] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.928755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.928773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.930340] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.930363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.932228] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1350.935554] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1350.935595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1350.935614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1350.935640] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1350.952392] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.952443] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.952509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.952687] [drm:drm_mode_addfb2] [FB:79]
>[ 1350.952823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.969066] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1350.969114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1350.969286] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1350.988063] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1350.988101] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1350.988224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.988275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.988330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.988374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.988421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.988466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1350.988519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.988569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.988618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.988666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.988706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.988749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.988828] [drm:intel_power_well_disable [i915]] disabling display
>[ 1350.988869] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1350.988915] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1350.988945] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1350.989120] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1350.989142] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1350.989234] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1350.989258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1350.989282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1350.989307] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1350.989326] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1350.989348] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1350.989370] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1350.989390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1350.989410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1350.989428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1350.989446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1350.989451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.989475] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1350.989479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1350.989505] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1350.989529] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1350.989554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1350.989577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1350.989603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1350.989628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1350.989653] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1350.989679] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1350.989704] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1350.989731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1350.989758] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1350.989824] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1350.989846] [drm:intel_power_well_enable [i915]] enabling display
>[ 1350.989868] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1350.989908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1350.989934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1350.989959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1350.989985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1350.990010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1350.990035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1350.990063] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1350.990090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1350.990163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1350.990193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1350.990222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1350.990256] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1350.990285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1350.992366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1350.992388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1350.992407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.992426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1350.993997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1350.994018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1350.994036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1350.995587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1350.995608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1350.997513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.000862] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.000949] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.000982] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.001024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.017725] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.017776] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.017842] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.018023] [drm:drm_mode_addfb2] [FB:77]
>[ 1351.018265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.034400] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.034449] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.034521] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.051549] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.051586] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.051630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.051671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.051716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.051756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.051796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.051835] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.051880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.051923] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.051965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.052007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.052046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.052086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.052242] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.052311] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.052370] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.052403] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.052554] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.052573] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.052661] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.052694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.052729] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.052766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.052797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.052830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.052863] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.052894] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.052926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.052956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.052986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.052993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.053022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.053030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.053060] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.053090] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.053141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.053173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.053204] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.053235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.053266] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.053298] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.053328] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.053362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.053398] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.053472] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.053504] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.053535] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.053586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.053617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.053647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.053678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.053706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.053737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.053771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.053803] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.053835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.053864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.053893] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.053927] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.053958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.056046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.056067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.056086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.056165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.057723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.057742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.057760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.059325] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.059346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.061209] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.064530] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.064576] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.064596] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.064622] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.081369] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.081419] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.081485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.081681] [drm:drm_mode_addfb2] [FB:78]
>[ 1351.081795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.098048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.098101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.098279] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.117062] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.117100] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.117231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.117285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.117342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.117391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.117439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.117489] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.117546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.117599] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.117652] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.117702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.117748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.117793] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.117863] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.117906] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.117955] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.117985] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.118147] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.118168] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.118261] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.118285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.118309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.118341] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.118359] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.118383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.118407] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.118430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.118454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.118477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.118500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.118505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.118527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.118532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.118555] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.118579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.118602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.118625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.118649] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.118672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.118695] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.118719] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.118742] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.118767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.118792] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.118854] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.118874] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.118893] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.118930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.118954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.118978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.119002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.119025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.119048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.119073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.119098] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.119175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.119206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.119236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.119269] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.119299] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.121374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.121397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.121416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.121436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.122995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.123015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.123034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.124596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.124618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.126512] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.129828] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.129897] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.129937] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.129989] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.146675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.146729] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.146800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.146982] [drm:drm_mode_addfb2] [FB:79]
>[ 1351.147119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.163350] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.163398] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.163470] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.180496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.180538] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.180582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.180623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.180667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.180707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.180747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.180787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.180831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.180874] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.180916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.180959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.180998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.181036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.181094] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.181243] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.181290] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.181324] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.181466] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.181485] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.181573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.181606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.181641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.181678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.181710] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.181743] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.181776] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.181807] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.181838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.181868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.181897] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.181904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.181933] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.181940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.181969] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.181999] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.182029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.182055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.182087] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.182141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.182172] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.182200] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.182230] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.182265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.182300] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.182373] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.182404] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.182435] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.182485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.182516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.182544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.182574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.182601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.182631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.182666] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.182699] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.182731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.182760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.182789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.182823] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.182855] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.184930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.184952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.184972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.184992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.186581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.186605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.186628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.188208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.188229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.190091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.193422] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.193468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.193488] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.193513] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.210265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.210315] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.210380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.210579] [drm:drm_mode_addfb2] [FB:77]
>[ 1351.210708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.226940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.226989] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.227061] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.244090] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.244161] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.244201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.244234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.244269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.244299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.244328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.244359] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.244394] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.244427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.244459] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.244490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.244528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.244556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.244590] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.244615] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.244641] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.244659] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.244785] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.244797] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.244855] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.244878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.244902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.244927] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.244947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.244968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.244989] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.245009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.245029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.245048] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.245066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.245070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.245098] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.245145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.245174] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.245201] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.245229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.245255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.245285] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.245311] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.245338] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.245365] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.245391] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.245422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.245454] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.245784] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.245805] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.245824] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.245861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.245884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.245904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.245924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.245944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.245968] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.245997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.246025] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.246052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.246079] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.246128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.246162] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.246191] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.248366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.248388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.248411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.248435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.250001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.250022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.250040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.251617] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.251638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.253649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.256910] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.256967] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.256986] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.257012] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.273761] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.273814] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.273885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.274149] [drm:drm_mode_addfb2] [FB:78]
>[ 1351.274487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.290440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.290488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.290560] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.307630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.307667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.307707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.307747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.307792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.307832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.307872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.307912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.307957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.307999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.308040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.308062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.308081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.308163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.308219] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.308262] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.308303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.308336] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.308491] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.308511] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.308607] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.308638] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.308672] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.308708] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.308736] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.308768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.308798] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.308827] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.308855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.308884] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.308911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.308918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.308945] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.308951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.308981] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.309007] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.309035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.309062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.309094] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.309153] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.309184] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.309211] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.309240] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.309274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.309309] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.309404] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.309435] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.309466] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.309516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.309547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.309575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.309603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.309629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.309659] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.309691] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.309723] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.309754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.309780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.309807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.309838] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.309868] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.311958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.311981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.312000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.312020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.313616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.313639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.313662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.315253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.315276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.317160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.320439] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.320478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.320502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.320533] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.337271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.337322] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.337390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.337591] [drm:drm_mode_addfb2] [FB:79]
>[ 1351.337730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.353949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.353998] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.354069] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.371154] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.371190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.371230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.371263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.371298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.371329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.371359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.371390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.371425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.371457] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.371488] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.371519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.371546] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.371579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.371624] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.371659] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.371694] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.371721] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.371890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.371907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.371987] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.372021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.372057] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.372097] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.372182] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.372226] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.372267] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.372305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.372344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.372380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.372416] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.372426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.372460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.372470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.372506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.372541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.372576] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.372623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.372668] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.372706] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.372746] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.372784] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.372829] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.372876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.372923] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.373059] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.373106] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.373190] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.373270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.373319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.373367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.373412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.373458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.373501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.373550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.373595] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.373635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.373665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.373691] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.373727] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.373759] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.375838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.375860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.375878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.375898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.377474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.377494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.377513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.379093] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.379131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.380999] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.384306] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.384382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.384415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.384458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.401165] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.401216] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.401283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.401481] [drm:drm_mode_addfb2] [FB:77]
>[ 1351.401597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.417839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.417888] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.417961] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.434986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.435024] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.435063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.435098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.435229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.435280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.435329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.435379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.435436] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.435488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.435540] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.435592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.435638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.435683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.435769] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.435836] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.435898] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.435949] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.436154] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.436185] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.436262] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.436285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.436317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.436340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.436358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.436378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.436398] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.436417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.436435] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.436452] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.436469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.436473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.436489] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.436493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.436516] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.436539] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.436563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.436586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.436610] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.436633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.436656] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.436679] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.436703] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.436728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.436753] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.436813] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.436833] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.436853] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.436889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.436913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.436937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.436960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.436984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.437007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.437033] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.437058] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.437082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.437166] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.437196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.437229] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.437259] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.439346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.439369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.439388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.439407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.440978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.440999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.441017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.442583] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.442605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.444508] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.447843] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.447944] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.447977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.448019] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.464723] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.464773] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.464839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.465038] [drm:drm_mode_addfb2] [FB:78]
>[ 1351.465257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.481397] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.481446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.481518] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.498543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.498580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.498624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.498665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.498709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.498750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.498790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.498830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.498875] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.498917] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.498960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.499002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.499038] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.499069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.499227] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.499296] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.499363] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.499420] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.499567] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.499585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.499675] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.499708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.499743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.499781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.499812] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.499845] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.499878] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.499910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.499941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.499972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.500001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.500009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.500038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.500045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.500076] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.500137] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.500168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.500199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.500233] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.500264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.500294] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.500325] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.500356] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.500390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.500426] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.500513] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.500545] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.500575] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.500626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.500657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.500687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.500718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.500747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.500778] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.500813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.500845] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.500877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.500906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.500935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.500970] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.501002] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.503062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.503083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.503158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.503195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.504761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.504782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.504800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.506363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.506384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.508253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.511592] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.511675] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.511694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.511720] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.528465] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.528516] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.528582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.528776] [drm:drm_mode_addfb2] [FB:79]
>[ 1351.528903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.545144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.545193] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.545265] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.562289] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.562326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.562366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.562400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.562435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.562465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.562494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.562525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.562561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.562593] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.562624] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.562655] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.562683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.562710] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.562763] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.562804] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.562845] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.562884] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.563008] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.563022] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.563093] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.563163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.563198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.563233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.563264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.563298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.563333] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.563364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.563396] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.563427] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.563458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.563466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.563495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.563502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.563526] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.563545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.563563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.563581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.563603] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.563625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.563651] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.563677] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.563703] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.563731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.563759] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.563814] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.563837] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.563859] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.563898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.563925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.563951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.563976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.564003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.564028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.564057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.564087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.564148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.564179] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.564206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.564240] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.564269] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.566353] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.566376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.566395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.566417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.567990] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.568011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.568029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.569614] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.569635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.571537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.574894] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.574976] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.575015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.575067] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.591751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.591801] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.591867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.592064] [drm:drm_mode_addfb2] [FB:77]
>[ 1351.592450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.608428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.608477] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.608550] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.625620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.625656] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.625696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.625730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.625765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.625795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.625825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.625856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.625891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.625924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.625964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.626007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.626047] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.626086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.626230] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.626288] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.626331] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.626364] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.626512] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.626530] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.626628] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.626659] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.626691] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.626725] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.626754] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.626785] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.626816] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.626845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.626874] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.626901] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.626929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.626935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.626962] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.626968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.626996] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.627023] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.627050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.627077] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.627150] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.627183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.627215] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.627245] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.627276] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.627311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.627347] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.627433] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.627465] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.627494] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.627545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.627577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.627608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.627638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.627668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.627700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.627734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.627767] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.627799] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.627828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.627857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.627891] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.627923] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.629983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.630005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.630023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.630042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.631651] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.631671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.631689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.633279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.633302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.635169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.638504] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.638537] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.638561] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.638593] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.655330] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.655381] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.655448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.655646] [drm:drm_mode_addfb2] [FB:78]
>[ 1351.655782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.672007] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.672055] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.672223] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.691038] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.691075] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.691210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.691265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.691323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.691372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.691420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.691471] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.691528] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.691581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.691633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.691684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.691729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.691775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.691849] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.691892] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.691939] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.691969] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.692160] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.692181] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.692259] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.692282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.692306] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.692335] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.692360] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.692386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.692412] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.692438] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.692463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.692486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.692510] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.692516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.692541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.692545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.692571] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.692593] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.692618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.692640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.692666] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.692691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.692717] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.692742] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.692767] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.692794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.692822] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.692876] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.692898] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.692920] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.692959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.692985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.693007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.693027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.693046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.693067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.693129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.693161] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.693192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.693219] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.693246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.693279] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.693308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.695390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.695412] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.695430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.695449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.697019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.697040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.697063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.698665] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.698687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.700566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.703886] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.703950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.703988] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.704014] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.720729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.720780] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.720846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.721044] [drm:drm_mode_addfb2] [FB:79]
>[ 1351.721292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.737406] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.737458] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.737533] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.754551] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.754589] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.754628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.754662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.754697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.754727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.754756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.754787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.754822] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.754863] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.754905] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.754947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.754987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.755026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.755083] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.755215] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.755286] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.755347] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.755479] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.755498] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.755586] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.755619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.755653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.755691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.755723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.755756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.755789] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.755821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.755852] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.755882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.755912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.755920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.755948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.755956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.755986] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.756015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.756046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.756076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.756132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.756161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.756192] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.756223] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.756253] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.756287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.756322] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.756411] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.756443] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.756474] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.756526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.756557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.756587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.756617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.756647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.756677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.756711] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.756744] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.756777] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.756806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.756835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.756869] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.756900] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.758964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.758987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.759010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.759034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.760647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.760669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.760687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.762259] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.762282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.764156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.767508] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.767573] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.767592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.767617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.784379] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.784430] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.784496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.784702] [drm:drm_mode_addfb2] [FB:77]
>[ 1351.784842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.801078] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.801170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.801242] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.818768] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.818806] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.818846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.818880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.818923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.818963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.819004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.819044] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.819089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.819208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.819265] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.819317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.819365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.819412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.819497] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.819568] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.819615] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.819648] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.819796] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.819809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.819865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.819886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.819909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.819935] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.819955] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.819977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.819998] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.820017] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.820037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.820056] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.820118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.820126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.820154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.820161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.820189] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.820216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.820244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.820269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.820300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.820327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.820354] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.820380] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.820407] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.820438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.820471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.820550] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.820581] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.820612] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.820665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.820697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.820727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.820758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.820787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.820818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.820842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.820862] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.820883] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.820900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.820919] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.820941] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.820963] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.823018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.823038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.823057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.823123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.824695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.824714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.824731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.826301] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.826322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.828188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.831525] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.831623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.831656] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.831698] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.848409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.848459] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.848525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.848729] [drm:drm_mode_addfb2] [FB:78]
>[ 1351.848854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.865143] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.865189] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.865261] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.882286] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.882324] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.882368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.882410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.882454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.882494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.882534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.882574] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.882619] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.882661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.882704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.882745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.882785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.882824] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.882880] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.882940] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.882990] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.883026] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.883297] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.883321] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.883439] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.883485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.883532] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.883573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.883600] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.883630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.883659] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.883686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.883713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.883738] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.883762] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.883769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.883792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.883798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.883832] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.883866] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.883901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.883934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.883969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.884002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.884037] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.884071] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.884142] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.884187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.884233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.884349] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.884380] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.884413] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.884473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.884508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.884543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.884577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.884611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.884644] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.884669] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.884692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.884716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.884736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.884757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.884781] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.884808] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.886871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.886892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.886910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.886928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.888497] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.888516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.888533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.890079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.890125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.891984] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.895354] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.895418] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.895451] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.895501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.912205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.912258] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.912327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.912532] [drm:drm_mode_addfb2] [FB:79]
>[ 1351.912661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.928898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.928946] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.929021] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1351.946069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1351.946141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1351.946180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.946214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.946249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.946279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.946307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.946339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.946375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.946407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.946439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.946469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.946497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.946524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.946577] [drm:intel_power_well_disable [i915]] disabling display
>[ 1351.946618] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1351.946663] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.946681] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1351.946806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1351.946818] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1351.946875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1351.946901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1351.946926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1351.946954] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1351.946978] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1351.947003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1351.947027] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1351.947052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1351.947140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1351.947172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1351.947200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1351.947208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.947236] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1351.947243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1351.947271] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1351.947299] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1351.947326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1351.947353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1351.947384] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1351.947410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1351.947438] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1351.947465] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1351.947492] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1351.947525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.947557] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1351.947635] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1351.947666] [drm:intel_power_well_enable [i915]] enabling display
>[ 1351.947696] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1351.947750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1351.947782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1351.947812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1351.947842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1351.947873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1351.947904] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1351.947940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1351.947972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1351.948004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.948030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1351.948055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1351.948109] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1351.948138] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1351.950206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1351.950227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1351.950246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.950265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1351.951824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1351.951844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1351.951861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1351.953416] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1351.953437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1351.955311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1351.958655] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1351.958745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1351.958778] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1351.958820] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1351.975507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1351.975554] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1351.975618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1351.975811] [drm:drm_mode_addfb2] [FB:77]
>[ 1351.975936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1351.992200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1351.992248] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1351.992337] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.010748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.010785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.010825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.010865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.010909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.010949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.010990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.011029] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.011073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.011177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.011230] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.011280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.011320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.011362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.011436] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.011493] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.011549] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.011593] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.011806] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.011834] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.011961] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.012008] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.012056] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.012163] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.012196] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.012231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.012265] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.012298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.012329] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.012360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.012390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.012398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.012426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.012434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.012464] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.012494] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.012523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.012553] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.012586] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.012615] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.012646] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.012673] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.012702] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.012736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.012770] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.012850] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.012882] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.012912] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.012964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.012996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.013027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.013057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.013116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.013149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.013186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.013219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.013253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.013283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.013314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.013349] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.013382] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.015456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.015478] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.015496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.015520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.017109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.017130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.017149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.018703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.018724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.020594] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.023884] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.023977] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.024009] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.024059] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.040747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.040795] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.040858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.041239] [drm:drm_mode_addfb2] [FB:78]
>[ 1352.041376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.057433] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.057482] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.057570] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.074610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.074648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.074687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.074721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.074756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.074787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.074816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.074848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.074883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.074916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.074948] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.074979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.075007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.075034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.075162] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.075233] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.075299] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.075352] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.075575] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.075601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.075657] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.075679] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.075703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.075731] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.075756] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.075783] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.075809] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.075836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.075862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.075887] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.075913] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.075919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.075943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.075948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.075974] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.075999] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.076025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.076051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.076106] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.076138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.076168] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.076197] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.076225] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.076257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.076290] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.076380] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.076411] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.076441] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.076494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.076527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.076559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.076590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.076614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.076635] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.076657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.076678] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.076699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.076717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.076735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.076758] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.076779] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.078825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.078846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.078864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.078882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.080445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.080465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.080483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.082061] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.082100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.083963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.087322] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.087397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.087430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.087472] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.104173] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.104221] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.104284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.104482] [drm:drm_mode_addfb2] [FB:79]
>[ 1352.104593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.120850] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.120896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.120966] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.137992] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.138030] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.138070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.138200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.138258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.138308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.138357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.138409] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.138466] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.138518] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.138569] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.138619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.138664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.138709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.138795] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.138860] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.138923] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.138964] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.139116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.139136] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.139222] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.139245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.139277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.139300] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.139321] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.139345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.139369] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.139393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.139416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.139437] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.139460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.139464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.139487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.139491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.139515] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.139535] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.139559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.139580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.139604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.139627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.139651] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.139674] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.139698] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.139722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.139748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.139807] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.139827] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.139847] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.139884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.139908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.139931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.139955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.139978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.140001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.140026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.140051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.140140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.140170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.140200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.140233] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.140263] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.142334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.142355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.142374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.142393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.143968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.143988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.144006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.145594] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.145615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.147608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.150907] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.150993] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.151026] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.151146] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.167770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.167820] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.167886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.168291] [drm:drm_mode_addfb2] [FB:77]
>[ 1352.168422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.184432] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.184481] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.184570] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.202908] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.202946] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.202986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.203020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.203055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.203174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.203218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.203251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.203289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.203322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.203353] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.203388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.203405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.203423] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.203460] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.203488] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.203516] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.203536] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.203643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.203655] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.203711] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.203733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.203755] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.203780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.203800] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.203822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.203842] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.203863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.203882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.203902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.203920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.203926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.203943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.203948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.203967] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.203991] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.204018] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.204043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.204108] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.204129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.204155] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.204181] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.204207] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.204235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.204263] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.204317] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.204339] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.204361] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.204400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.204425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.204447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.204467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.204487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.204508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.204530] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.204551] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.204572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.204590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.204608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.204631] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.204656] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.207050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.207089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.207108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.207128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.208699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.208719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.208737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.210300] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.210321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.212183] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.215494] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.215572] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.215591] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.215617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.232341] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.232389] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.232453] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.232633] [drm:drm_mode_addfb2] [FB:78]
>[ 1352.232761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.249019] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.249065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.249250] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.268012] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.268049] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.268182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.268234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.268291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.268339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.268387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.268436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.268493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.268546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.268597] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.268648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.268694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.268739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.268834] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.268877] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.268925] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.268955] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.269139] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.269159] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.269237] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.269261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.269285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.269317] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.269335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.269356] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.269375] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.269394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.269413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.269431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.269448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.269452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.269468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.269472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.269489] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.269506] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.269522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.269538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.269558] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.269580] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.269604] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.269627] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.269651] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.269675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.269701] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.269750] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.269770] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.269790] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.269827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.269849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.269869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.269888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.269906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.269924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.269944] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.269964] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.269982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.269999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.270021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.270046] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.270117] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.272187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.272210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.272229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.272249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.273819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.273839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.273858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.275420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.275441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.277313] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.280641] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.280697] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.280730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.280772] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.297476] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.297527] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.297593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.297790] [drm:drm_mode_addfb2] [FB:79]
>[ 1352.297920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.314152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.314201] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.314291] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.331303] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.331341] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.331380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.331414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.331449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.331479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.331509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.331541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.331583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.331626] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.331669] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.331711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.331751] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.331790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.331847] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.331894] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.331943] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.331979] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.332230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.332259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.332369] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.332404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.332431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.332457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.332477] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.332503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.332529] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.332555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.332581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.332607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.332633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.332639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.332663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.332668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.332694] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.332720] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.332743] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.332768] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.332794] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.332820] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.332846] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.332872] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.332898] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.332925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.332953] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.333015] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.333037] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.333088] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.333143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.333174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.333204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.333232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.333260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.333288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.333321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.333352] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.333383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.333411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.333437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.333471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.333503] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.335562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.335583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.335602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.335622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.337276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.337297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.337315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.338873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.338893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.340763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.344052] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.344144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.344176] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.344219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.360926] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.360976] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.361042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.361386] [drm:drm_mode_addfb2] [FB:77]
>[ 1352.361517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.377598] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.377646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.377735] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.394756] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.394794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.394834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.394868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.394903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.394934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.394963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.394995] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.395031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.395144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.395198] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.395245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.395287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.395335] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.395393] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.395435] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.395478] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.395510] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.395703] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.395731] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.395833] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.395856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.395879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.395909] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.395934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.395961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.395987] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.396013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.396042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.396103] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.396133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.396142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.396170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.396178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.396206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.396234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.396261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.396288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.396319] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.396345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.396372] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.396398] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.396424] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.396456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.396491] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.396569] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.396601] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.396631] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.396685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.396717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.396748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.396773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.396792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.396813] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.396835] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.396855] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.396882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.396907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.396932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.396960] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.396986] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.399034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.399073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.399092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.399112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.400694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.400716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.400735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.402306] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.402328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.404204] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.407524] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.407587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.407620] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.407662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.424355] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.424400] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.424463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.424646] [drm:drm_mode_addfb2] [FB:78]
>[ 1352.424762] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.441066] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.441149] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.441225] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.458256] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.458293] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.458333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.458367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.458410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.458451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.458491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.458531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.458575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.458618] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.458661] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.458703] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.458742] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.458781] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.458838] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.458885] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.458935] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.458970] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.459193] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.459225] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.459317] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.459351] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.459387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.459424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.459449] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.459472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.459494] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.459516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.459537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.459557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.459581] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.459588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.459612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.459617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.459644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.459669] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.459695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.459721] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.459748] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.459773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.459799] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.459825] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.459851] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.459878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.459906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.459958] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.459979] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.460001] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.460041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.460096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.460128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.460157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.460186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.460214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.460247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.460277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.460308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.460336] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.460363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.460396] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.460426] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.462493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.462514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.462532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.462556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.464159] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.464180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.464198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.465763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.465787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.467656] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.470976] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.471040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.471164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.471237] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.487820] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.487870] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.487936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.488250] [drm:drm_mode_addfb2] [FB:79]
>[ 1352.488419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.504514] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.504563] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.504633] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.521644] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.521682] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.521722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.521755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.521791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.521830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.521870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.521910] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.521955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.521997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.522039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.522175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.522228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.522279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.522366] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.522431] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.522496] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.522547] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.522757] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.522778] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.522877] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.522906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.522937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.522972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.523000] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.523029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.523110] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.523141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.523173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.523203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.523233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.523241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.523270] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.523278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.523308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.523335] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.523365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.523392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.523425] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.523452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.523480] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.523507] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.523535] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.523567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.523601] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.523677] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.523707] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.523736] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.523787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.523818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.523845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.523874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.523900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.523929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.523962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.523993] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.524025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.524074] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.524101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.524135] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.524164] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.526234] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.526254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.526272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.526291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.527866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.527889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.527907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.529473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.529495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.531366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.534681] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.534752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.534791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.534843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.551527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.551580] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.551651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.551874] [drm:drm_mode_addfb2] [FB:77]
>[ 1352.552015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.568225] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.568271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.568340] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.585356] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.585398] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.585443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.585483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.585527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.585568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.585607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.585647] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.585692] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.585734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.585776] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.585819] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.585858] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.585897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.585954] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.586001] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.586051] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.586179] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.586364] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.586382] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.586470] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.586503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.586539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.586576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.586608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.586642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.586675] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.586707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.586738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.586767] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.586797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.586804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.586832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.586839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.586868] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.586898] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.586927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.586957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.586990] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.587020] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.587075] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.587104] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.587135] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.587170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.587205] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.587295] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.587326] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.587357] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.587409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.587440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.587472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.587502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.587532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.587563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.587597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.587631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.587663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.587692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.587722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.587756] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.587787] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.589851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.589873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.589894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.589918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.591482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.591502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.591520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.593094] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.593115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.594973] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.598309] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.598409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.598442] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.598488] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.615186] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.615237] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.615303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.615522] [drm:drm_mode_addfb2] [FB:78]
>[ 1352.615664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.631884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.631930] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.632000] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.649012] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.649050] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.649187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.649241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.649298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.649347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.649395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.649448] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.649504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.649557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.649608] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.649660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.649706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.649748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.649803] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.649846] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.649894] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.649925] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.650098] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.650119] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.650206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.650230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.650261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.650285] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.650303] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.650323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.650343] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.650362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.650380] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.650398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.650414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.650419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.650435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.650439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.650456] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.650473] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.650489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.650505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.650524] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.650540] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.650556] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.650573] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.650588] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.650608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.650628] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.650676] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.650696] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.650716] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.650753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.650777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.650801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.650824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.650848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.650870] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.650895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.650920] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.650945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.650969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.650992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.651016] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.651039] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.653162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.653183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.653202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.653221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.654792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.654812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.654830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.656398] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.656422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.658294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.661638] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.661730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.661763] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.661806] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.678505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.678556] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.678621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.678843] [drm:drm_mode_addfb2] [FB:79]
>[ 1352.678986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.695204] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.695251] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.695354] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.714160] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.714198] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.714239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.714273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.714308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.714339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.714368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.714399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.714434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.714467] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.714498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.714530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.714558] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.714586] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.714640] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.714681] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.714723] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.714754] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.714949] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.714968] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.715142] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.715194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.715248] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.715306] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.715351] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.715401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.715448] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.715494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.715539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.715582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.715623] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.715637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.715681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.715693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.715738] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.715780] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.715822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.715863] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.715916] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.715961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.716006] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.716051] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.716137] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.716195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.716242] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.716345] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.716384] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.716419] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.716491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.716533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.716573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.716614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.716652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.716680] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.716710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.716738] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.716766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.716798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.716833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.716868] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.716902] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.718953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.718975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.718993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.719012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.720625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.720647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.720666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.722236] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.722258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.724120] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.727445] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.727487] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.727506] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.727532] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.744283] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.744333] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.744398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.744621] [drm:drm_mode_addfb2] [FB:77]
>[ 1352.744765] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.760980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.761027] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.761204] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.779988] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.780026] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.780156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.780210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.780267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.780316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.780363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.780414] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.780471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.780523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.780575] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.780626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.780680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.780709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.780765] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.780807] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.780847] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.780880] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.781055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.781072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.781137] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.781160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.781184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.781209] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.781229] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.781250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.781279] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.781298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.781317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.781334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.781356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.781361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.781384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.781388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.781413] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.781434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.781458] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.781479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.781503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.781525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.781549] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.781572] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.781595] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.781620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.781645] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.781694] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.781714] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.781734] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.781770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.781794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.781818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.781841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.781865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.781888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.781913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.781938] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.781963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.781986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.782009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.782033] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.782104] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.784195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.784218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.784240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.784264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.785828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.785849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.785872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.787425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.787447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.789318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.792667] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.792756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.792796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.792847] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.809531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.809582] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.809648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.809870] [drm:drm_mode_addfb2] [FB:78]
>[ 1352.809996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.826228] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.826276] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.826345] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.843359] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.843397] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.843437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.843477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.843521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.843562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.843602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.843641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.843685] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.843728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.843770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.843813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.843852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.843891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.843948] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.844002] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.844032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.844122] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.844253] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.844271] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.844359] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.844392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.844426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.844463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.844494] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.844527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.844560] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.844592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.844624] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.844654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.844683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.844690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.844719] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.844727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.844755] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.844784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.844814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.844843] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.844873] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.844902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.844933] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.844962] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.844991] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.845024] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.845090] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.845177] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.845208] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.845239] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.845291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.845322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.845354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.845381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.845411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.845442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.845476] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.845508] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.845541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.845572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.845602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.845636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.845667] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.847729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.847749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.847768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.847787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.849360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.849380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.849399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.850947] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.850968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.852830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.856149] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.856197] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.856216] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.856243] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.872992] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.873043] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.873215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.873472] [drm:drm_mode_addfb2] [FB:79]
>[ 1352.873607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.889692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.889740] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.889810] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.908378] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.908416] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.908456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.908489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.908525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.908555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.908584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.908615] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.908651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.908683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.908714] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.908746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.908774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.908802] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.908855] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.908896] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.908938] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.908969] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.909230] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.909259] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.909396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.909446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.909497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.909534] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.909564] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.909597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.909630] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.909661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.909692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.909722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.909752] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.909760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.909787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.909795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.909823] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.909852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.909881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.909910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.909943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.909973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.910004] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.910033] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.910088] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.910123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.910158] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.910248] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.910279] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.910310] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.910361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.910393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.910421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.910450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.910477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.910508] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.910542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.910574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.910607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.910636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.910665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.910699] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.910731] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.912800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.912823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.912846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.912871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.914446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.914467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.914485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.916031] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.916075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.917944] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.921314] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.921381] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.921421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.921472] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1352.938157] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.938208] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.938280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.938500] [drm:drm_mode_addfb2] [FB:77]
>[ 1352.938644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.954854] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1352.954901] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1352.954969] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1352.971982] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1352.972020] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1352.972154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.972207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.972265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.972314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.972362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.972412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1352.972469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.972522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.972574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.972626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.972672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.972718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.972804] [drm:intel_power_well_disable [i915]] disabling display
>[ 1352.972869] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1352.972932] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1352.972975] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1352.973143] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1352.973162] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1352.973254] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1352.973286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1352.973319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1352.973349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1352.973368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1352.973389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1352.973409] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1352.973429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1352.973452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1352.973474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1352.973497] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1352.973501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.973524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1352.973528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1352.973552] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1352.973573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1352.973596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1352.973620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1352.973643] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1352.973666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1352.973690] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1352.973713] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1352.973736] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1352.973761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1352.973786] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1352.973834] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1352.973854] [drm:intel_power_well_enable [i915]] enabling display
>[ 1352.973874] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1352.973910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1352.973934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1352.973958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1352.973981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1352.974005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1352.974074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1352.974113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1352.974147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1352.974183] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1352.974210] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1352.974240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1352.974277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1352.974307] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1352.976383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1352.976404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1352.976423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.976447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1352.978016] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1352.978048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1352.978066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1352.979629] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1352.979651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1352.981512] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1352.984834] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1352.984896] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1352.984929] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1352.984971] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.001653] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.001700] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.001762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.001996] [drm:drm_mode_addfb2] [FB:78]
>[ 1353.002225] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.018373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.018419] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.018489] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.035501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.035538] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.035582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.035623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.035667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.035707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.035747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.035786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.035831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.035873] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.035916] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.035958] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.035997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.036036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.036180] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.036252] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.036322] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.036369] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.036490] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.036502] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.036560] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.036583] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.036607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.036632] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.036653] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.036674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.036696] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.036716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.036736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.036755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.036773] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.036778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.036802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.036807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.036833] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.036859] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.036883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.036909] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.036935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.036960] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.036987] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.037015] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.037073] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.037106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.037140] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.037214] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.037246] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.037276] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.037330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.037362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.037393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.037424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.037455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.037486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.037522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.037556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.037587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.037607] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.037625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.037647] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.037668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.039714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.039735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.039753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.039772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.041345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.041365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.041383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.042942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.042963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.044833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.048181] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.048270] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.048303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.048346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.065077] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.065127] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.065194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.065410] [drm:drm_mode_addfb2] [FB:79]
>[ 1353.065558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.081744] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.081790] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.081860] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.098866] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.098904] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.098944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.098978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.099013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.099129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.099174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.099227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.099284] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.099335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.099386] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.099436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.099477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.099520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.099604] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.099668] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.099730] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.099783] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.099911] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.099934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.099988] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.100019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.100093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.100133] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.100165] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.100202] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.100236] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.100268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.100300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.100332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.100361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.100369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.100399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.100406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.100436] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.100465] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.100494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.100523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.100553] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.100582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.100609] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.100638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.100666] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.100699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.100734] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.100810] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.100840] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.100871] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.100922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.100954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.100985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.101015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.101067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.101100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.101133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.101169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.101202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.101232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.101262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.101297] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.101330] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.103402] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.103422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.103441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.103460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.105066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.105090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.105113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.106669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.106691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.108567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.111888] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.111951] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.111990] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.112016] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.128729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.128779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.128845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.129128] [drm:drm_mode_addfb2] [FB:77]
>[ 1353.129297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.145429] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.145476] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.145550] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.162556] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.162593] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.162633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.162668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.162703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.162734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.162764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.162796] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.162831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.162864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.162896] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.162927] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.162955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.162982] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.163118] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.163184] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.163257] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.163289] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.163417] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.163436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.163521] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.163550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.163583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.163619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.163646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.163678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.163708] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.163738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.163766] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.163795] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.163820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.163827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.163854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.163860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.163889] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.163914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.163942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.163967] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.163998] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.164049] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.164079] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.164106] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.164135] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.164171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.164206] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.164293] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.164323] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.164353] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.164403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.164433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.164460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.164489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.164515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.164544] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.164577] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.164609] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.164641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.164667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.164694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.164728] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.164756] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.166818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.166838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.166856] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.166875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.168444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.168467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.168490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.170063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.170086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.171956] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.175272] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.175338] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.175370] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.175412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.192119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.192172] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.192244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.192444] [drm:drm_mode_addfb2] [FB:78]
>[ 1353.192596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.208815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.208863] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.208931] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.226847] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.226885] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.226925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.226959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.226995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.227111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.227161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.227212] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.227270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.227324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.227360] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.227392] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.227422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.227449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.227504] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.227547] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.227590] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.227622] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.227746] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.227759] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.227814] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.227835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.227858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.227883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.227903] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.227924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.227946] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.227966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.227986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.228010] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.228067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.228075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.228102] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.228110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.228137] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.228164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.228190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.228217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.228248] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.228274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.228301] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.228329] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.228355] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.228386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.228418] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.228495] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.228526] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.228557] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.228610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.228641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.228672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.228702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.228731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.228762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.228796] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.228829] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.228852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.228870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.228888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.228910] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.228931] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.230961] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.230982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.231000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.231069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.232643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.232663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.232682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.234246] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.234267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.236128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.239465] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.239563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.239595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.239637] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.256339] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.256390] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.256456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.256653] [drm:drm_mode_addfb2] [FB:79]
>[ 1353.256806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.273039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.273129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.273204] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.290194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.290232] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.290271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.290305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.290341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.290372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.290402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.290434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.290469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.290501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.290533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.290573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.290612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.290652] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.290709] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.290756] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.290806] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.290842] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.291095] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.291123] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.291255] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.291303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.291352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.291404] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.291447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.291493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.291539] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.291583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.291627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.291668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.291708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.291719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.291757] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.291767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.291808] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.291848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.291889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.291928] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.291974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.292014] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.292105] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.292138] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.292168] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.292202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.292237] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.292314] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.292345] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.292376] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.292428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.292459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.292489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.292519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.292545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.292576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.292610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.292643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.292676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.292705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.292734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.292768] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.292799] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.294874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.294895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.294913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.294932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.296540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.296564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.296593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.298226] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.298247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.300108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.303396] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.303476] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.303495] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.303521] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.320271] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.320322] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.320388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.320608] [drm:drm_mode_addfb2] [FB:77]
>[ 1353.320750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.336969] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.337015] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.337190] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.355964] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.356002] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.356134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.356171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.356209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.356240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.356269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.356301] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.356339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.356373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.356407] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.356438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.356468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.356496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.356551] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.356593] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.356636] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.356666] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.356770] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.356783] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.356838] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.356866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.356892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.356922] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.356947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.356974] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.357003] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.357066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.357096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.357124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.357152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.357160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.357187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.357196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.357224] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.357250] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.357277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.357303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.357335] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.357361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.357388] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.357414] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.357441] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.357472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.357505] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.357582] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.357610] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.357629] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.357664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.357684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.357703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.357721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.357739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.357759] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.357782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.357802] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.357821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.357839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.357864] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.357891] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.357916] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.359964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.359988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.360010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.360093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.361664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.361685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.361704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.363258] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.363279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.365152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.368462] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.368534] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.368566] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.368609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.385313] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.385364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.385430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.385647] [drm:drm_mode_addfb2] [FB:78]
>[ 1353.385791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.402013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.402098] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.402168] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.419143] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.419180] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.419224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.419265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.419310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.419350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.419390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.419430] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.419475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.419517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.419560] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.419602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.419641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.419680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.419737] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.419783] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.419834] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.419870] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.420130] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.420156] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.420281] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.420326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.420374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.420424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.420465] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.420509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.420552] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.420594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.420635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.420675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.420713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.420723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.420760] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.420770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.420810] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.420849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.420887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.420927] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.420969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.421008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.421088] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.421136] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.421171] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.421209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.421248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.421330] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.421364] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.421398] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.421453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.421489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.421521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.421551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.421583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.421616] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.421654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.421690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.421725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.421757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.421788] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.421825] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.421860] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.423966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.423987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.424068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.424105] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.425690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.425712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.425731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.427296] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.427319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.429182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.432463] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.432501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.432524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.432556] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.449295] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.449345] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.449412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.449612] [drm:drm_mode_addfb2] [FB:79]
>[ 1353.449750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.465992] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.466068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.466137] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.483122] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.483159] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.483199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.483232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.483267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.483298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.483328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.483360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.483395] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.483428] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.483460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.483491] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.483520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.483547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.483592] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.483618] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.483642] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.483661] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.483775] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.483787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.483843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.483866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.483889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.483914] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.483933] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.483955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.483976] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.484006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.484076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.484105] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.484138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.484146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.484175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.484184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.484214] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.484244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.484275] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.484305] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.484338] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.484368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.484399] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.484429] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.484459] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.484494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.484529] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.484605] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.484636] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.484667] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.484718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.484749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.484780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.484810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.484840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.484869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.484903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.484936] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.484968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.484998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.485050] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.485085] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.485117] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.487202] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.487224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.487243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.487263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.488822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.488842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.488860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.490422] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.490442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.492312] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.495657] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.495747] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.495780] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.495822] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.512526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.512577] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.512642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.512865] [drm:drm_mode_addfb2] [FB:77]
>[ 1353.512990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.529222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.529269] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.529338] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.546352] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.546394] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.546439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.546480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.546524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.546564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.546604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.546643] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.546688] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.546731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.546773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.546815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.546855] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.546894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.546951] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.546998] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.547109] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.547143] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.547284] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.547301] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.547389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.547419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.547452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.547489] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.547519] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.547551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.547580] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.547610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.547639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.547668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.547694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.547701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.547728] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.547735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.547763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.547791] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.547820] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.547846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.547877] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.547902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.547930] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.547956] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.547984] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.548039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.548077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.548150] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.548181] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.548211] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.548262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.548293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.548320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.548348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.548374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.548404] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.548437] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.548468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.548499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.548525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.548553] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.548585] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.548615] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.550679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.550700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.550718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.550737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.552303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.552324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.552343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.553890] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.553911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.555783] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.559105] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.559165] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.559197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.559240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.575934] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.575982] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.576143] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.576436] [drm:drm_mode_addfb2] [FB:78]
>[ 1353.576574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.592644] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.592691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.592760] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.610459] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.610498] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.610538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.610578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.610623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.610663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.610703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.610743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.610788] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.610830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.610872] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.610914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.610953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.610993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.611138] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.611205] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.611273] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.611323] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.611551] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.611572] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.611670] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.611704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.611739] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.611778] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.611809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.611843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.611876] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.611908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.611940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.611970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.611999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.612040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.612070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.612078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.612108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.612139] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.612167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.612196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.612226] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.612256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.612286] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.612312] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.612340] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.612382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.612414] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.612484] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.612512] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.612540] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.612588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.612617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.612646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.612671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.612698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.612727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.612758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.612788] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.612818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.612845] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.612871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.612903] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.612932] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.615048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.615070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.615089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.615108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.616678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.616698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.616716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.618270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.618291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.620165] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.623509] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.623600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.623633] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.623676] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.640377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.640428] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.640493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.640714] [drm:drm_mode_addfb2] [FB:79]
>[ 1353.640856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.657081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.657137] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.657207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.674206] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.674243] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.674283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.674323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.674368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.674408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.674448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.674488] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.674533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.674576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.674618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.674660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.674699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.674738] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.674796] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.674842] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.674890] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.674923] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.675083] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.675103] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.675203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.675237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.675273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.675310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.675331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.675354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.675376] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.675401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.675427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.675453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.675479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.675485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.675510] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.675515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.675541] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.675566] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.675593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.675619] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.675645] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.675670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.675697] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.675722] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.675749] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.675776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.675804] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.675858] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.675880] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.675902] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.675942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.675968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.675995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.676063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.676094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.676125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.676157] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.676187] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.676218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.676244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.676271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.676303] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.676333] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.678416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.678438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.678456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.678476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.680044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.680064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.680085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.681646] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.681669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.683559] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.686909] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.686995] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.687107] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.687158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.703771] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.703822] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.703888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.704206] [drm:drm_mode_addfb2] [FB:77]
>[ 1353.704345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.720471] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.720517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.720605] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.737630] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.737667] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.737707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.737741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.737775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.737806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.737836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.737868] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.737903] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.737936] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.737968] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.737999] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.738105] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.738148] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.738233] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.738290] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.738334] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.738366] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.738509] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.738522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.738578] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.738599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.738625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.738654] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.738679] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.738707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.738733] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.738759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.738786] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.738812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.738837] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.738843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.738868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.738873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.738899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.738925] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.738950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.738976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.739044] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.739076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.739106] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.739134] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.739162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.739195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.739227] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.739304] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.739332] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.739363] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.739417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.739448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.739479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.739509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.739539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.739570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.739604] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.739638] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.739671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.739700] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.739722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.739744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.739766] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.741813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.741834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.741852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.741871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.743446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.743466] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.743483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.745039] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.745062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.746930] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.750253] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.750313] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.750345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.750387] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.767093] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.767146] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.767218] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.767439] [drm:drm_mode_addfb2] [FB:78]
>[ 1353.767585] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.783791] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.783837] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.783927] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.800897] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.800935] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.800975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.801093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.801150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.801195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.801240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.801284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.801339] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.801390] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.801440] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.801489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.801530] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.801575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.801660] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.801724] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.801786] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.801835] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.802040] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.802060] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.802160] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.802184] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.802208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.802234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.802262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.802283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.802303] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.802326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.802350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.802373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.802396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.802401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.802424] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.802428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.802452] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.802475] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.802498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.802520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.802544] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.802567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.802591] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.802614] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.802637] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.802662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.802687] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.802747] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.802767] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.802787] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.802823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.802847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.802871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.802895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.802918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.802941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.802966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.802991] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.803068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.803098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.803127] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.803161] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.803191] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.805253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.805275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.805295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.805316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.806866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.806886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.806903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.808460] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.808481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.810349] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.813688] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.813787] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.813827] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.813879] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.830570] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.830621] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.830689] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.830896] [drm:drm_mode_addfb2] [FB:79]
>[ 1353.831102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.847261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.847309] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.847383] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.864394] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.864432] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.864473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.864507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.864543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.864573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.864602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.864634] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.864668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.864700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.864731] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.864762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.864789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.864816] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.864869] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.864911] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.864961] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.864997] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.865271] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.865300] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.865409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.865443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.865478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.865515] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.865546] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.865580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.865614] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.865645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.865678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.865708] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.865737] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.865745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.865772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.865779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.865809] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.865838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.865868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.865898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.865930] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.865960] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.865987] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.866038] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.866068] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.866103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.866138] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.866230] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.866261] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.866291] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.866342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.866373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.866400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.866430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.866456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.866487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.866522] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.866554] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.866587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.866617] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.866648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.866681] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.866713] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.868789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.868811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.868830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.868849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.870413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.870437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.870460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.872040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.872062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.873924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.877234] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.877306] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.877338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.877380] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.894073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.894122] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.894186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.894388] [drm:drm_mode_addfb2] [FB:77]
>[ 1353.894512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.910760] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.910806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.910877] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.927906] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.927943] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.927983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.928111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.928170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.928220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.928268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.928320] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.928379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.928431] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.928482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.928533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.928579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.928624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.928709] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.928775] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.928830] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.928863] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.929075] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.929095] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.929164] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.929188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.929212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.929245] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.929264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.929284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.929304] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.929322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.929341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.929358] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.929374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.929379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.929395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.929399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.929416] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.929432] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.929448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.929464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.929484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.929500] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.929517] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.929533] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.929549] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.929569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.929590] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.929637] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.929654] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.929670] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.929702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.929720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.929738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.929755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.929771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.929789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.929808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.929826] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.929844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.929860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.929876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.929897] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.929915] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.931967] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.932004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.932023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.932042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.933610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.933633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.933656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.935230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.935251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1353.937116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1353.940430] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1353.940499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1353.940532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1353.940582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1353.957286] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.957336] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.957402] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.957628] [drm:drm_mode_addfb2] [FB:78]
>[ 1353.957771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.973986] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1353.974077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1353.974169] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1353.991194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1353.991232] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1353.991272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.991307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.991342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.991373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.991402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.991434] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1353.991469] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.991501] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.991533] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.991564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.991593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.991620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.991674] [drm:intel_power_well_disable [i915]] disabling display
>[ 1353.991715] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1353.991757] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1353.991787] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1353.991967] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1353.992048] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1353.992204] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1353.992252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1353.992303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1353.992355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1353.992397] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1353.992444] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1353.992492] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1353.992536] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1353.992580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1353.992622] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1353.992663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1353.992673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.992713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1353.992723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1353.992764] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1353.992805] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1353.992846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1353.992886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1353.992931] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1353.992971] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1353.993046] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1353.993084] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1353.993128] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1353.993185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1353.993225] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1353.993313] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1353.993348] [drm:intel_power_well_enable [i915]] enabling display
>[ 1353.993383] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1353.993443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1353.993479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1353.993515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1353.993550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1353.993583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1353.993615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1353.993654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1353.993691] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1353.993728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1353.993762] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1353.993796] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1353.993835] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1353.993871] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1353.995953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1353.995977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1353.996058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.996090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1353.997677] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1353.997697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1353.997715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1353.999278] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1353.999299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.001172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.004456] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.004488] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.004511] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.004542] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.021284] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.021335] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.021401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.021580] [drm:drm_mode_addfb2] [FB:79]
>[ 1354.021713] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.037958] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.038037] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.038110] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.055112] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.055149] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.055189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.055223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.055258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.055297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.055337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.055377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.055422] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.055465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.055507] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.055549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.055587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.055608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.055640] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.055666] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.055693] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.055712] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.055837] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.055849] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.055905] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.055928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.055951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.055987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.056055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.056087] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.056118] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.056148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.056177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.056205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.056232] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.056240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.056266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.056273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.056300] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.056327] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.056353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.056379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.056412] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.056441] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.056468] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.056494] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.056521] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.056554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.056589] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.056686] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.056718] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.056749] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.056805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.056838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.056867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.056888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.056907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.056929] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.056951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.056972] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.057031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.057061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.057087] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.057120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.057148] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.059217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.059238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.059256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.059275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.060849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.060868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.060886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.062443] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.062463] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.064340] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.067688] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.067778] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.067819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.067855] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.084554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.084605] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.084671] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.084866] [drm:drm_mode_addfb2] [FB:77]
>[ 1354.084997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.101230] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.101278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.101349] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.118376] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.118414] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.118454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.118488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.118523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.118553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.118584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.118616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.118651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.118684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.118716] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.118748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.118776] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.118803] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.118857] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.118898] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.118940] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.118976] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.119183] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.119201] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.119289] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.119321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.119355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.119392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.119423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.119456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.119489] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.119521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.119551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.119581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.119611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.119618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.119646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.119653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.119683] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.119712] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.119741] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.119767] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.119800] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.119829] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.119859] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.119888] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.119917] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.119950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.119984] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.120083] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.120115] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.120146] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.120201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.120231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.120262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.120294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.120323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.120354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.120387] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.120420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.120452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.120481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.120510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.120541] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.120572] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.122641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.122662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.122680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.122699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.124275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.124295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.124313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.125872] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.125895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.127771] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.131088] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.131154] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.131173] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.131203] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.147932] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.147985] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.148161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.148390] [drm:drm_mode_addfb2] [FB:78]
>[ 1354.148501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.164608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.164656] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.164727] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.181757] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.181794] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.181834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.181869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.181904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.181935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.181964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.182090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.182153] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.182208] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.182260] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.182311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.182356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.182401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.182468] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.182511] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.182551] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.182584] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.182712] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.182725] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.182797] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.182821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.182845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.182871] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.182894] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.182918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.182942] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.182976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.183050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.183081] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.183109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.183117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.183145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.183153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.183181] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.183209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.183237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.183263] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.183295] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.183322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.183352] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.183382] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.183408] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.183443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.183468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.183520] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.183540] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.183558] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.183592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.183618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.183644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.183670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.183697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.183722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.183751] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.183779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.183807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.183833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.183859] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.183886] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.183912] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.185971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.186013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.186032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.186052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.187640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.187672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.187697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.189262] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.189283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.191143] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.194482] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.194579] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.194612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.194654] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.211358] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.211409] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.211474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.211673] [drm:drm_mode_addfb2] [FB:79]
>[ 1354.211798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.228031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.228079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.228151] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.245179] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.245216] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.245261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.245302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.245346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.245386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.245426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.245466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.245511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.245553] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.245596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.245638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.245677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.245717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.245774] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.245820] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.245870] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.245906] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.246100] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.246118] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.246206] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.246240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.246276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.246313] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.246344] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.246378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.246411] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.246444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.246476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.246506] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.246536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.246544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.246572] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.246579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.246608] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.246637] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.246667] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.246696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.246729] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.246758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.246788] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.246817] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.246844] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.246876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.246910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.247019] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.247052] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.247081] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.247134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.247167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.247199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.247231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.247262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.247295] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.247330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.247362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.247395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.247424] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.247454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.247488] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.247519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.249576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.249596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.249614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.249633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.251230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.251253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.251275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.252839] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.252861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.254724] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.258042] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.258105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.258138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.258182] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.274884] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.274935] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.275091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.275334] [drm:drm_mode_addfb2] [FB:77]
>[ 1354.275460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.291602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.291650] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.291723] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.309916] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.309953] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.310087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.310141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.310198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.310246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.310294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.310345] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.310401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.310446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.310479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.310512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.310541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.310570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.310626] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.310669] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.310709] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.310741] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.310894] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.310906] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.310973] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.311044] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.311078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.311113] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.311142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.311175] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.311205] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.311235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.311265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.311293] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.311323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.311331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.311359] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.311368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.311396] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.311426] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.311455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.311484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.311517] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.311546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.311577] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.311606] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.311636] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.311668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.311693] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.311746] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.311769] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.311791] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.311832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.311858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.311884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.311910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.311937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.311962] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.312023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.312057] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.312089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.312116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.312144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.312177] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.312206] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.314276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.314297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.314319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.314343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.315922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.315944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.315963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.317567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.317589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.319490] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.322780] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.322867] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.322900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.322944] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.339652] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.339703] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.339769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.340030] [drm:drm_mode_addfb2] [FB:78]
>[ 1354.340230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.356368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.356421] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.356497] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.373511] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.373548] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.373587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.373621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.373656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.373687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.373716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.373747] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.373782] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.373824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.373867] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.373909] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.373955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.374036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.374091] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.374135] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.374177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.374210] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.374360] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.374380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.374476] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.374508] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.374542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.374578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.374606] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.374638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.374669] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.374701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.374729] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.374758] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.374784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.374791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.374818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.374825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.374854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.374880] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.374909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.374937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.374969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.375028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.375055] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.375084] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.375111] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.375145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.375179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.375258] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.375288] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.375317] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.375369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.375400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.375427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.375457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.375484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.375513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.375546] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.375578] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.375609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.375635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.375662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.375693] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.375723] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.377812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.377834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.377852] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.377872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.379446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.379467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.379484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.381077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.381101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.382966] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.386315] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.386410] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.386438] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.386473] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.403193] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.403243] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.403309] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.403507] [drm:drm_mode_addfb2] [FB:79]
>[ 1354.403636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.419869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.419918] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.420068] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.437064] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.437102] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.437143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.437176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.437211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.437242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.437271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.437303] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.437345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.437388] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.437433] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.437463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.437489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.437515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.437563] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.437599] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.437636] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.437664] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.437841] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.437859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.437942] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.437976] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.438070] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.438125] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.438167] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.438216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.438259] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.438303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.438343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.438385] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.438422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.438435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.438486] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.438497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.438541] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.438581] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.438624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.438663] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.438711] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.438750] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.438794] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.438831] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.438870] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.438915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.438967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.439120] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.439165] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.439208] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.439281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.439328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.439369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.439411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.439458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.439488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.439523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.439556] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.439589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.439615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.439643] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.439677] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.439709] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.441772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.441793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.441811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.441831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.443421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.443443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.443463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.445019] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.445041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.446910] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.450260] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.450346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.450378] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.450420] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.467122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.467176] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.467248] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.467430] [drm:drm_mode_addfb2] [FB:77]
>[ 1354.467554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.483799] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.483846] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.483917] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.500948] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.501019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.501059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.501093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.501128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.501158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.501187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.501225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.501270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.501313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.501355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.501398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.501437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.501476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.501534] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.501580] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.501630] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.501666] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.501851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.501870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.501965] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.502076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.502130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.502190] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.502237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.502291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.502339] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.502389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.502436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.502483] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.502528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.502542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.502585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.502597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.502644] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.502686] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.502732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.502774] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.502823] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.502867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.502912] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.502959] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.503029] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.503087] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.503133] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.503258] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.503299] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.503340] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.503409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.503449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.503489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.503524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.503562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.503598] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.503641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.503683] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.503726] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.503760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.503797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.503838] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.503878] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.506018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.506041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.506064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.506089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.507667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.507688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.507706] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.509265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.509286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.511184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.514430] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.514501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.514521] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.514546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.531296] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.531350] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.531421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.531604] [drm:drm_mode_addfb2] [FB:78]
>[ 1354.531726] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.547972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.548065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.548134] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.565125] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.565163] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.565203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.565238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.565273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.565303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.565333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.565364] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.565400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.565432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.565464] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.565495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.565531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.565556] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.565603] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.565640] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.565677] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.565704] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.565878] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.565895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.566054] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.566101] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.566152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.566204] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.566244] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.566291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.566334] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.566378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.566420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.566462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.566499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.566512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.566550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.566561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.566602] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.566640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.566681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.566718] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.566765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.566800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.566841] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.566880] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.566922] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.566967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.567055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.567181] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.567223] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.567263] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.567333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.567378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.567417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.567458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.567495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.567538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.567595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.567631] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.567667] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.567697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.567728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.567762] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.567796] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.569908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.569929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.569950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.570034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.571615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.571637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.571656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.573221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.573242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.575117] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.578423] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.578501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.578534] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.578575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.595256] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.595303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.595366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.595544] [drm:drm_mode_addfb2] [FB:79]
>[ 1354.595671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.611953] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.612047] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.612117] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.629107] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.629145] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.629185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.629220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.629255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.629286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.629316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.629354] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.629399] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.629442] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.629484] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.629527] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.629566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.629605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.629662] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.629709] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.629759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.629795] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.630024] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.630053] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.630187] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.630233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.630283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.630333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.630375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.630419] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.630461] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.630502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.630541] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.630581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.630616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.630626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.630663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.630673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.630713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.630751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.630789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.630824] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.630868] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.630903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.630942] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.631009] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.631038] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.631073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.631108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.631200] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.631231] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.631260] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.631311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.631342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.631370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.631398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.631424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.631454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.631486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.631518] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.631549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.631575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.631602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.631633] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.631664] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.633751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.633774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.633792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.633812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.635388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.635409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.635427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.637006] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.637027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.638897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.642209] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.642265] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.642284] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.642310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.659060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.659114] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.659186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.659369] [drm:drm_mode_addfb2] [FB:77]
>[ 1354.659507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.675773] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.675821] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.675894] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.692885] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.692927] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.692973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.693102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.693166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.693218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.693267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.693319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.693378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.693427] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.693460] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.693493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.693523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.693552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.693608] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.693651] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.693691] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.693724] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.693884] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.693898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.694013] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.694045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.694079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.694115] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.694143] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.694175] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.694205] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.694234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.694266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.694295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.694321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.694329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.694355] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.694363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.694393] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.694416] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.694435] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.694453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.694475] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.694493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.694511] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.694528] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.694546] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.694568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.694592] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.694659] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.694678] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.694696] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.694731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.694751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.694771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.694789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.694808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.694827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.694849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.694869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.694889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.694907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.694926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.694947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.694994] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.697062] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.697083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.697101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.697122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.698703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.698725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.698744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.700309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.700330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.702199] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.705527] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.705583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.705614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.705656] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.722361] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.722412] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.722478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.722677] [drm:drm_mode_addfb2] [FB:78]
>[ 1354.722805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.739038] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.739087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.739159] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.756174] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.756216] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.756261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.756302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.756347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.756387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.756426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.756466] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.756511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.756554] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.756596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.756638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.756677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.756717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.756774] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.756820] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.756871] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.756891] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.757036] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.757308] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.757409] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.757438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.757469] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.757503] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.757529] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.757558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.757585] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.757614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.757640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.757666] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.757690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.757697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.757722] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.757728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.757756] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.757781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.757808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.757832] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.757861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.757885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.757911] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.757935] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.758015] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.758047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.758083] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.758174] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.758435] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.758465] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.758517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.758548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.758577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.758606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.758632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.758662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.758695] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.758728] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.758759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.758785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.758813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.758847] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.758876] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.760995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.761017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.761035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.761054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.762619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.762639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.762657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.764226] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.764246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.766118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.769448] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.769498] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.769529] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.769569] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.786269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.786320] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.786387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.786587] [drm:drm_mode_addfb2] [FB:79]
>[ 1354.786720] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.803014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.803064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.803138] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.822086] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.822123] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.822163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.822197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.822232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.822263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.822292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.822324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.822359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.822392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.822424] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.822455] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.822483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.822510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.822564] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.822605] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.822647] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.822678] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.822861] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.822881] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.823065] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.823116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.823173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.823231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.823277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.823332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.823380] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.823430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.823476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.823526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.823571] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.823585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.823629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.823641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.823688] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.823734] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.823780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.823820] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.823869] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.823911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.823958] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.824037] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.824077] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.824127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.824180] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.824296] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.824342] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.824390] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.824440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.824472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.824499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.824528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.824554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.824584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.824617] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.824649] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.824680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.824706] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.824734] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.824764] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.824794] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.826886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.826908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.826927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.826996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.828558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.828578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.828596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.830153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.830173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.832033] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.835381] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.835468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.835501] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.835543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.852253] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.852303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.852369] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.852572] [drm:drm_mode_addfb2] [FB:77]
>[ 1354.852688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.868946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.869027] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.869101] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.886132] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.886170] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.886210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.886244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.886279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.886318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.886358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.886398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.886443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.886486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.886528] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.886570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.886610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.886649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.886707] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.886753] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.886803] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.886839] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.887012] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.887032] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.887128] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.887162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.887197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.887233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.887261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.887293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.887323] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.887353] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.887382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.887411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.887437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.887444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.887470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.887477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.887506] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.887532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.887560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.887585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.887617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.887643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.887671] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.887697] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.887724] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.887754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.887787] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.887882] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.887913] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.887943] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.888019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.888049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.888081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.888108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.888138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.888167] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.888203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.888237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.888269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.888296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.888325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.888361] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.888390] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.890459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.890481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.890500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.890519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.892108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.892130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.892148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.893700] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.893721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.895588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.898885] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.899045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.899092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.899137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.915759] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.915810] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.915876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.916200] [drm:drm_mode_addfb2] [FB:78]
>[ 1354.916332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.932452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.932499] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.932574] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1354.949620] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1354.949657] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1354.949697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.949731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.949765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.949795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.949824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.949856] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.949891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.949924] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.950044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.950101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.950149] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.950196] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.950282] [drm:intel_power_well_disable [i915]] disabling display
>[ 1354.950340] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1354.950381] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.950413] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1354.950565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1354.950585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1354.950683] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1354.950713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1354.950746] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1354.950779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1354.950805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1354.950835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1354.950862] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1354.950891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1354.950918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1354.950955] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1354.951015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1354.951024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.951054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1354.951062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1354.951093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1354.951120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1354.951150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1354.951176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1354.951208] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1354.951235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1354.951265] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1354.951291] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1354.951320] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1354.951353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.951387] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1354.951466] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1354.951496] [drm:intel_power_well_enable [i915]] enabling display
>[ 1354.951526] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1354.951576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1354.951607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1354.951634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1354.951662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1354.951688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1354.951718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1354.951750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1354.951781] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1354.951813] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.951839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1354.951867] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1354.951900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1354.951929] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1354.954018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1354.954040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1354.954060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.954079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1354.955641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1354.955661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1354.955679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1354.957232] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1354.957253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1354.959118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1354.962455] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1354.962554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1354.962586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1354.962612] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1354.979325] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1354.979373] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1354.979437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1354.979657] [drm:drm_mode_addfb2] [FB:79]
>[ 1354.979795] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1354.996028] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1354.996077] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1354.996148] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.013152] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.013190] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.013230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.013264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.013299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.013329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.013367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.013407] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.013452] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.013495] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.013537] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.013580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.013619] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.013659] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.013716] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.013762] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.013822] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.013841] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.014007] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.014027] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.014123] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.014158] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.014193] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.014231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.014261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.014285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.014306] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.014328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.014348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.014368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.014387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.014393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.014410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.014415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.014434] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.014452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.014471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.014488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.014511] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.014528] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.014547] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.014565] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.014583] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.014605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.014629] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.014682] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.014702] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.014720] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.014755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.014775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.014794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.014813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.014831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.014856] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.014884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.014912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.014942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.014998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.015028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.015062] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.015091] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.017162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.017182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.017201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.017220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.018792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.018813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.018830] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.020398] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.020418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.022296] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.025662] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.025730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.025762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.025804] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.042509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.042560] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.042625] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.042805] [drm:drm_mode_addfb2] [FB:77]
>[ 1355.042942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.059223] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.059274] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.059350] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.076338] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.076376] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.076416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.076450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.076485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.076516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.076546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.076577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.076612] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.076654] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.076697] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.076739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.076779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.076818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.076876] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.076922] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.077059] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.077108] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.077294] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.077312] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.077389] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.077416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.077443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.077472] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.077496] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.077523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.077549] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.077576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.077602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.077627] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.077652] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.077658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.077683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.077688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.077713] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.077739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.077764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.077789] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.077815] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.077840] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.077865] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.077891] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.077917] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.077973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.078011] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.078082] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.078114] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.078144] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.078199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.078232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.078264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.078296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.078325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.078358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.078393] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.078416] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.078437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.078456] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.078475] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.078497] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.078518] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.080563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.080584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.080606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.080631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.082195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.082216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.082234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.083781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.083802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.085662] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.088941] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.089049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.089089] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.089140] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.105823] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.105874] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.105940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.106286] [drm:drm_mode_addfb2] [FB:78]
>[ 1355.106415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.122500] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.122548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.122619] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.139649] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.139686] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.139729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.139771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.139815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.139855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.139895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.139935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.140056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.140113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.140168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.140222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.140269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.140315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.140400] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.140456] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.140501] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.140533] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.140675] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.140686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.140742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.140763] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.140787] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.140812] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.140833] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.140854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.140876] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.140897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.140917] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.140985] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.141013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.141021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.141047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.141055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.141083] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.141109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.141136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.141162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.141193] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.141219] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.141245] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.141271] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.141298] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.141331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.141362] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.141438] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.141469] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.141499] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.141551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.141584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.141615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.141645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.141674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.141706] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.141731] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.141752] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.141772] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.141790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.141808] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.141830] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.141852] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.143891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.143913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.143931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.143997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.145572] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.145593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.145611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.147166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.147187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.149047] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.152381] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.152482] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.152515] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.152558] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.169259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.169309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.169377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.169574] [drm:drm_mode_addfb2] [FB:79]
>[ 1355.169694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.185936] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.186028] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.186097] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.203086] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.203124] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.203163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.203197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.203231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.203261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.203290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.203321] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.203356] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.203389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.203420] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.203450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.203478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.203505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.203559] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.203600] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.203641] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.203672] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.203851] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.203870] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.204056] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.204108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.204160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.204217] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.204262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.204313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.204360] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.204410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.204459] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.204504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.204551] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.204563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.204608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.204619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.204666] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.204712] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.204758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.204804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.204855] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.204900] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.204935] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.205018] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.205061] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.205092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.205124] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.205202] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.205233] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.205265] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.205318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.205346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.205366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.205391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.205417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.205443] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.205471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.205498] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.205525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.205551] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.205575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.205602] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.205627] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.207670] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.207692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.207711] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.207730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.209317] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.209340] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.209358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.210937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.210975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.212844] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.216220] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.216261] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.216281] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.216307] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.233058] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.233109] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.233174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.233372] [drm:drm_mode_addfb2] [FB:77]
>[ 1355.233496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.249732] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.249780] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.249852] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.266877] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.266914] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.267051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.267104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.267159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.267208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.267257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.267306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.267363] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.267414] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.267466] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.267515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.267545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.267574] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.267629] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.267672] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.267712] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.267745] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.267893] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.267907] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.268045] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.268080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.268116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.268154] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.268186] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.268218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.268241] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.268262] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.268283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.268302] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.268320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.268325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.268344] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.268348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.268366] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.268391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.268417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.268442] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.268468] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.268493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.268518] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.268544] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.268569] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.268596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.268624] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.268680] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.268702] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.268724] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.268764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.268789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.268811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.268830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.268849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.268869] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.268891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.268912] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.268967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.268994] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.269021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.269054] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.269084] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.271153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.271174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.271197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.271220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.272799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.272822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.272840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.274407] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.274428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.276330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.279674] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.279749] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.279769] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.279794] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.296544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.296595] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.296661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.296842] [drm:drm_mode_addfb2] [FB:78]
>[ 1355.297072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.313262] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.313310] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.313383] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.330370] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.330408] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.330449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.330483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.330519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.330550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.330581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.330612] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.330648] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.330681] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.330712] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.330743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.330771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.330800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.330845] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.330870] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.330895] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.330914] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.331116] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.331135] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.331220] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.331253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.331287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.331324] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.331355] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.331388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.331421] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.331452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.331483] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.331513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.331542] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.331550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.331577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.331584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.331613] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.331643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.331672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.331701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.331731] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.331760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.331790] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.331820] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.331849] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.331881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.331916] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.332012] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.332043] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.332074] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.332126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.332157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.332190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.332221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.332251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.332280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.332314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.332345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.332377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.332406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.332435] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.332468] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.332500] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.334565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.334585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.334604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.334623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.336198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.336218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.336240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.337799] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.337820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.339690] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.343007] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.343059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.343078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.343104] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.359853] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.359906] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.360075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.360323] [drm:drm_mode_addfb2] [FB:79]
>[ 1355.360450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.376565] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.376615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.376692] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.393679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.393717] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.393757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.393790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.393825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.393855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.393883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.393915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.394044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.394099] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.394160] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.394194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.394224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.394254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.394306] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.394349] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.394389] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.394422] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.394565] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.394579] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.394651] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.394673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.394695] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.394719] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.394742] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.394766] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.394790] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.394814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.394837] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.394858] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.394880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.394885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.394908] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.394969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.395004] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.395034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.395064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.395092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.395124] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.395151] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.395179] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.395206] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.395233] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.395265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.395297] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.395374] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.395396] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.395415] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.395451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.395472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.395491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.395510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.395535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.395561] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.395589] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.395617] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.395644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.395670] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.395696] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.395723] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.395749] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.397812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.397834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.397853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.397872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.399467] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.399488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.399507] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.401079] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.401104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.402976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.406105] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.406210] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.406249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.406301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.422988] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.423040] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.423106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.423287] [drm:drm_mode_addfb2] [FB:77]
>[ 1355.423423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.439663] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.439711] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.439784] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.456789] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.456826] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.456866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.456899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.457025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.457079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.457128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.457181] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.457238] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.457291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.457342] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.457393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.457438] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.457490] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.457546] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.457589] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.457629] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.457661] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.457797] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.457809] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.457863] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.457885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.457907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.458000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.458029] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.458062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.458093] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.458125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.458155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.458184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.458214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.458222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.458250] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.458257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.458287] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.458316] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.458346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.458375] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.458409] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.458438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.458458] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.458476] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.458494] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.458516] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.458540] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.458594] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.458612] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.458631] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.458666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.458691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.458718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.458744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.458770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.458797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.458825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.458854] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.458882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.458908] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.458957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.458992] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.459022] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.461092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.461113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.461132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.461151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.462721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.462741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.462759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.464311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.464335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.466198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.469512] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.469579] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.469611] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.469653] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.486360] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.486411] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.486481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.486665] [drm:drm_mode_addfb2] [FB:78]
>[ 1355.486787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.503078] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.503130] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.503206] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.520197] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.520235] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.520275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.520310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.520345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.520375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.520404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.520436] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.520471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.520503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.520535] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.520566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.520594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.520622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.520675] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.520717] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.520759] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.520790] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.521004] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.521032] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.521157] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.521204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.521251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.521300] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.521341] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.521375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.521405] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.521433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.521460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.521485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.521509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.521517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.521540] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.521546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.521572] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.521595] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.521618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.521642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.521670] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.521702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.521737] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.521771] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.521805] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.521842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.521880] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.521990] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.522018] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.522046] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.522101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.522133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.522164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.522195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.522224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.522256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.522291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.522325] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.522357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.522387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.522415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.522438] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.522459] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.524515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.524539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.524561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.524585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.526188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.526210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.526229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.527790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.527811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.529674] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.532996] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.533059] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.533099] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.533141] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.549836] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.549887] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.550040] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.550287] [drm:drm_mode_addfb2] [FB:79]
>[ 1355.550398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.566552] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.566601] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.566673] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.584857] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.584894] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.585020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.585081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.585138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.585187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.585235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.585285] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.585341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.585375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.585408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.585441] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.585471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.585500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.585555] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.585597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.585637] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.585669] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.585828] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.585840] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.585897] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.585978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.586011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.586047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.586076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.586108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.586138] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.586168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.586196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.586224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.586250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.586259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.586287] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.586294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.586323] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.586350] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.586377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.586403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.586437] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.586466] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.586495] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.586524] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.586554] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.586588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.586622] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.586716] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.586736] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.586754] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.586790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.586811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.586830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.586850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.586868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.586888] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.586910] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.586960] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.586992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.587019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.587046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.587078] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.587106] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.589179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.589200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.589223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.589247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.590809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.590830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.590849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.592413] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.592434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.594334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.597608] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.597650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.597670] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.597695] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.614446] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.614497] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.614563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.614763] [drm:drm_mode_addfb2] [FB:77]
>[ 1355.614889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.631122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.631170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.631241] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.648269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.648307] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.648347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.648381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.648417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.648456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.648496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.648536] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.648581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.648624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.648666] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.648708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.648748] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.648795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.648829] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.648854] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.648883] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.648902] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.649127] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.649147] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.649242] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.649273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.649308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.649344] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.649372] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.649404] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.649433] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.649463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.649491] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.649520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.649546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.649553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.649581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.649588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.649616] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.649642] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.649670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.649695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.649726] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.649752] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.649779] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.649805] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.649833] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.649862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.649895] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.650002] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.650033] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.650062] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.650113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.650144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.650172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.650200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.650226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.650255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.650289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.650321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.650352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.650378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.650405] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.650439] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.650467] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.652536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.652558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.652577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.652596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.654169] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.654189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.654209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.655768] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.655789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.657660] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.661007] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.661078] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.661098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.661124] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.677873] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.677926] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.678104] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.678335] [drm:drm_mode_addfb2] [FB:78]
>[ 1355.678461] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.694589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.694641] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.694717] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.711716] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.711754] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.711795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.711829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.711864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.711895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.712020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.712073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.712132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.712184] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.712237] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.712292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.712321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.712351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.712406] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.712449] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.712490] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.712523] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.712674] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.712686] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.712741] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.712762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.712785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.712808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.712827] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.712846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.712867] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.712886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.712915] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.712982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.713010] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.713018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.713044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.713052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.713079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.713106] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.713133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.713159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.713191] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.713217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.713248] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.713277] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.713304] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.713337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.713372] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.713450] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.713482] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.713513] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.713568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.713602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.713625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.713645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.713664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.713689] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.713718] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.713746] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.713774] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.713800] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.713826] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.713853] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.713879] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.715975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.715997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.716016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.716035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.717617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.717638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.717656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.719211] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.719232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.721100] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.724448] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.724538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.724566] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.724602] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.741314] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.741364] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.741430] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.741623] [drm:drm_mode_addfb2] [FB:79]
>[ 1355.741752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.757989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.758037] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.758109] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.775136] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.775174] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.775214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.775248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.775284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.775314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.775344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.775376] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.775411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.775444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.775475] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.775507] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.775535] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.775562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.775615] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.775656] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.775697] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.775728] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.775890] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.775969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.776097] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.776143] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.776190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.776240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.776282] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.776324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.776354] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.776383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.776409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.776436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.776461] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.776468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.776492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.776497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.776522] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.776546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.776570] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.776593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.776621] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.776645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.776669] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.776692] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.776716] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.776744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.776781] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.776838] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.776861] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.776882] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.776965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.776999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.777034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.777066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.777098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.777132] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.777170] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.777207] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.777243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.777275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.777305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.777343] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.777378] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.779490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.779512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.779530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.779549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.781138] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.781161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.781180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.782733] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.782754] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.784631] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.787984] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.788069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.788095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.788129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.804847] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.804898] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.805068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.805342] [drm:drm_mode_addfb2] [FB:77]
>[ 1355.805481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.821553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.821602] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.821674] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.838679] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.838716] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.838756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.838789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.838824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.838863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.838903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.839020] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.839080] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.839134] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.839186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.839237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.839285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.839338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.839384] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.839412] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.839440] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.839461] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.839555] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.839567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.839626] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.839652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.839678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.839708] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.839733] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.839760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.839786] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.839812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.839838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.839864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.839889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.839930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.839964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.839972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.840003] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.840032] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.840060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.840087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.840119] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.840146] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.840174] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.840201] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.840227] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.840260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.840292] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.840369] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.840401] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.840431] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.840485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.840518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.840549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.840579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.840609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.840641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.840672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.840695] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.840717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.840735] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.840754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.840780] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.840807] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.842860] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.842884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.842903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.842985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.844557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.844578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.844597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.846161] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.846182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.848058] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.851364] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.851442] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.851475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.851517] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.868221] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.868272] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.868343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.868542] [drm:drm_mode_addfb2] [FB:78]
>[ 1355.868660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.884895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.884988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.885057] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.902046] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.902084] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.902125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.902158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.902193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.902224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.902254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.902302] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.902350] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.902383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.902415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.902447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.902474] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.902502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.902555] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.902597] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.902639] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.902669] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.902825] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.902837] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.902903] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.902975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.903010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.903047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.903076] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.903108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.903138] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.903168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.903197] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.903225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.903251] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.903259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.903285] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.903293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.903322] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.903352] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.903379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.903406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.903439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.903468] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.903497] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.903527] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.903556] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.903588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.903624] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.903702] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.903733] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.903764] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.903803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.903824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.903849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.903875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.903900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.903951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.903985] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.904016] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.904046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.904072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.904098] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.904130] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.904160] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.906225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.906246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.906264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.906285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.907849] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.907870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.907888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.909481] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.909502] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.911385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.914709] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.914768] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.914801] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.914843] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.931554] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.931607] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.931678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.932121] [drm:drm_mode_addfb2] [FB:79]
>[ 1355.932278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.948249] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1355.948298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1355.948390] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1355.965452] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1355.965490] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1355.965530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.965564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.965599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.965629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.965658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.965690] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.965725] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.965758] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.965789] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.965821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.965850] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.965878] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.966007] [drm:intel_power_well_disable [i915]] disabling display
>[ 1355.966074] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1355.966138] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.966188] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1355.966358] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1355.966377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1355.966464] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1355.966495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1355.966527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1355.966563] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1355.966592] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1355.966623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1355.966652] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1355.966682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1355.966710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1355.966740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1355.966766] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1355.966773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.966800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1355.966806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1355.966835] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1355.966862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1355.966892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1355.966948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1355.966978] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1355.967008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1355.967035] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1355.967065] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1355.967091] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1355.967124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1355.967159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1355.967247] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1355.967277] [drm:intel_power_well_enable [i915]] enabling display
>[ 1355.967307] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1355.967357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1355.967387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1355.967415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1355.967444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1355.967471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1355.967500] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1355.967532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1355.967564] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1355.967595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.967621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1355.967648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1355.967678] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1355.967709] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1355.969779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1355.969801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1355.969821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.969840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1355.971429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1355.971449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1355.971467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1355.973156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1355.973179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1355.975069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1355.978414] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1355.978504] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1355.978524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1355.978549] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1355.995257] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1355.995302] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1355.995364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1355.995541] [drm:drm_mode_addfb2] [FB:77]
>[ 1355.995667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.011957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.012010] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.012086] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.029104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.029141] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.029182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.029216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.029251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.029282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.029312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.029343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.029379] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.029411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.029442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.029473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.029501] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.029528] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.029582] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.029623] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.029672] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.029691] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.029815] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.029827] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.029883] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.029972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.030008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.030046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.030075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.030110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.030141] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.030174] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.030203] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.030235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.030262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.030272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.030299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.030307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.030338] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.030365] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.030395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.030421] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.030453] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.030480] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.030508] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.030534] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.030564] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.030598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.030632] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.030728] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.030759] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.030789] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.030841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.030872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.030899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.030954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.030981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.031013] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.031047] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.031080] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.031111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.031137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.031164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.031195] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.031225] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.033297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.033319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.033338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.033357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.034946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.034967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.034985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.036557] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.036578] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.038456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.041749] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.041842] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.041876] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.041984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.058620] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.058670] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.058736] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.059024] [drm:drm_mode_addfb2] [FB:78]
>[ 1356.059218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.075294] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.075342] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.075414] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.092439] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.092476] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.092516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.092551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.092585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.092615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.092644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.092675] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.092709] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.092742] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.092774] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.092805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.092833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.092860] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.093001] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.093070] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.093140] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.093174] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.093304] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.093316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.093371] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.093393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.093418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.093448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.093473] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.093500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.093526] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.093552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.093578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.093604] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.093630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.093636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.093660] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.093664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.093691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.093716] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.093742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.093767] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.093793] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.093818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.093844] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.093870] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.093897] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.093957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.093994] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.094084] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.094115] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.094146] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.094202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.094235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.094268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.094299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.094329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.094361] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.094389] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.094412] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.094432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.094458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.094484] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.094512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.094538] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.096585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.096606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.096628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.096653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.098216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.098237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.098255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.099803] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.099824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.101698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.105046] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.105133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.105166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.105208] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.121909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.121993] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.122063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.122264] [drm:drm_mode_addfb2] [FB:79]
>[ 1356.122399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.138587] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.138635] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.138706] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.155727] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.155765] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.155805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.155838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.155873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.155992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.156042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.156094] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.156152] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.156206] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.156241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.156275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.156304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.156332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.156385] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.156427] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.156470] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.156504] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.156644] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.156657] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.156713] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.156734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.156757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.156782] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.156802] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.156823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.156845] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.156865] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.156891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.156944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.156971] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.156980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.157006] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.157014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.157041] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.157068] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.157095] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.157121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.157151] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.157178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.157204] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.157231] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.157257] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.157289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.157320] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.157397] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.157429] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.157459] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.157512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.157543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.157573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.157602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.157632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.157662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.157696] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.157729] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.157752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.157770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.157789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.157811] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.157832] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.159874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.159911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.159929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.159949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.161521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.161542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.161560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.163110] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.163131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.164989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.168325] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.168425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.168458] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.168500] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.185203] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.185256] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.185328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.185515] [drm:drm_mode_addfb2] [FB:77]
>[ 1356.185637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.201879] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.201959] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.202031] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.220989] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.221027] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.221067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.221101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.221136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.221166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.221195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.221226] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.221261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.221302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.221345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.221387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.221427] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.221466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.221524] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.221571] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.221622] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.221657] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.221844] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.221863] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.222077] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.222131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.222195] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.222252] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.222297] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.222346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.222394] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.222441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.222487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.222533] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.222577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.222588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.222630] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.222641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.222684] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.222728] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.222771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.222813] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.222860] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.222902] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.222983] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.223029] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.223073] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.223125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.223177] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.223287] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.223318] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.223349] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.223400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.223432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.223460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.223490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.223520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.223551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.223586] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.223619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.223651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.223681] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.223711] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.223745] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.223777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.225848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.225869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.225887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.225958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.227529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.227552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.227575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.229138] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.229161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.231030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.234352] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.234420] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.234439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.234465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.251163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.251207] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.251270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.251448] [drm:drm_mode_addfb2] [FB:78]
>[ 1356.251576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.267865] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.267997] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.268105] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.286841] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.286878] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.286998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.287039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.287077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.287108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.287140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.287172] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.287210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.287245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.287277] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.287310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.287338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.287368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.287421] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.287462] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.287504] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.287536] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.287705] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.287724] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.287791] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.287812] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.287835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.287860] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.287885] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.287945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.287975] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.288005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.288034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.288061] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.288088] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.288097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.288123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.288131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.288158] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.288184] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.288210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.288236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.288266] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.288292] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.288319] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.288345] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.288370] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.288403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.288438] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.288518] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.288550] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.288580] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.288634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.288665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.288696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.288726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.288754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.288780] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.288809] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.288837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.288865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.288892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.288945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.288979] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.289009] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.291074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.291097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.291120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.291144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.292707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.292728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.292747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.294299] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.294319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.296181] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.299520] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.299617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.299649] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.299699] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.316395] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.316446] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.316512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.316708] [drm:drm_mode_addfb2] [FB:79]
>[ 1356.316834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.333070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.333122] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.333213] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.350222] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.350264] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.350309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.350350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.350395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.350434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.350474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.350514] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.350558] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.350601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.350643] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.350685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.350724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.350763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.350820] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.350866] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.351000] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.351059] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.351204] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.351222] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.351309] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.351340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.351373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.351409] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.351438] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.351470] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.351499] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.351531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.351559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.351587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.351612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.351620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.351646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.351652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.351681] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.351707] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.351734] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.351759] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.351790] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.351816] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.351844] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.351869] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.351924] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.351954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.351988] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.352076] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.352106] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.352137] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.352187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.352217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.352245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.352274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.352300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.352329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.352362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.352393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.352425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.352451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.352478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.352510] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.352541] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.354605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.354629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.354652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.354676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.356252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.356273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.356292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.357873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.357904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.359763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.363080] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.363144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.363176] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.363218] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.379951] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.380002] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.380068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.380259] [drm:drm_mode_addfb2] [FB:77]
>[ 1356.380386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.396639] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.396687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.396775] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.414461] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.414499] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.414539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.414574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.414616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.414657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.414697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.414736] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.414781] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.414824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.414866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.414989] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.415039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.415089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.415176] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.415240] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.415307] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.415357] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.415557] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.415578] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.415678] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.415710] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.415742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.415776] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.415805] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.415836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.415866] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.415953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.415987] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.416020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.416053] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.416061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.416091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.416099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.416130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.416159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.416187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.416217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.416250] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.416279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.416309] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.416339] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.416365] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.416398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.416433] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.416508] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.416539] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.416569] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.416621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.416653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.416684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.416714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.416744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.416775] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.416808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.416841] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.416873] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.416928] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.416959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.416995] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.417026] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.419097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.419118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.419136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.419155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.420718] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.420738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.420756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.422312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.422333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.424208] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.427557] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.427645] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.427685] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.427736] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.444422] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.444473] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.444540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.444743] [drm:drm_mode_addfb2] [FB:78]
>[ 1356.444873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.461123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.461170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.461245] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.478255] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.478293] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.478333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.478367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.478401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.478431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.478459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.478491] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.478526] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.478559] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.478591] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.478622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.478650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.478678] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.478733] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.478767] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.478802] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.478828] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.479055] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.479079] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.479195] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.479239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.479283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.479332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.479374] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.479417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.479461] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.479502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.479544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.479583] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.479622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.479631] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.479668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.479678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.479721] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.479752] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.479781] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.479811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.479844] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.479873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.479925] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.479957] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.479985] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.480020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.480055] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.480146] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.480177] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.480207] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.480259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.480291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.480321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.480348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.480377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.480405] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.480439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.480471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.480504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.480533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.480562] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.480596] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.480628] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.482708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.482730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.482750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.482770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.484343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.484363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.484381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.485936] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.485957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.487816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.491079] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.491133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.491152] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.491177] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.507953] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.508006] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.508077] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.508281] [drm:drm_mode_addfb2] [FB:79]
>[ 1356.508397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.524643] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.524692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.524781] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.541750] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.541787] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.541827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.541861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.541982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.542028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.542077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.542122] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.542186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.542229] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.542271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.542313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.542347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.542383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.542454] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.542510] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.542562] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.542603] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.542773] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.542790] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.542879] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.542976] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.543025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.543077] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.543119] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.543166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.543216] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.543248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.543280] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.543310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.543340] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.543348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.543377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.543384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.543413] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.543443] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.543472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.543501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.543534] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.543564] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.543595] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.543624] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.543653] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.543687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.543721] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.543802] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.543833] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.543864] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.543940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.543972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.544004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.544035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.544066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.544098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.544133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.544168] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.544202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.544231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.544262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.544296] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.544328] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.546399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.546420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.546438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.546457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.548048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.548072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.548095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.549647] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.549669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.551543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.554843] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.554999] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.555047] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.555115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.571705] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.571758] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.571830] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.572158] [drm:drm_mode_addfb2] [FB:77]
>[ 1356.572291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.588419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.588467] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.588555] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.606216] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.606251] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.606288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.606320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.606354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.606382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.606410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.606440] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.606480] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.606521] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.606561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.606601] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.606638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.606675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.606719] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.606745] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.606773] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.606792] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.606945] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.606965] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.607062] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.607095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.607131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.607169] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.607200] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.607234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.607268] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.607300] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.607332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.607362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.607391] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.607399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.607428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.607435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.607465] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.607495] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.607525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.607554] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.607587] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.607617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.607646] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.607676] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.607706] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.607739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.607774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.607850] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.607906] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.607936] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.607989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.608023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.608054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.608086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.608117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.608150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.608186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.608220] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.608253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.608283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.608313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.608349] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.608383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.610468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.610489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.610508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.610527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.612116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.612139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.612158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.613717] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.613739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.615612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.618945] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.618978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.618997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.619023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.635774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.635825] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.635971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.636220] [drm:drm_mode_addfb2] [FB:78]
>[ 1356.636349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.652427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.652476] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.652565] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.669593] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.669631] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.669671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.669705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.669739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.669770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.669799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.669831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.669866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.669984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.670037] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.670085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.670131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.670162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.670218] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.670264] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.670306] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.670339] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.670439] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.670451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.670507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.670529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.670554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.670583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.670608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.670636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.670662] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.670688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.670714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.670741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.670765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.670771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.670796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.670802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.670828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.670852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.670919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.670950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.670984] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.671012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.671041] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.671069] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.671096] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.671127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.671160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.671236] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.671264] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.671295] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.671348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.671380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.671410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.671441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.671471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.671503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.671537] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.671570] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.671595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.671614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.671633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.671655] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.671676] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.673720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.673744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.673767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.673791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.675388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.675409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.675428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.676986] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.677006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.678868] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.682226] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.682314] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.682347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.682391] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.699072] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.699123] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.699193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.699374] [drm:drm_mode_addfb2] [FB:79]
>[ 1356.699508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.715747] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.715792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.715879] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.732977] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.733015] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.733054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.733088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.733123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.733154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.733183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.733215] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.733250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.733283] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.733314] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.733346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.733374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.733401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.733455] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.733506] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.733531] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.733549] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.733676] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.733687] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.733744] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.733767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.733790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.733815] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.733835] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.733865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.733945] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.733975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.734005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.734032] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.734059] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.734067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.734093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.734100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.734128] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.734154] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.734181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.734207] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.734238] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.734264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.734291] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.734318] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.734344] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.734378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.734412] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.734490] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.734522] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.734552] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.734607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.734640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.734671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.734702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.734733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.734765] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.734797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.734820] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.734841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.734861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.734910] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.734943] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.734972] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.737042] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.737065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.737088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.737113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.738679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.738700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.738719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.740287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.740308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.742181] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.745530] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.745617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.745651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.745687] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.762401] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.762454] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.762525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.762711] [drm:drm_mode_addfb2] [FB:77]
>[ 1356.762847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.779096] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.779145] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.779219] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.796229] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.796271] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.796317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.796357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.796401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.796442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.796481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.796520] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.796565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.796608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.796650] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.796692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.796731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.796770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.796826] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.796929] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.796972] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.797008] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.797156] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.797174] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.797240] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.797262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.797286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.797311] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.797331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.797354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.797376] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.797397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.797416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.797436] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.797454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.797460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.797484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.797489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.797515] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.797541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.797567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.797590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.797617] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.797641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.797668] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.797694] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.797720] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.797747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.797775] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.797826] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.797847] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.797899] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.797952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.797983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.798013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.798041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.798069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.798098] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.798130] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.798162] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.798193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.798220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.798247] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.798282] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.798313] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.800396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.800418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.800436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.800456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.802035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.802057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.802076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.803629] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.803651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.805503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.808815] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.808963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.809000] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.809044] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.825674] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.825725] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.825790] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.826094] [drm:drm_mode_addfb2] [FB:78]
>[ 1356.826248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.842372] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.842421] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.842513] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.859539] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.859581] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.859626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.859667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.859712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.859752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.859792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.859831] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.859876] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.860002] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.860059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.860109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.860153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.860201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.860286] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.860343] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.860385] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.860414] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.860506] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.860519] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.860575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.860596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.860619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.860644] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.860664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.860687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.860708] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.860729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.860749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.860769] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.860787] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.860792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.860810] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.860815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.860841] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.860870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.860928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.860957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.860988] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.861016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.861043] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.861071] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.861097] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.861128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.861160] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.861420] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.861442] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.861464] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.861503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.861529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.861556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.861582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.861608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.861633] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.861662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.861690] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.861717] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.861743] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.861768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.861796] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.861822] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.863922] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.863943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.863962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.863980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.865560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.865582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.865604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.867172] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.867194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.869067] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.872404] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.872503] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.872535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.872586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.889279] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.889330] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.889396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.889588] [drm:drm_mode_addfb2] [FB:79]
>[ 1356.889700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.905957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.906005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.906077] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.923102] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.923139] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.923179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.923213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.923248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.923278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.923307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.923338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.923373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.923406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.923437] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.923468] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.923496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.923523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.923577] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.923622] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.923672] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.923708] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.923913] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.923939] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.924241] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.924272] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.924305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.924338] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.924366] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.924395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.924424] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.924451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.924478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.924503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.924528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.924535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.924559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.924565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.924589] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.924613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.924637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.924660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.924689] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.924712] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.924745] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.924779] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.924814] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.924847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.924904] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.924997] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.925197] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.925216] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.925254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.925279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.925305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.925332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.925357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.925383] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.925411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.925439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.925466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.925493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.925518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.925545] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.925571] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.927624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.927646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.927668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.927692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.929258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.929279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.929297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.930854] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.930887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.932747] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.936073] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.936114] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.936133] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.936164] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1356.952933] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.952981] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.953044] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.953245] [drm:drm_mode_addfb2] [FB:77]
>[ 1356.953367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.969605] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1356.969653] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1356.969724] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1356.986766] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1356.986803] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1356.986842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.986966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.987025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.987075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.987122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.987163] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1356.987202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.987242] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.987268] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.987295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.987319] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.987344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.987389] [drm:intel_power_well_disable [i915]] disabling display
>[ 1356.987425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1356.987460] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1356.987487] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1356.987616] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1356.987632] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1356.987704] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1356.987730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1356.987760] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1356.987793] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1356.987819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1356.987850] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1356.987928] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1356.987966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1356.988005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1356.988041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1356.988076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1356.988088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.988122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1356.988132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1356.988168] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1356.988202] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1356.988246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1356.988272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1356.988303] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1356.988329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1356.988356] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1356.988382] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1356.988409] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1356.988439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1356.988471] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1356.988564] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1356.988595] [drm:intel_power_well_enable [i915]] enabling display
>[ 1356.988625] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1356.988677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1356.988709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1356.988740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1356.988770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1356.988800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1356.988831] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1356.988865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1356.988919] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1356.988951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1356.988977] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1356.989004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1356.989037] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1356.989065] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1356.991129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1356.991150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1356.991168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.991187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1356.992746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1356.992766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1356.992783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1356.994344] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1356.994365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1356.996265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1356.999543] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1356.999583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1356.999606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1356.999638] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.016378] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.016429] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.016494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.016695] [drm:drm_mode_addfb2] [FB:78]
>[ 1357.016821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.033051] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.033099] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.033170] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.050198] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.050236] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.050275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.050309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.050344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.050375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.050405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.050437] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.050472] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.050505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.050536] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.050567] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.050595] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.050622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.050676] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.050701] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.050726] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.050744] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.050902] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.050924] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.051014] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.051038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.051065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.051094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.051119] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.051146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.051172] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.051198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.051224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.051250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.051275] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.051281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.051306] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.051311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.051337] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.051362] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.051389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.051414] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.051441] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.051466] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.051491] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.051517] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.051540] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.051567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.051595] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.051650] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.051672] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.051695] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.051734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.051760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.051786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.051812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.051839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.051896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.051930] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.051963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.051995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.052022] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.052049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.052081] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.052112] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.054179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.054200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.054219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.054238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.055802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.055822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.055840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.057438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.057459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.059342] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.062671] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.062724] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.062757] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.062798] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.079512] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.079564] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.079630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.079837] [drm:drm_mode_addfb2] [FB:79]
>[ 1357.080113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.096186] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.096235] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.096327] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.113391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.113428] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.113467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.113501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.113536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.113567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.113606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.113645] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.113690] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.113733] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.113775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.113817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.113856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.113969] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.114052] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.114117] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.114159] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.114191] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.114345] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.114366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.114467] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.114499] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.114531] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.114565] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.114594] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.114625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.114655] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.114684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.114713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.114741] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.114769] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.114776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.114802] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.114808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.114836] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.114920] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.114952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.114983] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.115016] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.115047] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.115078] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.115110] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.115140] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.115172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.115208] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.115284] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.115316] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.115347] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.115398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.115430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.115460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.115490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.115520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.115548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.115582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.115614] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.115647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.115676] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.115705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.115738] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.115769] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.117867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.117902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.117921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.117940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.119513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.119537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.119560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.121132] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.121154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.123038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.126368] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.126405] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.126425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.126451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.143208] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.143260] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.143325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.143523] [drm:drm_mode_addfb2] [FB:77]
>[ 1357.143654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.159942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.159988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.160080] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.177111] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.177148] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.177189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.177222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.177257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.177287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.177315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.177347] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.177382] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.177415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.177446] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.177477] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.177505] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.177540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.177584] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.177619] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.177653] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.177679] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.177834] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.177895] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.178020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.178061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.178106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.178153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.178190] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.178232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.178272] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.178313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.178350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.178388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.178422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.178431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.178466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.178475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.178512] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.178555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.178588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.178618] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.178655] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.178686] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.178719] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.178750] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.178783] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.178818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.178858] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.178997] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.179032] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.179068] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.179129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.179163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.179199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.179231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.179266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.179299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.179338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.179375] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.179413] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.179444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.179476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.179512] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.179555] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.181633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.181655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.181674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.181698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.183268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.183289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.183307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.184860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.184906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.186766] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.190068] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.190144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.190173] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.190210] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.206937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.206988] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.207054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.207258] [drm:drm_mode_addfb2] [FB:78]
>[ 1357.207370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.223629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.223677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.223751] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.240793] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.240830] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.240963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.241017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.241074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.241123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.241158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.241190] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.241235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.241279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.241323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.241367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.241407] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.241448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.241505] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.241553] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.241604] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.241641] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.241784] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.241803] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.241955] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.241986] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.242020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.242056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.242084] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.242118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.242150] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.242179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.242212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.242233] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.242251] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.242256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.242274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.242278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.242297] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.242315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.242333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.242350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.242372] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.242390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.242407] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.242426] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.242443] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.242465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.242488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.242553] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.242573] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.242591] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.242626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.242647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.242666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.242684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.242703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.242722] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.242743] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.242763] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.242783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.242801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.242818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.242841] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.242896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.244969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.244990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.245008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.245027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.246613] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.246636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.246654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.248220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.248242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.250115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.253425] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.253497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.253529] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.253571] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.270278] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.270329] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.270394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.270590] [drm:drm_mode_addfb2] [FB:79]
>[ 1357.270716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.286952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.287002] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.287091] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.304104] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.304142] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.304181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.304215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.304250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.304279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.304309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.304340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.304375] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.304407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.304438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.304469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.304497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.304525] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.304578] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.304619] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.304661] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.304691] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.304923] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.304956] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.305102] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.305151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.305210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.305260] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.305300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.305345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.305387] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.305429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.305467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.305508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.305544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.305554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.305591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.305600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.305640] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.305677] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.305717] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.305753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.305796] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.305832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.305908] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.305947] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.305988] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.306029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.306077] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.306204] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.306234] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.306264] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.306315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.306346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.306373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.306401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.306427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.306458] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.306491] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.306522] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.306554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.306580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.306608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.306638] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.306668] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.308755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.308778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.308796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.308816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.310441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.310462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.310480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.312042] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.312063] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.313923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.317258] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.317361] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.317407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.317446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.334135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.334186] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.334251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.334447] [drm:drm_mode_addfb2] [FB:77]
>[ 1357.334573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.352578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.352621] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.352697] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.368669] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.368706] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.368746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.368779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.368815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.368846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.368965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.369016] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.369074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.369127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.369180] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.369216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.369245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.369273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.369327] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.369370] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.369414] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.369447] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.369602] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.369621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.369706] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.369738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.369780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.369805] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.369826] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.369892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.369923] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.369953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.369981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.370008] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.370035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.370044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.370069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.370077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.370104] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.370130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.370157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.370184] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.370214] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.370240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.370266] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.370293] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.370318] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.370349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.370384] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.370461] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.370493] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.370523] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.370575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.370607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.370638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.370668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.370698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.370729] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.370762] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.370784] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.370805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.370823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.370872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.370904] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.370933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.373002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.373023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.373042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.373061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.374630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.374650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.374668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.376230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.376251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.378123] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.381431] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.381507] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.381539] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.381581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.398272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.398320] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.398384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.398580] [drm:drm_mode_addfb2] [FB:78]
>[ 1357.398704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.414961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.415013] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.415105] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.432116] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.432154] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.432193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.432226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.432261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.432292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.432321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.432353] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.432396] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.432439] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.432481] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.432523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.432563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.432602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.432660] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.432707] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.432757] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.432793] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.433065] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.433094] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.433234] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.433269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.433299] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.433325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.433350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.433378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.433403] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.433430] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.433456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.433482] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.433507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.433512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.433537] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.433542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.433568] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.433594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.433620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.433646] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.433671] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.433696] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.433721] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.433746] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.433773] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.433800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.433829] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.433938] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.433970] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.434000] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.434056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.434089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.434121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.434153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.434183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.434216] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.434249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.434271] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.434292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.434317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.434343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.434370] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.434397] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.436451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.436473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.436492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.436511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.438095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.438116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.438134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.439683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.439704] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.441576] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.444896] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.444959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.444991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.445033] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.461739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.461792] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.461942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.462175] [drm:drm_mode_addfb2] [FB:79]
>[ 1357.462310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.478413] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.478461] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.478550] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.495563] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.495605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.495651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.495691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.495736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.495776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.495816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.495855] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.495988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.496046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.496101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.496155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.496202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.496237] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.496291] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.496333] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.496377] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.496409] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.496564] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.496583] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.496665] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.496687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.496710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.496735] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.496755] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.496781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.496807] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.496837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.496896] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.496925] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.496954] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.496962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.496989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.496997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.497025] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.497052] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.497079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.497105] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.497136] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.497161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.497188] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.497214] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.497241] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.497272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.497307] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.497384] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.497415] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.497446] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.497498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.497531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.497561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.497592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.497621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.497650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.497672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.497693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.497714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.497739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.497765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.497792] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.497819] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.499914] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.499936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.499954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.499974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.501547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.501567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.501585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.503147] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.503168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.505028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.508372] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.508464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.508497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.508540] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.525241] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.525292] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.525358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.525555] [drm:drm_mode_addfb2] [FB:77]
>[ 1357.525668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.541918] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.541966] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.542055] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.559069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.559106] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.559147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.559180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.559216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.559246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.559276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.559307] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.559342] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.559374] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.559406] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.559437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.559465] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.559492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.559545] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.559586] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.559627] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.559658] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.559822] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.559898] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.560053] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.560097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.560145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.560195] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.560235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.560279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.560320] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.560362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.560401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.560442] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.560479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.560489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.560526] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.560535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.560575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.560611] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.560649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.560684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.560728] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.560763] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.560802] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.560838] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.560913] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.560957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.561005] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.561123] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.561156] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.561190] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.561247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.561280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.561314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.561345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.561377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.561408] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.561444] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.561479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.561515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.561544] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.561575] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.561610] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.561644] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.563727] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.563748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.563766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.563785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.565385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.565405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.565423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.567060] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.567081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.568950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.572304] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.572377] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.572404] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.572438] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.589147] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.589192] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.589255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.589448] [drm:drm_mode_addfb2] [FB:78]
>[ 1357.589557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.605898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.605947] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.606030] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.623051] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.623089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.623129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.623163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.623197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.623227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.623255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.623286] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.623321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.623354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.623393] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.623432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.623469] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.623506] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.623560] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.623604] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.623652] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.623686] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.623904] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.623934] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.624071] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.624117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.624167] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.624220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.624261] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.624308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.624352] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.624403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.624440] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.624478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.624515] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.624524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.624559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.624568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.624606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.624640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.624676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.624709] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.624751] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.624784] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.624822] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.624895] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.624936] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.624981] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.625028] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.625129] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.625169] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.625209] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.625274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.625314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.625350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.625387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.625424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.625454] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.625486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.625517] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.625549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.625577] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.625605] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.625636] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.625666] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.627741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.627763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.627781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.627800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.629421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.629441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.629459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.631022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.631043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.632904] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.636252] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.636340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.636373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.636414] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.653096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.653143] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.653207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.653425] [drm:drm_mode_addfb2] [FB:79]
>[ 1357.653561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.669815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.669891] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.669980] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.686975] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.687017] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.687062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.687103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.687148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.687188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.687228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.687267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.687312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.687354] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.687397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.687439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.687478] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.687517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.687574] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.687620] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.687670] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.687706] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.687897] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.687917] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.688012] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.688043] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.688079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.688117] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.688146] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.688179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.688209] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.688240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.688269] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.688298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.688324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.688332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.688358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.688365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.688394] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.688420] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.688447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.688473] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.688504] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.688529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.688557] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.688583] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.688610] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.688639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.688672] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.688765] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.688794] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.688825] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.688907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.688937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.688968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.688996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.689026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.689055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.689089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.689122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.689155] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.689182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.689212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.689247] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.689276] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.691348] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.691369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.691387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.691406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.693001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.693023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.693042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.694596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.694618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.696492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.699814] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.699929] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.699965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.699991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.716704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.716755] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.716821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.717225] [drm:drm_mode_addfb2] [FB:77]
>[ 1357.717364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.733404] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.733451] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.733541] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.750535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.750572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.750612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.750646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.750681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.750720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.750760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.750800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.750844] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.750967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.751023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.751073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.751122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.751171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.751226] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.751272] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.751309] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.751330] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.751431] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.751443] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.751498] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.751519] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.751542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.751571] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.751596] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.751623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.751649] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.751676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.751702] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.751728] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.751752] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.751758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.751783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.751788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.751816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.751877] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.751909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.751937] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.751969] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.751997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.752026] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.752053] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.752080] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.752111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.752143] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.752220] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.752249] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.752279] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.752332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.752364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.752395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.752425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.752455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.752486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.752520] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.752553] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.752579] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.752599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.752624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.752652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.752678] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.754729] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.754753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.754776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.754800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.756413] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.756433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.756452] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.758012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.758032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.759891] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.763227] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.763327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.763362] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.763403] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.780089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.780141] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.780207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.780410] [drm:drm_mode_addfb2] [FB:78]
>[ 1357.780560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.796779] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.796827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.796997] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.814425] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.814463] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.814503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.814537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.814573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.814604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.814642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.814682] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.814727] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.814770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.814812] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.814935] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.814983] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.815026] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.815111] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.815182] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.815249] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.815302] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.815467] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.815486] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.815573] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.815606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.815643] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.815672] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.815697] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.815724] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.815750] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.815777] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.815803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.815836] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.815899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.815907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.815935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.815943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.815971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.815999] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.816027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.816057] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.816089] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.816117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.816148] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.816178] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.816208] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.816241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.816276] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.816353] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.816377] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.816395] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.816431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.816452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.816471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.816490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.816515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.816541] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.816569] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.816597] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.816626] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.816651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.816677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.816704] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.816730] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.818776] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.818797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.818820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.818903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.820481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.820501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.820520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.822078] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.822100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.823969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.827316] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.827407] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.827447] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.827499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.844182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.844233] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.844299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.844493] [drm:drm_mode_addfb2] [FB:79]
>[ 1357.844624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.860901] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.860946] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.861035] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.878026] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.878064] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.878104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.878137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.878172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.878201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.878230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.878261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.878296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.878328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.878358] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.878389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.878416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.878444] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.878497] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.878538] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.878580] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.878611] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.878789] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.878879] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.879033] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.879089] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.879140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.879193] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.879234] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.879281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.879325] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.879371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.879412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.879454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.879492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.879503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.879542] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.879552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.879594] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.879632] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.879673] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.879713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.879759] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.879797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.879840] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.879920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.879960] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.880008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.880070] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.880163] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.880193] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.880224] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.880275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.880303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.880334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.880360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.880389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.880417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.880449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.880482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.880514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.880540] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.880568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.880602] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.880631] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.882702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.882725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.882748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.882772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.884359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.884381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.884404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.886032] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.886054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.887916] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.891248] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.891282] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.891305] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.891337] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.908060] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.908108] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.908171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.908351] [drm:drm_mode_addfb2] [FB:77]
>[ 1357.908465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.924754] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.924802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.924971] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1357.943776] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1357.943815] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1357.943949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.944003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.944060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.944108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.944156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.944205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.944261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.944313] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.944365] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.944415] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.944461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.944513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.944569] [drm:intel_power_well_disable [i915]] disabling display
>[ 1357.944612] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1357.944652] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.944685] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1357.944856] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1357.944871] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1357.944935] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1357.944959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1357.944984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1357.945009] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1357.945029] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1357.945050] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1357.945072] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1357.945100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1357.945118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1357.945136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1357.945152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1357.945156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.945173] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1357.945176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1357.945193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1357.945209] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1357.945226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1357.945241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1357.945261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1357.945277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1357.945294] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1357.945310] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1357.945326] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1357.945345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.945367] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1357.945414] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1357.945431] [drm:intel_power_well_enable [i915]] enabling display
>[ 1357.945447] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1357.945479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1357.945497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1357.945514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1357.945531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1357.945547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1357.945565] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1357.945584] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1357.945602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1357.945627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.945650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1357.945673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1357.945698] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1357.945721] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1357.947795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1357.947817] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1357.947896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.947934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1357.949502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1357.949522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1357.949540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1357.951094] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1357.951115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1357.952986] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1357.956303] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1357.956369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1357.956401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1357.956444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1357.973148] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1357.973201] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1357.973269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1357.973467] [drm:drm_mode_addfb2] [FB:78]
>[ 1357.973593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1357.989823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1357.989916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1357.989986] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.006976] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.007019] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.007064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.007105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.007150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.007189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.007230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.007270] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.007315] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.007357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.007400] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.007442] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.007481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.007520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.007578] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.007624] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.007675] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.007711] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.007925] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.007947] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.008044] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.008076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.008111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.008149] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.008177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.008209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.008239] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.008269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.008297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.008325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.008351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.008358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.008384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.008391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.008420] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.008445] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.008473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.008498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.008530] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.008555] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.008583] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.008608] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.008636] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.008665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.008698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.008776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.008806] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.008859] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.008915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.008945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.008976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.009004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.009034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.009062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.009096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.009130] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.009165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.009192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.009222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.009256] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.009285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.011376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.011398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.011417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.011437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.013019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.013043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.013066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.014627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.014649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.016524] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.019871] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.019959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.019992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.020034] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.036739] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.036791] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.036955] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.037196] [drm:drm_mode_addfb2] [FB:79]
>[ 1358.037322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.053452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.053500] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.053573] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.070562] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.070599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.070639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.070674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.070709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.070739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.070769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.070801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.070920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.070974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.071021] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.071073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.071119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.071164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.071249] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.071323] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.071354] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.071375] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.071476] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.071488] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.071543] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.071564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.071590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.071619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.071644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.071671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.071698] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.071724] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.071750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.071777] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.071804] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.071844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.071876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.071883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.071914] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.071942] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.071969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.071996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.072027] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.072054] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.072082] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.072109] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.072135] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.072165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.072198] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.072274] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.072306] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.072336] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.072390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.072422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.072453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.072482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.072512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.072543] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.072574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.072596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.072616] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.072635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.072653] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.072680] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.072705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.074763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.074785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.074803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.074881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.076455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.076476] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.076494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.078059] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.078080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.079954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.083298] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.083388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.083421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.083463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.100166] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.100217] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.100282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.100462] [drm:drm_mode_addfb2] [FB:77]
>[ 1358.100596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.116882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.116928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.116999] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.133994] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.134032] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.134072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.134105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.134140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.134171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.134201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.134232] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.134267] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.134299] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.134330] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.134361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.134389] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.134416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.134470] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.134511] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.134553] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.134584] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.134763] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.134781] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.134946] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.134988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.135033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.135081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.135118] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.135162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.135201] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.135241] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.135278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.135316] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.135350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.135359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.135394] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.135403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.135440] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.135477] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.135513] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.135546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.135587] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.135620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.135657] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.135693] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.135736] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.135767] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.135800] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.135898] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.135930] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.135961] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.136012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.136041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.136071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.136098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.136126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.136154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.136186] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.136218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.136250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.136275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.136302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.136337] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.136365] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.138439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.138460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.138479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.138501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.140079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.140102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.140125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.141687] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.141709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.143580] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.146906] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.146947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.146966] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.146992] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.163743] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.163794] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.163959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.164203] [drm:drm_mode_addfb2] [FB:78]
>[ 1358.164331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.180417] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.180465] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.180536] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.197561] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.197599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.197639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.197673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.197708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.197738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.197768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.197800] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.197920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.197974] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.198026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.198071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.198111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.198151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.198222] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.198259] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.198301] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.198333] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.198468] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.198484] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.198558] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.198587] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.198618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.198650] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.198676] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.198705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.198732] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.198766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.198804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.198877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.198914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.198926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.198964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.198973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.199019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.199049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.199078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.199107] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.199141] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.199170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.199200] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.199228] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.199257] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.199291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.199325] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.199408] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.199442] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.199475] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.199532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.199567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.199600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.199634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.199666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.199700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.199726] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.199748] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.199771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.199791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.199843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.199877] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.199909] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.201981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.202001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.202020] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.202039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.203598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.203618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.203636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.205186] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.205217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.207084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.210350] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.210400] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.210419] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.210445] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.227191] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.227240] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.227303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.227501] [drm:drm_mode_addfb2] [FB:79]
>[ 1358.227613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.243870] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.243915] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.243986] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.262049] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.262087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.262131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.262172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.262216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.262256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.262296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.262335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.262380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.262423] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.262465] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.262508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.262543] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.262563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.262596] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.262621] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.262648] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.262667] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.262779] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.262833] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.262930] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.262962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.262997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.263035] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.263064] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.263097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.263127] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.263159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.263187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.263216] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.263242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.263249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.263276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.263282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.263311] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.263339] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.263366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.263392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.263423] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.263449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.263477] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.263503] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.263530] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.263563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.263596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.263673] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.263703] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.263733] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.263783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.263811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.263866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.263897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.263928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.263957] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.263991] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.264024] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.264057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.264083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.264113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.264148] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.264177] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.266249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.266270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.266292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.266317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.267916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.267936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.267954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.269517] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.269538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.271420] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.274713] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.274789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.274874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.274908] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.291590] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.291641] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.291709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.292029] [drm:drm_mode_addfb2] [FB:77]
>[ 1358.292166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.308290] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.308338] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.308430] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.325466] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.325504] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.325543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.325577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.325611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.325641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.325670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.325702] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.325736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.325768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.325799] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.325921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.325956] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.325991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.326064] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.326123] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.326178] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.326222] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.326361] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.326377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.326450] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.326478] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.326508] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.326541] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.326567] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.326595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.326623] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.326649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.326675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.326699] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.326722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.326728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.326752] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.326758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.326782] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.326818] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.326896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.326932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.326962] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.326988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.327015] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.327041] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.327067] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.327099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.327130] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.327207] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.327231] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.327250] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.327284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.327304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.327324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.327342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.327361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.327380] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.327401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.327421] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.327447] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.327473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.327498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.327526] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.327552] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.329606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.329627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.329645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.329664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.331253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.331275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.331295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.332850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.332871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.334740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.338088] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.338159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.338179] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.338205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.354941] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.354993] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.355063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.355247] [drm:drm_mode_addfb2] [FB:78]
>[ 1358.355378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.371628] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.371677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.371748] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.390708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.390746] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.390789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.390917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.390980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.391031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.391081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.391131] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.391188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.391241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.391293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.391342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.391371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.391401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.391456] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.391499] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.391539] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.391572] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.391728] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.391741] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.391812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.391877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.391910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.391950] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.391980] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.392015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.392041] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.392066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.392093] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.392119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.392144] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.392150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.392175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.392180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.392206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.392232] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.392257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.392283] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.392309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.392334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.392360] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.392385] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.392412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.392438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.392468] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.392521] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.392543] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.392565] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.392605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.392630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.392653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.392673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.392693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.392713] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.392737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.392757] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.392778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.392798] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.392854] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.392888] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.392917] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.395001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.395026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.395049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.395073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.396636] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.396657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.396676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.398239] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.398260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.400130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.403473] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.403572] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.403599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.403633] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.420340] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.420391] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.420457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.420637] [drm:drm_mode_addfb2] [FB:79]
>[ 1358.420771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.437017] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.437065] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.437138] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.454165] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.454203] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.454243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.454277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.454313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.454344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.454373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.454405] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.454441] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.454473] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.454514] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.454557] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.454596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.454635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.454692] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.454739] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.454779] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.454864] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.455010] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.455028] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.455119] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.455150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.455184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.455220] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.455248] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.455280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.455310] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.455341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.455369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.455397] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.455423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.455430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.455457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.455464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.455494] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.455520] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.455547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.455573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.455604] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.455630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.455658] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.455683] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.455711] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.455740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.455773] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.455869] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.455900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.455931] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.455982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.456013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.456042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.456072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.456098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.456129] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.456162] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.456193] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.456226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.456252] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.456280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.456313] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.456342] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.458415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.458439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.458463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.458487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.460061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.460083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.460105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.461659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.461680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.463549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.466878] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.466931] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.466963] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.467009] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.483718] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.483771] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.483930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.484207] [drm:drm_mode_addfb2] [FB:77]
>[ 1358.484348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.500415] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.500463] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.500538] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.517535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.517573] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.517613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.517647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.517682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.517711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.517740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.517772] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.517890] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.517942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.517995] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.518046] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.518088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.518139] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.518195] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.518237] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.518277] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.518309] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.518459] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.518473] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.518538] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.518564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.518591] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.518619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.518644] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.518670] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.518696] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.518722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.518747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.518773] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.518798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.518838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.518871] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.518878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.518909] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.518938] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.518967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.518994] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.519025] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.519053] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.519084] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.519113] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.519141] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.519175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.519210] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.519288] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.519319] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.519350] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.519402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.519424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.519445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.519464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.519484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.519504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.519532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.519561] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.519589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.519614] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.519640] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.519668] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.519694] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.521746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.521768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.521790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.521870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.523444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.523465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.523483] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.525045] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.525065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.526940] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.530284] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.530358] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.530377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.530402] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.547130] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.547177] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.547240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.547432] [drm:drm_mode_addfb2] [FB:78]
>[ 1358.547542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.563896] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.563944] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.564033] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.581023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.581061] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.581100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.581134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.581169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.581200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.581230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.581262] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.581297] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.581330] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.581362] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.581394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.581422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.581450] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.581505] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.581540] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.581575] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.581602] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.581743] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.581760] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.581932] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.581973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.582019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.582067] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.582104] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.582147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.582186] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.582226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.582265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.582302] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.582339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.582348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.582383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.582392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.582430] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.582464] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.582511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.582543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.582582] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.582615] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.582651] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.582685] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.582720] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.582756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.582799] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.582946] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.582985] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.583023] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.583087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.583126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.583161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.583199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.583232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.583270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.583311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.583351] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.583390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.583422] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.583457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.583500] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.583532] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.585611] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.585634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.585657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.585681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.587271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.587295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.587318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.588920] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.588942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.590800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.594168] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.594260] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.594293] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.594335] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.611039] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.611090] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.611156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.611358] [drm:drm_mode_addfb2] [FB:79]
>[ 1358.611472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.627753] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.627802] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.627975] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.646748] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.646785] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.646917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.646955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.646992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.647023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.647052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.647083] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.647120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.647154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.647185] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.647216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.647254] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.647294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.647352] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.647399] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.647450] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.647486] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.647643] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.647662] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.647753] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.647806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.647872] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.647908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.647937] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.647969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.647999] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.648030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.648058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.648087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.648114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.648123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.648148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.648156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.648184] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.648214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.648243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.648270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.648300] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.648329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.648351] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.648369] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.648387] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.648408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.648431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.648482] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.648500] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.648518] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.648552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.648572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.648597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.648623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.648649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.648675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.648703] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.648731] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.648759] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.648785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.648838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.648873] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.648902] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.650970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.650993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.651016] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.651040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.652602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.652623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.652642] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.654206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.654227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.656089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.659408] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.659470] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.659502] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.659544] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.676251] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.676303] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.676374] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.676574] [drm:drm_mode_addfb2] [FB:77]
>[ 1358.676707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.692927] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.692975] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.693046] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.710071] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.710108] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.710148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.710182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.710218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.710248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.710278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.710309] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.710345] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.710377] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.710408] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.710439] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.710467] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.710495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.710549] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.710593] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.710644] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.710680] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.710918] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.710949] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.711115] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.711164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.711221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.711269] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.711307] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.711349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.711388] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.711428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.711465] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.711503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.711536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.711545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.711580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.711589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.711627] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.711661] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.711698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.711731] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.711772] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.711842] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.711882] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.711918] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.711958] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.712003] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.712048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.712168] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.712208] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.712251] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.712305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.712336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.712368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.712397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.712429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.712459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.712494] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.712529] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.712563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.712591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.712621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.712654] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.712687] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.714780] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.714822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.714841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.714861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.716434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.716454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.716472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.718036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.718058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.719931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.723274] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.723366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.723400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.723439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.740144] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.740194] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.740262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.740482] [drm:drm_mode_addfb2] [FB:78]
>[ 1358.740613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.756861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.756907] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.756975] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.773972] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.774009] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.774049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.774083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.774118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.774149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.774178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.774210] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.774245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.774279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.774311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.774343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.774380] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.774420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.774477] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.774524] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.774574] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.774610] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.774766] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.774816] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.774912] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.774943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.774977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.775014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.775042] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.775074] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.775105] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][modeset]
>[ 1358.775135] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1358.775163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.775192] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.775218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.775225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.775252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.775259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.775288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.775315] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.775343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.775368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.775399] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.775425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.775453] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1358.775479] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1358.775507] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1358.775536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.775569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe B
>[ 1358.775663] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.775693] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.775722] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.775772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.775828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.775858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.775889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.775919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.775953] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.775988] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.776021] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.776054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.776081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.776111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.776146] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 2, on? 0) for crtc 39
>[ 1358.776175] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.778243] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.778264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.778283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.778302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.779894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.779914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.779931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.781484] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.781505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.783372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.786692] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1358.786755] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.786788] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 1358.786914] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.803543] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.803593] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.803658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.804044] [drm:drm_mode_addfb2] [FB:79]
>[ 1358.804172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.820238] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 1358.820285] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.820362] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1358.837368] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 2, on? 1) for crtc 39
>[ 1358.837405] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.837445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.837478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.837512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.837542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.837570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.837602] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.837637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.837670] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.837702] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.837733] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.837761] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.837789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.837944] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.838008] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.838051] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1358.838085] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.838341] [drm:drm_mode_addfb2] [FB:77]
>[ 1358.838371] [drm:drm_mode_addfb2] [FB:78]
>[ 1358.867677] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[ 1358.867839] [drm:drm_mode_setcrtc] [CRTC:39:pipe B]
>[ 1358.867932] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1358.867997] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1358.868010] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.868078] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.868100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.868122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.868146] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.868169] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.868193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.868217] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1358.868241] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1358.868265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.868289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.868312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.868317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.868339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.868343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.868367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.868391] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.868414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.868437] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.868461] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.868484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.868508] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1358.868531] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1358.868554] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1358.868579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.868605] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1358.871860] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.871879] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.871895] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.871931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.871952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.871970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.871988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.872005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.872024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.872044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.872063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.872082] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.872099] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.872115] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.872136] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1358.872155] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.874218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.874239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.874262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.874286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.875892] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.875913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.875932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.877484] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.877508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.879382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.882679] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1358.882766] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.882875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1358.882950] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.899547] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.899598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1358.899664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.916214] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1358.916232] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.933044] [drm:drm_mode_addfb2] [FB:79]
>[ 1358.933176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.949580] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1358.949628] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1358.949701] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1358.966722] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1358.966760] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1358.966892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.966945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.967004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.967055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.967089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.967121] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.967159] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.967194] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.967226] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.967258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.967286] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.967315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.967369] [drm:intel_power_well_disable [i915]] disabling display
>[ 1358.967410] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1358.967453] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1358.967484] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1358.967636] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1358.967654] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1358.967740] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1358.967779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1358.967874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1358.967928] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1358.967973] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1358.968015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1358.968046] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1358.968074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1358.968103] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1358.968130] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1358.968156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1358.968164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.968190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1358.968198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1358.968225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1358.968251] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1358.968277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1358.968303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1358.968334] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1358.968363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1358.968392] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1358.968418] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1358.968444] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1358.968479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1358.968513] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1358.968604] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1358.968636] [drm:intel_power_well_enable [i915]] enabling display
>[ 1358.968666] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1358.968719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1358.968752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1358.968783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1358.968837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1358.968865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1358.968894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1358.968926] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1358.968959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1358.968991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.969020] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1358.969049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1358.969083] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1358.969115] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1358.971157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1358.971177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1358.971195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.971214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1358.972777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1358.972814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1358.972837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1358.974394] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1358.974416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1358.976304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1358.979596] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1358.979682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1358.979709] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1358.979745] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1358.996455] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1358.996505] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1358.996572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1358.996833] [drm:drm_mode_addfb2] [FB:77]
>[ 1358.997036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.013184] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.013232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.013307] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.030319] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.030357] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.030396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.030430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.030465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.030496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.030525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.030556] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.030592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.030624] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.030655] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.030686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.030713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.030740] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.030882] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.030951] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.031016] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.031068] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.031289] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.031316] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.031454] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.031505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.031554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.031591] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.031622] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.031655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.031688] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.031719] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.031750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.031780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.031833] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.031842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.031872] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.031880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.031912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.031942] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.031973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.032003] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.032037] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.032067] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.032094] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.032124] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.032155] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.032189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.032224] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.032311] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.032342] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.032373] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.032424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.032455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.032486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.032516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.032546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.032576] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.032610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.032642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.032674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.032704] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.032732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.032766] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.032824] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.034886] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.034906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.034924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.034943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.036515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.036535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.036554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.038116] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.038140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.040012] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.043344] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.043450] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.043490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.043542] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.060225] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.060276] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.060347] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.060548] [drm:drm_mode_addfb2] [FB:78]
>[ 1359.060681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.076939] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.076986] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.077057] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.094052] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.094089] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.094129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.094164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.094199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.094229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.094258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.094290] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.094325] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.094357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.094388] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.094419] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.094448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.094485] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.094542] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.094589] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.094639] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.094675] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.094893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.094923] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.095077] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.095126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.095190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.095226] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.095256] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.095288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.095318] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.095349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.095377] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.095406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.095432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.095439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.095466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.095472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.095501] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.095527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.095556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.095581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.095612] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.095638] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.095667] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.095694] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.095722] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.095751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.095819] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.095894] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.095924] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.095955] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.096006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.096036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.096064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.096092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.096117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.096147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.096180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.096211] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.096244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.096271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.096299] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.096329] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.096360] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.098436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.098458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.098477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.098496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.100064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.100084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.100103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.101659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.101683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.103557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.106910] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.106992] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.107024] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.107075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.123760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.123842] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.123907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.124105] [drm:drm_mode_addfb2] [FB:79]
>[ 1359.124231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.140484] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.140535] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.140610] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.157594] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.157636] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.157681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.157722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.157766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.157892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.157944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.157997] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.158056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.158111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.158164] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.158200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.158229] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.158258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.158312] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.158354] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.158397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.158428] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.158568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.158586] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.158662] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.158683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.158706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.158734] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.158763] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.158824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.158854] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.158884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.158912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.158939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.158965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.158973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.159000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.159007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.159035] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.159061] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.159088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.159115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.159145] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.159171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.159198] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.159224] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.159250] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.159280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.159314] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.159392] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.159423] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.159453] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.159507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.159540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.159570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.159601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.159630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.159662] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.159686] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.159707] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.159727] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.159746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.159770] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.159829] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.159858] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.161930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.161951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.161970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.161989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.163558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.163578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.163596] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.165148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.165168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.167038] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.170388] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.170474] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.170507] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.170550] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.187250] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.187301] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.187368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.187546] [drm:drm_mode_addfb2] [FB:77]
>[ 1359.187668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.203927] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.203975] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.204047] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.221073] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.221111] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.221151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.221185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.221228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.221268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.221308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.221348] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.221392] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.221435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.221477] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.221519] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.221559] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.221598] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.221655] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.221702] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.221751] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.221878] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.222053] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.222072] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.222161] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.222194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.222229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.222266] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.222297] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.222330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.222364] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.222395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.222426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.222457] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.222486] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.222493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.222521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.222528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.222558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.222587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.222617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.222647] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.222676] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.222705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.222735] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.222765] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.222817] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.222853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.222890] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.222964] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.222995] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.223026] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.223077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.223108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.223136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.223166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.223193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.223223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.223257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.223290] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.223323] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.223352] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.223383] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.223416] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.223448] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.225513] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.225534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.225552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.225571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.227144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.227164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.227187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.228767] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.228805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.230675] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.234047] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.234108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.234147] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.234201] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.250888] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.250943] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.251014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.251209] [drm:drm_mode_addfb2] [FB:78]
>[ 1359.251336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.267567] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.267619] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.267694] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.284705] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.284743] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.284875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.284933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.284991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.285041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.285089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.285139] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.285196] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.285250] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.285301] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.285353] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.285396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.285425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.285480] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.285523] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.285563] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.285602] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.285747] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.285788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.285886] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.285917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.285951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.285997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.286023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.286053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.286080] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.286108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.286135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.286162] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.286186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.286193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.286218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.286224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.286252] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.286276] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.286302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.286326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.286355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.286380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.286406] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.286430] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.286457] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.286487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.286518] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.286589] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.286617] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.286645] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.286692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.286721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.286747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.286814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.286847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.286878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.286913] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.286946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.286980] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.287007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.287036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.287072] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.287101] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.289192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.289217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.289240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.289264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.290867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.290891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.290914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.292473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.292495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.294367] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.297664] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.297744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.297832] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.297893] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.314531] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.314581] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.314648] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.314972] [drm:drm_mode_addfb2] [FB:79]
>[ 1359.315114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.331246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.331297] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.331375] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.348354] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.348392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.348432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.348466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.348501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.348532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.348562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.348593] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.348628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.348661] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.348692] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.348723] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.348752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.348844] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.348900] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.348943] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.348984] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.349017] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.349165] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.349183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.349272] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.349304] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.349339] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.349377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.349408] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.349441] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.349473] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.349505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.349536] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.349566] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.349596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.349603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.349632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.349640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.349670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.349700] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.349729] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.349758] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.349820] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.349852] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.349883] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.349913] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.349944] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.349978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.350013] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.350105] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.350137] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.350167] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.350217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.350249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.350280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.350311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.350341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.350372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.350406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.350438] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.350471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.350500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.350529] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.350563] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.350595] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.352654] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.352674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.352692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.352711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.354305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.354326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.354344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.355923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.355945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.357908] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.361219] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.361285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.361312] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.361348] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.378068] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.378120] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.378185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.378382] [drm:drm_mode_addfb2] [FB:77]
>[ 1359.378510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.394745] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.394823] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.394895] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.412304] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.412341] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.412381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.412421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.412465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.412506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.412546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.412585] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.412630] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.412673] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.412715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.412757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.412872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.412924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.413006] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.413073] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.413139] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.413190] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.413360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.413380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.413477] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.413509] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.413543] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.413579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.413608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.413642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.413672] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.413702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.413731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.413761] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.413821] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.413830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.413860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.413868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.413899] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.413927] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.413958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.413985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.414018] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.414045] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.414074] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.414105] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.414135] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.414169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.414204] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.414283] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.414315] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.414344] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.414395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.414425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.414455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.414482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.414510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.414538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.414571] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.414603] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.414635] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.414662] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.414690] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.414721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.414752] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.416854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.416874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.416897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.416921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.418489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.418509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.418528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.420085] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.420106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.421985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.425336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.425421] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.425460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.425495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.442198] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.442249] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.442317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.442519] [drm:drm_mode_addfb2] [FB:78]
>[ 1359.442656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.458873] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.458926] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.459018] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.476026] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.476063] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.476102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.476136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.476171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.476201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.476230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.476261] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.476296] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.476328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.476359] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.476390] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.476417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.476445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.476501] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.476548] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.476598] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.476635] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.476796] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.476818] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.476916] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.476949] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.476983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.477019] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.477047] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.477079] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.477109] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.477139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.477167] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.477196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.477222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.477229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.477256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.477262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.477291] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.477317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.477346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.477371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.477402] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.477428] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.477456] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.477482] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.477509] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.477539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.477572] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.477666] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.477695] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.477725] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.477801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.477831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.477862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.477891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.477921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.477950] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.477984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.478018] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.478052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.478081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.478111] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.478147] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.478176] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.480266] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.480287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.480305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.480324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.481929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.481952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.481971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.483533] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.483555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.485429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.488756] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.488864] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.488900] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.488926] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.505627] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.505679] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.505745] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.506081] [drm:drm_mode_addfb2] [FB:79]
>[ 1359.506218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.522342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.522389] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.522479] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.539469] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.539507] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.539547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.539581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.539617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.539647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.539677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.539709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.539752] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.539878] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.539935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.539993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.540024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.540055] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.540111] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.540154] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.540194] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.540227] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.540364] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.540384] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.540483] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.540512] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.540544] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.540578] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.540605] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.540635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.540662] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.540691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.540717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.540754] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.540815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.540824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.540853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.540861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.540892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.540919] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.540950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.540978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.541011] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.541039] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.541069] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.541095] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.541126] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.541156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.541191] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.541268] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.541298] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.541328] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.541380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.541411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.541439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.541468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.541494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.541523] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.541556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.541589] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.541620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.541646] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.541673] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.541705] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.541736] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.543827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.543848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.543867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.543886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.545450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.545470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.545488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.547043] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.547064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.548935] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.552273] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.552363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.552390] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.552424] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.569156] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.569208] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.569275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.569474] [drm:drm_mode_addfb2] [FB:77]
>[ 1359.569601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.585851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.585903] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.585982] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.602976] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.603014] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.603054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.603087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.603122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.603152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.603182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.603213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.603249] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.603281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.603312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.603343] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.603371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.603398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.603458] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.603484] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.603508] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.603527] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.603652] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.603663] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.603720] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.603753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.603830] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.603866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.603895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.603927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.603957] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.603987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.604016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.604045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.604072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.604080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.604108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.604116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.604145] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.604174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.604202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.604228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.604261] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.604291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.604320] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.604350] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.604380] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.604412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.604447] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.604528] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.604559] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.604579] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.604624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.604654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.604683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.604712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.604739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.604794] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.604827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.604858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.604889] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.604918] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.604945] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.604977] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.605007] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.607076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.607097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.607115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.607135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.608755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.608787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.608806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.610365] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.610405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.612275] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.615076] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.615152] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.615183] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.615223] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.631940] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.631992] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.632059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.632262] [drm:drm_mode_addfb2] [FB:78]
>[ 1359.632392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.648634] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.648683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.648758] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.667290] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.667328] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.667367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.667401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.667436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.667466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.667495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.667527] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.667563] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.667595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.667626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.667658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.667686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.667713] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.667858] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.667904] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.667946] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.667979] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.668126] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.668145] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.668234] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.668267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.668302] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.668340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.668371] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.668404] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.668437] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.668469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.668500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.668530] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.668559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.668567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.668596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.668603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.668632] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.668662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.668691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.668719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.668752] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.668805] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.668837] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.668867] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.668897] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.668932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.668967] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.669059] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.669090] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.669120] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.669171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.669203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.669234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.669265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.669294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.669326] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.669359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.669392] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.669425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.669454] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.669483] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.669517] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.669548] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.671621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.671644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.671663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.671682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.673273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.673293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.673311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.674887] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.674908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.676795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.680099] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.680162] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.680182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.680207] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.696957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.697009] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.697076] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.697259] [drm:drm_mode_addfb2] [FB:79]
>[ 1359.697394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.713636] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.713686] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.713775] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.730831] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.730869] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.730909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.730943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.730978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.731018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.731058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.731097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.731142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.731185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.731227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.731269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.731312] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.731333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.731366] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.731391] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.731419] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.731438] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.731565] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.731577] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.731635] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.731660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.731685] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.731713] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.731747] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.731836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.731872] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.731906] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.731939] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.731971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.732002] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.732011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.732040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.732048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.732079] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.732109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.732140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.732168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.732202] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.732232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.732262] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.732291] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.732330] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.732364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.732400] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.732475] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.732507] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.732539] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.732592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.732625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.732658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.732689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.732721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.732753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.732815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.732849] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.732885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.732916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.732946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.732983] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.733016] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.735109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.735131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.735150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.735169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.736752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.736789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.736808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.738370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.738392] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.740276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.743578] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.743644] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.743663] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.743693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.760432] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.760481] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.760545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.760903] [drm:drm_mode_addfb2] [FB:77]
>[ 1359.761081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.777134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.777184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.777256] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.794289] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.794326] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.794366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.794400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.794435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.794466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.794495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.794526] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.794562] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.794595] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.794626] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.794658] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.794686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.794714] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.794825] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.794869] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.794910] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.794942] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.795088] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.795106] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.795195] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.795228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.795262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.795300] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.795331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.795365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.795397] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.795429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.795461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.795491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.795521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.795529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.795558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.795565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.795595] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.795624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.795654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.795683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.795715] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.795745] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.795799] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.795830] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.795862] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.795897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.795932] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.796020] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.796051] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.796083] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.796133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.796165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.796195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.796226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.796255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.796287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.796322] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.796355] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.796387] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.796417] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.796446] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.796479] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.796511] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.798569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.798591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.798610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.798631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.800216] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.800237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.800255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.801848] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.801869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.803735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.807059] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.807117] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.807136] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.807167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.823898] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.823951] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.824021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.824225] [drm:drm_mode_addfb2] [FB:78]
>[ 1359.824342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.840588] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.840640] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.840716] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.857811] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.857853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.857898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.857939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.857983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.858023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.858063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.858103] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.858148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.858190] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.858235] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.858265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.858291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.858316] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.858361] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.858397] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.858433] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.858460] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.858619] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.858635] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.858715] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.858748] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.858836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.858884] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.858922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.858965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.859005] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.859044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.859081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.859118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.859153] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.859164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.859198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.859208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.859249] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.859287] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.859322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.859356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.859396] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.859435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.859474] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.859512] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.859550] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.859594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.859639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.859796] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.859839] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.859879] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.859954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.859997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.860038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.860078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.860118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.860150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.860187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.860223] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.860258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.860296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.860325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.860354] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.860383] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.862441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.862462] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.862480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.862499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.864069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.864088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.864106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.865668] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.865688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.867568] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.870884] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.870950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.870988] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.871037] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.887731] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.887814] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.887881] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.888077] [drm:drm_mode_addfb2] [FB:79]
>[ 1359.888191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.904447] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.904495] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.904569] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.921556] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.921593] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.921633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.921668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.921711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.921751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.921878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.921936] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.921996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.922049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.922101] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.922152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.922198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.922244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.922331] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.922396] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.922460] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.922511] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.922682] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.922696] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.922819] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.922851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.922886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.922924] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.922953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.922985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.923015] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.923045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.923073] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.923102] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.923128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.923135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.923162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.923169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.923198] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.923224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.923252] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.923277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.923309] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.923334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.923363] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.923388] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.923416] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.923445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.923478] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.923559] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.923589] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.923618] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.923677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.923705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.923732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.923799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.923828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.923860] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.923894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.923926] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.923961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.923988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.924017] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.924052] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.924081] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.926158] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.926180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.926203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.926227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.927797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.927819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.927838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.929409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.929432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.931303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.934627] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.934686] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.934719] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.934859] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1359.951464] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.951515] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.951582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.951855] [drm:drm_mode_addfb2] [FB:77]
>[ 1359.952058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.968166] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1359.968215] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1359.968290] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1359.985299] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1359.985336] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1359.985376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.985410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.985444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.985475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.985504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.985535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1359.985570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.985602] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.985633] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.985664] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.985692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.985719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.985850] [drm:intel_power_well_disable [i915]] disabling display
>[ 1359.985919] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1359.985987] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1359.986021] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1359.986156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1359.986169] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1359.986227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1359.986253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1359.986280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1359.986310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1359.986335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1359.986362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1359.986388] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1359.986414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1359.986440] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1359.986466] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1359.986491] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1359.986497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.986522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1359.986526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1359.986553] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1359.986579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1359.986605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1359.986630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1359.986657] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1359.986682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1359.986708] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1359.986734] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1359.986790] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1359.986824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1359.986858] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1359.986929] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1359.986961] [drm:intel_power_well_enable [i915]] enabling display
>[ 1359.986991] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1359.987046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1359.987079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1359.987110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1359.987142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1359.987171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1359.987203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1359.987237] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1359.987270] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1359.987295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1359.987313] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1359.987332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1359.987355] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1359.987380] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1359.989445] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1359.989468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1359.989486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.989506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1359.991082] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1359.991103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1359.991121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1359.992671] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1359.992692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1359.994606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1359.997950] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1359.998041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1359.998074] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1359.998116] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.014821] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.014873] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.014940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.015142] [drm:drm_mode_addfb2] [FB:78]
>[ 1360.015273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.031537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.031586] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.031676] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.048644] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.048681] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.048720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.048837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.048893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.048941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.048988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.049034] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.049092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.049144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.049194] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.049244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.049285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.049328] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.049403] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.049445] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.049484] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.049516] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.049675] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.049688] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.049818] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.049856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.049894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.049933] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.049965] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.050001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.050036] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.050070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.050102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.050133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.050164] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.050171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.050200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.050208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.050238] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.050267] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.050293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.050322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.050355] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.050384] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.050411] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.050439] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.050468] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.050501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.050536] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.050632] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.050663] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.050694] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.050769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.050804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.050833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.050865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.050896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.050928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.050963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.050997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.051030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.051060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.051091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.051125] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.051157] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.053247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.053267] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.053290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.053314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.054962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.054983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.055001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.056565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.056588] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.058463] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.061718] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.061780] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.061799] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.061825] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.078576] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.078629] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.078702] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.079029] [drm:drm_mode_addfb2] [FB:79]
>[ 1360.079181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.095289] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.095341] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.095433] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.112423] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.112460] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.112503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.112545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.112589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.112630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.112670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.112710] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.112836] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.112892] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.112946] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.112995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.113034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.113078] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.113159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.113219] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.113278] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.113325] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.113548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.113576] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.113709] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.113825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.113870] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.113918] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.113957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.113999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.114041] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.114081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.114120] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.114158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.114196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.114206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.114240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.114250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.114287] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.114326] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.114362] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.114399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.114437] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.114474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.114512] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.114549] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.114586] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.114626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.114669] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.114806] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.114840] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.114874] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.114928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.114962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.114994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.115027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.115057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.115090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.115125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.115158] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.115192] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.115222] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.115253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.115288] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.115321] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.117400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.117421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.117443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.117468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.119058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.119080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.119099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.120658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.120679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.122553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.125896] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.125996] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.126015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.126041] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.142796] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.142847] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.142913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.143113] [drm:drm_mode_addfb2] [FB:77]
>[ 1360.143247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.159483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.159535] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.159627] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.176590] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.176632] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.176677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.176719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.176848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.176896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.176944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.176990] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.177044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.177096] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.177146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.177190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.177216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.177244] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.177301] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.177343] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.177384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.177416] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.177567] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.177580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.177649] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.177674] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.177700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.177729] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.177793] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.177830] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.177864] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.177898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.177930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.177961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.177992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.178002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.178031] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.178039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.178070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.178100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.178130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.178157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.178190] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.178221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.178252] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.178282] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.178308] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.178340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.178375] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.178474] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.178505] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.178536] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.178587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.178619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.178650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.178680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.178710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.178790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.178826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.178858] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.178891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.178920] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.178949] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.178984] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.179016] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.181105] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.181127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.181146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.181166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.182733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.182772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.182791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.184360] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.184382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.186270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.189510] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.189587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.189606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.189632] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.206363] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.206411] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.206476] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.206658] [drm:drm_mode_addfb2] [FB:78]
>[ 1360.206868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.223048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.223095] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.223184] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.240204] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.240241] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.240280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.240314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.240349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.240380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.240410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.240441] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.240477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.240517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.240547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.240576] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.240602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.240628] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.240678] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.240717] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.240833] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.240884] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.241072] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.241099] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.241227] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.241270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.241318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.241371] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.241412] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.241458] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.241510] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.241545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.241578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.241613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.241644] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.241652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.241686] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.241694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.241729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.241790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.241822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.241856] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.241893] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.241928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.241960] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.241995] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.242027] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.242066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.242108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.242195] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.242230] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.242265] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.242324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.242358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.242394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.242426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.242459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.242492] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.242533] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.242565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.242596] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.242622] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.242649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.242680] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.242710] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.244798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.244819] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.244838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.244856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.246433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.246453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.246474] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.248029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.248051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.249920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.253255] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.253355] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.253388] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.253431] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.270135] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.270187] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.270253] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.270453] [drm:drm_mode_addfb2] [FB:79]
>[ 1360.270581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.286854] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.286902] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.286991] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.303972] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.304011] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.304050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.304084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.304120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.304150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.304180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.304211] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.304247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.304279] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.304311] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.304342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.304370] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.304398] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.304452] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.304493] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.304534] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.304566] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.304815] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.304843] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.304977] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.305025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.305074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.305126] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.305169] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.305215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.305261] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.305305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.305349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.305390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.305431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.305441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.305480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.305489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.305530] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.305571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.305611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.305651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.305695] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.305735] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.305816] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.305847] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.305878] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.305913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.305949] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.306025] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.306056] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.306087] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.306138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.306170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.306200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.306230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.306256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.306287] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.306321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.306354] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.306386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.306416] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.306445] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.306478] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.306510] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.308578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.308600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.308619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.308638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.310211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.310231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.310250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.311830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.311853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.313716] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.317020] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.317100] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.317123] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.317155] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.333894] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.333946] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.334015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.334219] [drm:drm_mode_addfb2] [FB:77]
>[ 1360.334354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.350570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.350618] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.350707] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.367818] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.367856] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.367895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.367929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.367965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.367996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.368026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.368057] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.368092] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.368125] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.368156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.368187] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.368216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.368243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.368298] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.368340] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.368365] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.368383] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.368510] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.368522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.368579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.368602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.368625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.368651] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.368671] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.368692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.368725] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.368794] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.368831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.368863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.368894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.368902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.368931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.368939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.368970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.369000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.369031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.369060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.369095] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.369125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.369156] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.369186] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.369216] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.369250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.369286] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.369365] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.369396] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.369426] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.369477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.369509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.369536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.369565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.369592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.369622] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.369657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.369689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.369722] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.369773] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.369804] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.369840] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.369872] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.371963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.371985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.372004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.372024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.373594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.373614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.373636] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.375189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.375210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.377085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.380405] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.380468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.380500] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.380537] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.397248] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.397299] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.397366] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.397564] [drm:drm_mode_addfb2] [FB:78]
>[ 1360.397696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.413968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.414020] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.414114] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.431110] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.431147] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.431187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.431221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.431257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.431288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.431317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.431349] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.431384] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.431417] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.431457] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.431499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.431539] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.431578] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.431611] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.431639] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.431669] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.431691] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.431891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.431910] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.431998] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.432022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.432046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.432071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.432092] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.432114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.432136] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.432156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.432181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.432208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.432233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.432239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.432264] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.432269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.432294] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.432320] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.432344] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.432370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.432395] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.432421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.432447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.432472] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.432498] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.432525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.432552] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.432614] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.432636] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.432657] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.432697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.432752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.432784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.432813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.432842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.432871] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.432906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.432937] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.432968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.432995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.433021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.433053] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.433083] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.435147] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.435168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.435186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.435205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.436772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.436793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.436811] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.438363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.438387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.440261] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.443547] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.443644] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.443676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.443717] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.460424] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.460475] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.460542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.460821] [drm:drm_mode_addfb2] [FB:79]
>[ 1360.461006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.477140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.477188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.477263] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.494249] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.494286] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.494326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.494359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.494394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.494433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.494473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.494513] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.494557] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.494600] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.494642] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.494685] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.494724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.494818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.494896] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.494939] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.494982] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.495014] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.495164] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.495183] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.495271] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.495300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.495333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.495369] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.495396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.495428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.495458] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.495488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.495517] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.495546] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.495572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.495579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.495606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.495613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.495642] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.495668] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.495697] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.495748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.495781] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.495809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.495838] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.495866] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.495897] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.495931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.495966] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.496054] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.496084] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.496114] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.496164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.496195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.496222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.496250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.496276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.496306] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.496338] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.496371] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.496403] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.496429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.496457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.496491] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.496519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.498580] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.498601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.498623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.498647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.500248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.500269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.500288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.501871] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.501893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.503755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.507077] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.507122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.507141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.507167] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.523918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.523970] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.524037] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.524235] [drm:drm_mode_addfb2] [FB:77]
>[ 1360.524350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.540594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.540642] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.540714] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.557811] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.557848] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.557888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.557921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.557956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.557987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.558016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.558048] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.558082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.558114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.558146] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.558176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.558213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.558236] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.558280] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.558315] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.558350] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.558376] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.558532] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.558548] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.558628] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.558660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.558693] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.558801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.558846] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.558893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.558938] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.558982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.559025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.559066] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.559106] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.559118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.559156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.559166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.559206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.559257] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.559302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.559345] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.559393] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.559438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.559483] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.559527] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.559570] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.559618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.559667] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.559819] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.559865] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.559910] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.559985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.560032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.560079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.560124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.560171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.560217] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.560273] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.560312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.560350] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.560386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.560420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.560457] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.560495] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.562604] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.562625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.562644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.562663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.564261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.564281] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.564299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.565866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.565887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.567754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.571095] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.571188] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.571221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.571264] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.587967] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.588018] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.588084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.588280] [drm:drm_mode_addfb2] [FB:78]
>[ 1360.588407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.604676] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.604808] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.604914] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.623665] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.623703] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.623827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.623875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.623930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.623974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.624022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.624067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.624121] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.624174] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.624224] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.624275] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.624315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.624359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.624443] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.624508] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.624569] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.624618] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.624825] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.624839] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.624898] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.624921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.624944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.624969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.624988] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.625010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.625031] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.625052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.625071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.625090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.625108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.625113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.625130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.625134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.625153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.625177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.625203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.625228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.625253] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.625278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.625304] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.625329] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.625355] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.625381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.625409] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.625470] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.625492] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.625513] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.625551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.625573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.625594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.625613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.625631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.625651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.625672] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.625693] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.625756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.625785] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.625815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.625851] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.625881] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.627948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.627969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.627987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.628006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.629570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.629591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.629609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.631162] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.631183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.633053] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.636391] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.636491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.636532] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.636583] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.653268] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.653320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.653386] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.653583] [drm:drm_mode_addfb2] [FB:79]
>[ 1360.653711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.669943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.669994] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.670070] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.687089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.687126] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.687166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.687200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.687236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.687267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.687297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.687329] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.687365] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.687398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.687429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.687461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.687489] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.687516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.687569] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.687611] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.687660] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.687696] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.687987] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.688014] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.688157] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.688191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.688221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.688247] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.688267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.688290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.688312] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.688332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.688353] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.688372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.688390] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.688395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.688419] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.688424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.688450] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.688476] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.688502] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.688528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.688554] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.688579] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.688606] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.688631] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.688658] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.688684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.688741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.688831] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.688862] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.688894] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.688950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.688984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.689016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.689048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.689076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.689097] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.689124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.689153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.689180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.689207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.689232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.689260] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.689285] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.691332] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.691353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.691372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.691391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.692955] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.692975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.692993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.694550] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.694571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.696442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.699766] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.699824] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.699856] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.699898] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.716605] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.716656] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.716797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.717155] [drm:drm_mode_addfb2] [FB:77]
>[ 1360.717283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.733282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.733331] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.733404] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.751651] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.751688] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.751812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.751852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.751891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.751923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.751953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.751985] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.752023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.752057] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.752090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.752123] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.752151] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.752180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.752234] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.752276] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.752318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.752349] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.752515] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.752533] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.752598] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.752620] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.752642] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.752668] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.752689] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.752752] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.752782] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.752811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.752841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.752868] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.752895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.752903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.752928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.752936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.752962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.752989] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.753015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.753041] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.753070] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.753096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.753123] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.753148] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.753174] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.753204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.753236] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.753314] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.753345] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.753376] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.753429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.753461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.753491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.753521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.753550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.753581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.753614] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.753645] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.753666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.753684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.753732] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.753763] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.753792] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.755844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.755867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.755886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.755907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.757449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.757471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.757491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.759024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.759047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.760888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.763958] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.764004] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.764025] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.764053] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.780802] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.780853] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.780921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.781129] [drm:drm_mode_addfb2] [FB:78]
>[ 1360.781262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.797475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.797529] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.797622] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.814616] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.814653] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.814694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.814813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.814872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.814917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.814970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.815012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.815062] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.815109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.815154] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.815200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.815238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.815277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.815356] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.815416] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.815473] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.815520] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.815778] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.815799] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.815894] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.815928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.815963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.815999] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.816030] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.816051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.816071] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.816090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.816109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.816126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.816143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.816148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.816164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.816168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.816190] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.816214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.816237] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.816260] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.816293] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.816314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.816338] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.816368] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.816386] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.816410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.816435] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.816487] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.816508] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.816527] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.816564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.816586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.816606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.816629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.816653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.816676] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.816701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.816779] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.816815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.816848] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.816880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.816917] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.816949] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.819044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.819068] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.819091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.819115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.820706] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.820744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.820763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.822326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.822348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.824235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.827512] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.827561] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.827590] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.827627] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.844335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.844385] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.844448] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.844644] [drm:drm_mode_addfb2] [FB:79]
>[ 1360.844849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.861022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.861072] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.861161] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.878174] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.878212] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.878251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.878285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.878321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.878351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.878380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.878412] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.878447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.878479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.878511] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.878542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.878570] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.878597] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.878651] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.878696] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.878817] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.878871] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.879389] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.879412] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.879497] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.879524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.879553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.879584] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.879608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.879635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.879666] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.879698] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.879771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.879814] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.879849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.879861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.879896] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.879906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.879944] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.879978] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.880015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.880048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.880088] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.880122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.880456] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.880485] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.880513] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.880544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.880577] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.880673] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.880712] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.880768] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.880822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.880983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.881006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.881030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.881054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.881077] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.881103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.881128] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.881152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.881176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.881199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.881224] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.881247] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.883481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.883503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.883522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.883541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.885116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.885136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.885155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.886711] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.886742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.888611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.891931] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.891988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.892015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.892050] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.908776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.908828] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.908894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.909090] [drm:drm_mode_addfb2] [FB:77]
>[ 1360.909206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.925450] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.925502] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.925592] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1360.942591] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1360.942628] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1360.942669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.942703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.942820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.942866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.942915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.942960] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.943015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.943065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.943116] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.943165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.943206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.943251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.943334] [drm:intel_power_well_disable [i915]] disabling display
>[ 1360.943399] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1360.943459] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.943508] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.943765] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1360.943787] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1360.943897] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1360.943930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.943963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1360.943993] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1360.944012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1360.944032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.944053] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1360.944072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1360.944090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1360.944107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1360.944123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.944128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.944144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.944147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1360.944164] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1360.944181] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1360.944197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.944213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.944232] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1360.944249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.944265] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1360.944281] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1360.944296] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1360.944316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.944337] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1360.944384] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.944402] [drm:intel_power_well_enable [i915]] enabling display
>[ 1360.944418] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1360.944450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1360.944469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1360.944486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1360.944502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1360.944518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1360.944536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1360.944556] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1360.944574] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1360.944592] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.944608] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1360.944624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1360.944644] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1360.944663] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1360.946770] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.946791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.946814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.946838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.948404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1360.948425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1360.948447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.950012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.950033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.951920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.955173] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1360.955237] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1360.955257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1360.955283] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1360.972033] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1360.972087] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1360.972160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1360.972359] [drm:drm_mode_addfb2] [FB:78]
>[ 1360.972492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.988776] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1360.988829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1360.988920] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.005931] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.005969] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.006009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.006042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.006078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.006108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.006137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.006169] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.006203] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.006223] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.006241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.006260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.006276] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.006293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.006327] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.006356] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.006386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.006408] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.006535] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.006547] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.006605] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.006630] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.006655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.006693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.006768] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.006806] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.006841] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.006874] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.006907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.006938] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.006969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.006978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.007007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.007015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.007045] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.007077] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.007108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.007138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.007172] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.007202] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.007242] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.007273] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.007303] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.007337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.007374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.007473] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.007506] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.007538] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.007592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.007625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.007657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.007688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.007739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.007771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.007807] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.007842] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.007877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.007907] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.007934] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.007969] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.008002] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.010091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.010113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.010132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.010152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.011797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.011818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.011837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.013394] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.013415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.015288] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.018541] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.018607] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.018630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.018662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.035380] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.035428] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.035493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.035870] [drm:drm_mode_addfb2] [FB:79]
>[ 1361.036005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.052118] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.052166] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.052256] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.069258] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.069296] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.069336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.069370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.069405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.069436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.069465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.069497] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.069532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.069564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.069596] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.069627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.069656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.069683] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.069829] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.069899] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.069966] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.070019] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.070218] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.070236] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.070325] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.070359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.070396] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.070444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.070464] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.070486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.070508] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.070529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.070554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.070581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.070606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.070612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.070637] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.070642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.070668] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.070693] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.070747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.070778] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.070810] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.070839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.070870] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.070898] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.070926] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.070959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.070992] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.071082] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.071112] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.071143] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.071197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.071229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.071261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.071293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.071315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.071335] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.071358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.071379] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.071400] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.071418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.071437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.071459] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.071480] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.073521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.073541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.073559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.073579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.075144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.075164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.075182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.076798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.076820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.078681] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.081981] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.082075] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.082112] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.082161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.098854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.098905] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.098971] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.099166] [drm:drm_mode_addfb2] [FB:77]
>[ 1361.099297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.115531] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.115580] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.115669] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.132709] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.132778] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.132818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.132852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.132887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.132918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.132947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.132979] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.133014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.133046] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.133078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.133109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.133137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.133164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.133218] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.133259] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.133300] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.133331] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.133529] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.133549] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.133644] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.133683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.133803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.133865] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.133916] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.133972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.134025] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.134078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.134128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.134178] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.134226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.134240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.134285] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.134298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.134345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.134393] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.134442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.134488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.134541] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.134587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.134633] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.134678] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.134748] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.134799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.134855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.134980] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.135021] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.135061] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.135129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.135172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.135212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.135251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.135290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.135328] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.135372] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.135415] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.135457] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.135496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.135534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.135579] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.135621] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.137741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.137762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.137781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.137800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.139377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.139399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.139418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.140984] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.141005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.142875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.146104] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.146140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.146159] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.146185] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.162917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.162966] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.163032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.163227] [drm:drm_mode_addfb2] [FB:78]
>[ 1361.163356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.179612] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.179660] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.179816] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.198638] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.198675] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.198791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.198841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.198897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.198946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.198993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.199043] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.199100] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.199150] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.199201] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.199250] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.199291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.199331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.199383] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.199425] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.199470] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.199500] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.199638] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.199651] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.199782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.199816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.199852] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.199889] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.199920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.199953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.199988] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.200021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.200053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.200083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.200113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.200120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.200149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.200156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.200186] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.200216] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.200245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.200274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.200306] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.200336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.200366] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.200395] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.200422] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.200454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.200488] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.200593] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.200622] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.200650] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.200739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.200775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.200805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.200837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.200868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.200900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.200935] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.200969] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.201003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.201033] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.201063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.201099] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.201131] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.203208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.203230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.203250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.203269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.204858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.204884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.204909] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.206445] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.206468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.208333] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.211609] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.211650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.211674] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.211765] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.228447] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.228501] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.228573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.229008] [drm:drm_mode_addfb2] [FB:79]
>[ 1361.229124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.245122] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.245170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.245257] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.262269] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.262305] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.262345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.262379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.262414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.262444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.262474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.262505] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.262540] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.262573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.262605] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.262637] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.262666] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.262768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.262854] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.262900] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.262944] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.262978] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.263097] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.263109] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.263166] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.263188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.263212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.263237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.263256] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.263279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.263300] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.263321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.263340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.263359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.263376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.263382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.263399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.263404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.263422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.263447] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.263473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.263500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.263526] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.263551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.263577] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.263602] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.263627] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.263654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.263682] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.263791] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.263820] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.263848] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.263902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.263933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.263962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.263994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.264024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.264056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.264090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.264124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.264156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.264186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.264216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.264251] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.264276] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.266423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.266444] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.266462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.266486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.268061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.268081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.268099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.269673] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.269705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.271574] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.274886] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.274959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.274998] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.275052] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.291760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.291811] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.291877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.292072] [drm:drm_mode_addfb2] [FB:77]
>[ 1361.292198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.308419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.308469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.308556] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.325541] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.325579] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.325619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.325652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.325688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.325803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.325847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.325899] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.325955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.326006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.326056] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.326109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.326150] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.326193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.326277] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.326336] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.326375] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.326406] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.326553] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.326565] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.326621] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.326642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.326664] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.326756] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.326789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.326824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.326858] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.326892] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.326925] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.326957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.326988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.326997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.327026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.327034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.327065] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.327095] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.327122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.327151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.327185] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.327215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.327241] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.327270] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.327299] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.327329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.327364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.327441] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.327472] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.327502] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.327554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.327585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.327616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.327646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.327676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.327728] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.327764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.327798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.327832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.327861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.327892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.327927] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.327959] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.330033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.330055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.330074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.330093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.331672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.331704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.331722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.333283] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.333304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.335224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.338530] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.338592] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.338611] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.338637] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.355387] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.355438] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.355504] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.355777] [drm:drm_mode_addfb2] [FB:78]
>[ 1361.355973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.372064] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.372112] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.372201] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.389213] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.389250] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.389290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.389324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.389359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.389390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.389419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.389451] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.389486] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.389519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.389559] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.389602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.389642] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.389684] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.389791] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.389835] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.389878] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.389911] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.390057] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.390076] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.390164] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.390198] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.390232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.390270] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.390300] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.390334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.390366] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.390397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.390429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.390459] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.390488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.390497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.390525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.390532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.390562] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.390591] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.390621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.390650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.390682] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.390736] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.390768] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.390798] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.390829] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.390864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.390899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.390987] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.391018] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.391049] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.391099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.391132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.391162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.391193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.391223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.391255] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.391289] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.391321] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.391354] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.391382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.391411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.391445] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.391476] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.393540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.393562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.393583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.393607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.395170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.395191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.395209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.396805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.396826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.398688] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.402003] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.402074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.402098] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.402129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.418870] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.418922] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.418988] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.419189] [drm:drm_mode_addfb2] [FB:79]
>[ 1361.419318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.435547] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.435595] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.435686] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.452780] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.452818] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.452857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.452891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.452926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.452956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.452985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.453017] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.453052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.453094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.453124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.453153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.453180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.453205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.453256] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.453295] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.453334] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.453363] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.453548] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.453567] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.453656] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.453777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.453833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.453890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.453937] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.453988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.454039] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.454088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.454147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.454197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.454244] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.454258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.454303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.454315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.454363] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.454410] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.454461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.454507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.454561] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.454607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.454654] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.454722] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.454768] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.454821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.454875] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.455022] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.455070] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.455124] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.455190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.455232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.455272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.455307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.455345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.455386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.455430] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.455473] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.455516] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.455554] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.455589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.455633] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.455674] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.457800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.457820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.457839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.457857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.459434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.459456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.459475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.461040] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.461061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.462931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.466284] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.466370] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.466396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.466430] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.483145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.483196] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.483262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.483457] [drm:drm_mode_addfb2] [FB:77]
>[ 1361.483588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.499861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.499910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.499999] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.516995] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.517033] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.517072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.517105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.517140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.517179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.517219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.517259] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.517304] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.517346] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.517389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.517431] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.517470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.517509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.517585] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.517623] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.517654] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.517740] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.517891] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.517910] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.518001] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.518031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.518064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.518100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.518128] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.518160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.518190] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.518220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.518249] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.518277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.518303] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.518310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.518337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.518343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.518373] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.518401] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.518428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.518453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.518484] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.518510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.518538] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.518563] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.518592] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.518621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.518654] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.518765] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.518796] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.518826] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.518877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.518908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.518936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.518965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.518991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.519023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.519055] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.519087] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.519119] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.519146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.519175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.519206] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.519235] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.521310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.521333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.521352] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.521371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.522940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.522960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.522978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.524529] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.524550] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.526418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.529771] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.529856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.529889] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.529933] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.546637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.546688] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.546976] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.547170] [drm:drm_mode_addfb2] [FB:78]
>[ 1361.547284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.563332] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.563381] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.563456] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.581836] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.581874] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.581913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.581947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.581982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.582013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.582042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.582075] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.582110] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.582143] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.582175] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.582216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.582255] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.582295] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.582352] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.582398] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.582448] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.582484] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.582650] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.582715] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.582865] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.582908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.582947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.582986] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.583019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.583053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.583088] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.583128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.583158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.583184] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.583210] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.583217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.583242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.583248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.583274] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.583298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.583324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.583348] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.583378] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.583402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.583429] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.583453] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.583478] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.583508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.583541] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.583614] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.583641] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.583666] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.583762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.583802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.583842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.583879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.583917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.583955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.583999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.584042] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.584084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.584130] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.584157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.584189] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.584218] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.586284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.586305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.586324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.586343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.587917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.587937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.587960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.589519] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.589540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.591414] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.594739] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.594795] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.594827] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.594869] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.611578] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.611630] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.611778] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.612084] [drm:drm_mode_addfb2] [FB:79]
>[ 1361.612212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.628255] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.628303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.628392] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.645402] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.645439] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.645483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.645525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.645569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.645610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.645650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.645767] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.645828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.645884] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.645935] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.645987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.646028] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.646072] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.646156] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.646220] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.646282] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.646331] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.646556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.646575] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.646674] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.646768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.646820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.646872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.646915] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.646962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.647008] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.647053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.647096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.647138] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.647179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.647190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.647230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.647240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.647281] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.647321] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.647362] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.647397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.647442] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.647483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.647525] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.647562] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.647602] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.647655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.647711] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.647789] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.647821] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.647852] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.647907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.647937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.647967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.647997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.648027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.648058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.648091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.648124] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.648156] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.648185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.648214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.648248] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.648279] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.650352] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.650374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.650393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.650413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.651988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.652008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.652025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.653573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.653593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.655454] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.658776] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.658843] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.658862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.658893] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.675616] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.675670] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.675840] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.676083] [drm:drm_mode_addfb2] [FB:77]
>[ 1361.676211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.692292] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.692340] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.692428] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.709445] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.709482] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.709522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.709556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.709591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.709622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.709652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.709765] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.709824] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.709879] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.709932] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.709984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.710032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.710071] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.710130] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.710158] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.710187] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.710207] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.710310] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.710322] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.710378] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.710399] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.710424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.710455] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.710480] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.710507] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.710533] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.710560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.710586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.710612] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.710637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.710643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.710676] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.710713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.710745] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.710774] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.710803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.710830] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.710861] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.710889] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.710917] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.710943] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.710971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.711002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.711035] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.711111] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.711142] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.711173] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.711226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.711259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.711290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.711320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.711350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.711381] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.711415] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.711442] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.711463] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.711488] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.711514] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.711542] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.711568] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.713616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.713639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.713662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.713742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.715302] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.715322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.715341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.716902] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.716923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.718796] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.722137] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.722231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.722264] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.722306] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.739009] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.739060] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.739129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.739328] [drm:drm_mode_addfb2] [FB:78]
>[ 1361.739463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.755761] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.755810] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.755900] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.772897] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.772934] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.772974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.773008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.773043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.773073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.773103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.773134] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.773169] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.773202] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.773234] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.773265] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.773293] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.773320] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.773374] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.773415] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.773456] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.773487] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.773697] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.773717] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.773817] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.773852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.773888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.773926] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.773957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.773990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.774023] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.774055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.774086] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.774116] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.774145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.774153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.774181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.774188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.774218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.774247] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.774276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.774305] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.774337] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.774367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.774397] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.774427] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.774457] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.774489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.774525] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.774596] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.774628] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.774658] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.774741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.774774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.774807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.774838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.774870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.774902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.774937] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.774971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.775004] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.775034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.775064] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.775100] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.775132] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.777204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.777225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.777247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.777271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.778856] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.778879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.778902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.780452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.780474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.782348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.785643] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.785731] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.785773] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.785799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.802500] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.802549] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.802613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.802961] [drm:drm_mode_addfb2] [FB:79]
>[ 1361.803093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.819188] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.819241] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.819333] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.836353] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.836391] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.836431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.836465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.836501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.836532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.836561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.836592] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.836627] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.836660] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.836773] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.836823] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.836868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.836896] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.836952] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.836998] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.837040] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.837069] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.837174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.837186] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.837243] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.837264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.837287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.837312] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.837331] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.837353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.837374] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.837394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.837419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.837445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.837471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.837477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.837502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.837507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.837533] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.837558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.837583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.837609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.837635] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.837667] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.837731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.837761] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.837790] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.837823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.837856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.837933] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.837964] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.837995] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.838048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.838081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.838113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.838144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.838175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.838198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.838220] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.838241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.838262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.838280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.838305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.838332] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.838358] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.840409] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.840430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.840448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.840467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.842032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.842052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.842070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.843657] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.843694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.845565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.848939] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.849001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.849041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.849081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.865776] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.865830] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.865901] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.866095] [drm:drm_mode_addfb2] [FB:77]
>[ 1361.866209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.882453] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.882501] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.882589] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.899562] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.899605] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.899650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.899771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.899830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.899878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.899923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.899968] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.900022] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.900073] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.900122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.900171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.900215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.900243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.900298] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.900340] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.900379] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.900411] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.900568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.900580] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.900638] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.900730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.900768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.900808] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.900842] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.900877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.900912] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.900947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.900978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.901010] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.901040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.901048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.901077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.901084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.901115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.901144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.901174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.901203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.901236] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.901265] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.901291] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.901320] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.901350] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.901384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.901419] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.901494] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.901525] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.901555] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.901607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.901638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.901690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.901720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.901751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.901783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.901818] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.901852] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.901885] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.901916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.901946] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.901981] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.902013] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.904087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.904108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.904127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.904146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.905771] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.905793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.905812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.907374] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.907395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.909268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.912532] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.912584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.912604] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.912630] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.929382] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.929434] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.929500] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.929785] [drm:drm_mode_addfb2] [FB:78]
>[ 1361.929952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.946038] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1361.946084] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1361.946154] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1361.964597] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1361.964635] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1361.964761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.964816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.964873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.964924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.964973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.965018] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.965056] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.965090] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.965122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.965154] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.965182] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.965211] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.965264] [drm:intel_power_well_disable [i915]] disabling display
>[ 1361.965306] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1361.965348] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.965380] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1361.965530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1361.965558] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1361.965613] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1361.965640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1361.965710] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1361.965745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1361.965774] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1361.965804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1361.965834] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1361.965863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1361.965891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1361.965919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1361.965945] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1361.965954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.965980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1361.965987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1361.966014] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1361.966040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1361.966067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1361.966092] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1361.966122] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1361.966149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1361.966179] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1361.966207] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1361.966233] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1361.966263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1361.966298] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1361.966375] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1361.966407] [drm:intel_power_well_enable [i915]] enabling display
>[ 1361.966438] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1361.966491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1361.966523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1361.966554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1361.966584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1361.966603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1361.966623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1361.966646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1361.966700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1361.966731] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.966757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1361.966784] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1361.966816] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1361.966844] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1361.968911] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1361.968932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1361.968950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.968969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1361.970540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1361.970561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1361.970579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1361.972142] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1361.972163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1361.974056] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1361.977397] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1361.977494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1361.977534] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1361.977586] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1361.994269] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1361.994322] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1361.994394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1361.994590] [drm:drm_mode_addfb2] [FB:79]
>[ 1361.994820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.010947] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.010999] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.011075] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.028092] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.028129] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.028168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.028203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.028237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.028272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.028312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.028352] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.028397] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.028440] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.028482] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.028524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.028563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.028602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.028735] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.028803] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.028874] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.028927] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.029096] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.029115] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.029203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.029235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.029266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.029302] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.029330] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.029362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.029392] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.029422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.029451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.029479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.029505] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.029513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.029539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.029546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.029575] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.029602] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.029630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.029680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.029713] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.029741] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.029771] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.029798] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.029829] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.029863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.029898] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.029987] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.030018] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.030047] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.030098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.030130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.030158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.030187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.030215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.030245] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.030278] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.030310] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.030341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.030367] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.030395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.030425] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.030455] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.032530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.032552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.032572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.032591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.034185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.034206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.034224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.035864] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.035887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.037775] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.041117] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.041210] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.041243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.041284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.057982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.058032] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.058096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.058295] [drm:drm_mode_addfb2] [FB:77]
>[ 1362.058420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.074723] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.074774] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.074845] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.091849] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.091887] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.091927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.091961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.091997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.092027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.092057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.092089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.092124] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.092166] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.092209] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.092251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.092291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.092330] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.092387] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.092437] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.092466] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.092485] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.092607] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.092621] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.092757] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.092789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.092814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.092840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.092860] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.092882] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.092904] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.092925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.092945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.092964] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.092982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.092987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.093005] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.093009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.093028] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.093046] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.093065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.093082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.093105] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.093122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.093141] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.093158] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.093176] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.093197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.093221] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.093272] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.093291] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.093309] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.093343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.093364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.093382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.093407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.093433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.093459] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.093487] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.093515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.093542] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.093568] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.093593] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.093621] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.093647] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.095755] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.095778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.095797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.095816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.097389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.097410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.097432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.098997] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.099018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.100888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.104202] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.104269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.104301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.104343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.121050] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.121102] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.121170] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.121368] [drm:drm_mode_addfb2] [FB:78]
>[ 1362.121499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.137768] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.137817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.137889] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.154881] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.154919] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.154958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.154991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.155026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.155057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.155087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.155119] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.155154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.155187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.155219] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.155251] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.155279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.155306] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.155360] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.155401] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.155442] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.155473] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.155717] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.155749] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.155892] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.155934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.155982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.156020] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.156048] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.156080] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.156111] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.156141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.156169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.156197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.156222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.156230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.156255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.156260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.156288] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.156313] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.156339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.156362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.156392] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.156418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.156443] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.156468] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.156492] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.156521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.156559] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.156635] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.156708] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.156748] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.156820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.156863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.156901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.156939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.156984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.157017] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.157054] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.157091] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.157126] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.157157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.157189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.157220] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.157245] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.159305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.159326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.159344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.159363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.160949] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.160974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.160997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.162558] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.162580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.164445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.167302] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.167360] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.167383] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.167415] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.184161] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.184214] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.184283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.184487] [drm:drm_mode_addfb2] [FB:79]
>[ 1362.184618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.200854] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.200902] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.200976] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.217986] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.218023] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.218063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.218097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.218132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.218162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.218192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.218223] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.218259] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.218291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.218323] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.218363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.218388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.218412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.218459] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.218496] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.218533] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.218560] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.218729] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.218754] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.218903] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.218951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.219000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.219054] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.219096] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.219143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.219184] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.219213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.219241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.219268] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.219293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.219300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.219325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.219331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.219358] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.219388] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.219407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.219424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.219447] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.219464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.219490] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.219516] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.219543] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.219570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.219599] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.219702] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.219730] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.219759] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.219814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.219845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.219875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.219906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.219935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.219967] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.220001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.220033] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.220067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.220096] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.220125] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.220153] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.220174] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.222238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.222259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.222278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.222297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.223875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.223896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.223915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.225473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.225494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.227366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.230710] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.230794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.230822] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.230865] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.247577] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.247628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.247791] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.248061] [drm:drm_mode_addfb2] [FB:77]
>[ 1362.248180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.264254] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.264302] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.264392] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.283361] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.283397] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.283437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.283470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.283506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.283536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.283566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.283597] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.283632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.283745] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.283798] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.283843] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.283871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.283900] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.283956] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.283997] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.284037] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.284069] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.284202] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.284223] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.284321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.284353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.284385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.284420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.284449] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.284480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.284511] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.284540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.284570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.284598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.284625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.284686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.284717] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.284726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.284757] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.284788] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.284819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.284849] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.284882] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.284912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.284943] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.284971] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.285001] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.285035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.285071] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.285145] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.285177] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.285208] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.285259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.285291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.285321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.285352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.285381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.285412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.285446] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.285479] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.285512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.285541] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.285572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.285605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.285637] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.287733] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.287754] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.287773] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.287792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.289367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.289392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.289415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.290971] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.290993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.292864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.296111] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.296183] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.296207] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.296238] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.312962] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.313013] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.313080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.313276] [drm:drm_mode_addfb2] [FB:78]
>[ 1362.313405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.329722] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.329771] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.329860] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.346855] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.346893] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.346933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.346967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.347003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.347034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.347064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.347096] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.347131] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.347164] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.347205] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.347234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.347261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.347287] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.347337] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.347376] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.347418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.347453] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.347624] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.347701] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.347843] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.347893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.347945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.348000] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.348046] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.348095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.348143] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.348190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.348240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.348279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.348318] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.348328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.348364] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.348374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.348412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.348452] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.348490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.348528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.348570] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.348607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.348646] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.348722] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.348762] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.348808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.348855] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.348980] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.349021] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.349061] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.349129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.349171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.349220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.349253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.349286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.349320] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.349357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.349394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.349429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.349462] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.349493] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.349530] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.349564] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.351673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.351695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.351714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.351733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.353306] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.353326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.353345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.354896] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.354916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.356788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.360136] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.360223] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.360256] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.360298] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.377001] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.377053] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.377120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.377316] [drm:drm_mode_addfb2] [FB:79]
>[ 1362.377443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.393716] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.393764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.393853] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.410844] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.410882] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.410922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.410955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.410991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.411021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.411050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.411082] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.411117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.411149] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.411181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.411212] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.411241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.411268] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.411321] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.411362] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.411403] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.411434] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.411614] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.411696] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.411841] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.411892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.411944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.411999] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.412045] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.412094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.412143] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.412189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.412237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.412281] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.412324] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.412336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.412377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.412388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.412432] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.412475] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.412518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.412561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.412609] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.412652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.412731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.412768] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.412804] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.412846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.412888] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.413000] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.413037] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.413074] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.413136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.413174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.413211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.413248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.413283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.413321] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.413358] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.413397] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.413437] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.413472] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.413508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.413548] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.413586] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.415704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.415725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.415743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.415763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.417336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.417359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.417378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.418941] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.418963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.420838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.424095] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.424156] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.424176] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.424202] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.440950] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.441002] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.441069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.441265] [drm:drm_mode_addfb2] [FB:77]
>[ 1362.441394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.457625] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.457719] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.457809] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.474806] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.474843] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.474883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.474924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.474968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.475009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.475049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.475088] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.475133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.475176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.475218] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.475267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.475296] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.475322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.475368] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.475403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.475440] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.475467] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.475664] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.475692] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.475818] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.475864] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.475910] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.475959] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.475999] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.476043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.476087] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.476129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.476170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.476210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.476248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.476258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.476302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.476310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.476345] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.476381] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.476416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.476450] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.476489] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.476523] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.476558] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.476593] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.476628] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.476707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.476748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.476862] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.476899] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.476935] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.476998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.477036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.477073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.477109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.477141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.477178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.477219] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.477258] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.477303] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.477333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.477362] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.477396] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.477427] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.479502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.479523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.479542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.479560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.481166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.481188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.481208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.482799] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.482822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.484690] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.488031] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.488125] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.488158] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.488201] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.504889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.504941] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.505007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.505186] [drm:drm_mode_addfb2] [FB:78]
>[ 1362.505322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.521576] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.521627] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.521795] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.540584] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.540622] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.540750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.540805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.540863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.540907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.540953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.540998] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.541052] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.541103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.541152] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.541201] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.541241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.541284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.541367] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.541431] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.541492] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.541543] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.541780] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.541792] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.541850] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.541872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.541895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.541920] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.541945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.541971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.541997] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.542022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.542048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.542071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.542096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.542101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.542125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.542130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.542156] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.542181] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.542207] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.542231] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.542257] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.542282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.542307] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.542332] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.542358] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.542384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.542411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.542463] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.542485] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.542506] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.542545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.542571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.542597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.542622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.542680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.542714] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.542750] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.542785] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.542818] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.542846] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.542876] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.542912] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.542941] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.545006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.545027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.545046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.545065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.546628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.546665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.546683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.548245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.548269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.550170] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.553496] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.553554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.553587] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.553629] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.570333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.570387] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.570459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.570728] [drm:drm_mode_addfb2] [FB:79]
>[ 1362.570902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.587049] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.587097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.587170] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.605558] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.605596] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.605635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.605751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.605808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.605858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.605905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.605955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.606014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.606051] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.606085] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.606117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.606146] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.606173] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.606230] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.606258] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.606286] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.606306] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.606402] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.606414] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.606469] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.606495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.606521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.606550] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.606575] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.606602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.606634] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.606691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.606721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.606750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.606776] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.606785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.606811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.606818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.606846] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.606873] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.606900] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.606926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.606957] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.606983] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.607010] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.607036] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.607063] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.607094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.607129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.607207] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.607238] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.607269] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.607321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.607354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.607386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.607416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.607446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.607477] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.607503] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.607525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.607545] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.607564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.607582] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.607605] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.607631] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.609716] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.609737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.609755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.609774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.611343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.611363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.611381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.612942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.612963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.614831] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.618173] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.618269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.618309] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.618361] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.635045] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.635096] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.635162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.635343] [drm:drm_mode_addfb2] [FB:77]
>[ 1362.635475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.651720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.651771] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.651848] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.668846] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.668884] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.668923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.668957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.668992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.669031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.669071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.669111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.669156] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.669198] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.669240] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.669282] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.669322] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.669361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.669418] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.669465] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.669515] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.669551] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.669782] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.669800] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.669889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.669920] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.669955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.669991] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.670019] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.670051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.670081] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.670112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.670139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.670167] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.670193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.670200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.670227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.670234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.670262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.670288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.670316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.670341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.670372] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.670397] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.670425] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.670451] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.670479] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.670508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.670540] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.670616] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.670674] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.670705] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.670756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.670789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.670819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.670849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.670876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.670907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.670942] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.670974] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.671009] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.671036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.671065] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.671098] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.671131] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.673223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.673244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.673263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.673282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.674873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.674895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.674914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.676476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.676498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.678371] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.681698] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.681752] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.681785] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.681827] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.698534] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.698586] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.698728] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.698964] [drm:drm_mode_addfb2] [FB:78]
>[ 1362.699090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.715212] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.715261] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.715333] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.732297] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.732335] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.732375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.732409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.732445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.732476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.732506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.732537] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.732572] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.732605] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.732718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.732771] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.732815] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.732861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.732947] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.733011] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.733073] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.733122] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.733356] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.733377] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.733475] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.733506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.733539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.733574] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.733604] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.733691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.733726] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.733760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.733793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.733826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.733855] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.733864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.733894] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.733901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.733931] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.733960] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.733989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.734016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.734048] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.734076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.734106] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.734136] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.734166] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.734199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.734233] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.734309] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.734340] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.734370] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.734421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.734453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.734483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.734514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.734543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.734574] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.734608] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.734663] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.734699] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.734729] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.734760] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.734795] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.734827] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.736899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.736920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.736942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.736966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.738544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.738566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.738585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.740202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.740224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.742098] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.745426] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.745485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.745525] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.745577] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.762245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.762297] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.762364] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.762557] [drm:drm_mode_addfb2] [FB:79]
>[ 1362.762787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.778976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.779024] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.779096] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.797561] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.797599] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.797724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.797778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.797835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.797885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.797933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.797964] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.797997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.798026] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.798055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.798092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.798128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.798164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.798216] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.798259] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.798304] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.798338] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.798479] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.798495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.798575] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.798610] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.798699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.798749] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.798789] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.798832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.798873] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.798915] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.798960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.798992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.799022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.799031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.799061] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.799070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.799101] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.799130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.799160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.799189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.799224] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.799253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.799286] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.799318] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.799348] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.799382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.799422] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.799509] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.799544] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.799579] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.799667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.799705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.799740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.799774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.799808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.799842] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.799877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.799913] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.799957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.799987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.800016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.800050] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.800077] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.802122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.802143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.802161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.802180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.803745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.803765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.803783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.805347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.805377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.807256] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.810581] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.810713] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.810762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.810829] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.827419] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.827470] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.827537] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.827900] [drm:drm_mode_addfb2] [FB:77]
>[ 1362.828031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.844135] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.844184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.844255] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.862559] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.862597] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.862717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.862765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.862821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.862865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.862910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.862955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.863009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.863060] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.863110] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.863158] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.863199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.863241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.863324] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.863392] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.863429] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.863458] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.863637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.863658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.863755] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.863789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.863824] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.863869] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.863898] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.863929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.863960] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.863989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.864018] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.864046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.864073] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.864080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.864106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.864113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.864140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.864167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.864194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.864218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.864247] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.864274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.864299] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.864325] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.864349] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.864379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.864411] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.864486] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.864515] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.864543] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.864591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.864631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.864694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.864726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.864758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.864790] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.864826] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.864859] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.864892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.864922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.864953] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.864989] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.865021] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.867103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.867127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.867149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.867173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.868779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.868801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.868820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.870367] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.870391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.872255] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.875561] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.875666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.875701] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.875732] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.892398] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.892447] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.892511] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.892800] [drm:drm_mode_addfb2] [FB:78]
>[ 1362.892955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.909153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.909204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.909295] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.926267] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.926305] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.926345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.926379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.926415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.926454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.926495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.926535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.926580] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.926623] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.926730] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.926775] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.926812] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.926849] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.926925] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.926985] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.927042] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.927087] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.927247] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.927264] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.927339] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.927368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.927399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.927432] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.927459] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.927488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.927516] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.927543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.927576] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.927615] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.927704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.927713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.927744] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.927753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.927784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.927813] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.927842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.927872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.927905] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.927934] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.927966] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.927997] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.928026] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.928061] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.928100] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.928186] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.928220] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.928254] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.928313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.928340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.928361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.928382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.928402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.928425] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.928449] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.928471] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.928492] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.928512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.928531] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.928556] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.928578] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.930675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.930695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.930714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.930733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.932303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.932323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.932345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.933911] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.933932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.935803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1362.939061] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1362.939121] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1362.939140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1362.939166] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1362.955915] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.955967] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.956034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.956214] [drm:drm_mode_addfb2] [FB:79]
>[ 1362.956333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.972629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1362.972709] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1362.972800] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1362.989794] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1362.989831] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1362.989871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.989904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.989947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.989988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.990028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.990067] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1362.990120] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.990155] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.990186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.990216] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.990242] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.990269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.990319] [drm:intel_power_well_disable [i915]] disabling display
>[ 1362.990357] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1362.990397] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1362.990427] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1362.990595] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1362.990672] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1362.990815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1362.990865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1362.990917] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1362.990973] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1362.991018] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1362.991068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1362.991124] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1362.991166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1362.991208] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1362.991247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1362.991285] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1362.991295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.991332] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1362.991341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1362.991380] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1362.991418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1362.991457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1362.991494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1362.991537] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1362.991575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1362.991614] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1362.991689] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1362.991731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1362.991776] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1362.991823] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1362.991924] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1362.991964] [drm:intel_power_well_enable [i915]] enabling display
>[ 1362.992005] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1362.992076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1362.992117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1362.992160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1362.992193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1362.992225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1362.992256] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1362.992292] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1362.992328] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1362.992363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1362.992395] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1362.992426] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1362.992464] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1362.992498] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1362.994577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1362.994597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1362.994667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.994702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1362.996284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1362.996306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1362.996329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1362.997884] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1362.997908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1362.999784] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.003105] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.003165] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.003197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.003239] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.019944] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.019996] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.020063] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.020301] [drm:drm_mode_addfb2] [FB:77]
>[ 1363.020439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.036692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.036744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.036837] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.053832] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.053870] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.053910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.053944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.053980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.054019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.054059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.054099] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.054144] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.054187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.054229] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.054271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.054310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.054349] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.054406] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.054453] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.054503] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.054539] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.054743] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.054762] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.054854] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.054888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.054923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.054950] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.054970] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.054992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.055015] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.055035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.055055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.055074] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.055093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.055098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.055115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.055120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.055139] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.055157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.055175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.055193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.055215] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.055239] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.055266] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.055292] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.055318] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.055345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.055373] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.055435] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.055457] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.055479] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.055519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.055545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.055571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.055597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.055652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.055684] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.055717] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.055749] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.055780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.055807] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.055834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.055867] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.055896] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.057962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.057984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.058003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.058022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.059598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.059629] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.059647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.061206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.061228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.063096] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.066433] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.066530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.066562] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.066603] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.083306] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.083355] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.083418] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.083691] [drm:drm_mode_addfb2] [FB:78]
>[ 1363.083891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.099991] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.100038] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.100109] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.117152] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.117189] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.117229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.117264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.117299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.117338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.117378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.117418] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.117462] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.117505] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.117547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.117589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.117701] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.117752] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.117838] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.117902] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.117967] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.118016] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.118185] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.118203] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.118290] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.118320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.118353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.118389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.118417] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.118448] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.118479] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.118510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.118537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.118565] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.118591] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.118624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.118652] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.118660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.118691] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.118718] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.118747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.118773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.118805] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.118832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.118861] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.118887] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.118918] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.118952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.118987] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.119062] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.119092] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.119121] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.119171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.119201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.119228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.119256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.119282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.119311] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.119343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.119374] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.119406] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.119432] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.119459] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.119489] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.119519] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.121590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.121630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.121648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.121667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.123238] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.123260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.123279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.124839] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.124860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.126742] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.130077] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.130178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.130210] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.130259] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.146956] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.147007] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.147073] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.147271] [drm:drm_mode_addfb2] [FB:79]
>[ 1363.147400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.163676] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.163722] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.163791] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.180782] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.180819] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.180859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.180894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.180930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.180961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.180991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.181023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.181058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.181091] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.181122] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.181162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.181202] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.181241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.181299] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.181345] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.181395] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.181431] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.181577] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.181633] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.181732] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.181767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.181802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.181840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.181871] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.181905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.181938] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.181970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.182004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.182034] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.182064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.182071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.182100] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.182107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.182136] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.182167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.182197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.182226] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.182259] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.182288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.182318] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.182347] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.182377] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.182410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.182445] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.182524] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.182555] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.182585] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.182666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.182699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.182732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.182763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.182796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.182828] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.182864] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.182897] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.182931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.182961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.182992] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.183027] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.183059] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.185129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.185150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.185168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.185187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.186765] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.186787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.186805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.188355] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.188376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.190240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.193536] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.193698] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.193743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.193789] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.210399] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.210451] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.210518] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.210820] [drm:drm_mode_addfb2] [FB:77]
>[ 1363.210962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.227100] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.227150] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.227224] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.245545] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.245583] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.245716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.245772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.245828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.245878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.245926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.245982] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.246030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.246074] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.246118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.246161] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.246199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.246238] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.246309] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.246365] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.246418] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.246460] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.246665] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.246690] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.246812] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.246843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.246875] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.246908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.246934] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.246972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.246998] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.247022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.247046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.247069] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.247090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.247095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.247117] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.247122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.247144] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.247165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.247186] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.247215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.247246] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.247276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.247306] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.247336] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.247366] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.247398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.247431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.247494] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.247520] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.247546] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.247592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.247668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.247706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.247742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.247775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.247811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.247849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.247886] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.247922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.247954] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.247993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.248025] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.248054] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.250135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.250157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.250176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.250195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.251782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.251805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.251824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.253377] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.253398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.255284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.258610] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.258722] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.258762] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.258814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.275496] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.275550] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.275693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.275942] [drm:drm_mode_addfb2] [FB:78]
>[ 1363.276062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.292187] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.292231] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.292299] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.310543] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.310580] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.310705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.310747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.310794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.310835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.310877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.310917] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.310963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.311007] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.311051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.311095] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.311135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.311176] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.311236] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.311282] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.311333] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.311369] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.311498] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.311516] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.311594] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.311659] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.311694] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.311730] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.311759] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.311790] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.311820] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.311849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.311878] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.311906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.311932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.311941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.311969] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.311976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.312006] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.312033] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.312060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.312089] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.312121] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.312150] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.312180] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.312210] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.312238] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.312271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.312305] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.312375] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.312394] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.312412] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.312446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.312466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.312485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.312504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.312522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.312547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.312575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.312628] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.312661] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.312688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.312716] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.312748] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.312777] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.314847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.314869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.314887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.314906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.316465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.316488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.316511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.318076] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.318097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.320010] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.323351] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.323445] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.323478] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.323520] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.340224] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.340275] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.340341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.340540] [drm:drm_mode_addfb2] [FB:79]
>[ 1363.340781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.356940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.356988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.357061] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.375540] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.375578] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.375704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.375758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.375817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.375868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.375908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.375942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.375980] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.376014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.376055] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.376100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.376129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.376157] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.376212] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.376260] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.376310] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.376347] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.376502] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.376520] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.376624] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.376723] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.376775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.376831] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.376870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.376901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.376932] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.376963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.376993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.377021] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.377051] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.377058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.377087] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.377094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.377123] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.377153] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.377183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.377211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.377244] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.377265] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.377283] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.377302] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.377319] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.377340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.377364] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.377415] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.377433] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.377452] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.377486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.377506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.377525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.377543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.377562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.377581] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.377632] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.377664] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.377694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.377720] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.377746] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.377778] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.377807] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.379878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.379899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.379921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.379945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.381515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.381535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.381554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.383132] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.383153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.385021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.388314] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.388399] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.388427] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.388462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.405192] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.405262] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.405361] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.405575] [drm:drm_mode_addfb2] [FB:77]
>[ 1363.405905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.421905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.421954] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.422027] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.440536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.440574] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.440709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.440764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.440822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.440870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.440919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.440969] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.441028] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.441081] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.441133] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.441190] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.441220] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.441249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.441304] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.441348] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.441388] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.441420] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.441575] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.441616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.441708] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.441732] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.441756] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.441784] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.441809] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.441835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.441868] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.441888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.441907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.441929] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.441952] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.441957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.441980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.441984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.442007] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.442031] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.442054] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.442076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.442100] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.442123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.442147] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.442170] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.442193] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.442218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.442243] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.442294] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.442314] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.442334] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.442371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.442394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.442418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.442441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.442465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.442488] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.442514] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.442539] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.442564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.442587] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.442656] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.442696] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.442726] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.444817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.444841] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.444864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.444888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.446460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.446481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.446500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.448063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.448084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.449954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.453304] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.453390] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.453430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.453465] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.470168] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.470220] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.470292] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.470478] [drm:drm_mode_addfb2] [FB:78]
>[ 1363.470706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.486844] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.486892] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.486964] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.503990] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.504027] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.504067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.504101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.504136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.504166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.504195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.504227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.504262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.504294] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.504326] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.504356] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.504384] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.504412] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.504464] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.504505] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.504547] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.504578] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.504808] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.504826] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.504913] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.504946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.504981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.505018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.505048] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.505081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.505114] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.505146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.505177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.505207] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.505236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.505243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.505272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.505279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.505308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.505337] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.505366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.505395] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.505427] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.505456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.505487] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.505516] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.505546] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.505579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.505639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.505715] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.505747] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.505778] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.505829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.505863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.505894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.505924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.505953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.505986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.506019] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.506052] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.506084] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.506113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.506142] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.506177] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.506208] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.508277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.508301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.508324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.508348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.509924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.509945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.509964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.511509] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.511530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.513401] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.516753] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.516836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.516869] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.516910] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.533648] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.533699] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.533766] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.533966] [drm:drm_mode_addfb2] [FB:79]
>[ 1363.534097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.550291] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.550339] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.550411] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.567432] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.567470] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.567510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.567544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.567579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.567700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.567751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.567803] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.567862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.567914] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.567965] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.568016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.568061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.568106] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.568187] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.568229] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.568270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.568303] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.568443] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.568455] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.568511] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.568532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.568554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.568587] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.568645] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.568683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.568714] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.568746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.568776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.568805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.568832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.568841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.568870] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.568878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.568908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.568935] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.568966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.568992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.569025] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.569052] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.569081] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.569107] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.569135] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.569170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.569206] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.569281] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.569311] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.569340] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.569390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.569421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.569448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.569478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.569504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.569534] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.569566] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.569618] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.569651] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.569680] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.569709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.569744] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.569774] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.571844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.571864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.571883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.571901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.573465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.573485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.573503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.575068] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.575089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.577004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.580360] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.580422] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.580441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.580467] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.597213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.597261] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.597325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.597527] [drm:drm_mode_addfb2] [FB:77]
>[ 1363.597740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.613923] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.613976] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.614071] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.631129] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.631167] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.631207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.631241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.631276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.631306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.631335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.631366] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.631401] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.631434] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.631472] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.631499] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.631524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.631549] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.631667] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.631730] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.631788] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.631835] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.632017] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.632043] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.632134] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.632164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.632200] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.632242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.632277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.632314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.632350] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.632383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.632419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.632463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.632489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.632496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.632519] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.632524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.632547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.632576] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.632634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.632665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.632702] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.632733] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.632765] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.632795] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.632826] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.632861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.632899] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.633003] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.633038] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.633073] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.633134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.633172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.633204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.633227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.633255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.633285] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.633318] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.633350] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.633382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.633411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.633440] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.633471] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.633504] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.635547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.635568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.635644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.635678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.637242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.637261] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.637279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.638836] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.638856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.640732] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.644028] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.644111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.644140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.644178] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.660885] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.660935] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.661001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.661190] [drm:drm_mode_addfb2] [FB:78]
>[ 1363.661314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.677596] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.677674] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.677767] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.694781] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.694818] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.694857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.694892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.694926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.694956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.694985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.695015] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.695050] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.695082] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.695113] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.695144] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.695171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.695198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.695251] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.695293] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.695334] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.695364] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.695557] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.695658] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.695806] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.695866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.695916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.695969] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.696009] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.696056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.696100] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.696144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.696185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.696227] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.696265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.696276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.696315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.696325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.696367] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.696408] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.696448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.696485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.696530] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.696568] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.696646] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.696686] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.696731] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.696777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.696827] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.696931] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.696965] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.697000] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.697060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.697096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.697129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.697164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.697195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.697231] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.697270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.697309] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.697346] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.697377] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.697410] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.697450] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.697484] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.699562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.699602] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.699621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.699640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.701215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.701235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.701253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.702817] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.702838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.704698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.708050] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.708117] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.708137] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.708163] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.724891] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.724937] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.725001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.725199] [drm:drm_mode_addfb2] [FB:79]
>[ 1363.725324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.741589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.741691] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.741760] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.758753] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.758790] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.758829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.758863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.758906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.758946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.758986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.759026] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.759071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.759114] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.759156] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.759205] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.759234] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.759261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.759306] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.759340] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.759378] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.759404] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.759558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.759615] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.759742] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.759787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.759834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.759883] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.759924] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.759968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.760011] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.760053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.760095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.760135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.760173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.760183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.760229] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.760237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.760272] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.760308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.760342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.760376] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.760416] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.760450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.760484] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.760519] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.760553] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.760592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.760665] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.760757] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.760795] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.760831] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.760893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.760931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.760967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.761000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.761034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.761071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.761112] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.761150] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.761189] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.761231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.761261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.761296] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.761327] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.763417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.763439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.763458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.763477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.765056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.765077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.765095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.766687] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.766708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.768572] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.771937] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.772022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.772055] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.772097] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.788801] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.788854] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.788926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.789124] [drm:drm_mode_addfb2] [FB:77]
>[ 1363.789254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.805487] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.805544] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.805700] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.822694] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.822732] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.822772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.822806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.822842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.822873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.822903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.822935] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.822971] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.823004] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.823035] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.823066] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.823094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.823122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.823176] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.823217] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.823259] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.823290] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.823486] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.823505] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.823693] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.823750] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.823808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.823870] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.823920] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.823976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.824029] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.824081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.824132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.824181] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.824226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.824240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.824284] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.824295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.824341] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.824385] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.824431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.824477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.824528] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.824577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.824631] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.824661] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.824689] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.824724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.824760] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.824839] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.824871] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.824901] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.824953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.824985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.825016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.825046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.825073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.825103] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.825138] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.825171] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.825203] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.825232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.825261] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.825293] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.825325] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.827417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.827440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.827459] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.827482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.829058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.829079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.829098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.830691] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.830712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.832573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.835893] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.835956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.835975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.836001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.852751] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.852803] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.852869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.853093] [drm:drm_mode_addfb2] [FB:78]
>[ 1363.853237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.869465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.869514] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.869586] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.886682] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.886721] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.886764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.886806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.886850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.886890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.886930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.886977] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.887015] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.887048] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.887078] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.887107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.887134] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.887160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.887210] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.887248] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.887289] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.887318] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.887504] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.887522] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.887701] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.887748] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.887802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.887858] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.887902] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.887952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.887997] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.888046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.888088] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.888132] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.888171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.888185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.888224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.888234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.888276] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.888314] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.888355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.888393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.888439] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.888477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.888519] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.888556] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.888637] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.888681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.888732] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.888841] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.888886] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.888929] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.889004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.889035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.889063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.889091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.889118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.889147] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.889180] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.889212] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.889243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.889270] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.889297] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.889328] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.889359] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.891436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.891458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.891477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.891497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.893058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.893078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.893096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.894669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.894690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.896562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.899923] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.900007] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.900040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.900082] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.916787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.916839] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.916906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.917105] [drm:drm_mode_addfb2] [FB:79]
>[ 1363.917221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.933502] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.933551] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.933721] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1363.952527] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1363.952564] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1363.952696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.952749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.952807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.952856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.952905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.952957] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.953014] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.953067] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.953118] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.953169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.953215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.953260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.953337] [drm:intel_power_well_disable [i915]] disabling display
>[ 1363.953380] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1363.953429] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.953459] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1363.953623] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1363.953643] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1363.953734] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1363.953757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1363.953781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1363.953813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1363.953831] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1363.953851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1363.953871] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1363.953890] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1363.953913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1363.953935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1363.953958] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1363.953962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.953985] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1363.953989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1363.954013] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1363.954036] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1363.954060] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1363.954082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1363.954106] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1363.954129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1363.954152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1363.954175] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1363.954199] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1363.954223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.954248] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1363.954299] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1363.954320] [drm:intel_power_well_enable [i915]] enabling display
>[ 1363.954339] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1363.954376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1363.954400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1363.954424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1363.954447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1363.954470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1363.954493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1363.954519] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1363.954544] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1363.954569] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.954638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1363.954674] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1363.954707] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1363.954739] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1363.956827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1363.956849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1363.956869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.956888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1363.958448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1363.958469] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1363.958487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1363.960051] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1363.960071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1363.961985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1363.965337] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1363.965420] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1363.965453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1363.965495] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1363.982201] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1363.982252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1363.982318] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1363.982516] [drm:drm_mode_addfb2] [FB:77]
>[ 1363.982735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1363.998914] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1363.998965] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1363.999041] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.016023] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.016061] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.016101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.016135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.016178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.016219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.016259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.016299] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.016343] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.016386] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.016429] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.016471] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.016510] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.016550] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.016705] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.016774] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.016848] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.016890] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.017068] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.017091] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.017203] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.017244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.017288] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.017335] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.017375] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.017416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.017458] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.017498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.017539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.017576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.017642] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.017654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.017691] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.017701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.017740] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.017780] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.017819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.017862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.017896] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.017926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.017954] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.017985] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.018016] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.018051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.018086] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.018178] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.018209] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.018240] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.018291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.018323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.018355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.018386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.018417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.018448] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.018482] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.018515] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.018547] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.018602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.018633] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.018669] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.018701] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.020764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.020785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.020803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.020822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.022390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.022410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.022428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.023981] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.024001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.025871] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.029153] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.029186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.029205] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.029230] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.045983] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.046037] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.046109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.046312] [drm:drm_mode_addfb2] [FB:78]
>[ 1364.046446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.062698] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.062746] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.062819] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.079810] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.079848] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.079892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.079933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.079977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.080018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.080057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.080097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.080142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.080185] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.080227] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.080269] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.080308] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.080344] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.080377] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.080403] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.080431] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.080450] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.080604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.080624] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.080722] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.080754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.080788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.080824] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.080852] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.080884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.080914] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.080944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.080972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.081001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.081027] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.081034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.081060] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.081067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.081096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.081123] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.081151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.081176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.081207] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.081233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.081261] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.081286] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.081314] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.081343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.081376] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.081455] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.081485] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.081515] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.081565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.081621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.081650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.081681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.081708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.081739] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.081774] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.081807] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.081841] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.081869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.081898] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.081933] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.081962] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.084059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.084081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.084100] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.084119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.085686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.085707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.085725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.087282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.087306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.089179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.092473] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.092562] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.092641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.092690] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.109343] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.109395] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.109461] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.109852] [drm:drm_mode_addfb2] [FB:79]
>[ 1364.109978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.126058] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.126107] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.126181] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.143193] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.143236] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.143280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.143322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.143366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.143406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.143446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.143486] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.143531] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.143573] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.143700] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.143769] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.143801] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.143833] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.143889] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.143932] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.143973] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.144006] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.144159] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.144179] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.144281] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.144311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.144342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.144377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.144403] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.144433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.144461] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.144490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.144516] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.144542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.144619] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.144628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.144657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.144665] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.144696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.144723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.144754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.144780] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.144813] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.144840] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.144871] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.144898] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.144927] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.144961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.144996] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.145075] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.145105] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.145136] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.145187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.145218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.145244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.145273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.145299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.145329] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.145362] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.145394] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.145425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.145451] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.145479] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.145509] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.145539] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.147630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.147651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.147669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.147688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.149263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.149283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.149301] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.150859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.150879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.152775] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.156098] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.156142] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.156161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.156187] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.172937] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.172989] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.173056] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.173237] [drm:drm_mode_addfb2] [FB:77]
>[ 1364.173375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.189615] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.189664] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.189737] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.208274] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.208313] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.208353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.208387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.208423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.208453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.208483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.208515] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.208551] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.208677] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.208732] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.208787] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.208835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.208884] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.208969] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.209035] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.209098] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.209156] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.209312] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.209332] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.209427] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.209456] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.209488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.209523] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.209559] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.209628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.209660] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.209692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.209721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.209751] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.209778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.209788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.209816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.209824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.209854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.209881] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.209911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.209941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.209974] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.210003] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.210033] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.210062] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.210091] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.210124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.210159] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.210258] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.210288] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.210318] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.210369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.210397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.210427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.210454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.210482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.210510] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.210542] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.210598] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.210630] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.210657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.210686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.210721] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.210751] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.212822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.212843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.212861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.212880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.214456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.214478] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.214497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.216088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.216109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.218015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.221360] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.221434] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.221453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.221480] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.238206] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.238252] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.238315] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.238494] [drm:drm_mode_addfb2] [FB:78]
>[ 1364.238749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.254943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.254992] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.255065] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.272090] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.272128] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.272167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.272201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.272236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.272266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.272296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.272327] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.272369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.272412] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.272455] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.272497] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.272536] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.272636] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.272692] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.272735] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.272778] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.272811] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.272947] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.272967] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.273064] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.273095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.273130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.273166] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.273195] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.273227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.273256] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.273286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.273314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.273343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.273368] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.273376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.273402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.273409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.273438] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.273463] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.273492] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.273517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.273548] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.273595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.273625] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.273652] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.273681] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.273710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.273745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.273838] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.273869] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.273899] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.273950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.273981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.274008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.274038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.274064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.274094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.274127] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.274159] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.274191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.274217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.274245] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.274279] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.274308] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.276375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.276397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.276415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.276435] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.277999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.278019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.278041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.279612] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.279633] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.281503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.284833] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.284870] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.284889] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.284915] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.301666] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.301716] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.301782] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.301980] [drm:drm_mode_addfb2] [FB:79]
>[ 1364.302093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.318383] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.318431] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.318504] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.335491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.335529] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.335569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.335697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.335757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.335807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.335856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.335907] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.335964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.336020] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.336054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.336086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.336116] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.336145] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.336201] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.336243] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.336284] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.336316] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.336470] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.336483] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.336552] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.336619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.336653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.336691] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.336723] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.336758] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.336789] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.336822] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.336851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.336882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.336909] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.336919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.336948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.336955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.336984] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.337011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.337040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.337066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.337097] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.337122] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.337150] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.337176] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.337203] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.337233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.337266] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.337364] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.337395] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.337424] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.337475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.337503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.337532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.337558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.337610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.337641] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.337675] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.337708] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.337741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.337768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.337797] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.337832] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.337861] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.339935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.339956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.339975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.339994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.341599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.341621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.341640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.343205] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.343226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.345089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.348336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.348409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.348432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.348464] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.365202] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.365254] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.365326] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.365527] [drm:drm_mode_addfb2] [FB:77]
>[ 1364.365780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.381898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.381944] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.382012] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.399028] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.399070] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.399115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.399156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.399200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.399240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.399280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.399319] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.399364] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.399406] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.399449] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.399494] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.399515] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.399534] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.399636] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.399680] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.399723] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.399756] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.399905] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.399926] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.400020] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.400053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.400086] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.400121] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.400149] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.400181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.400211] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.400243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.400271] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.400300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.400327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.400334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.400361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.400367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.400397] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.400425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.400453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.400478] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.400509] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.400535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.400592] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.400623] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.400650] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.400683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.400718] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.400814] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.400846] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.400877] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.400932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.400963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.400995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.401025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.401055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.401084] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.401117] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.401149] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.401180] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.401206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.401235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.401266] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.401297] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.403365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.403387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.403406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.403425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.405002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.405032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.405059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.406673] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.406695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.408560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.411851] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.411892] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.411911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.411937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.428687] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.428739] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.428806] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.429005] [drm:drm_mode_addfb2] [FB:78]
>[ 1364.429134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.445343] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.445386] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.445454] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.462496] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.462534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.462659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.462707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.462764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.462809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.462854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.462906] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.462954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.463000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.463044] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.463088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.463124] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.463163] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.463237] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.463294] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.463349] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.463392] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.463637] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.463664] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.463795] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.463843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.463891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.463948] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.463984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.464024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.464064] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.464101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.464138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.464173] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.464207] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.464216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.464250] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.464258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.464293] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.464327] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.464358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.464391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.464431] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.464465] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.464497] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.464531] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.464598] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.464639] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.464680] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.464776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.464813] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.464851] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.464911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.464953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.464981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.465011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.465040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.465071] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.465104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.465137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.465169] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.465198] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.465227] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.465260] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.465292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.467361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.467382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.467400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.467420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.469009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.469031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.469050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.470608] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.470629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.472499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.475849] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.475935] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.475967] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.476010] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.492713] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.492765] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.492831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.493010] [drm:drm_mode_addfb2] [FB:79]
>[ 1364.493146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.509390] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.509439] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.509511] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.526537] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.526608] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.526648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.526682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.526718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.526748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.526777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.526809] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.526845] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.526877] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.526909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.526940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.526968] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.526996] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.527049] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.527090] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.527131] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.527162] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.527360] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.527380] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.527480] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.527517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.527558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.527665] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.527715] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.527767] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.527817] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.527866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.527915] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.527961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.528005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.528019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.528061] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.528073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.528117] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.528161] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.528206] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.528251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.528301] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.528346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.528393] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.528441] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.528471] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.528505] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.528539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.528658] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.528690] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.528717] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.528769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.528801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.528832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.528863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.528896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.528928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.528964] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.528997] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.529031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.529060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.529090] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.529122] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.529153] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.531229] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.531254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.531277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.531301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.532877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.532899] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.532917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.534465] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.534486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.536349] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.539701] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.539776] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.539803] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.539837] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.556544] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.556624] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.556688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.556881] [drm:drm_mode_addfb2] [FB:77]
>[ 1364.557009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.573280] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.573333] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.573409] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.590431] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.590473] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.590518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.590559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.590685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.590735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.590785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.590832] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.590896] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.590940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.590982] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.591024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.591058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.591094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.591162] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.591218] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.591270] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.591312] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.591495] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.591513] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.591691] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.591737] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.591785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.591834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.591875] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.591926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.591964] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.592001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.592037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.592071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.592103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.592112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.592144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.592152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.592185] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.592218] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.592248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.592281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.592318] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.592351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.592381] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.592414] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.592449] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.592487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.592526] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.592657] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.592692] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.592728] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.592787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.592823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.592859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.592893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.592932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.592963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.592997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.593030] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.593062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.593092] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.593121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.593154] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.593186] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.595254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.595276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.595295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.595314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.596882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.596902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.596920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.598475] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.598496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.600370] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.603683] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.603751] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.603783] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.603825] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.620535] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.620620] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.620687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.620886] [drm:drm_mode_addfb2] [FB:78]
>[ 1364.621001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.637211] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.637259] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.637331] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.654343] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.654382] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.654422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.654456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.654491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.654521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.654629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.654679] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.654737] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.654789] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.654840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.654891] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.654932] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.654975] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.655059] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.655124] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.655191] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.655222] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.655353] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.655366] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.655431] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.655453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.655475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.655502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.655525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.655616] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.655652] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.655686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.655719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.655750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.655781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.655788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.655818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.655826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.655856] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.655887] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.655916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.655945] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.655976] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.656004] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.656034] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.656064] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.656090] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.656123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.656158] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.656235] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.656266] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.656296] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.656347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.656378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.656410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.656440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.656471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.656502] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.656536] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.656597] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.656627] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.656657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.656687] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.656722] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.656755] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.658830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.658852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.658871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.658890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.660460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.660482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.660505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.662103] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.662124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.664015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.667350] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.667433] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.667453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.667483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.684218] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.684267] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.684331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.684526] [drm:drm_mode_addfb2] [FB:79]
>[ 1364.684777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.700904] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.700952] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.701027] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.718079] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.718117] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.718157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.718190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.718225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.718255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.718285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.718317] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.718359] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.718402] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.718445] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.718487] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.718523] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.718610] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.718667] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.718709] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.718751] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.718782] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.718938] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.718958] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.719057] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.719089] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.719121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.719156] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.719184] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.719215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.719245] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.719275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.719305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.719333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.719360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.719366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.719393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.719400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.719428] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.719454] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.719481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.719508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.719549] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.719609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.719639] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.719670] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.719701] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.719736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.719772] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.719849] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.719880] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.719912] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.719963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.719995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.720026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.720056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.720083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.720113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.720148] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.720181] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.720214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.720243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.720271] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.720305] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.720337] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.722406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.722427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.722445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.722464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.724032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.724053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.724071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.725648] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.725671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.727555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.730868] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.730942] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.730961] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.730987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.747738] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.747790] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.747856] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.748052] [drm:drm_mode_addfb2] [FB:77]
>[ 1364.748181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.764453] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.764501] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.764672] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.781665] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.781703] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.781743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.781776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.781812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.781843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.781873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.781904] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.781940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.781982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.782012] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.782041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.782067] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.782094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.782144] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.782183] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.782222] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.782252] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.782434] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.782451] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.782542] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.782637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.782687] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.782745] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.782792] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.782844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.782893] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.782942] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.782989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.783036] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.783081] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.783094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.783137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.783149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.783193] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.783238] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.783283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.783326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.783375] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.783419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.783464] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.783507] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.783549] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.783625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.783678] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.783817] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.783863] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.783908] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.783983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.784031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.784078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.784114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.784149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.784187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.784227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.784266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.784304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.784341] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.784376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.784413] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.784451] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.786579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.786601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.786620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.786639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.788208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.788227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.788245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.789807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.789827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.791696] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.795014] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.795077] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.795109] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.795151] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.811861] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.811912] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.811978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.812178] [drm:drm_mode_addfb2] [FB:78]
>[ 1364.812307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.828537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.828631] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.828702] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.845688] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.845725] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.845765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.845799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.845835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.845866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.845896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.845928] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.845963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.845996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.846028] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.846060] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.846088] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.846117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.846170] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.846216] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.846266] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.846302] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.846458] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.846470] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.846537] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.846604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.846638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.846678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.846710] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.846746] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.846780] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.846815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.846847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.846879] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.846909] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.846918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.846947] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.846955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.846985] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.847016] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.847047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.847077] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.847111] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.847141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.847172] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.847532] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.847587] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.847621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.847745] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.847846] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.847874] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.847902] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.847951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.847981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.848010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.848038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.848065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.848094] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.848126] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.848155] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.848185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.848214] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.848241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.848272] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.848301] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.850388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.850411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.850430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.850449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.852023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.852044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.852062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.853634] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.853655] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.855522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.858808] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.858850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.858875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.858906] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.875646] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.875697] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.875763] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.875961] [drm:drm_mode_addfb2] [FB:79]
>[ 1364.876091] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.892321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.892369] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.892441] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.909463] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.909501] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.909541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.909659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.909715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.909759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.909805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.909850] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.909907] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.909951] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.909983] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.910015] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.910041] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.910069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.910123] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.910165] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.910205] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.910238] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.910407] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.910420] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.910477] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.910500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.910533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.910609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.910642] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.910678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.910713] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.910747] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.910779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.910811] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.910843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.910852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.910882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.910890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.910921] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.910951] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.910979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.911009] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.911043] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.911073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.911099] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.911130] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.911160] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.911194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.911229] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.911305] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.911336] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.911367] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.911418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.911449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.911480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.911509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.911538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.911592] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.911628] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.911662] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.911695] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.911724] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.911755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.911789] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.911820] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.913898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.913920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.913938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.913957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.915520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.915552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.915570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.917146] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.917168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.919062] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.922314] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.922379] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.922398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.922423] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1364.939176] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.939227] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.939294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.939501] [drm:drm_mode_addfb2] [FB:77]
>[ 1364.939735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.955875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1364.955924] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1364.955998] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1364.973006] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1364.973043] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1364.973083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.973118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.973153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.973184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.973214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.973246] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1364.973281] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.973314] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.973345] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.973376] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.973411] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.973434] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.973479] [drm:intel_power_well_disable [i915]] disabling display
>[ 1364.973514] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1364.973624] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1364.973669] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1364.973835] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1364.973859] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1364.973974] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1364.974016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1364.974061] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1364.974110] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1364.974151] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1364.974195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1364.974238] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1364.974279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1364.974320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1364.974359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1364.974397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1364.974416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.974445] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1364.974452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1364.974481] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1364.974511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1364.974565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1364.974593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1364.974628] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1364.974656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1364.974687] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1364.974716] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1364.974747] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1364.974781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1364.974817] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1364.974909] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1364.974940] [drm:intel_power_well_enable [i915]] enabling display
>[ 1364.974970] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1364.975022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1364.975053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1364.975085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1364.975115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1364.975145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1364.975176] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1364.975209] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1364.975242] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1364.975274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1364.975304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1364.975333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1364.975367] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1364.975398] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1364.977481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1364.977502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1364.977524] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.977603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1364.979190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1364.979212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1364.979231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1364.980795] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1364.980816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1364.982692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1364.986003] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1364.986071] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1364.986101] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1364.986141] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.002845] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.002896] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.002967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.003191] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.003319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.019556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.019645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.019735] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.036728] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.036771] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.036817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.036858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.036903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.036943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.036983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.037023] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.037068] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.037111] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.037153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.037195] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.037235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.037274] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.037332] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.037379] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.037429] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.037465] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.037722] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.037752] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.037889] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.037920] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.037954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.037990] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.038020] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.038052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.038081] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.038112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.038139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.038168] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.038194] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.038201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.038227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.038234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.038264] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.038290] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.038317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.038343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.038374] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.038399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.038428] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.038453] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.038481] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.038510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.038569] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.038641] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.038672] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.038703] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.038754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.038785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.038816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.038843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.038871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.038899] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.038931] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.038963] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.038995] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.039021] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.039049] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.039079] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.039109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.041189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.041211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.041230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.041249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.042835] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.042857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.042876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.044424] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.044446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.046319] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.049673] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.049756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.049796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.049848] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.066521] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.066604] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.066668] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.066891] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.067029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.083231] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.083278] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.083366] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.100357] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.100394] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.100434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.100468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.100503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.100612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.100658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.100704] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.100764] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.100815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.100866] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.100916] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.100957] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.101001] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.101088] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.101152] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.101214] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.101263] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.101415] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.101428] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.101494] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.101526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.101598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.101637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.101670] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.101705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.101739] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.101774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.101806] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.101836] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.101866] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.101874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.101903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.101910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.101939] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.101969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.101998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.102027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.102061] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.102090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.102121] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.102147] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.102176] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.102210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.102245] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.102325] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.102357] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.102387] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.102439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.102470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.102501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.102530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.102582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.102615] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.102650] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.102684] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.102718] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.102749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.102780] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.102815] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.102847] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.104918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.104939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.104957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.104976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.106590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.106612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.106631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.108183] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.108205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.110081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.113378] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.113465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.113497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.113600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.130245] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.130296] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.130363] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.130755] [drm:drm_mode_addfb2] [FB:77]
>[ 1365.130884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.146928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.146975] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.147064] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.164069] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.164107] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.164147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.164180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.164215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.164245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.164274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.164305] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.164341] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.164373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.164405] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.164436] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.164473] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.164513] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.164637] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.164703] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.164767] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.164800] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.164944] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.164963] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.165050] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.165080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.165113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.165149] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.165177] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.165209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.165238] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.165269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.165297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.165326] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.165352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.165359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.165386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.165393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.165422] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.165448] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.165477] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.165502] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.165558] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.165585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.165615] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.165642] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.165672] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.165706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.165741] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.165830] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.165859] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.165889] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.165939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.165970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.165997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.166027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.166053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.166083] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.166116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.166147] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.166178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.166204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.166231] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.166262] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.166292] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.168367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.168389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.168412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.168437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.170006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.170026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.170044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.171636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.171657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.173520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.176878] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.176967] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.176990] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.177022] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.193756] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.193810] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.193882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.194086] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.194222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.210448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.210497] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.210675] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.228858] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.228895] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.228939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.228981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.229025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.229066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.229105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.229145] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.229189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.229240] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.229274] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.229305] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.229332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.229358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.229406] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.229443] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.229482] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.229510] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.229769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.229794] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.229918] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.229958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.229992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.230028] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.230056] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.230086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.230116] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.230144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.230172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.230198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.230223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.230229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.230261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.230266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.230291] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.230317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.230343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.230369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.230395] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.230421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.230447] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.230473] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.230500] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.230557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.230593] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.230683] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.230712] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.230743] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.230798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.230832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.230865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.230896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.230928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.230958] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.230982] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.231003] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.231024] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.231043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.231062] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.231085] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.231106] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.233153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.233174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.233192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.233210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.234797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.234820] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.234839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.236399] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.236420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.238294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.241582] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.241662] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.241681] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.241707] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.258458] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.258509] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.258686] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.258944] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.259086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.275155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.275202] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.275272] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.292281] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.292319] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.292360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.292394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.292429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.292460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.292490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.292522] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.292655] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.292710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.292759] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.292792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.292821] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.292852] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.292904] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.292947] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.292987] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.293020] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.293152] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.293166] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.293230] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.293257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.293283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.293312] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.293337] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.293363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.293388] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.293414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.293439] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.293461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.293485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.293490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.293515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.293555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.293590] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.293624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.293653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.293684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.293719] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.293747] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.293778] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.293806] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.293836] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.293871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.293906] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.293982] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.294012] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.294042] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.294092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.294123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.294151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.294179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.294205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.294235] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.294268] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.294299] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.294331] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.294357] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.294385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.294415] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.294445] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.296562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.296583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.296602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.296621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.298195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.298215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.298234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.299786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.299807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.301674] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.304985] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.305041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.305060] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.305086] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.321837] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.321891] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.321963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.322186] [drm:drm_mode_addfb2] [FB:77]
>[ 1365.322314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.338536] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.338626] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.338696] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.355683] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.355720] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.355760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.355794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.355829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.355859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.355889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.355920] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.355956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.355997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.356040] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.356083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.356122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.356160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.356206] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.356241] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.356278] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.356304] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.356459] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.356475] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.356650] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.356692] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.356741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.356792] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.356833] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.356877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.356921] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.356964] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.357006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.357038] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.357064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.357070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.357095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.357100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.357125] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.357159] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.357181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.357204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.357231] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.357253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.357275] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.357298] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.357319] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.357347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.357376] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.357444] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.357467] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.357490] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.357579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.357615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.357650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.357685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.357718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.357753] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.357793] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.357831] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.357869] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.357902] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.357936] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.357976] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.358012] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.360120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.360141] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.360159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.360178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.361781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.361805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.361828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.363391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.363413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.365278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.368537] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.368595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.368615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.368641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.385390] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.385442] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.385508] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.385865] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.386006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.402090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.402136] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.402206] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.419215] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.419258] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.419303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.419344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.419388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.419428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.419469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.419509] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.419651] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.419700] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.419747] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.419792] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.419832] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.419872] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.419944] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.420001] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.420056] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.420099] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.420285] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.420303] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.420380] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.420410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.420441] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.420475] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.420506] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.420602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.420653] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.420685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.420714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.420745] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.420772] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.420782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.420809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.420817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.420847] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.420874] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.420905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.420932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.420964] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.420989] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.421018] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.421045] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.421072] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.421105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.421139] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.421218] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.421249] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.421278] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.421329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.421359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.421387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.421415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.421441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.421471] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.421504] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.421557] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.421590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.421618] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.421647] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.421682] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.421712] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.423785] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.423807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.423825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.423844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.426579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.426616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.426648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.428208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.428229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.430102] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.433416] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.433483] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.433514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.433634] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.450265] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.450316] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.450382] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.450682] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.450852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.466963] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.467011] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.467079] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.484089] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.484127] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.484167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.484200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.484235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.484265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.484294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.484326] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.484368] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.484411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.484453] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.484495] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.484615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.484663] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.484749] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.484814] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.484877] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.484927] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.485156] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.485188] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.485330] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.485388] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.485437] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.485489] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.485589] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.485638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.485687] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.485732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.485778] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.485821] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.485864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.485876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.485916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.485927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.485970] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.486010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.486051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.486087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.486132] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.486172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.486214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.486250] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.486290] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.486338] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.486390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.486468] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.486499] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.486553] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.486607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.486641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.486673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.486705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.486735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.486767] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.486803] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.486836] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.486868] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.486897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.486923] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.486956] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.486988] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.489097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.489120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.489143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.489167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.490751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.490772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.490790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.492342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.492362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.494239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.497564] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.497626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.497654] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.497690] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.514402] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.514453] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.514520] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.514850] [drm:drm_mode_addfb2] [FB:77]
>[ 1365.514978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.531103] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.531152] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.531227] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.548234] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.548271] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.548315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.548356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.548400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.548440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.548480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.548519] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.548657] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.548716] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.548771] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.548817] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.548847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.548877] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.548933] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.548976] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.549017] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.549050] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.549194] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.549207] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.549278] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.549299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.549321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.549344] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.549362] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.549382] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.549403] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.549422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.549445] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.549467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.549490] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.549549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.549581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.549588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.549619] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.549647] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.549675] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.549702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.549733] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.549760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.549788] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.549815] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.549843] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.549874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.549910] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.549987] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.550018] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.550049] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.550103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.550135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.550167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.550198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.550227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.550257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.550280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.550300] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.550321] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.550339] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.550358] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.550380] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.550401] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.552452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.552473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.552493] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.552563] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.554128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.554149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.554171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.555737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.555758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.557638] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.560953] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.561021] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.561055] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.561081] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.577779] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.577827] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.577892] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.578107] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.578247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.594517] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.594596] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.594685] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.611661] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.611699] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.611739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.611779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.611823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.611863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.611903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.611942] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.611987] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.612030] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.612072] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.612114] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.612153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.612193] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.612240] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.612265] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.612295] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.612316] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.612442] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.612456] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.612582] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.612618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.612655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.612694] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.612725] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.612760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.612794] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.612827] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.612860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.612891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.612922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.612931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.612959] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.612967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.612997] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.613026] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.613056] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.613085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.613118] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.613147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.613176] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.613205] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.613234] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.613267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.613302] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.613399] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.613431] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.613461] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.613539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.613574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.613605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.613637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.613668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.613701] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.613736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.613770] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.613805] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.613835] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.613866] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.613900] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.613933] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.616008] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.616029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.616048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.616066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.617665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.617688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.617707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.619266] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.619290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.621163] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.624447] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.624478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.624498] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.624585] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.641275] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.641327] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.641393] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.641769] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.641885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.657991] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.658039] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.658112] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.675101] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.675138] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.675178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.675211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.675246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.675277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.675306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.675338] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.675373] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.675407] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.675439] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.675470] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.675498] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.675594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.675647] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.675689] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.675730] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.675761] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.675893] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.675912] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.675998] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.676027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.676060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.676096] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.676124] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.676156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.676185] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.676215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.676244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.676272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.676300] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.676307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.676333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.676340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.676368] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.676396] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.676424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.676449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.676480] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.676532] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.676562] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.676591] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.676620] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.676649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.676683] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.676772] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.676802] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.676833] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.676883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.676914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.676941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.676969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.676995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.677025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.677058] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.677090] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.677121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.677147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.677175] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.677205] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.677236] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.679300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.679321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.679339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.679358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.680931] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.680950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.680968] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.682539] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.682560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.684418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.687790] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.687835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.687855] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.687880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.704632] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.704684] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.704750] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.704947] [drm:drm_mode_addfb2] [FB:77]
>[ 1365.705072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.721310] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.721359] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.721430] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.738452] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.738490] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.738613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.738661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.738715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.738758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.738803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.738848] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.738902] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.738955] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.739010] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.739043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.739069] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.739097] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.739153] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.739195] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.739235] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.739266] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.739422] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.739436] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.739507] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.739574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.739612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.739650] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.739683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.739718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.739934] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.739954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.739975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.739998] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.740021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.740026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.740049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.740053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.740077] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.740100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.740123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.740146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.740169] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.740192] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.740216] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.740239] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.740263] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.740288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.740313] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.740372] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.740392] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.740412] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.740449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.740472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.740496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.740574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.740610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.740646] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.740683] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.740718] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.740753] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.740783] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.740814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.740851] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.740884] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.743212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.743233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.743252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.743271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.744857] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.744880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.744899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.746487] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.746521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.748390] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.751703] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.751776] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.751816] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.751867] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.768555] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.768606] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.768672] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.768868] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.768995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.785269] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.785318] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.785390] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.802396] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.802434] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.802474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.802587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.802646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.802692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.802739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.802784] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.802840] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.802891] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.802942] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.802991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.803032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.803075] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.803159] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.803224] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.803285] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.803317] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.803473] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.803528] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.803623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.803647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.803671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.803704] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.803722] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.803742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.803762] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.803781] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.803800] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.803817] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.803834] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.803838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.803854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.803858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.803875] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.803892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.803908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.803924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.803943] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.803959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.803976] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.803992] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.804007] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.804027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.804048] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.804105] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.804123] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.804139] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.804172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.804190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.804207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.804224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.804240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.804262] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.804288] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.804313] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.804338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.804371] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.804396] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.804422] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.804448] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.806548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.806570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.806592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.806617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.808201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.808223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.808242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.809806] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.809828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.811698] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.815048] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.815133] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.815166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.815208] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.831913] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.831964] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.832031] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.832231] [drm:drm_mode_addfb2] [FB:79]
>[ 1365.832361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.848627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.848675] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.848748] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.865739] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.865776] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.865816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.865850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.865885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.865916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.865946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.865978] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.866012] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.866045] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.866077] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.866108] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.866136] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.866174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.866232] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.866278] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.866329] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.866365] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.866616] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.866647] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.866801] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.866847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.866895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.866944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.866984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.867028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.867072] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.867115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.867156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.867195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.867235] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.867245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.867283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.867293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.867331] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.867370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.867408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.867446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.867488] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.867563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.867605] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.867642] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.867682] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.867727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.867774] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.867890] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.867924] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.867957] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.868013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.868048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.868078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.868111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.868143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.868177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.868214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.868250] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.868285] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.868317] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.868348] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.868385] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.868420] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.870544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.870565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.870584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.870608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.872189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.872209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.872230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.873793] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.873814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.875688] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.879019] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.879055] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.879075] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.879101] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.895841] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.895887] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.895951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.896148] [drm:drm_mode_addfb2] [FB:77]
>[ 1365.896275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.912546] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.912594] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.912672] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.929685] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.929722] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.929762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.929796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.929831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.929861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.929891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.929923] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.929966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.930009] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.930051] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.930093] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.930133] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.930164] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.930198] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.930223] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.930250] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.930268] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.930396] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.930409] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.930466] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.930500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.930564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.930603] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.930633] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.930668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.930698] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.930730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.930759] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.930789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.930816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.930825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.930853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.930861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.930890] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.930917] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.930947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.930973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.931005] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.931032] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.931061] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.931087] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.931117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.931146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.931179] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.931259] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.931289] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.931319] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.931369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.931399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.931426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.931454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.931485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.931538] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.931570] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.931604] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.931638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.931665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.931694] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.931725] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.931756] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.933826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.933846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.933865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.933885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.935486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.935524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.935542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.937106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1365.937129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1365.939033] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1365.942359] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1365.942417] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1365.942451] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1365.942494] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1365.959205] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.959260] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.959332] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.959609] [drm:drm_mode_addfb2] [FB:78]
>[ 1365.959786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.975898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1365.975946] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1365.976022] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1365.993031] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1365.993074] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1365.993119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.993160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.993204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.993244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.993284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.993324] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1365.993369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.993411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.993454] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.993496] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.993615] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.993650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.993707] [drm:intel_power_well_disable [i915]] disabling display
>[ 1365.993750] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1365.993794] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1365.993826] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1365.993962] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1365.993981] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1365.994075] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1365.994106] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1365.994140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1365.994175] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1365.994203] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1365.994236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1365.994266] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1365.994296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1365.994324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1365.994353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1365.994379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1365.994386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.994412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1365.994419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1365.994449] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1365.994476] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1365.994532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1365.994560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1365.994593] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1365.994620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1365.994650] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1365.994678] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1365.994707] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1365.994741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1365.994776] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1365.994855] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1365.994886] [drm:intel_power_well_enable [i915]] enabling display
>[ 1365.994915] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1365.994965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1365.994996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1365.995024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1365.995053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1365.995079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1365.995109] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1365.995142] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1365.995174] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1365.995206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1365.995232] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1365.995260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1365.995291] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1365.995321] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1365.997387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1365.997408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1365.997426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1365.997450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1365.999066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1365.999087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1365.999106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.001810] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.001844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.003723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.006968] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.007041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.007060] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.007085] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.023844] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.023895] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.023961] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.024149] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.024268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.040574] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.040620] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.040691] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.057708] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.057750] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.057795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.057836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.057880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.057920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.057960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.057999] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.058044] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.058087] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.058137] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.058171] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.058199] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.058224] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.058268] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.058303] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.058340] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.058366] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.058568] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.058595] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.058718] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.058760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.058804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.058851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.058888] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.058930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.058969] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.059009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.059046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.059084] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.059118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.059128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.059170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.059177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.059210] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.059240] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.059271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.059300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.059336] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.059367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.059400] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.059429] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.059461] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.059530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.059570] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.059658] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.059692] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.059728] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.059785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.059820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.059855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.059886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.059918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.059949] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.059986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.060023] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.060059] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.060089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.060121] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.060159] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.060199] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.062268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.062289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.062308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.062327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.063902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.063922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.063942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.065494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.065540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.067411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.070736] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.070792] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.070827] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.070873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.087575] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.087625] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.087692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.087886] [drm:drm_mode_addfb2] [FB:77]
>[ 1366.088014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.104250] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.104298] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.104386] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.121391] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.121429] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.121469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.121588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.121646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.121696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.121745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.121787] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.121825] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.121859] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.121900] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.121944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.121984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.122025] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.122083] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.122131] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.122181] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.122218] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.122373] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.122392] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.122489] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.122581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.122614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.122649] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.122678] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.122709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.122739] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.122769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.122797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.122825] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.122852] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.122861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.122887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.122895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.122922] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.122952] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.122982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.123010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.123044] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.123073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.123103] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.123134] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.123162] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.123196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.123230] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.123308] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.123335] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.123354] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.123389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.123409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.123430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.123449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.123468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.123517] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.123550] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.123581] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.123612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.123638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.123665] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.123697] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.123726] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.125791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.125831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.125851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.125872] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.127480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.127521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.127545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.129110] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.129132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.131024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.134348] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.134407] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.134440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.134482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.151187] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.151238] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.151304] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.151554] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.151760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.167862] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.167910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.167986] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.185029] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.185067] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.185106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.185141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.185176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.185206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.185235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.185267] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.185302] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.185334] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.185366] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.185397] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.185425] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.185452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.185582] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.185649] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.185713] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.185762] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.185985] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.186013] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.186124] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.186155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.186188] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.186223] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.186250] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.186282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.186311] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.186341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.186370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.186398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.186424] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.186431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.186459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.186490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.186521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.186548] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.186577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.186606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.186640] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.186666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.186696] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.186723] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.186752] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.186786] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.186821] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.186893] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.186923] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.186953] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.187003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.187035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.187062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.187090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.187116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.187145] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.187178] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.187210] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.187241] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.187267] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.187294] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.187325] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.187354] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.189429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.189453] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.189476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.189553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.191119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.191139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.191157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.192709] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.192730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.194602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.197932] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.197985] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.198018] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.198060] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.214764] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.214818] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.214890] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.215091] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.215227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.231481] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.231560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.231633] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.248625] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.248663] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.248707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.248748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.248792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.248832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.248872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.248912] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.248956] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.248999] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.249041] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.249083] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.249122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.249162] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.249219] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.249266] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.249316] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.249353] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.249564] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.249585] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.249684] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.249718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.249753] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.249791] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.249822] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.249855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.249889] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.249920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.249952] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.249982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.250012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.250019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.250047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.250055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.250084] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.250113] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.250142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.250171] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.250203] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.250233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.250263] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.250293] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.250323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.250356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.250390] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.250467] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.250523] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.250553] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.250606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.250640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.250671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.250705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.250735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.250768] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.250804] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.250837] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.250870] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.250899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.250930] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.250965] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.250997] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.253072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.253094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.253116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.253141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.254730] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.254752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.254775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.256330] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.256351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.258221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.261550] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.261600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.261641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.261666] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.278389] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.278441] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.278589] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.278837] [drm:drm_mode_addfb2] [FB:77]
>[ 1366.278966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.295086] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.295135] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.295210] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.312219] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.312261] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.312306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.312348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.312392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.312432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.312473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.312604] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.312668] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.312723] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.312775] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.312828] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.312874] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.312915] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.312969] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.313012] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.313053] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.313085] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.313208] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.313221] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.313285] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.313309] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.313332] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.313357] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.313377] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.313399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.313424] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.313450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.313477] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.313540] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.313570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.313579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.313608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.313616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.313647] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.313675] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.313705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.313732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.313765] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.313793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.313824] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.313850] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.313879] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.313912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.313947] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.314023] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.314054] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.314083] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.314134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.314165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.314193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.314222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.314250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.314280] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.314312] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.314344] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.314375] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.314401] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.314429] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.314462] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.314515] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.316587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.316608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.316627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.316647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.318219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.318239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.318261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.319825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.319846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.321717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.325042] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.325098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.325117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.325142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.341880] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.341932] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.341998] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.342195] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.342313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.358597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.358649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.358740] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.375737] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.375775] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.375814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.375848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.375882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.375912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.375941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.375973] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.376008] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.376049] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.376092] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.376135] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.376174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.376215] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.376294] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.376337] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.376388] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.376408] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.376540] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.376559] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.376658] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.376691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.376729] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.376766] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.376797] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.376831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.376863] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.376895] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.376927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.376956] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.376985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.376993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.377021] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.377028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.377057] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.377087] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.377116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.377145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.377177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.377206] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.377236] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.377266] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.377292] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.377325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.377359] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.377436] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.377468] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.377534] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.377587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.377621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.377653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.377685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.377716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.377748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.377783] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.377817] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.377851] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.377880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.377912] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.377947] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.377979] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.380054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.380076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.380095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.380118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.381694] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.381715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.381733] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.383280] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.383301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.385172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.388466] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.388554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.388586] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.388611] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.405334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.405384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.405449] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.405792] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.405926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.422034] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.422081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.422171] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.439163] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.439201] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.439241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.439275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.439312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.439342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.439372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.439404] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.439447] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.439564] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.439619] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.439675] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.439719] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.439765] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.439846] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.439898] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.439947] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.439987] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.440174] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.440200] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.440316] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.440359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.440402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.440448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.440544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.440590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.440633] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.440674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.440715] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.440755] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.440792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.440810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.440838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.440845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.440875] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.440904] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.440934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.440960] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.440993] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.441024] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.441055] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.441085] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.441111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.441143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.441178] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.441254] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.441285] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.441315] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.441367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.441398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.441429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.441459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.441513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.441547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.441582] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.441616] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.441649] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.441679] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.441709] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.441745] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.441776] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.443850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.443873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.443892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.443911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.445473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.445508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.445526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.447092] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.447113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.449005] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.452305] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.452385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.452420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.452466] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.469171] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.469222] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.469288] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.469584] [drm:drm_mode_addfb2] [FB:77]
>[ 1366.469784] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.485887] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.485935] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.486009] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.502998] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.503035] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.503075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.503108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.503144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.503175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.503204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.503236] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.503271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.503303] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.503334] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.503365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.503394] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.503421] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.503531] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.503603] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.503666] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.503717] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.503940] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.503969] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.504103] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.504149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.504201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.504238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.504266] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.504297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.504327] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.504357] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.504385] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.504413] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.504439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.504447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.504499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.504507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.504538] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.504565] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.504594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.504621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.504653] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.504680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.504710] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.504737] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.504767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.504801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.504837] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.504926] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.504956] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.504985] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.505035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.505066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.505093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.505121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.505147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.505177] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.505210] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.505241] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.505273] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.505300] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.505327] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.505358] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.505388] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.507479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.507509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.507528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.507547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.509109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.509129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.509147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.510709] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.510729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.512599] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.515908] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.515985] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.516025] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.516077] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.532762] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.532814] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.532880] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.533078] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.533207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.549479] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.549561] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.549638] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.566627] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.566670] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.566714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.566755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.566799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.566839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.566879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.566918] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.566963] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.567006] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.567048] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.567089] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.567129] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.567168] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.567225] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.567271] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.567322] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.567357] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.567605] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.567637] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.567782] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.567827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.567874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.567923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.567964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.568008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.568052] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.568093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.568134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.568173] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.568212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.568222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.568259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.568268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.568308] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.568347] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.568386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.568424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.568467] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.568539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.568577] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.568618] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.568656] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.568710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.568748] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.568831] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.568865] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.568898] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.568954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.568988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.569021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.569050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.569082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.569116] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.569154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.569190] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.569226] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.569258] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.569289] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.569326] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.569361] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.571435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.571457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.571520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.571556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.573122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.573143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.573165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.574718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.574739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.576606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.579925] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.579978] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.579997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.580023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.596770] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.596821] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.596888] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.597085] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.597216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.613442] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.613515] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.613587] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.630592] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.630630] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.630670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.630704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.630738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.630768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.630798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.630830] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.630865] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.630898] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.630929] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.630959] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.630987] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.631014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.631068] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.631109] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.631155] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.631173] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.631302] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.631314] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.631372] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.631395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.631419] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.631444] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.631534] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.631566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.631601] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.631634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.631667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.631698] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.631728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.631737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.631766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.631774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.631804] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.631834] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.631865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.631895] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.631929] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.631959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.631990] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.632021] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.632051] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.632085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.632120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.632201] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.632232] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.632262] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.632314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.632345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.632373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.632402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.632429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.632460] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.632516] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.632549] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.632581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.632611] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.632638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.632674] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.632706] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.634782] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.634803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.634821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.634840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.636414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.636436] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.636455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.638059] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.638080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.639952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.643278] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.643335] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.643375] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.643401] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.660115] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.660167] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.660233] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.660430] [drm:drm_mode_addfb2] [FB:77]
>[ 1366.660750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.676832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.676881] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.676953] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.693941] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.693978] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.694018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.694052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.694086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.694117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.694147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.694179] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.694214] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.694247] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.694278] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.694310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.694338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.694365] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.694418] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.694459] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.694581] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.694640] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.694769] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.694788] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.694875] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.694905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.694939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.694975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.695005] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.695036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.695065] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.695095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.695122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.695150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.695178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.695185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.695211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.695218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.695246] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.695272] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.695300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.695325] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.695356] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.695382] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.695410] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.695436] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.695465] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.695519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.695554] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.695643] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.695674] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.695704] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.695754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.695784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.695813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.695841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.695866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.695895] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.695928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.695959] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.695990] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.696016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.696043] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.696076] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.696107] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.698193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.698218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.698241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.698265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.699832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.699853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.699872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.701456] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.701494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.703361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.706679] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.706746] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.706786] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.706837] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.723524] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.723575] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.723641] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.723838] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.723965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.740201] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.740249] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.740322] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.757347] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.757385] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.757425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.757460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.757580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.757626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.757675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.757720] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.757777] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.757827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.757877] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.757926] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.757967] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.758010] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.758095] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.758137] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.758176] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.758208] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.758367] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.758389] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.758457] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.758528] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.758566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.758605] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.758638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.758673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.758708] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.758742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.758774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.758806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.758836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.758844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.758872] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.758881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.758912] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.758942] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.758971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.759000] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.759029] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.759058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.759088] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.759114] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.759143] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.759173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.759208] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.759285] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.759316] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.759346] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.759397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.759429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.759460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.759512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.759542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.759575] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.759610] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.759644] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.759677] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.759708] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.759739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.759775] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.759807] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.761880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.761902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.761921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.761940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.763504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.763524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.763542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.765100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.765121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.766990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.770318] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.770380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.770400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.770425] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.787151] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.787206] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.787277] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.787543] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.787740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.803879] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.803928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.804001] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.822394] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.822431] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.822553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.822604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.822659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.822703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.822749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.822793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.822849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.822900] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.822952] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.823002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.823042] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.823086] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.823170] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.823234] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.823298] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.823347] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.823604] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.823634] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.823754] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.823786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.823809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.823833] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.823855] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.823879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.823903] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.823927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.823951] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.823971] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.823994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.823998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.824021] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.824026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.824049] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.824073] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.824096] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.824118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.824142] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.824165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.824188] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.824212] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.824235] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.824260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.824285] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.824333] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.824353] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.824373] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.824409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.824433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.824500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.824534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.824566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.824597] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.824631] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.824665] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.824698] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.824725] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.824755] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.824790] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.824820] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.826893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.826917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.826940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.826964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.828573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.828594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.828613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.830170] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.830191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.832063] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.835386] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.835448] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.835564] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.835635] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.852227] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.852278] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.852345] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.852719] [drm:drm_mode_addfb2] [FB:77]
>[ 1366.852847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.868940] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.868988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.869059] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.886051] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.886087] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.886127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.886162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.886197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.886227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.886257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.886289] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.886324] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.886357] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.886389] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.886420] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.886458] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.886572] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.886655] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.886720] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.886783] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.886832] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.887054] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.887082] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.887192] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.887222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.887255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.887290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.887318] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.887350] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.887379] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.887409] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.887436] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.887491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.887517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.887527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.887554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.887562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.887592] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.887619] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.887649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.887675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.887708] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.887734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.887763] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.887790] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.887821] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.887854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.887887] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.887977] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.888007] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.888036] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.888087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.888117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.888145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.888173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.888199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.888228] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.888261] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.888293] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.888325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.888351] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.888378] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.888409] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.888439] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.890525] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.890546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.890565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.890584] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.892143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.892164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.892182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.893734] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.893755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.895623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.898942] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.899005] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.899037] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.899079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.915786] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.915837] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.915903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.916099] [drm:drm_mode_addfb2] [FB:78]
>[ 1366.916231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.932463] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.932556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.932627] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1366.949616] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1366.949659] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1366.949704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.949745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.949790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.949830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.949870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.949909] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.949954] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.949997] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.950039] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.950081] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.950120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.950159] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.950217] [drm:intel_power_well_disable [i915]] disabling display
>[ 1366.950263] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1366.950313] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.950349] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1366.950570] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1366.950601] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1366.950729] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1366.950763] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1366.950798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1366.950836] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1366.950868] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1366.950901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1366.950934] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1366.950966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1366.950998] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1366.951028] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1366.951057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1366.951065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.951093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1366.951100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1366.951131] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1366.951160] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1366.951190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1366.951219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1366.951252] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1366.951282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1366.951312] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1366.951343] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1366.951374] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1366.951407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.951441] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1366.951553] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1366.951584] [drm:intel_power_well_enable [i915]] enabling display
>[ 1366.951616] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1366.951668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1366.951699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1366.951727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1366.951757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1366.951786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1366.951815] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1366.951849] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1366.951882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1366.951914] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.951944] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1366.951973] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1366.952007] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1366.952039] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1366.954114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1366.954136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1366.954154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.954173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1366.955749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1366.955769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1366.955787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1366.957334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1366.957355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1366.959227] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1366.962578] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1366.962664] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1366.962705] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1366.962756] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1366.979439] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1366.979523] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1366.979590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1366.979787] [drm:drm_mode_addfb2] [FB:79]
>[ 1366.979902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1366.996155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1366.996204] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1366.996276] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.013257] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.013295] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.013335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.013369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.013404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.013434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.013547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.013595] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.013658] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.013710] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.013762] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.013814] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.013861] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.013906] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.013985] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.014049] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.014112] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.014165] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.014291] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.014305] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.014370] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.014394] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.014418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.014445] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.014511] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.014547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.014581] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.014615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.014648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.014680] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.014709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.014718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.014748] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.014755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.014784] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.014813] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.014842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.014869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.014901] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.014931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.014961] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.014990] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.015021] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.015053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.015089] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.015166] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.015197] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.015227] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.015279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.015311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.015341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.015372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.015402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.015433] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.015493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.015525] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.015560] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.015590] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.015621] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.015656] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.015688] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.017760] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.017780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.017798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.017817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.019393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.019415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.019434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.021028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.021049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.022925] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.026250] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.026307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.026340] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.026390] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.043089] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.043141] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.043207] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.043406] [drm:drm_mode_addfb2] [FB:77]
>[ 1367.043608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.059804] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.059852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.059924] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.076914] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.076951] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.076991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.077025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.077061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.077091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.077121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.077153] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.077188] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.077221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.077253] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.077284] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.077311] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.077338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.077392] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.077433] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.077541] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.077588] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.077750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.077768] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.077856] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.077891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.077919] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.077945] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.077969] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.077997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.078024] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.078049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.078076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.078102] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.078127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.078133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.078157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.078162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.078188] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.078214] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.078240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.078265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.078291] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.078316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.078342] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.078368] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.078394] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.078422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.078480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.078571] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.078602] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.078633] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.078690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.078723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.078755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.078787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.078816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.078839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.078862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.078883] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.078903] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.078922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.078940] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.078963] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.078984] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.081055] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.081076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.081094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.081113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.082689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.082709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.082731] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.084279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.084301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.086172] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.089495] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.089558] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.089597] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.089649] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.106335] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.106386] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.106452] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.106791] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.106926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.123034] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.123081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.123151] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.140159] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.140197] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.140237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.140271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.140306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.140336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.140366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.140397] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.140432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.140548] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.140602] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.140654] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.140697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.140741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.140827] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.140891] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.140954] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.141006] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.141192] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.141213] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.141308] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.141340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.141373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.141407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.141447] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.141510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.141545] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.141579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.141611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.141643] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.141673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.141682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.141712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.141720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.141750] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.141781] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.141810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.141840] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.141874] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.141904] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.141930] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.141958] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.141984] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.142016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.142050] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.142131] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.142162] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.142193] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.142245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.142277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.142308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.142338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.142367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.142398] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.142432] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.142487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.142522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.142552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.142583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.142618] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.142650] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.144721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.144742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.144760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.144779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.146342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.146362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.146380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.147961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.147981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.149877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.153228] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.153313] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.153350] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.153385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.170091] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.170142] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.170208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.170501] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.170705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.186749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.186795] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.186868] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.203895] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.203932] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.203973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.204006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.204041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.204072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.204101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.204133] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.204168] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.204200] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.204231] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.204262] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.204290] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.204334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.204425] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.204526] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.204568] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.204600] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.204746] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.204764] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.204851] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.204882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.204915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.204951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.204980] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.205011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.205042] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.205072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.205102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.205130] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.205158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.205165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.205192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.205198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.205227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.205255] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.205281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.205310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.205339] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.205368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.205395] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.205422] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.205473] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.205503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.205539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.205627] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.205657] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.205688] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.205739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.205769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.205797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.205826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.205852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.205882] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.205916] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.205947] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.205979] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.206007] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.206036] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.206066] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.206096] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.208164] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.208185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.208203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.208222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.209795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.209815] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.209832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.211380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.211402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.213311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.216626] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.216678] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.216697] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.216722] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.233507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.233558] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.233624] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.233825] [drm:drm_mode_addfb2] [FB:77]
>[ 1367.233955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.250150] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.250199] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.250271] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.267282] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.267325] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.267369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.267410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.267531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.267581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.267631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.267678] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.267734] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.267785] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.267839] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.267871] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.267897] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.267924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.267979] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.268021] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.268060] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.268092] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.268259] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.268272] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.268328] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.268351] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.268374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.268399] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.268419] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.268509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.268545] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.268578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.268611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.268642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.268673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.268682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.268711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.268719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.268750] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.268779] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.268810] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.268840] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.268870] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.268898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.268929] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.268958] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.268984] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.269016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.269051] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.269128] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.269160] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.269190] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.269244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.269276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.269307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.269338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.269368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.269400] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.269435] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.269487] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.269522] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.269552] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.269583] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.269618] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.269651] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.271720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.271741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.271759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.271779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.273356] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.273378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.273397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.275007] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.275028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.276901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.280179] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.280219] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.280243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.280274] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.297012] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.297066] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.297137] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.297332] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.297544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.313727] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.313776] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.313849] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.330839] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.330877] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.330917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.330951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.330986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.331017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.331046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.331078] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.331113] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.331154] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.331197] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.331240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.331279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.331310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.331344] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.331369] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.331396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.331415] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.331597] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.331616] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.331705] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.331735] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.331769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.331804] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.331833] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.331865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.331895] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.331925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.331952] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.331981] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.332007] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.332014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.332041] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.332047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.332076] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.332102] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.332130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.332155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.332186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.332212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.332240] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.332266] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.332294] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.332323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.332355] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.332468] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.332501] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.332531] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.332583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.332617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.332647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.332677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.332705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.332736] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.332771] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.332804] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.332838] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.332865] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.332894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.332928] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.332958] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.335051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.335073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.335092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.335111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.336695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.336717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.336737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.338295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.338316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.340177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.343499] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.343559] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.343578] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.343604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.360333] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.360384] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.360524] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.360769] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.360885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.377016] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.377064] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.377137] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.394159] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.394197] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.394237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.394270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.394304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.394334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.394363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.394394] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.394429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.394547] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.394601] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.394657] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.394693] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.394730] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.394799] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.394854] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.394906] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.394948] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.395124] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.395150] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.395273] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.395318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.395365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.395414] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.395514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.395563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.395609] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.395660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.395692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.395725] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.395755] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.395763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.395792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.395799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.395828] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.395858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.395884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.395912] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.395946] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.395976] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.396006] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.396032] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.396061] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.396094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.396129] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.396205] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.396236] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.396267] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.396319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.396350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.396381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.396411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.396463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.396496] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.396532] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.396565] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.396599] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.396629] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.396660] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.396695] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.396727] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.398798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.398821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.398844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.398868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.400441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.400475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.400494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.402048] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.402070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.403954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.407282] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.407338] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.407371] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.407412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.424111] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.424162] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.424228] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.424499] [drm:drm_mode_addfb2] [FB:77]
>[ 1367.424694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.440820] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.440868] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.440945] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.457980] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.458022] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.458067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.458108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.458153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.458193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.458233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.458272] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.458317] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.458360] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.458402] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.458509] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.458566] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.458612] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.458695] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.458759] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.458824] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.458874] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.459092] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.459111] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.459199] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.459229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.459262] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.459298] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.459326] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.459358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.459387] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.459418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.459472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.459502] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.459530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.459538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.459565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.459573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.459603] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.459633] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.459662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.459689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.459721] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.459749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.459778] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.459804] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.459832] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.459865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.459900] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.459988] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.460018] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.460047] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.460098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.460129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.460156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.460184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.460210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.460239] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.460271] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.460302] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.460333] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.460359] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.460388] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.460418] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.460473] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.462550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.462573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.462592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.462612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.464182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.464206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.464229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.465784] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.465806] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.467676] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.471028] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.471111] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.471144] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.471187] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.487890] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.487944] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.488014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.488211] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.488341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.504568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.504617] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.504706] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.521718] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.521755] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.521795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.521828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.521863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.521894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.521924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.521955] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.521990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.522023] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.522054] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.522085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.522113] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.522140] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.522193] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.522234] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.522275] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.522306] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.522556] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.522582] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.522706] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.522748] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.522793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.522841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.522878] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.522921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.522960] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.523002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.523039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.523077] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.523112] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.523121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.523156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.523165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.523203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.523240] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.523276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.523310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.523351] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.523385] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.523423] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.523494] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.523540] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.523575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.523613] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.523713] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.523747] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.523780] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.523835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.523868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.523897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.523929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.523958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.523990] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.524025] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.524059] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.524094] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.524122] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.524153] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.524186] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.524219] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.526296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.526316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.526335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.526353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.527968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.527991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.528010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.529596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.529619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.531488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.534805] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.534854] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.534873] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.534904] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.551650] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.551702] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.551768] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.551964] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.552093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.568327] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.568376] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.568538] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.585536] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.585574] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.585613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.585647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.585683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.585714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.585743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.585775] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.585811] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.585843] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.585874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.585905] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.585943] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.585991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.586037] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.586072] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.586108] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.586134] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.586303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.586319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.586399] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.586432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.586526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.586579] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.586621] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.586667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.586708] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.586751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.586789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.586828] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.586863] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.586875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.586914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.586924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.586964] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.587002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.587051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.587087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.587131] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.587166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.587207] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.587244] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.587283] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.587328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.587374] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.587533] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.587575] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.587616] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.587687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.587726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.587768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.587805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.587844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.587883] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.587927] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.587971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.588014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.588054] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.588085] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.588120] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.588154] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.590242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.590263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.590282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.590301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.591873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.591893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.591911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.593465] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.593488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.595351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.598704] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.598790] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.598830] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.598881] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.615566] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.615618] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.615688] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.615893] [drm:drm_mode_addfb2] [FB:77]
>[ 1367.616031] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.632277] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.632325] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.632416] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.649485] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.649523] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.649563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.649598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.649633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.649672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.649712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.649752] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.649797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.649839] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.649882] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.649924] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.649963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.650002] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.650060] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.650106] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.650157] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.650193] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.650394] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.650487] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.650631] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.650688] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.650740] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.650795] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.650840] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.650890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.650938] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.650984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.651031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.651075] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.651118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.651130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.651171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.651182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.651225] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.651268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.651311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.651356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.651403] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.651477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.651508] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.651540] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.651570] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.651604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.651639] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.651735] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.651767] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.651797] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.651848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.651880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.651911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.651942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.651969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.652000] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.652035] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.652069] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.652101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.652131] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.652160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.652194] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.652226] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.654303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.654324] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.654342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.654366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.655953] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.655977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.656001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.657585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.657608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.659472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.662769] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.662840] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.662860] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.662886] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.679637] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.679689] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.679756] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.679936] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.680057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.696311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.696360] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.696529] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.713527] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.713564] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.713604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.713638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.713673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.713712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.713752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.713792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.713837] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.713880] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.713922] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.713964] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.714005] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.714032] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.714078] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.714113] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.714150] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.714176] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.714303] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.714319] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.714396] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.714520] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.714571] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.714622] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.714664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.714712] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.714757] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.714801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.714845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.714886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.714923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.714935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.714974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.714984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.715024] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.715064] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.715104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.715143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.715186] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.715225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.715266] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.715303] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.715342] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.715385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.715431] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.715561] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.715601] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.715642] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.715709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.715753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.715795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.715837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.715877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.715920] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.715966] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.716019] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.716052] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.716080] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.716109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.716141] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.716172] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.718249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.718269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.718288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.718307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.719894] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.719917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.719939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.721534] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.721556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.723420] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.726787] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.726871] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.726904] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.726947] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.743628] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.743675] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.743739] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.743920] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.744051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.760325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.760374] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.760536] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.777535] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.777572] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.777612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.777645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.777680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.777711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.777740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.777778] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.777823] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.777866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.777909] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.777952] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.777991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.778030] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.778088] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.778134] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.778184] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.778220] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.778467] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.778495] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.778629] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.778676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.778725] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.778777] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.778819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.778866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.778911] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.778955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.778999] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.779040] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.779081] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.779091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.779130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.779140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.779180] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.779221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.779262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.779302] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.779347] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.779389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.779439] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.779494] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.779526] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.779561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.779596] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.779692] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.779723] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.779754] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.779806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.779838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.779868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.779899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.779930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.779961] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.779995] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.780029] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.780061] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.780091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.780120] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.780154] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.780185] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.782255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.782277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.782297] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.782316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.783889] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.783909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.783927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.785517] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.785537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.787408] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.790747] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.790789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.790809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.790835] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.807587] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.807638] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.807705] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.807902] [drm:drm_mode_addfb2] [FB:77]
>[ 1367.808030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.824303] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.824351] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.824512] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.841501] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.841539] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.841578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.841613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.841648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.841679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.841709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.841741] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.841784] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.841827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.841869] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.841899] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.841925] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.841951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.842000] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.842036] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.842075] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.842102] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.842279] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.842297] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.842382] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.842416] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.842501] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.842553] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.842599] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.842648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.842694] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.842740] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.842785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.842830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.842881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.842895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.842939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.842951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.842995] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.843040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.843085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.843128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.843179] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.843223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.843268] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.843313] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.843358] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.843407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.843480] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.843623] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.843669] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.843714] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.843790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.843838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.843882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.843931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.843968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.844001] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.844041] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.844079] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.844117] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.844152] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.844186] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.844227] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.844265] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.846364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.846386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.846408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.846474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.848043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.848064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.848083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.849669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.849692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.851571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.854921] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.855009] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.855058] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.855089] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.871774] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.871823] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.871886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.872086] [drm:drm_mode_addfb2] [FB:78]
>[ 1367.872212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.888462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.888510] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.888600] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.905610] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.905648] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.905692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.905733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.905777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.905818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.905857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.905897] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.905941] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.905984] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.906026] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.906068] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.906107] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.906147] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.906204] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.906250] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.906301] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.906336] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.906558] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.906582] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.906699] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.906739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.906784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.906832] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.906869] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.906911] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.906950] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.906992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.907029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.907067] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.907102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.907111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.907146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.907155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.907192] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.907227] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.907263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.907297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.907338] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.907380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.907409] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.907462] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.907489] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.907523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.907558] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.907647] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.907678] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.907709] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.907760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.907792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.907820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.907849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.907875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.907906] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.907940] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.907971] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.908003] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.908029] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.908057] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.908088] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.908118] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.910185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.910205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.910224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.910243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.911817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.911837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.911855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.913405] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.913442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.915309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.918619] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.918675] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.918694] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.918720] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.935473] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.935524] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.935591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.935790] [drm:drm_mode_addfb2] [FB:79]
>[ 1367.935921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.952147] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1367.952196] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1367.952285] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1367.969271] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1367.969309] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1367.969348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.969382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.969499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.969546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.969595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.969641] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.969697] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.969748] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.969800] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.969831] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.969857] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.969886] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.969941] [drm:intel_power_well_disable [i915]] disabling display
>[ 1367.969982] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1367.970022] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.970053] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1367.970215] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1367.970229] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1367.970298] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1367.970322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1367.970348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1367.970375] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1367.970396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1367.970468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1367.970503] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1367.970537] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1367.970570] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1367.970601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1367.970633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1367.970642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.970672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1367.970680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1367.970709] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1367.970739] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1367.970770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1367.970799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1367.970833] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1367.970862] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1367.970892] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1367.970921] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1367.970947] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1367.970979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1367.971015] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1367.971111] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1367.971141] [drm:intel_power_well_enable [i915]] enabling display
>[ 1367.971172] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1367.971224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1367.971255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1367.971286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1367.971316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1367.971346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1367.971378] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1367.971411] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1367.971468] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1367.971502] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.971533] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1367.971564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1367.971599] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1367.971631] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1367.973705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1367.973727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1367.973750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.973774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1367.975347] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1367.975368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1367.975387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1367.976972] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1367.976993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1367.978860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1367.982110] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1367.982177] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1367.982196] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1367.982222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1367.998972] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1367.999024] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1367.999091] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1367.999270] [drm:drm_mode_addfb2] [FB:77]
>[ 1367.999389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.015691] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.015744] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.015837] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.032830] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.032867] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.032907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.032941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.032977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.033007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.033037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.033069] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.033104] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.033137] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.033169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.033200] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.033235] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.033260] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.033308] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.033345] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.033388] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.033489] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.033668] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.033693] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.033815] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.033857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.033903] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.033953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.033991] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.034035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.034076] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.034119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.034158] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.034198] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.034242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.034250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.034283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.034291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.034324] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.034353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.034385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.034444] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.034482] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.034514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.034549] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.034582] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.034615] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.034654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.034694] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.034776] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.034810] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.034843] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.034901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.034937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.034968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.035001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.035032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.035065] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.035102] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.035138] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.035174] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.035204] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.035243] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.035274] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.035305] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.037372] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.037393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.037466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.037497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.039056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.039077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.039096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.040647] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.040669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.042528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.045834] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.045913] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.045945] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.045987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.062691] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.062742] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.062809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.063006] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.063121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.079364] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.079413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.079582] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.098355] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.098392] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.098517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.098566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.098619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.098663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.098709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.098760] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.098808] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.098853] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.098898] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.098942] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.098978] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.099016] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.099088] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.099146] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.099200] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.099245] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.099471] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.099490] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.099579] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.099616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.099654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.099695] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.099729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.099772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.099796] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.099825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.099844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.099867] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.099890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.099894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.099917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.099921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.099945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.099969] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.099992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.100014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.100038] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.100061] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.100084] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.100107] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.100130] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.100155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.100181] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.100229] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.100249] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.100269] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.100305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.100329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.100353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.100376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.100400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.100475] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.100511] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.100547] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.100581] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.100613] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.100644] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.100681] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.100714] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.102800] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.102823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.102842] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.102862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.104452] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.104472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.104490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.106038] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.106059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.107932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.111161] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.111196] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.111215] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.111240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.127989] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.128042] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.128109] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.128308] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.128523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.144671] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.144720] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.144792] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.161816] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.161853] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.161893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.161927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.161961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.161992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.162022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.162054] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.162089] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.162122] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.162153] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.162185] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.162213] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.162246] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.162291] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.162326] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.162362] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.162388] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.162635] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.162660] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.162777] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.162816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.162860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.162907] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.162945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.162986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.163024] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.163065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.163105] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.163143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.163177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.163187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.163222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.163231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.163276] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.163304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.163335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.163362] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.163397] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.163451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.163485] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.163514] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.163546] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.163583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.163621] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.163717] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.163752] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.163784] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.163839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.163873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.163903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.163934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.163963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.163996] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.164031] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.164066] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.164100] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.164128] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.164160] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.164193] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.164226] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.166304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.166325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.166344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.166365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.167987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.168008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.168026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.169587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.169608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.171472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.174742] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.174788] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.174808] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.174834] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.191579] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.191628] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.191692] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.191874] [drm:drm_mode_addfb2] [FB:77]
>[ 1368.192006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.208257] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.208303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.208373] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.225491] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.225534] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.225579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.225619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.225664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.225704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.225743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.225792] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.225830] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.225862] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.225892] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.225921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.225947] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.225972] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.226019] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.226056] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.226094] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.226121] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.226298] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.226315] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.226401] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.226498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.226551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.226603] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.226643] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.226691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.226734] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.226778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.226818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.226859] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.226899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.226911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.226949] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.226960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.227002] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.227039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.227082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.227118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.227162] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.227197] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.227239] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.227276] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.227315] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.227361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.227405] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.227545] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.227587] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.227628] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.227698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.227740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.227781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.227822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.227862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.227894] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.227928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.227961] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.227993] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.228019] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.228048] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.228079] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.228109] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.230177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.230201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.230224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.230248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.231830] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.231851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.231870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.233452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.233473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.235348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.238675] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.238729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.238768] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.238819] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.255507] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.255556] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.255620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.255842] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.255982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.272210] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.272258] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.272350] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.289341] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.289379] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.289505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.289556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.289610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.289654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.289701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.289746] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.289800] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.289851] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.289901] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.289951] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.289991] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.290034] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.290120] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.290186] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.290247] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.290305] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.290476] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.290496] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.290590] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.290625] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.290660] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.290705] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.290734] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.290766] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.290796] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.290826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.290855] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.290882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.290907] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.290913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.290939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.290946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.290973] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.291000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.291024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.291050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.291081] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.291108] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.291133] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.291160] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.291187] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.291219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.291251] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.291320] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.291349] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.291377] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.291482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.291516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.291550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.291581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.291613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.291645] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.291682] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.291715] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.291749] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.291779] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.291809] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.291845] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.291877] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.293975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.293998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.294022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.294046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.295628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.295649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.295667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.297225] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.297246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.299107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.302405] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.302489] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.302519] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.302545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.319254] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.319303] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.319368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.319719] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.319857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.335984] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.336033] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.336106] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.353095] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.353133] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.353173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.353206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.353242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.353272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.353302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.353334] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.353369] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.353493] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.353550] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.353602] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.353650] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.353697] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.353772] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.353815] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.353855] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.353887] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.354025] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.354046] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.354147] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.354176] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.354207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.354241] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.354268] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.354298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.354325] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.354353] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.354389] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.354450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.354481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.354490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.354519] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.354527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.354557] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.354586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.354615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.354642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.354675] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.354702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.354731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.354758] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.354787] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.354822] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.354856] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.354935] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.354966] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.354996] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.355048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.355076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.355106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.355133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.355161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.355189] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.355221] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.355252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.355283] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.355310] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.355337] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.355371] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.355424] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.357509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.357533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.357556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.357581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.359155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.359176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.359195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.360747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.360768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.362630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.365952] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.366011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.366030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.366055] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.382793] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.382844] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.382911] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.383091] [drm:drm_mode_addfb2] [FB:77]
>[ 1368.383211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.399470] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.399519] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.399591] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.416615] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.416653] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.416693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.416727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.416763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.416793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.416822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.416854] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.416889] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.416921] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.416953] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.416984] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.417011] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.417039] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.417092] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.417133] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.417183] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.417201] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.417316] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.417330] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.417402] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.417465] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.417500] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.417538] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.417568] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.417602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.417633] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.417664] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.417693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.417723] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.417749] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.417757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.417784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.417792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.417821] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.417848] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.417878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.417903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.417935] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.417960] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.417989] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.418014] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.418042] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.418074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.418108] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.418186] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.418216] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.418246] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.418296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.418327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.418354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.418383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.418431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.418463] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.418497] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.418531] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.418564] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.418591] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.418620] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.418652] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.418684] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.420757] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.420780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.420803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.420827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.422426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.422448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.422466] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.424029] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.424050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.425927] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.429225] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.429310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.429342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.429382] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.446090] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.446141] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.446208] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.446463] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.446660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.462805] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.462853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.462927] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.479916] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.479952] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.479992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.480026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.480061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.480091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.480121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.480152] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.480187] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.480218] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.480249] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.480280] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.480307] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.480334] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.480388] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.480527] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.480569] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.480604] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.480750] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.480769] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.480857] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.480888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.480919] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.480955] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.480983] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.481015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.481045] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.481075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.481104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.481133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.481158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.481165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.481191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.481198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.481227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.481252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.481280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.481307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.481338] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.481364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.481418] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.481445] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.481475] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.481504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.481539] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.481611] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.481640] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.481671] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.481722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.481752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.481779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.481808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.481838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.481866] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.481897] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.481929] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.481960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.481986] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.482014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.482045] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.482075] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.484140] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.484164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.484187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.484211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.485775] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.485796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.485814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.487381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.487418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.489287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.492598] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.492671] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.492703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.492747] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.509453] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.509504] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.509573] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.509773] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.509907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.526130] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.526183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.526259] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.545194] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.545231] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.545271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.545305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.545339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.545378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.545494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.545541] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.545601] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.545653] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.545704] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.545754] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.545795] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.545839] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.545924] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.545989] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.546057] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.546089] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.546243] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.546265] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.546321] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.546343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.546365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.546457] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.546491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.546527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.546562] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.546594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.546627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.546659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.546689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.546697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.546725] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.546732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.546763] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.546792] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.546819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.546847] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.546879] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.546909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.546939] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.546968] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.546998] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.547028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.547063] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.547138] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.547169] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.547199] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.547251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.547283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.547313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.547343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.547373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.547429] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.547465] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.547499] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.547532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.547563] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.547594] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.547629] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.547661] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.549748] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.549773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.549796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.549820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.551382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.551429] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.551448] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.553013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.553034] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.554934] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.558233] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.558316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.558335] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.558361] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.575097] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.575151] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.575223] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.575511] [drm:drm_mode_addfb2] [FB:77]
>[ 1368.575720] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.591772] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.591821] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.591892] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.610324] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.610362] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.610481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.610529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.610584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.610628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.610673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.610717] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.610770] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.610821] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.610871] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.610922] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.610963] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.611006] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.611090] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.611154] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.611216] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.611265] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.611530] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.611546] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.611623] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.611654] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.611685] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.611722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.611756] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.611802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.611847] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.611889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.611929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.611967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.612005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.612015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.612049] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.612056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.612080] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.612103] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.612126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.612149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.612177] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.612208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.612242] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.612276] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.612309] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.612345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.612382] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.612548] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.612579] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.612610] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.612668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.612701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.612733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.612764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.612795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.612827] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.612852] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.612874] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.612894] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.612913] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.612931] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.612958] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.612983] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.615050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.615073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.615092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.615112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.616687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.616707] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.616725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.618272] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.618293] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.620164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.623516] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.623599] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.623632] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.623674] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.640377] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.640465] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.640532] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.640736] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.640867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.657051] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.657100] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.657171] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.674186] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.674224] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.674264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.674297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.674332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.674361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.674473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.674525] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.674583] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.674637] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.674689] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.674741] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.674789] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.674834] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.674892] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.674935] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.674978] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.675017] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.675122] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.675133] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.675189] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.675210] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.675233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.675257] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.675277] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.675298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.675319] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.675339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.675359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.675418] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.675446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.675454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.675480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.675488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.675515] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.675541] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.675568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.675594] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.675624] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.675650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.675676] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.675702] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.675728] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.675760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.675792] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.675868] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.675900] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.675930] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.675983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.676015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.676045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.676075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.676104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.676135] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.676165] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.676186] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.676206] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.676225] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.676249] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.676277] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.676303] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.678346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.678367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.678440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.678475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.680036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.680057] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.680075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.681637] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.681658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.683517] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.686870] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.686953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.686985] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.687027] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.703729] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.703781] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.703847] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.704043] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.704158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.720445] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.720498] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.720575] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.739401] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.739471] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.739511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.739545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.739588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.739629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.739670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.739709] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.739754] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.739797] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.739840] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.739882] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.739921] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.739960] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.740017] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.740064] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.740114] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.740151] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.740338] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.740429] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.740585] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.740631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.740681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.740734] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.740775] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.740822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.740866] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.740910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.740951] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.740993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.741030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.741041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.741080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.741090] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.741132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.741170] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.741211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.741248] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.741296] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.741335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.741377] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.741457] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.741499] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.741553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.741595] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.741684] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.741719] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.741755] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.741815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.741852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.741884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.741919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.741950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.741986] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.742024] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.742063] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.742101] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.742132] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.742165] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.742205] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.742239] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.744325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.744347] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.744366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.744437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.746006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.746026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.746044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.747596] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.747618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.749478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.752819] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.752896] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.752916] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.752941] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.769692] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.769743] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.769810] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.770008] [drm:drm_mode_addfb2] [FB:77]
>[ 1368.770135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.786437] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.786485] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.786558] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.803547] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.803589] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.803635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.803676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.803720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.803761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.803800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.803840] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.803885] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.803928] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.803970] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.804014] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.804035] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.804058] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.804093] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.804122] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.804152] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.804173] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.804296] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.804310] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.804383] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.804448] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.804484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.804522] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.804553] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.804587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.804620] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.804653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.804684] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.804715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.804744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.804752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.804780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.804787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.804816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.804845] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.804876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.804904] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.804937] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.804966] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.804995] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.805024] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.805053] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.805086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.805120] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.805196] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.805228] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.805258] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.805312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.805342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.805372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.805421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.805451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.805479] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.805513] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.805546] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.805580] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.805609] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.805638] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.805672] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.805705] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.807777] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.807798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.807817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.807840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.809423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.809446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.809464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.811024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.811045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.812909] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.816215] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.816277] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.816295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.816321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.833073] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.833124] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.833191] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.833473] [drm:drm_mode_addfb2] [FB:78]
>[ 1368.833675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.849749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.849798] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.849870] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.866921] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.866963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.867008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.867049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.867094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.867134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.867173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.867213] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.867257] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.867300] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.867343] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.867385] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.867481] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.867512] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.867568] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.867612] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.867654] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.867687] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.867837] [drm:drm_mode_setcrtc] [CRTC:46:pipe C]
>[ 1368.867858] [drm:drm_mode_setcrtc] [CONNECTOR:53:DP-1]
>[ 1368.867960] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.867992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.868024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.868058] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.868087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.868118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.868148] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][modeset]
>[ 1368.868178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1368.868207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.868235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.868262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.868269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.868295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.868302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.868329] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.868367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.868440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.868468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1368.868503] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.868533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.868564] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1368.868595] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1368.868626] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1368.868662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.868698] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe C
>[ 1368.869034] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.869062] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.869078] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.869113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.869133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.869152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.869169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.869192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.869215] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.869241] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.869266] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.869291] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.869314] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.869338] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.869362] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 4, on? 0) for crtc 46
>[ 1368.869439] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.871698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.871719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.871742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.871766] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.873380] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.873423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.873446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.875001] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.875023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.876898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.880199] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1368.880281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.880313] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 1368.880355] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.897061] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.897112] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.897178] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.897602] [drm:drm_mode_addfb2] [FB:79]
>[ 1368.897748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.913737] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 1368.913788] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1368.913864] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1368.930912] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 4, on? 1) for crtc 46
>[ 1368.930963] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1368.931003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.931037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.931073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.931103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.931142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.931182] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.931227] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.931270] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.931312] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.931355] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.931466] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.931517] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.931605] [drm:intel_power_well_disable [i915]] disabling display
>[ 1368.931670] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1368.931735] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1368.931786] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1368.935300] [IGT] kms_flip: exiting, ret=0
>[ 1368.954335] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1368.954373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1368.954445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1368.954480] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1368.954507] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1368.954536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1368.954565] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1368.954591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1368.954617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1368.954641] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1368.954665] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1368.954671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.954694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1368.954698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1368.954722] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1368.954745] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1368.954768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1368.954791] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1368.954818] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1368.954841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1368.954864] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1368.954886] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1368.954908] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1368.954935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1368.954965] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1368.955047] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1368.955073] [drm:intel_power_well_enable [i915]] enabling display
>[ 1368.955096] [drm:hsw_set_power_well [i915]] Enabling power well
>[ 1368.955142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1368.955167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1368.955191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1368.955215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1368.955238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1368.955263] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1368.955291] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1368.955317] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1368.955342] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.955368] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1368.955428] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1368.955465] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1368.955492] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1368.957555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1368.957575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1368.957593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.957611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1368.959184] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1368.959202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1368.959219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1368.960778] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1368.960797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1368.962670] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1368.965794] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1368.965832] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1368.965851] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1368.965882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1368.965946] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1368.965966] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1368.982639] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1368.982688] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1368.982757] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1368.982998] Console: switching to colour frame buffer device 240x75
>[ 1369.090214] Console: switching to colour dummy device 80x25
>[ 1369.090327] [IGT] kms_flip: executing
>[ 1369.101274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1369.101327] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1369.103472] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1369.103509] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1369.105604] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1369.105614] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1369.107732] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1369.107773] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1369.109888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1369.109900] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1369.109907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1369.109937] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1369.109980] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1369.111084] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1369.112018] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1369.112047] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1369.112081] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1369.112106] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1369.113135] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1369.113156] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1369.114271] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1369.114274] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1369.114439] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1369.114444] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1369.114454] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1369.114458] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1369.114467] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1369.114471] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1369.114486] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1369.114492] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.114497] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.114503] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.114508] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1369.114511] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1369.114514] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1369.114518] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1369.114521] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.114524] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.114527] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1369.114531] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1369.114534] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1369.114537] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1369.114540] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1369.114543] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1369.114547] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1369.114550] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1369.114553] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1369.114556] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1369.114560] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1369.114563] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1369.114566] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1369.114570] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1369.114573] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1369.114576] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1369.114579] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1369.114582] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1369.114586] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1369.114589] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1369.114592] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1369.114634] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1369.114659] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1369.116454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1369.116490] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1369.118469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1369.118480] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1369.120452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1369.120491] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1369.122451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1369.122462] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1369.122470] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1369.122852] [IGT] kms_flip: starting subtest 2x-blocking-absolute-wf_vblank
>[ 1369.126582] [IGT] kms_flip: exiting, ret=77
>[ 1369.149627] Console: switching to colour frame buffer device 240x75
>[ 1369.255993] Console: switching to colour dummy device 80x25
>[ 1369.256104] [IGT] kms_flip: executing
>[ 1369.268206] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1]
>[ 1369.268258] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1369.269462] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1369.269505] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1369.271454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1369.271465] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1369.273444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1369.273483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1369.275447] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1369.275458] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1369.275466] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:HDMI-A-1] disconnected
>[ 1369.275495] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1]
>[ 1369.275538] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1369.276644] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1369.277574] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1369.277599] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1369.277621] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1369.277642] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1369.278663] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1369.278684] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1369.279803] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[ 1369.279806] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[ 1369.279908] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1369.279911] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1369.279916] [drm:drm_mode_debug_printmodeline] Modeline 114:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 1369.279918] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[ 1369.279924] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 1369.279927] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[ 1369.279936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] probed modes :
>[ 1369.279939] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1369.279942] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.279945] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.279948] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1369.279951] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 1369.279954] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1369.279957] [drm:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 1369.279960] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.279963] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 1369.279966] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 1369.279969] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1369.279972] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 1369.279975] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 1369.279978] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1369.279981] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1369.279984] [drm:drm_mode_debug_printmodeline] Modeline 64:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1369.279987] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1369.279990] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 1369.279993] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 1369.279996] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1369.279998] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1369.280001] [drm:drm_mode_debug_printmodeline] Modeline 74:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1369.280004] [drm:drm_mode_debug_printmodeline] Modeline 67:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1369.280007] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 1369.280010] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1369.280013] [drm:drm_mode_debug_printmodeline] Modeline 63:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 1369.280016] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1369.280019] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1369.280022] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1369.280025] [drm:drm_mode_debug_printmodeline] Modeline 70:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1369.280063] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[ 1369.280086] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1369.281584] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1369.281615] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1369.283730] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1369.283740] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1369.285858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1369.285897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1369.288011] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1369.288022] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1369.288029] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[ 1369.288526] [IGT] kms_flip: starting subtest 2x-flip-vs-panning
>[ 1369.291823] [IGT] kms_flip: exiting, ret=77
>[ 1369.316398] Console: switching to colour frame buffer device 240x75
>[ 1369.434538] [IGT] debugfs_emon_crash: executing
>[ 1372.407005] [IGT] debugfs_emon_crash: exiting, ret=0
>[ 1372.505579] Console: switching to colour dummy device 80x25
>[ 1372.505719] [IGT] drm_import_export: executing
>[ 1372.517257] [IGT] drm_import_export: starting subtest flink
>[ 1397.780941] [IGT] drm_import_export: exiting, ret=0
>[ 1397.805638] Console: switching to colour frame buffer device 240x75
>[ 1397.913791] Console: switching to colour dummy device 80x25
>[ 1397.913943] [IGT] drm_import_export: executing
>[ 1397.925191] [IGT] drm_import_export: starting subtest import-close-race-flink
>[ 1440.468164] [IGT] drm_import_export: exiting, ret=0
>[ 1440.489498] Console: switching to colour frame buffer device 240x75
>[ 1440.599155] Console: switching to colour dummy device 80x25
>[ 1440.599290] [IGT] drm_import_export: executing
>[ 1440.614430] [IGT] drm_import_export: starting subtest import-close-race-prime
>[ 1451.563733] [IGT] drm_import_export: exiting, ret=0
>[ 1451.598326] Console: switching to colour frame buffer device 240x75
>[ 1451.706249] Console: switching to colour dummy device 80x25
>[ 1451.706405] [IGT] drm_import_export: executing
>[ 1451.728447] [IGT] drm_import_export: starting subtest prime
>[ 1479.487121] [IGT] drm_import_export: exiting, ret=0
>[ 1479.520336] Console: switching to colour frame buffer device 240x75
>[ 1479.629882] Console: switching to colour dummy device 80x25
>[ 1479.630032] [IGT] drm_vma_limiter: executing
>[ 1484.176897] [IGT] drm_vma_limiter: exiting, ret=0
>[ 1484.257470] Console: switching to colour frame buffer device 240x75
>[ 1485.158532] Console: switching to colour dummy device 80x25
>[ 1485.158757] [IGT] drm_vma_limiter_cached: executing
>[ 1491.934405] [IGT] drm_vma_limiter_cached: exiting, ret=0
>[ 1491.996942] Console: switching to colour frame buffer device 240x75
>[ 1492.110796] Console: switching to colour dummy device 80x25
>[ 1492.110906] [IGT] drm_vma_limiter_cpu: executing
>[ 1498.551795] [IGT] drm_vma_limiter_cpu: exiting, ret=0
>[ 1500.787221] Console: switching to colour frame buffer device 240x75
>[ 1500.934213] Console: switching to colour dummy device 80x25
>[ 1500.934355] [IGT] drm_vma_limiter_gtt: executing
>[ 1507.962198] [IGT] drm_vma_limiter_gtt: exiting, ret=0
>[ 1507.992908] Console: switching to colour frame buffer device 240x75
>[ 1509.606648] [IGT] drv_debugfs_reader: executing
>[ 1509.630374] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1509.863215] [IGT] drv_debugfs_reader: exiting, ret=0
>[ 1509.964642] Console: switching to colour dummy device 80x25
>[ 1509.964764] [IGT] drv_missed_irq: executing
>[ 1512.218515] [drm:i915_ring_test_irq_set [i915]] Masking interrupts on rings 0x0000001f
>[ 1512.218678] [drm:i915_ring_test_irq_set [i915]] Masking interrupts on rings 0x00000000
>[ 1512.299802] [drm:i915_ring_test_irq_set [i915]] Masking interrupts on rings 0x0000001f
>[ 1513.843320] [drm:missed_breadcrumb [i915]] render ring missed breadcrumb at intel_engine_disarm_breadcrumbs+0xb9/0xc0 [i915], irq posted? yes
>[ 1515.825524] [drm:missed_breadcrumb [i915]] bsd ring missed breadcrumb at intel_engine_disarm_breadcrumbs+0xb9/0xc0 [i915], irq posted? yes
>[ 1517.810149] [drm:missed_breadcrumb [i915]] bsd2 ring missed breadcrumb at intel_engine_disarm_breadcrumbs+0xb9/0xc0 [i915], irq posted? yes
>[ 1519.793548] [drm:missed_breadcrumb [i915]] blitter ring missed breadcrumb at intel_engine_disarm_breadcrumbs+0xb9/0xc0 [i915], irq posted? yes
>[ 1521.842076] [drm:missed_breadcrumb [i915]] video enhancement ring missed breadcrumb at intel_engine_disarm_breadcrumbs+0xb9/0xc0 [i915], irq posted? yes
>[ 1521.864625] [drm:i915_ring_test_irq_set [i915]] Masking interrupts on rings 0x00000000
>[ 1521.866186] [IGT] drv_missed_irq: exiting, ret=0
>[ 1521.920653] Console: switching to colour frame buffer device 240x75
>[ 1522.035270] Console: switching to colour dummy device 80x25
>[ 1522.035451] [IGT] drv_suspend: executing
>[ 1522.046861] [IGT] drv_suspend: starting subtest debugfs-reader
>[ 1522.060160] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.083916] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.107554] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.132761] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.157145] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.180583] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.204574] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.227831] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.252199] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.276963] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.300718] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.324886] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.348444] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.372704] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.397463] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.420669] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.448467] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.472208] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.495523] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.520026] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.543467] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.566652] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.590753] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.615502] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.639178] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.663861] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.687446] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.710759] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.737398] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.761638] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.786666] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.811292] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.835248] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.858744] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.883203] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.906824] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.932205] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.956596] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1522.979868] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.006262] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.030579] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.055553] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.080234] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.086597] PM: Syncing filesystems ... done.
>[ 1523.086832] PM: Preparing system for sleep (mem)
>[ 1523.087452] Freezing user space processes ... (elapsed 0.015 seconds) done.
>[ 1523.103414] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 1523.104798] PM: Suspending system (mem)
>[ 1523.104909] Suspending console(s) (use no_console_suspend to debug)
>[ 1523.107832] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[ 1523.107889] sd 0:0:0:0: [sda] Stopping disk
>[ 1523.108885] e1000e: EEE TX LPI TIMER: 00000011
>[ 1523.110152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1523.121366] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 1523.121427] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[ 1523.121533] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1523.139819] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1523.139901] [drm:intel_disable_shared_dpll [i915]] disable LCPLL 810 (active 1, on? 1) for crtc 32
>[ 1523.139936] [drm:intel_disable_shared_dpll [i915]] disabling LCPLL 810
>[ 1523.139979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1523.140063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1523.140092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1523.140117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1523.140141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1523.140167] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1523.140197] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1523.140225] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1523.140252] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1523.140279] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1523.140302] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1523.140325] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1523.140387] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1523.223246] PM: suspend of devices complete after 117.177 msecs
>[ 1523.224773] [drm:intel_power_well_disable [i915]] disabling display
>[ 1523.224801] [drm:hsw_set_power_well [i915]] Requesting to disable the power well
>[ 1523.224817] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1523.224841] [drm:hsw_enable_pc8 [i915]] Enabling package C8+
>[ 1523.236127] PM: late suspend of devices complete after 12.874 msecs
>[ 1523.238525] ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
>[ 1523.238787] e1000e 0000:00:19.0: System wakeup enabled by ACPI
>[ 1523.250143] PM: noirq suspend of devices complete after 14.006 msecs
>[ 1523.250528] ACPI: Preparing to enter system sleep state S3
>[ 1523.274610] PM: Saving platform NVS memory
>[ 1523.274765] Disabling non-boot CPUs ...
>[ 1523.287692] smpboot: CPU 1 is now offline
>[ 1523.305078] Broke affinity for irq 23
>[ 1523.305085] Broke affinity for irq 42
>[ 1523.306400] smpboot: CPU 2 is now offline
>[ 1523.321207] Broke affinity for irq 8
>[ 1523.321211] Broke affinity for irq 9
>[ 1523.321216] Broke affinity for irq 23
>[ 1523.321220] Broke affinity for irq 42
>[ 1523.321223] Broke affinity for irq 43
>[ 1523.322283] smpboot: CPU 3 is now offline
>[ 1523.324348] ACPI: Low-level resume complete
>[ 1523.324498] PM: Restoring platform NVS memory
>[ 1523.325041] Suspended for 16.020 seconds
>[ 1523.325245] Enabling non-boot CPUs ...
>[ 1523.325383] x86: Booting SMP configuration:
>[ 1523.325389] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[ 1523.327468]  cache: parent cpu1 should not be sleeping
>[ 1523.328988] CPU1 is up
>[ 1523.329110] smpboot: Booting Node 0 Processor 2 APIC 0x1
>[ 1523.330562]  cache: parent cpu2 should not be sleeping
>[ 1523.331481] CPU2 is up
>[ 1523.331549] smpboot: Booting Node 0 Processor 3 APIC 0x3
>[ 1523.332843]  cache: parent cpu3 should not be sleeping
>[ 1523.334694] CPU3 is up
>[ 1523.343574] ACPI: Waking up from system sleep state S3
>[ 1523.371504] pcieport 0000:00:1c.3: Enabling MPC IRBNCE
>[ 1523.371515] pcieport 0000:00:1c.3: Intel PCH root port ACS workaround enabled
>[ 1523.371723] ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
>[ 1523.372097] PM: noirq resume of devices complete after 12.593 msecs
>[ 1523.372352] [drm:hsw_disable_pc8 [i915]] Disabling package C8+
>[ 1523.372482] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1523.372523] [drm:intel_power_well_enable [i915]] enabling display
>[ 1523.374628] PM: early resume of devices complete after 2.459 msecs
>[ 1523.374971] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0xa2ccc018
>[ 1523.375032] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 1523.375061] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 1523.377289] hpet1: lost 7173 rtc interrupts
>[ 1523.378885] e1000e 0000:00:19.0: System wakeup disabled by ACPI
>[ 1523.380361] rtc_cmos 00:03: System wakeup disabled by ACPI
>[ 1523.382861] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
>[ 1523.382896] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 1523.382929] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 1523.382960] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 1523.383240] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[ 1523.383275] [drm:init_workarounds_ring [i915]] render ring: Number of context specific w/a: 11
>[ 1523.383317] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[ 1523.383357] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[ 1523.383398] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[ 1523.383437] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[ 1523.383478] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1523.383601] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[ 1523.383637] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: disabled
>[ 1523.383677] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[ 1523.383710] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[ 1523.383750] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[ 1523.383782] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[ 1523.383817] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 1523.383859] [drm:intel_modeset_setup_hw_state [i915]] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 1523.383887] [drm:intel_modeset_setup_hw_state [i915]] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[ 1523.383911] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[ 1523.383935] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[ 1523.383958] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[ 1523.383984] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: disabled, pipe A
>[ 1523.384011] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[ 1523.384035] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[ 1523.384059] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[ 1523.384082] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[ 1523.384112] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:HDMI-A-1] hw state readout: disabled
>[ 1523.384143] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:53:DP-1] hw state readout: disabled
>[ 1523.384186] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[ 1523.384224] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[ 1523.384249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 1523.384275] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1523.384299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1523.384305] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1523.384329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1523.384334] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1523.384359] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1523.384383] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1523.384407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1523.384430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1523.384456] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1523.384480] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1523.384503] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1523.384527] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1523.384551] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1523.384577] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[ 1523.384601] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 1523.384624] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1523.384646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1523.384651] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1523.384674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1523.384679] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1523.384703] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1523.384727] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1523.384749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1523.384772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1523.384798] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1523.384822] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1523.384845] [drm:intel_dump_pipe_config [i915]] [PLANE:33:primary B] disabled, scaler_id = 0
>[ 1523.384869] [drm:intel_dump_pipe_config [i915]] [PLANE:35:sprite B] disabled, scaler_id = 0
>[ 1523.384891] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = 0
>[ 1523.384917] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[ 1523.384940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[ 1523.384963] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1523.384986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1523.384991] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1523.385013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1523.385018] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 1523.385042] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 1523.385061] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 1523.385080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1523.385099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1523.385118] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1523.385134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1523.385162] [drm:intel_dump_pipe_config [i915]] [PLANE:40:primary C] disabled, scaler_id = 0
>[ 1523.385177] [drm:intel_dump_pipe_config [i915]] [PLANE:42:sprite C] disabled, scaler_id = 0
>[ 1523.385193] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = 0
>[ 1523.385214] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 810 enabled but not in use, disabling
>[ 1523.385231] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 1350 enabled but not in use, disabling
>[ 1523.385248] [drm:intel_modeset_setup_hw_state [i915]] LCPLL 2700 enabled but not in use, disabling
>[ 1523.385295] [drm:intel_atomic_check [i915]] [CONNECTOR:53:DP-1] checking for sink bpp constrains
>[ 1523.385312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1523.385333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 1523.385355] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1523.385372] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 1523.385391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1523.385409] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[ 1523.385431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1523.385455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 1523.385478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 1523.385505] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1523.385511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1523.385533] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1523.385537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[ 1523.385560] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x5
>[ 1523.385583] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 1523.385606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1523.385629] [drm:intel_dump_pipe_config [i915]] ips: 1, double wide: 0
>[ 1523.385653] [drm:hsw_dump_hw_state [i915]] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[ 1523.385675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1523.385699] [drm:intel_dump_pipe_config [i915]] [PLANE:26:primary A] disabled, scaler_id = 0
>[ 1523.385722] [drm:intel_dump_pipe_config [i915]] [PLANE:28:sprite A] disabled, scaler_id = 0
>[ 1523.385745] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = 0
>[ 1523.385770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1523.385795] [drm:intel_reference_shared_dpll [i915]] using LCPLL 810 for pipe A
>[ 1523.385881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 0 kHz, ref 0 kHz
>[ 1523.385914] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 0 kHz, ref: 0 kHz
>[ 1523.385938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[ 1523.385962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DDI C]
>[ 1523.385985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST A]
>[ 1523.386008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST B]
>[ 1523.386032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DP-MST C]
>[ 1523.386055] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1523.386082] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1523.386108] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 1
>[ 1523.386133] [drm:verify_single_dpll_state.isra.70 [i915]] WRPLL 2
>[ 1523.386169] [drm:verify_single_dpll_state.isra.70 [i915]] SPLL
>[ 1523.386194] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1523.386217] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 1350
>[ 1523.386240] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 2700
>[ 1523.386286] [drm:intel_enable_shared_dpll [i915]] enable LCPLL 810 (active 1, on? 0) for crtc 32
>[ 1523.386315] [drm:intel_enable_shared_dpll [i915]] enabling LCPLL 810
>[ 1523.388554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1523.388579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1523.388581] sd 0:0:0:0: [sda] Starting disk
>[ 1523.388605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1523.388626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1523.390212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[ 1523.390231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[ 1523.390249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1523.391794] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1523.391815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1523.393699] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1523.397082] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1523.397137] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:53:DP-1], [ENCODER:52:DDI C]
>[ 1523.397174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 1523.397213] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 1523.397320] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1523.397349] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1523.413889] [drm:verify_connector_state.isra.46 [i915]] [CONNECTOR:53:DP-1]
>[ 1523.413932] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[ 1523.413997] [drm:verify_single_dpll_state.isra.70 [i915]] LCPLL 810
>[ 1523.414032] [drm:intel_atomic_commit_tail [i915]] [CRTC:39:pipe B]
>[ 1523.414071] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe C]
>[ 1523.414289] [drm:intel_hdmi_detect [i915]] [CONNECTOR:48:HDMI-A-1]
>[ 1523.414350] [drm:intel_opregion_register [i915]] 3 outputs detected
>[ 1523.416363] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1523.416396] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1523.417467] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 1523.417475] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1523.419560] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1523.419592] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 1523.421669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 1523.421677] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1523.421684] [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:HDMI-A-1] status updated from disconnected to disconnected
>[ 1523.421717] [drm:intel_dp_detect [i915]] [CONNECTOR:53:DP-1]
>[ 1523.422819] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 06 00 00 00 00
>[ 1523.423755] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[ 1523.423777] [drm:intel_dp_print_rates [i915]] source rates: 162000, 270000, 540000
>[ 1523.423797] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 1523.423815] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 1523.424839] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0
>[ 1523.424858] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 1523.425812] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-1] status updated from connected to connected
>[ 1523.425845] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[ 1523.427937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1523.427974] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1523.430086] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 1523.430096] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1523.431318] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1523.431353] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 1523.433237] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 1523.433246] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[ 1523.433254] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from disconnected to disconnected
>[ 1523.600500] PM: resume of devices complete after 225.876 msecs
>[ 1523.601478] PM: Finishing wakeup.
>[ 1523.601482] Restarting tasks ... 
>[ 1523.601715] pcieport 0000:00:1c.0: Enabling MPC IRBNCE
>[ 1523.601719] pcieport 0000:00:1c.0: Intel PCH root port ACS workaround enabled
>[ 1523.603163] done.
>[ 1523.632887] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.659475] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.683042] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.699390] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[ 1523.706870] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.716627] ata1.00: configured for UDMA/133
>[ 1523.730544] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.754194] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.783025] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.807050] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.830260] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.854030] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.877452] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.900666] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.923839] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.946846] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.971080] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1523.995345] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.019509] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.043423] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.067023] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.090139] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.113521] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.136762] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.160413] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.183652] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.207098] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.230510] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.256207] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.279891] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.303252] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.326325] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.349693] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.373181] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.397475] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.420915] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.444573] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.467512] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.490605] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.514618] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.537764] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.561669] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.585994] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.609835] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6
>[ 1524.614967] [IGT] drv_suspend: exiting, ret=0
>[ 1524.615540] [drm:intel_print_rc6_info [i915]] Enabling RC6 states: RC6 on
>[ 1524.681769] Console: switching to colour frame buffer device 240x75
>[ 1524.795509] Console: switching to colour dummy device 80x25
>[ 1524.795682] [IGT] drv_suspend: executing
>[ 1524.809632] [IGT] drv_suspend: starting subtest fence-restore-tiled2untiled

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